Activation circuit and storage device

Abstract

The invention discloses an activation circuit and a storage device. The activation circuit is applied to control a storage array. The activation circuit comprises an activation signal generation circuit which is used for generating an initial activation signal and a working condition indication signal; the trimming signal generation circuit is used for receiving the working condition indication signal and generating a trimming signal corresponding to the working condition indication signal; and the control circuit is used for trimming the initial activation signal based on the trimming signal to obtain a target activation signal, and controlling the storage array based on the target activation signal. Based on the mode, the reliability of the storage array can be improved.

Description

Technical Field

[0001] The present application relates to the field of storage control technology, and in particular to an activation circuit and a storage device. Background Art

[0002] In the prior art, in existing storage devices, such as DRAM (Dynamic Random Access Memory) devices or other types of storage devices, parameters for generating trimming signals are usually pre-stored. The trimming signals can be used to perform pulse width trimming on an activation signal input to a storage array of the storage device for activation control (such as row control), thereby making the activation signal after pulse width trimming more suitable for the storage operation of the storage device.

[0003] The defect of the prior art is that the parameters pre-stored in the existing storage device for generating the trimming signal are fixed parameters pre-burned into the storage device, that is, the trimming of the activation signal based on the trimming signal corresponding to the fixed parameter is a fixed adjustment, which makes the activation signal less adaptable when the storage device is in different working conditions and has different demand characteristics, which can easily lead to poor stability during the operation of the storage array and reduce the reliability of the storage array. Summary of the invention

[0004] The main technical problem solved by this application is how to improve the reliability of the storage array.

[0005] In order to solve the above technical problems, the first technical solution adopted in the present application is: an activation circuit, used to control the storage array; the activation circuit includes: an activation signal generating circuit, the activation signal generating circuit is used to generate an initial activation signal and an operating condition indication signal; an adjustment signal generating circuit, the adjustment signal generating circuit is used to receive the operating condition indication signal, and generate an adjustment signal corresponding to the operating condition indication signal; a control circuit, the control circuit is used to adjust the initial activation signal based on the adjustment signal to obtain a target activation signal, and control the storage array based on the target activation signal.

[0006] Among them, receiving the operating condition indication signal and generating the adjustment signal corresponding to the operating condition indication signal includes: in response to different received operating condition indication signals, generating different adjustment signals to trigger the control circuit to generate target activation signals with different strengths or timings.

[0007] Wherein, the operating condition indication signal includes a first indication signal and a second indication signal, and the generation conditions of the first indication signal and the second indication signal are different; receiving the operating condition indication signal and generating a trimming signal corresponding to the operating condition indication signal include: in response to receiving the first indication signal, generating a first trimming signal as a trimming signal; in response to not receiving the first indication signal and receiving the second indication signal, generating a second trimming signal as a trimming signal; in response to not receiving the first indication signal and not receiving the second indication signal, generating a third trimming signal as a trimming signal.

[0008] The first indication signal is a signal generated when an operation mode control instruction of the storage array is received, and the second indication signal is a signal generated when the environmental sensing data received from the storage array meets a preset condition.

[0009] Among them, the trimming signal generating circuit includes: a first data selection unit, a first input end of the first data selection unit is used to receive a third trimming signal, a second input end of the first data selection unit is used to receive a second trimming signal, a control end of the first data selection unit is used to receive a second indication signal, the first data selection unit is used to output the third trimming signal in response to its control end not receiving the second indication signal, and output the second trimming signal in response to its control end receiving the second indication signal; a second data selection unit, a first input end of the second data selection unit is used to receive a signal output by the first data selection unit, a second input end of the second data selection unit is used to receive the first trimming signal, the control end of the second data selection unit is used to receive the first indication signal, the second data selection unit is used to output the signal output by the first data selection unit in response to its control end not receiving the first indication signal, and output the first trimming signal in response to its control end receiving the first indication signal.

[0010] The control circuit includes at least one signal strength adjustment circuit, which is used to control the connection or disconnection of each branch of the signal strength adjustment circuit based on the adjustment signal, and the signal strength adjustment circuit is used to adjust the signal strength of the initial activation signal.

[0011] The control circuit includes at least one pulse width adjustment circuit, which is used to control the activation and deactivation of the pulse width adjustment circuit based on the adjustment signal. The pulse width adjustment circuit is used to adjust the pulse width of the initial activation signal when enabled and maintain the pulse width of the initial activation signal when disabled.

[0012] The trimming signal includes trimming data, and the number of bits of the trimming data is at least two; the control circuit includes: at least two pulse width trimming circuits connected in series in sequence, each pulse width trimming circuit is used to receive a corresponding data control bit in the trimming data, the pulse width trimming circuit is used to be enabled in response to the received data control bit satisfying a first condition, and to be disabled in response to the received data control bit satisfying a second condition, the input end of the first pulse width trimming circuit of the at least two pulse width trimming circuits connected in series in sequence receives an initial activation signal, and the output end of the last pulse width trimming circuit of the at least two pulse width trimming circuits connected in series in sequence sends a target activation signal.

[0013] The pulse width adjustment circuit includes: an OR gate unit, wherein the first input end of the OR gate unit is used as the input end of the pulse width adjustment circuit, and the output end of the OR gate unit is used as the output end of the pulse width adjustment circuit; a delay unit, wherein the input end of the delay unit is connected to the first input end of the OR gate unit; and an AND gate unit, wherein the first input end of the AND gate unit is connected to the output end of the delay unit, the second input end of the AND gate unit is used to receive a corresponding data control bit in the adjustment data, and the output end of the AND gate unit is connected to the second input end of the OR gate unit.

[0014] In order to solve the above technical problems, the second technical solution adopted in the present application is: a storage device, including a storage array and the above activation circuit, the activation circuit is used to control the storage array, and the target activation signal includes multiple signals for controlling the activation operation of the storage array.

[0015] The beneficial effect of the present application is that: different from the prior art, in the technical solution of the present application, the activation circuit includes an activation signal generating circuit, a trimming signal generating circuit and a control circuit, the activation signal generating circuit is used to generate an initial activation signal and an operating condition indication signal, the trimming signal generating circuit is used to receive the operating condition indication signal, and generate a trimming signal corresponding to the operating condition indication signal, the control circuit is used to trim the initial activation signal based on the trimming signal to obtain a target activation signal, and control the storage array based on the target activation signal. Based on the above method, the current operating condition of the storage array can be determined according to the operating condition indication signal, so as to generate a trimming signal adapted to the current operating condition based on the operating condition indication signal, and the trimming of the initial activation signal is realized, so that the adaptability between the target activation signal obtained after trimming and the current operating condition of the storage array is improved, thereby improving the stability of the storage array during operation, and further improving the reliability of the storage array. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a schematic structural diagram of an embodiment of the activation circuit of the present application;

[0018] Figure 2 is a structural schematic diagram of another embodiment of the activation circuit of the present application;

[0019] Figure 3 is a structural schematic diagram of another embodiment of the activation circuit of the present application;

[0020] Figure 4 It is a waveform diagram of an embodiment of the present application in which a pulse width trimming circuit is enabled;

[0021] Figure 5 It is a schematic diagram of the waveform before and after the timing adjustment of this application;

[0022] Figure 6 It is a structural diagram of an embodiment of the third trimming circuit of the present application.

[0023] Figure numerals: 11, activation signal generating circuit; 12, adjustment signal generating circuit; 121, first data selecting unit; 122, second data selecting unit; 13, control circuit; 131, pulse width adjustment circuit; 1311, OR gate unit; 1312, delay unit; 1313, AND gate unit; 132, signal strength adjustment circuit; 2, storage array. DETAILED DESCRIPTION

[0024] The present application is further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the present application, but are not intended to limit the scope of the present application. Similarly, the following examples are only some embodiments of the present application rather than all embodiments, and all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of the present application.

[0025] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0026] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "install", "set", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or connected through an intermediate medium. For ordinary technicians in this field, the above-mentioned specific meanings belonging to this application can be connected according to specific circumstances.

[0027] This application proposes an activation circuit, see Figures 1 to 3 , Figure 1 is a schematic diagram of the structure of an embodiment of the activation circuit of the present application, Figure 2 is a schematic diagram of the structure of another embodiment of the activation circuit of the present application, Figure 3 is a structural diagram of another embodiment of the activation circuit of the present application, such as Figures 1 to 3 As shown, the activation circuit is applied to control the storage array 2.

[0028] The activation circuit includes an activation signal generating circuit 11 , a trimming signal generating circuit 12 and a control circuit 13 .

[0029] The activation signal generating circuit 11 is used to generate an initial activation signal and an operating condition indication signal. Specifically, the activation signal generating circuit 11 may be a global control circuit, which is used to send a corresponding activation signal to the control circuit 13 so that the control circuit 13 activates the corresponding row storage unit in the storage array 2 to refresh the data, and may also be used to trigger the generation of an operating condition indication signal for representing different operating conditions in response to the operating mode of the storage array and / or the environmental factors of the storage array meeting different preset conditions.

[0030] The trimming signal generating circuit 12 is used to receive the working condition indication signal and generate a trimming signal corresponding to the working condition indication signal. The trimming signal generating circuit 12 can determine the current working condition of the storage array according to the received working condition indication signal to generate a trimming signal corresponding to the current working condition for trimming the initial activation signal.

[0031] The control circuit 13 is used to adjust the initial activation signal based on the adjustment signal to obtain the target activation signal, and control the storage array 2 based on the target activation signal. Among them, the control circuit 13 can adjust the initial activation signal based on the adjustment signal based on the received adjustment signal matching the current working condition to obtain the target activation signal, so that the target activation signal can be more suitable for controlling the operation of the storage array under the current working condition. For example, if the pulse width of the activation signal required to activate the storage array under the current working condition is wider than the initial activation signal, the pulse width of the initial activation signal can be increased by the adjustment signal to obtain the target activation signal to control the control circuit 13. The target activation signal has a wider pulse width than the target activation signal, which can better adapt to the operation requirements of the storage array 2 under the current working condition, so that the storage array 2 under different working conditions can operate more stably under the adjustment effect of the corresponding generated adjustment signal, thereby improving the reliability of the storage array.

[0032] For example, when the current working condition is refresh mode (Refresh mode) or low temperature mode (LowTemperature mode), different adjustment signals can be generated respectively. The initial activation signal is adjusted based on the different adjustment signals respectively, and different target activation signals can be obtained respectively. Different target activation signals can be more suitable for the operation of the storage array 2 under the corresponding working conditions, thereby improving the reliability of the storage array 2 under various types of working conditions.

[0033] It should be noted that the activation signal may specifically refer to an activation signal used to activate each row in the storage array to achieve data refresh during the storage array refresh cycle. For example, the activation signal may specifically be a high-level signal on the word line (WordLine) used to activate the corresponding row storage unit for data refresh.

[0034] Trimming in chip testing is specifically a process in which a corresponding trimming signal is sent from the outside to the inside of the chip during the testing process after the chip is manufactured and before the chip leaves the factory. For example, after testing, the final adjusted trimming signal is burned into the chip's non-volatile memory (such as a fuse) for storage to adjust the behavior corresponding to certain parameters of the chip, or to change the connection method and working status of certain devices inside the chip to achieve the effect of changing the performance or function of the chip.

[0035] The trim signal may specifically be a partial signal of the trim signal, and the trim signal may specifically be a trimming signal used to perform signal processing on a signal generated or received during the operation of the storage array, and the signal processing trimming may specifically be an amplitude addition or subtraction trimming of the corresponding signal, or a pulse width trimming, or a phase trimming, or other types of trimming signals, and different parts of the trim signal may be used to perform corresponding trimming on different signals, for example, in the technical solution of the present application, a partial signal in the trim signal generated based on the current operating condition represented by the operating condition indication signal may be used as a trimming signal to trim the initial activation signal, so that the target activation signal obtained after the trimming can be more adapted to the current operating condition, so as to improve the reliability of the storage array operating based on the target activation signal, wherein the trimming of the initial activation signal may be an adjustment of at least one of the amplitude, pulse width, phase and other characteristics of the initial activation signal, and the specific adjustment may be determined according to actual needs and is not limited here.

[0036] Different from the prior art, in the technical solution of the present application, the activation circuit includes an activation signal generating circuit, a trimming signal generating circuit and a control circuit, the activation signal generating circuit is used to generate an initial activation signal and an operating condition indication signal, the trimming signal generating circuit is used to receive the operating condition indication signal and generate a trimming signal corresponding to the operating condition indication signal, the control circuit is used to trim the initial activation signal based on the trimming signal to obtain a target activation signal, and control the storage array based on the target activation signal. Based on the above method, the current operating condition of the storage array can be determined according to the operating condition indication signal, so as to generate a trimming signal adapted to the current operating condition based on the operating condition indication signal, and the initial activation signal can be trimmed, so that the adaptability between the target activation signal obtained after trimming and the current operating condition of the storage array is improved, thereby improving the stability of the storage array during operation, and further improving the reliability of the storage array.

[0037] In one embodiment, adjusting the initial activation signal based on the adjustment signal to obtain the target activation signal may specifically include:

[0038] The initial activation signal is adjusted in intensity, timing or function based on the adjustment signal to obtain a target activation signal.

[0039] Specifically, when the current operating condition is the refresh mode (Refresh mode) or the low temperature mode (Low Temperature mode), relative to the case where the current operating condition is in the normal mode, it is usually necessary to make the target activation signal directly used to control the storage array 2 have a larger pulse width relative to the initial activation signal. Controlling the storage array 2 based on the target activation signal with a larger pulse width can optimize power consumption, increase speed, and enhance stability.

[0040] Based on the above method, the initial activation signal can be adjusted in pulse width, timing or function based on the corresponding adjustment signal to obtain the corresponding target activation signal. The different adjustment signals generated under different working conditions can make the target activation signal have different pulse width, timing or function relative to the initial activation signal, so as to be more suitable for the storage array 2 under different working conditions, thereby improving the stability of the storage array 2 during operation, and thus improving the reliability of the storage array 2.

[0041] For example, Figure 2 As shown, the control circuit 13 may include at least a first trimming circuit X, a second trimming circuit Y and a third trimming circuit Z.

[0042] The first trimming circuit X, the second trimming circuit Y and the third trimming circuit Z can be used to trim different characteristics of the initial activation signal, for example, the first trimming circuit X can be used to trim the pulse width of the initial activation signal, the second trimming circuit Y can be used to trim the timing of the initial activation signal, and the third trimming circuit Z can be used to trim the intensity of the initial activation signal.

[0043] In practice, the first trimming circuit X can be used to increase or decrease the pulse width of the initial activation signal ACT to obtain the target activation signal ACT_F, that is, the pulse width of the target activation signal ACT_F can be made larger or smaller than the pulse width of the initial activation signal ACT to achieve timing trimming. <n:0>The first bit group in confirms the pulse width amplitude required to be adjusted or the target pulse width required to be adjusted, so as to perform corresponding pulse width adjustment on the initial activation signal ACT to obtain the target activation signal ACT_F.

[0044] See also Figure 5 , Figure 5 This is a schematic diagram of the waveform before and after the timing adjustment of this application. Figure 5 As shown, the second trimming circuit Y can be used to delay the initial activation signal ACT, for example, to delay the initial activation signal ACT with a delay time of D, so that the target activation signal ACT_F has a delay of D relative to the initial activation signal ACT, thereby achieving timing trimming. <n:0>The second bit group in confirms the delay time D that needs to be adjusted, so as to perform corresponding timing adjustment on the initial activation signal ACT to obtain the target activation signal ACT_F.

[0045] See also Figure 6 , Figure 6 is a schematic diagram of the structure of an embodiment of the third trimming circuit of the present application. Figure 6 As shown, the third trimming circuit Z may include at least two switch tubes, and the third trimming circuit Z may receive a Trim <n:0>The third bit group in the switching tube, the driving end of each switching tube is used to receive the corresponding bit in the third bit group, the first end of the switching tube is used to receive the power supply voltage VIN, and the second end of the switching tube is used to output the voltage signal VOUT, so as to generate an initial activation signal or a target activation signal based on the voltage signal VOUT, that is, by controlling different numbers of switching tubes to be turned on, the signal strength of the initial activation signal or the target activation signal can be adjusted. Taking the number of switching tubes as two as an example, the driving end of one switching tube can receive Z1 in the third bit group, and the driving end of the other switching tube can receive Z2 in the third bit group. By assigning different combinations of values ​​of ZI and Z2, different adjustments to the signal strength can be achieved.

[0046] It is worth noting that other embodiments of the present invention may only include any combination of one or more of the first trimming circuit X, the second trimming circuit Y and the third trimming circuit Z. <n:0>The first bit group, the second bit group and any combination of one or more of the first bit group are included, that is, the first bit group, the second bit group and the third bit group are all Trim <n:0>For the part in the control circuit 13, other types of adjustment circuits can also be set in the control circuit 13 to perform corresponding adjustment processing based on the series of other parts. The specific adjustment can be determined according to needs and is not limited here.

[0047] Alternatively, if Figure 6 As shown, the third trimming circuit Z in the control circuit 13 may include at least one signal strength adjustment circuit 132. The control circuit 13 is used to control the connection or disconnection of each branch of the signal strength adjustment circuit 132 based on the trimming signal. The signal strength adjustment circuit 132 is used to adjust the signal strength of the initial activation signal.

[0048] Specifically, for example, Figure 6 As shown, a signal strength adjustment circuit 132 may specifically include a switch tube, and a third trimming circuit Z may receive a Trim <n:0>The driving end of each switch tube is used to receive the corresponding bit in the corresponding partial sequence, the first end of the switch tube is used to receive the power supply voltage VIN, and the second end of the switch tube is used to output the voltage signal VOUT, so as to generate an initial activation signal or a target activation signal based on the voltage signal VOUT, that is, by controlling different numbers of switch tubes to be turned on or off, the connection or disconnection of each branch of the signal strength adjustment circuit 132 can be controlled, so as to adjust the signal strength of the initial activation signal or the target activation signal.

[0049] like Figure 6 As shown, taking the number of switch tubes as two as an example, the driving end of one switch tube can receive Z1 in the corresponding part of the sequence, and the driving end of the other switch tube can receive Z2 in the corresponding part of the sequence. By assigning different combinations of values ​​of ZI and Z2, the conduction and disconnection of switch tubes in different combinations can be realized, and the connection or disconnection of each branch of the control signal strength adjustment circuit 132 can be realized, thereby realizing different adjustments to the signal strength.

[0050] By analogy, the third adjustment circuit Z may also include other numbers of switch tubes to adjust the signal strength in more gears, which is not limited here.

[0051] Alternatively, if Figure 3 As shown, the first trimming circuit X in the control circuit 13 may include at least one pulse width trimming circuit 131. The control circuit 13 is used to control the activation and deactivation of the pulse width trimming circuit 131 based on the trimming signal. The pulse width trimming circuit 131 is used to perform pulse width trimming on the initial activation signal when enabled, and maintain the pulse width of the initial activation signal when disabled.

[0052] Specifically, the pulse width adjustment circuit 131 can be used to increase or decrease the pulse width of the passing signal or to maintain the pulse width. Which of the three processes is performed is determined by the corresponding bit of the adjustment data contained in the adjustment signal received by the pulse width adjustment circuit 131, that is, each pulse width adjustment circuit 131 in all the pulse width adjustment circuits 131 can be controlled by the adjustment signal to be in an enabled or disabled state. Therefore, by making the adjustment signal different under different working conditions, the number of pulse width adjustment circuits 131 enabled in all the pulse width adjustment circuits 131 and / or the objects of the pulse width adjustment circuits 131 enabled can be different under different working conditions, so that the initial activation signal (such as Figure 3 After the ACT shown in FIG. 1 passes through all the pulse width adjustment circuits 131 in sequence, the pulse width adjustment circuits 131 enabled in all the pulse width adjustment circuits 131 respectively perform pulse width adjustment processing to improve the target activation signal (such as Figure 3 The ACT_F) shown in FIG. 1 is compatible with the storage array 2 under the current working condition, thereby improving the stability of the storage array 2.

[0053] Furthermore, the trimming signal includes trimming data, and the number of bits of the trimming data is at least two.

[0054] like Figure 3 As shown, the control circuit 13 includes:

[0055] At least two pulse width trimming circuits 131 are connected in series, each of which is used to receive a corresponding data control bit in the trimming data. The pulse width trimming circuit 131 is used to be enabled in response to the received data control bit satisfying a first condition, and to be disabled in response to the received data control bit satisfying a second condition, wherein the input end of the first pulse width trimming circuit 131 of the at least two pulse width trimming circuits 131 connected in series receives an initial activation signal, and the output end of the last pulse width trimming circuit 131 of the at least two pulse width trimming circuits 131 connected in series sends a target activation signal.

[0056] Specifically, as described in the above embodiment, the trim signal can be a partial signal of the trim signal, and the information contained in the partial signal of the trim signal can be trim data with at least two bits. At least two pulse width trimming circuits 131 connected in series receive different bits of the trim data, such as receiving the Trim signal. <0> 、Trim <1> …Trim <n>The pulse width trimming circuit 131 may be enabled when the corresponding bit of the received trimming data is 1 to perform pulse width trimming (increasing the pulse width or decreasing the pulse width) on the passing signal, and disabled when the corresponding bit of the received trimming data is 0 to perform pulse width maintenance on the passing signal.

[0057] Based on the above method, the initial activation signal (such as Figure 3 After the ACT shown in FIG. 1 passes through all the pulse width adjustment circuits 131 in sequence, the pulse width adjustment circuits 131 enabled in all the pulse width adjustment circuits 131 respectively adjust the pulse width, thereby improving the target activation signal (such as Figure 3 The ACT_F) shown in FIG. 1 is compatible with the storage array 2 under the current working condition, thereby improving the stability of the storage array 2.

[0058] Furthermore, if Figure 3 As shown, the pulse width adjustment circuit 131 includes an OR gate unit 1311 , a delay unit 1312 and an AND gate unit 1313 .

[0059] The first input terminal of the OR gate unit 1311 serves as the input terminal of the PWM circuit 131 , and the output terminal of the OR gate unit 1311 serves as the output terminal of the PWM circuit 131 .

[0060] An input terminal of the delay unit 1312 is connected to a first input terminal of the OR gate unit 1311 .

[0061] The first input end of the AND gate unit 1313 is connected to the output end of the delay unit 1312 , the second input end of the AND gate unit 1313 is used to receive a corresponding data control bit in the trimming data, and the output end of the AND gate unit 1313 is connected to the second input end of the OR gate unit 1311 .

[0062] Specifically, see Figure 4 , Figure 4 It is a waveform diagram of an embodiment of the present application in which the pulse width trimming circuit is enabled.

[0063] like Figure 3 As shown, when the data control bit received at the second input end of the AND gate unit 1313 is 1, the signal outputted from the output end of the AND gate unit 1313 is a delayed signal relative to the signal inputted from the first input end of the OR gate unit 1311, that is, Figure 4 As shown, taking the first pulse width adjustment circuit 131 as an example, the data control bit received at the second input end of the AND gate unit 1313 is 1. After the initial activation signal ACT is input into the delay unit 1312, the signal delayed by the delay unit 1312 can output the delayed signal ACT_D through the output end of the AND gate unit 1313. The delayed signal ACT_D is a signal obtained after delaying the initial activation signal ACT. By inputting the initial activation signal ACT and the delayed signal ACT_D into the two input ends of the OR gate unit 1311 respectively, the pulse width of the signal output by the OR gate unit 1311 can be increased, and the first pulse width increase signal ACT_1 obtained by the pulse width increase processing of the first pulse width adjustment circuit 131 can be obtained.

[0064] Subsequently, the initial activation signal ACT passes through all the pulse width adjustment circuits 131 in sequence. Each time the pulse width adjustment circuit 131 is passed through, if the pulse width adjustment circuit 131 is disabled, the pulse width of the passed signal remains unchanged. If the pulse width adjustment circuit 131 is enabled, the pulse width of the passed signal increases. The final output ACT_F is the target activation signal.

[0065] It should be noted that, among all the pulse width adjustment circuits 131, the delay time lengths corresponding to the delay units 1312 of any two pulse width adjustment circuits 131 during delay processing may be different or the same, that is, after the signal has been delayed by any two pulse width adjustment circuits 131, the amplitude of the pulse width increase may be different or the same, which is not limited here.

[0066] Based on the above method, the pulse width adjustment circuit 131 can be constructed based on simple gate devices, and the function of increasing the pulse width of the initial activation signal to different degrees can be realized based on the adjustment signal, thereby improving the structural and functional stability of the pulse width adjustment circuit 131.

[0067] In one embodiment, receiving the operating condition indication signal and generating the adjustment signal corresponding to the operating condition indication signal may specifically include:

[0068] In response to different received operating condition indication signals, different adjustment signals are generated to trigger the control circuit 13 to generate target activation signals with different intensities or timings.

[0069] Specifically, under different working conditions, for example, when the storage array 2 is in refresh mode, when the storage array 2 is in low temperature mode, and when the storage array 2 is in other types of modes, the working conditions faced by the storage array 2 are usually different. At this time, it is usually necessary to control the storage array 2 using target activation signals generated by different trimming processes under different working conditions to meet the activation requirements under the corresponding working conditions. For example, the timing of the signal may specifically include the pulse width of the signal, that is, a target activation signal with a corresponding timing (with a corresponding pulse width) can be generated based on the trimming signal. Under one working condition, the pulse width of the target activation signal may need to be relatively large, while under another working condition, the pulse width of the target activation signal may need to be relatively small. Therefore, by generating different trimming signals under the indication of the working condition indication signals corresponding to different working conditions to adapt to the storage array 2 under the corresponding working conditions, the stability and reliability of the storage array 2 during operation can be effectively improved.

[0070] It should be noted that in other examples, target activation signals of different strengths, or target activation signals of different timings (pulse width or other timing parameters other than pulse width), or target activation signals of combinations of different strengths and timings can be generated based on different operating condition indication signals, which are not limited here.

[0071] Optionally, the operating condition indication signal includes a first indication signal and a second indication signal, and the generation conditions of the first indication signal and the second indication signal are different.

[0072] Receiving an operating condition indication signal and generating a trimming signal corresponding to the operating condition indication signal, including:

[0073] In response to receiving the first indication signal, a first trimming signal is generated as the trimming signal.

[0074] In response to not receiving the first indication signal and receiving the second indication signal, a second trimming signal is generated as the trimming signal.

[0075] In response to not receiving the first indication signal and not receiving the second indication signal, a third trimming signal is generated as the trimming signal.

[0076] Specifically, the first indication signal and the second indication signal may be indication signals with different processing priorities, respectively, wherein the processing priority of the first indication signal may be higher than the processing priority of the second indication signal. If the first indication signal is received, the first adjustment signal is used as the adjustment signal regardless of whether the second indication signal is received. If the first indication signal is not received, it is determined whether the second indication signal is received to determine whether the second adjustment signal or the third adjustment signal is used as the adjustment signal, thereby achieving generation of different adjustment signals that meet corresponding operating conditions based on different combinations of the received first indication signal and the second indication signal.

[0077] For example, the first indication signal may be a signal generated when an operation mode control instruction of the storage array 2 is received, such as a refresh mode indication signal REF, and the second indication signal may be a signal generated when the environmental sensor data received from the storage array 2 meets a preset condition, such as a low temperature mode indication signal LT. When the refresh mode indication signal REF is received, the adjustment signal is directly determined based on the refresh mode indication signal REF, and when the refresh mode indication signal REF is not received, it is determined which adjustment signal to generate based on whether the low temperature mode indication signal LT is received, so that the adjustment signal is more suitable for the storage array 2 operating under the corresponding working conditions, thereby improving the stability and reliability of the storage array 2.

[0078] The above is only an example. In other examples, the refresh mode indication signal REF can also be replaced by other types of signals related to the operation mode of the storage array 2, such as a self-refresh mode indication signal, a sleep mode indication signal, or other types of operation mode indication signals, which are not limited here. The low temperature mode indication signal LT can also be replaced by other types of signals related to the detection conditions of the environment in which the storage array 2 is located, such as a high temperature mode indication signal, a low humidity mode indication signal, a high humidity mode indication signal, a jitter mode indication signal, or other types of signals related to the detection conditions of the environment in which the storage array 2 is located, which are not limited here.

[0079] Furthermore, if Figure 3 As shown, the trimming signal generating circuit 12 includes a first data selecting unit 121 and a second data selecting unit 122 .

[0080] The first input end of the first data selection unit 121 is used to receive the third adjustment signal, the second input end of the first data selection unit 121 is used to receive the second adjustment signal, the control end of the first data selection unit 121 is used to receive the second indication signal, and the first data selection unit 121 is used to output the third adjustment signal in response to the control end not receiving the second indication signal, and output the second adjustment signal in response to the control end receiving the second indication signal.

[0081] The first input end of the second data selection unit 122 is used to receive the signal output by the first data selection unit 121, the second input end of the second data selection unit 122 is used to receive the first adjustment signal, the control end of the second data selection unit 122 is used to receive the first indication signal, and the second data selection unit 122 is used to output the signal output by the first data selection unit 121 in response to its control end not receiving the first indication signal, and output the first adjustment signal in response to its control end receiving the first indication signal.

[0082] Specifically, the first data selection unit 121 and the second data selection unit 122 can both be data selectors, which output when the indication signal (such as the refresh mode indication signal REF or the low temperature mode indication signal LT) received at the control end is 0. Figure 3 The signal inputted by the input terminal corresponding to the "0" symbol in the control terminal is outputted when the indication signal received by the control terminal is 1. Figure 3 The signal input to the input terminal corresponds to the "1" symbol.

[0083] like Figure 3 As shown, when the refresh mode indication signal REF is 1 and the low temperature mode indication signal LT is any value, Trim <n:0>That is Trim_REF <n:0>.

[0084] When the refresh mode indication signal REF is 0 and the low temperature mode indication signal LT is 1, Trim <n:0>That is Trim_LT <n:0>.

[0085] When the refresh mode indication signal REF is 0 and the low temperature mode indication signal LT is 0, Trim <n:0>That is Trim_ACT <n:0>.

[0086] Based on the above method, based on the structure of the cascaded data selector, an adjustment signal generating circuit 12 having the related functions of the processing priority described in the previous embodiment can be constructed. When the adjustment signal generating circuit 12 is capable of generating more types of adjustment signals according to more types of indication signals, it is also possible to continue to cascade more data selection units on the basis of the first data selection unit 121 and the second data selection unit 122. That is, the stability and scalability of the adjustment signal generating circuit 12 are relatively high.

[0087] The present application also proposes a storage device, such as Figures 1 to 3 As shown, the storage device includes the activation circuit and the storage array 2 described in any one of the above embodiments, and the activation circuit is used to control the storage array 2.

[0088] Specifically, the storage device may refer to a DRAM (Dynamic Random Access Memory) device, or may be other types of memory devices, which may be determined according to actual needs and is not limited here.

[0089] Different from the prior art, in the technical solution of the present application, the activation circuit includes an activation signal generating circuit, a trimming signal generating circuit and a control circuit, the activation signal generating circuit is used to generate an initial activation signal and an operating condition indication signal, the trimming signal generating circuit is used to receive the operating condition indication signal and generate a trimming signal corresponding to the operating condition indication signal, the control circuit is used to trim the initial activation signal based on the trimming signal to obtain a target activation signal, and control the storage array based on the target activation signal. Based on the above method, the current operating condition of the storage array can be determined according to the operating condition indication signal, so as to generate a trimming signal adapted to the current operating condition based on the operating condition indication signal, and the initial activation signal can be trimmed, so that the adaptability between the target activation signal obtained after trimming and the current operating condition of the storage array is improved, thereby improving the stability of the storage array during operation, and further improving the reliability of the storage array.

[0090] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0091] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0092] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0093] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (which can be a personal computer, server, network device or other system that can fetch instructions from the instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0094] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application. < / n>

Claims

1. An activation circuit, characterized in that: Used to control storage arrays; The activation circuit comprises: An activation signal generating circuit, the activation signal generating circuit being used to generate an initial activation signal and an operating condition indication signal; a trimming signal generating circuit, the trimming signal generating circuit being used to receive the operating condition indication signal and generate a trimming signal corresponding to the operating condition indication signal; and A control circuit is used to adjust the initial activation signal based on the adjustment signal to obtain a target activation signal, and control the storage array based on the target activation signal.

2. The activation circuit according to claim 1, characterized in that: The receiving the operating condition indication signal and generating a trimming signal corresponding to the operating condition indication signal comprises: In response to the different received operating condition indication signals, different adjustment signals are generated to trigger the control circuit to generate target activation signals with different strengths or timings.

3. The activation circuit according to claim 2, characterized in that: The operating condition indication signal comprises a first indication signal and a second indication signal, and the generation conditions of the first indication signal and the second indication signal are different; The receiving the operating condition indication signal and generating a trimming signal corresponding to the operating condition indication signal comprises: In response to receiving the first indication signal, generating a first adjustment signal as the adjustment signal; In response to not receiving the first indication signal and receiving the second indication signal, generating a second trimming signal as the trimming signal; In response to not receiving the first indication signal and not receiving the second indication signal, generating a third trimming signal as the trimming signal.

4. The activation circuit according to claim 3, characterized in that: The first indication signal is a signal generated when an operation mode control instruction of the storage array is received, and the second indication signal is a signal generated when environmental sensing data received from the storage array meets a preset condition.

5. The activation circuit according to claim 3 or 4, characterized in that: The trimming signal generating circuit comprises: a first data selection unit, wherein a first input end of the first data selection unit is used to receive the third trimming signal, a second input end of the first data selection unit is used to receive the second trimming signal, a control end of the first data selection unit is used to receive the second indication signal, and the first data selection unit is used to output the third trimming signal in response to the control end not receiving the second indication signal, and output the second trimming signal in response to the control end receiving the second indication signal; A second data selection unit, wherein the first input end of the second data selection unit is used to receive the signal output by the first data selection unit, the second input end of the second data selection unit is used to receive the first adjustment signal, the control end of the second data selection unit is used to receive the first indication signal, the second data selection unit is used to output the signal output by the first data selection unit in response to the control end not receiving the first indication signal, and output the first adjustment signal in response to the control end receiving the first indication signal.

6. The activation circuit according to any one of claims 1 to 4, characterized in that: The control circuit includes at least one signal strength adjustment circuit, and the control circuit is used to control the connection or disconnection of each branch of the signal strength adjustment circuit based on the adjustment signal, and the signal strength adjustment circuit is used to adjust the signal strength of the initial activation signal.

7. The activation circuit according to claims 1 to 4, characterized in that: The control circuit includes at least one pulse width adjustment circuit, and the control circuit is used to control the activation and deactivation of the pulse width adjustment circuit based on the adjustment signal. The pulse width adjustment circuit is used to adjust the pulse width of the initial activation signal when enabled, and maintain the pulse width of the initial activation signal when disabled.

8. The activation circuit according to claim 7, characterized in that: The trimming signal includes trimming data, and the number of bits of the trimming data is at least two; The control circuit comprises: At least two pulse width trimming circuits are connected in series in sequence, each of which is used to receive a corresponding data control bit in the trimming data, and the pulse width trimming circuit is used to be enabled in response to the received data control bit satisfying a first condition, and to be disabled in response to the received data control bit satisfying a second condition, wherein the input end of the first pulse width trimming circuit of the at least two pulse width trimming circuits connected in series in sequence receives the initial activation signal, and the output end of the last pulse width trimming circuit of the at least two pulse width trimming circuits connected in series in sequence sends the target activation signal.

9. The activation circuit according to claim 8, characterized in that: The pulse width adjustment circuit comprises: An OR gate unit, wherein a first input end of the OR gate unit serves as an input end of the pulse width trimming circuit, and an output end of the OR gate unit serves as an output end of the pulse width trimming circuit; A delay unit, wherein an input end of the delay unit is connected to a first input end of the OR gate unit; An AND gate unit, wherein the first input end of the AND gate unit is connected to the output end of the delay unit, the second input end of the AND gate unit is used to receive a corresponding data control bit in the trimming data, and the output end of the AND gate unit is connected to the second input end of the OR gate unit.

10. A storage device, characterized in that: A memory array and an activation circuit as claimed in any one of claims 1 to 9, wherein the activation circuit is used to control the memory array, wherein the target activation signal includes a plurality of signals for controlling activation operations of the memory array.

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