Memory and memory operating method

Abstract

The invention discloses a memory and a memory operation method. The memory comprises a memory array and a peripheral circuit, the storage array comprises a data storage block for storing data and an error correction code storage block for storing an error correction code, the peripheral circuit comprises an error correction code operation module, and the error correction code operation module is used for receiving data of a specific address and the error correction code corresponding to the specific address according to an error correction command, detecting the error correction code and sending the detected error correction code to the data storage block. And judging whether the error correction code needs to be updated or not. Through the configuration, the data of the storage blocks can obtain error correction codes more comprehensively, so that the bit error rate of the memory is reduced, and the reliability of the memory is improved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a memory with enhanced data error correction code and a memory operation method. Background Art

[0002] In the process of verifying data, the verification technology of the verification data may be, for example, ECC (Error Correcting Code, or error correction code) technology, which usually requires corresponding external logic devices to implement the corresponding verification function. However, the more the number of these external logic devices, the larger the area they occupy. Therefore, how to ensure and enhance the low bit error rate and high reliability of the memory without increasing the area and design complexity is a long-standing problem. Summary of the invention

[0003] The present application provides a memory with enhanced data error correction code and a memory operation method to improve the technical problems of the bit error rate and reliability of the memory.

[0004] In a first aspect, the present application provides a memory, the memory comprising:

[0005] A storage array, the storage array comprising a data storage block for storing data and an error correction code storage block for storing an error correction code; and

[0006] The peripheral circuit includes an error correction code operation module, which is used to receive data of a specific address and an error correction code corresponding to the specific address according to an error correction command, and detect the error correction code to determine whether to update the error correction code.

[0007] In some embodiments, the error correction code includes at least one stack error correction code, one of the stack error correction codes corresponds to a storage stack, the storage stack includes multiple storage units in the data storage block having specific start and end addresses for storing the data, and the data includes at least one stack data corresponding to one of the storage stacks.

[0008] In some embodiments, the detection includes detecting whether the pile error correction code is a preset null value. If the pile error correction code is the preset null value, a new pile error correction code is generated for the pile data, and the new pile error correction code is used to replace the pile error correction code.

[0009] In some embodiments, the error correction command is a first error correction command, the specific address includes a start address, the data covers the storage stack, and the storage stack covers the start address.

[0010] In some embodiments, the specific address includes the starting address and a specific range of addresses starting from the starting address, and the specific range of addresses includes at least one storage stack, and the error correction code includes each of the sub-stack error correction codes corresponding to the at least one storage stack.

[0011] In some embodiments, the error correction command is a second error correction command, and the specific address includes a start address and an end address, and the start address and the end address cover at least one of the storage stacks, and the error correction code includes each of the sub-stack error correction codes corresponding to the at least one storage stack.

[0012] In some embodiments, the first error correction command and the second error correction command have different command codes.

[0013] In some embodiments, the first error correction command and the second error correction command have the same command code, and the error correction code operation module is further used to determine whether the specific address includes the end address, and detect error correction codes corresponding to addresses in different ranges.

[0014] In a second aspect, the present application provides a memory, the memory comprising:

[0015] A storage array, the storage array comprising a data storage block for storing data, and an error correction code storage block for storing an error correction code; the data storage block comprises at least one storage stack, the storage stack comprises a plurality of storage cells having a specific head address and tail address in the data storage block; the data comprises at least one stacked data corresponding to one of the storage stacks; the error correction code comprises at least one stacked error correction code corresponding to one of the storage stacks; and,

[0016] The peripheral circuit includes an error correction code operation module, and the error correction code operation module is used to enable and generate the heap error correction code corresponding to the heap data when the heap data fills up one of the storage heaps.

[0017] In some embodiments, the data is stored in at least one of the storage stacks, and when the previous storage stack is not full, it is determined whether the next storage stack is full, and when it is full, the stack error correction code corresponding to the stack data of the next storage stack is generated and enabled.

[0018] In some embodiments, the storage stack stores at least one piece of data, and when the storage stack is not full with the previous piece of data, the next piece of data continues to be written into the storage stack until the storage stack is full, and the stack error correction code corresponding to the stack data of the storage stack is generated and enabled.

[0019] In some embodiments, the error correction code operation module is further used to receive data of a specific address and an error correction code corresponding to the specific address according to an error correction command, and detect the error correction code to determine whether to update the error correction code.

[0020] In some embodiments, the detection includes detecting whether the pile error correction code is a preset null value. If the pile error correction code is the preset null value, a new pile error correction code is generated for the pile data, and the new pile error correction code is used to replace the pile error correction code.

[0021] In a third aspect, the present application provides a memory operation method, wherein the memory includes a memory array and a peripheral circuit, and the operation method includes:

[0022] A data storage block for storing data and an error correction code storage block for storing error correction codes are arranged in the storage array; and,

[0023] An error correction code operation module is provided in the peripheral circuit, through which data of a specific address and an error correction code corresponding to the specific address are received according to an error correction command, and the error correction code is detected to determine whether the error correction code needs to be updated.

[0024] In some embodiments, the operating method also includes configuring the error correction code to include at least one stack error correction code, one of the stack error correction codes corresponds to a storage stack, the storage stack is a plurality of storage units in the data storage block having a specific start address and end address for storing the data, and the data includes at least one stack data corresponding to one of the storage stacks.

[0025] In some embodiments, it is characterized in that the operation method also includes: detecting whether the pile error correction code is a preset null value, if the pile error correction code is the preset null value, generating a new pile error correction code for the pile data, and replacing the pile error correction code with the new pile error correction code.

[0026] In some embodiments, it is characterized in that the operating method also includes: according to a first error correction command, receiving the data at the specific address including a starting address and a specific range of addresses starting from the starting address, and the storage stack corresponding to the data covers the starting address.

[0027] In some embodiments, the operating method also includes receiving the data at the specific address including a starting address and an ending address according to a second error correction command, and the starting address and the ending address cover at least one of the storage stacks, and the error correction code includes each of the sub-stack error correction codes corresponding to the at least one storage stack.

[0028] In a fourth aspect, the present application provides a memory operation method, the operation method comprising:

[0029] A data storage block for storing data and an error correction code storage block for storing error correction codes are arranged in a storage array; and the data storage block includes at least one storage stack, and the storage stack is a plurality of storage units with specific head addresses and tail addresses in the data storage block; the data includes at least one stack data corresponding to one of the storage stacks; the error correction code includes at least one stack error correction code corresponding to one of the storage stacks; and,

[0030] An error correction code operation module is provided in the peripheral circuit, and when one of the storage piles is fully written with the data in the pile, the pile-by-pile error correction code corresponding to the pile-by-pile data is enabled and generated through the error correction code operation module.

[0031] In some embodiments, the method also includes receiving data of a specific address and an error correction code corresponding to the specific address according to an error correction command, and detecting the error correction code, and the detection includes detecting whether the pile error correction code is a preset null value. If the pile error correction code is the preset null value, a new pile error correction code is generated for the pile data, and the pile error correction code is replaced by the new pile error correction code.

[0032] According to the memory and memory operation method provided by the present application, a data storage block for storing data and an error correction code storage block for storing error correction codes are set in the storage array, and an error correction code operation module is set in the peripheral circuit to receive data of a specific address and an error correction code corresponding to the specific address according to an error correction command, and detect the error correction code to determine whether to update the error correction code, and if the result of the judgment is that the error correction code needs to be updated, calculate a new error correction code for the data, and store the new error correction code in the error correction code storage block. Through the error correction code reinforcement operation brought about by the aforementioned error correction command, the data of the storage block can obtain the error correction code more comprehensively, so that the reliability of the stored data is further improved, the bit error rate of the memory is reduced, and the error of data reading is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0034] Figure 1 It is a schematic block diagram of an exemplary electronic system with a storage system disclosed according to an embodiment of the present application.

[0035] Figure 2 This is a system block diagram of a memory using flash memory as an example disclosed in an embodiment of the present application.

[0036] Figure 3 A schematic diagram of the arrangement and connection of storage units in a storage array.

[0037] Figure 4 Schematic diagram of data storage distribution in a storage array according to an embodiment of the present application.

[0038] Figure 5a It is a schematic diagram of signals at the input and output ends of the error correction code operation module according to an embodiment of the present application.

[0039] Figure 5b It is a schematic diagram of the setting of the error correction code according to the embodiment of the present application.

[0040] Figure 6 The flowchart of the error correction code operation module according to the embodiment of the present application when performing a programming operation.

[0041] Figure 7 FIG. 4 is a timing diagram of bus signals during programming and reading according to an embodiment of the present application.

[0042] Figure 8 It is a schematic diagram of storage locations and ECC generation of a storage array according to an embodiment of the present application.

[0043] Fig. 9 This is a flow chart of the error correction code enhancement operation performed by the error correction code operation module according to the embodiment of the present application according to the first error correction command.

[0044] Fig.10 This is a flow chart of the error correction code enhancement operation performed by the error correction code operation module according to the embodiment of the present application according to the second error correction command.

[0045] Fig.11a and Fig.11b Schematic diagrams of the evolution of error correction code reinforcement operations using different error correction commands according to the embodiments of the present application are respectively shown.

[0046] Fig.12 This is a flow chart of the error correction code enhancement operation performed by the error correction code operation module according to the embodiment of the present application according to the third error correction command. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0048] The terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "one", "one" and "item" used herein are also intended to include plural numbers. It should also be understood that the terms "include" and / or "comprise" used herein specify the existence of stated features, integers, steps, operations, units and / or components, without excluding the existence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0049] Figure 1 A schematic block diagram of an exemplary electronic system 100 having a storage system 110 according to some embodiments of the present application is shown. The electronic system 100 may be, for example, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0050] like Figure 1 As shown, the electronic system 100 may include at least a storage system 110 and a host 120. The storage system 110 has a controller 111 and one or more memories 112. The host 120 may be a processor (e.g., a central processing unit, CPU) or a system on a chip (SoC) (e.g., an application processor, AP) of an electronic device. Specifically, the host 120 may be configured to send data to the memory 112 or receive data from the memory 112.

[0051] According to some embodiments, the controller 111 is coupled to the memory 112 and the host 120, and is configured to control the memory 112. Further, the controller 111 can manage the data stored in the memory 112 and communicate with the host 120. In some embodiments, the controller 111 is designed to control the memory used in electronic devices such as personal computers, digital cameras, mobile phones, etc., or a data or program storage device in a mobile device such as a smart phone, a tablet computer, a laptop computer, etc.

[0052] The controller 111 may be configured to control the operation of the memory 112, such as a read operation (Read), an erase operation (Erase), and a program operation (Program). The controller 111 may also be configured to manage various functions related to data stored or to be stored in the memory 112, such as but not limited to bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 111 is also configured to process error correction codes (ECC) related to data read from or written to the memory 112. In some embodiments, the controller 111 may also be configured to perform any other suitable functions, such as formatting the memory 112.

[0053] The controller 111 may communicate with an external device (e.g., the host 120) according to a specific communication protocol. For example, the controller 111 may communicate with an external device through at least one of various interface protocols, and the interface protocol may be, for example, a universal serial bus (USB) protocol, a multimedia (Multi Media Card, MMC) protocol, a peripheral component interconnect (Peripheral Component Interconnect, PCI) protocol, a high-speed PCI (Peripheral Component Interconnect Express, PCI-E) protocol, an advanced technology attachment (Advanced Technology Attachment, ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (Small Computer System Interface, SCSI) protocol, an enhanced small disk interface (Enhanced Small Device Interface, ESDI) protocol, an integrated drive electronics (Integrated Drive Electronics, IDE) protocol, and a FireWire protocol.

[0054] Figure 1The memory used can be various types of memory, including but not limited to EPROM, DRAM, NAND flash memory, parallel NOR flash memory, serial (SPI) NOR flash memory, PCRAM, FRAM, etc. Taking the comparison between EPROM and SPI NOR flash (SPINOR flash memory) as an example, EPROM usually uses IIC serial bus, which is low speed, single-duplex, and the communication rate is generally hundreds of KHz. SPI Flash uses SPI bus, which is high speed, full-duplex, and the communication rate is generally hundreds of MHz. SPI Flash belongs to Flash ROM flash memory. Compared with EPROM, it has faster reading and writing speed, and SPI Flash is usually used to store frequently read data, such as font files or program codes.

[0055] In some embodiments, the minimum unit of SPI Flash erasure is a sector. When writing data to a certain address, first read the data at this address to see if it is 0xFF. If it is not 0xFF, then the data writing fails. Therefore, the usual write operation is to directly erase the sector where the address is located before writing to a certain address, and then write the data. Of course, if all the contents of this sector are 0xFF, there is no need to erase it and it can be written directly. The capacity of SPI Flash is usually in MB level, such as 2MB to 512MB, or multiple SPI flashes are combined into a memory chip with a capacity of GB level. As for the comparison of other types of memory, I will not explain them one by one here.

[0056] In some memories (especially NAND flash memory), in order to further improve reliability, verification technology / functions (such as error correction code, ECC, error correction code) have become a necessary function. Common configurations include using single-bit correction SEC (Single Error Correction) or single-bit correction-double error detection SEC-DED (Single Error Correction-Double Error Detection) to perform data error correction. SEC-DED has the function of correcting one bit of data or detecting two bits of error. Common SEC-DED implementations include Hamming code and Hsiao code. Various ECC methods are widely used and will not be described in detail here.

[0057] Figure 2Next, a system block diagram of a memory using flash memory (especially SPI flash) as an example according to some embodiments of the present application is shown. In addition, in order to facilitate the explanation of the technical concept of the present application, although only SPI flash is used as an example to represent the aforementioned various memories, it should be understood that the application scope of the technology disclosed in the present application is not limited to SPI flash, but can also be parallel NOR flash and other types of memories.

[0058] like Figure 2 As shown, the memory 10 includes a storage array 10a and a peripheral circuit 10b. The peripheral circuit 10b may include at least a control logic unit 11, a status register 12, a high voltage generator 13, a page address latch / counter 14, a byte address latch / counter 15, a write protection logic unit / row decoder 16, a column decoder / page buffer / sense amplifier 17, an ECC operation module 18, and various data buses IO3, CS#, SI, SO, etc. It should be understood that in some examples, the peripheral circuit 10b may also include other peripheral circuits not shown in FIG. Figure 2 Other circuits shown in FIG.

[0059] The storage array 10a includes a general data storage block 210 and an ECC storage block 220. The data storage block 210 is used to store general data, while the ECC storage block 220 is used to store an error correction code (ECC). The ECC storage block can be a special address block set according to each actual storage block or each storage page in the storage array 10a, and can be set in an extended position in each storage page or a storage stack of a specific size to store the error correction code (ECC) associated with the data error correction operation in the error correction code storage block.

[0060] Specifically, Figure 3 As shown, Figure 3 The configuration of the data storage block 210 and the ECC storage block 220 in the storage array 10a can be as follows: Figure 3 The device includes memory cells 211 arranged in a matrix, and word lines WL 212 and bit lines BL 213 respectively connecting the memory cells 211 in a first direction and a second direction. The first direction and the second direction are usually perpendicular to each other.

[0061] Further, each memory cell 211 is provided in the form of a NOR flash array. Each memory cell 211 can maintain a continuous analog value, such as a voltage or a charge, which depends on the number of electrons captured by each memory cell 211 in the corresponding area. In some embodiments, each memory cell 211 may include a gate layer, and a channel structure composed of a tunneling insulating layer, a charge storage layer, a blocking insulating layer, and a polysilicon layer as a channel. The memory cell 211 may be a floating gate type memory cell including a floating gate transistor, or a charge trap type memory cell including a charge trap transistor.

[0062] In some embodiments, each storage cell 211 may be a single level cell (SLC), wherein the single level cell has two levels of threshold states, and therefore, each single level cell may store one bit (or referred to as "bit") of data, for example, the first level threshold state "0" may correspond to the first voltage range, and the second level threshold state "1" may correspond to the second voltage range. In other embodiments, each storage cell 211 may be a multi-level cell capable of storing more than one bit of data in more than two levels of multi-level threshold states, for example, each storage cell 211 may be a multi-level cell (MLC) capable of storing two bits of data, or a triple level cell (TLC) capable of storing three bits of data, or a quad level cell (QLC) capable of storing four bits of data. One of the multi-level threshold states of the storage cell 211 is an erased state. However, in the ECC storage block 220, each storage unit 211 is usually a single-level cell (SLC), but it can also adopt multi-level storage in accordance with the number of levels of the data storage block 210. In the embodiment of the present application, for ease of description, only a single-level cell will be used as an example.

[0063] In some embodiments, the error correction code disclosed according to the embodiments of the present application includes multiple stack error correction codes, one of the stack error correction codes corresponds to a storage stack (chunk), and each of the storage stacks is a location in the data storage block with a specific start address and end address for storing the data of a specific number of bytes.

[0064] Specifically, Figure 4 Further disclosed is a schematic diagram of data storage distribution in the storage array 10a according to some embodiments of the present application. Figure 4As shown, the data storage location in the data storage block 210 is divided into a plurality of storage chunks 210a[N] according to address settings. The storage chunks 210a[N] may be 210a[0]-210a[N], where N is an integer greater than or equal to zero.

[0065] exist Figure 4 In order to avoid complexity, only one storage stack is labeled 210a, and the other storage stacks are parallel to 210a. In the following description, only 210a is used to represent one storage stack. Each storage stack 210a[N] has a specific first address and last address in the data storage block 210, and is used to store the data of a specific number of bytes. Figure 4 In the example shown, each storage heap 210a is set to 16 bytes. However, it should be understood that the size of each storage heap can be changed and is not limited to this number of bytes.

[0066] In some embodiments, the number of bytes of a storage stack 210a may correspond to the number of bytes detected by a detection amplifier 17 each time, so as to match the hardware design of the memory.

[0067] The error correction code ECC includes a plurality of sub-stack error correction codes ECC[N], each of which also has an error correction code storage position 220a corresponding to each data storage stack 210a. Therefore, one of the sub-stack error correction codes ECC[N] corresponds to one storage stack 210a[N] and also corresponds to one error correction code storage position 220a. Figure 4 In order to avoid complexity, only one error correction code storage position is marked with the label 220a, and the other error correction code storage positions are parallel to the position shown in 220a.

[0068] The above is a description of the storage array 10a disclosed in the embodiment of the present application. Figure 2 The peripheral circuit 10b will be further described.

[0069] First, the control logic unit 11 can be coupled with each circuit in the peripheral circuit 10b as described above (for example, the status register 12, the high voltage generator 13, the page address latch / counter 14, the byte address latch / counter 15, the write protection logic unit / row decoder 16, the column decoder / page buffer / detection amplifier 17, the ECC operation module 18, and various data buses (CLK, CS#, SO, SI, IO2, IO3) and control the operation of each circuit. In the SPI NOR flash, the control logic unit 11 is particularly a serial control logic unit.

[0070] The control logic unit 11 can also be coupled to an interface (not shown) externally, and the interface receives signals CLK, CS#, SO, SI, IO2, IO3, etc. from various data buses. The interface also acts as a control buffer to perform buffering from Figure 1 The controller receives the control command and relays the command to the control logic unit 11, and performs buffering of status information received from the control logic unit 11 and relays the command to the controller.

[0071] Furthermore, the interface shown can also be coupled to the write protection logic unit / row decoder 16, the column decoder / page buffer / sense amplifier 17 via various data buses, and act as a data I / O (Input / Output) interface and a data buffer to perform operations of buffering data and relaying the data to the storage array 10a, and to perform operations of relaying or buffering data from the storage array 10a. Among them, the aforementioned various operations on the data storage array 210 in the storage array 10a all include operations on the error correction code (ECC) storage block 220 in the storage array 10a.

[0072] The status register 12 is coupled to the control logic unit 11 and may include at least a status register, a command register and an address register to store status information, a command operation code (OP code) and a command address for controlling the operation of each of the above circuits.

[0073] The voltage generator 13 can be configured to be controlled by the control logic unit 11 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verification voltage, erase voltage, etc.), bit line voltages and source line voltages to be supplied to the memory array 10a.

[0074] The page address latch / counter 14 and the byte address latch / counter 15 are used to latch the data of a data page in conjunction with the received address each time programming is performed, so as to program the page data into the storage array 10a in sequence, and calculate the address of each programming and the number of programming times until a data page is completely stored and then replaced with the next data page.

[0075] The write protection logic unit / row decoder 16 may be configured to be controlled by the control logic unit 11 to select / deselect the memory cells 211 in the memory array 10a. The write protection logic unit / row decoder 16 may also be configured to drive the word lines WL using the word line voltage generated from the voltage generator 13. As described in detail below, the write protection logic unit / row decoder 16 is configured to perform operations such as programming, erasing, and verifying on the memory cells 211 coupled to one or more selected word lines WL.

[0076] The column decoder / page buffer / sense amplifier 17 can be configured to read data from the memory array 10a and program (also referred to as "write") data to the memory array 10a according to the control signal from the control logic unit 11. Specifically, in one example, the column decoder / page buffer / sense amplifier 17 can store data to be programmed into a memory page of the memory array 10a, for example, 256 bytes. In another example, the column decoder / page buffer / sense amplifier 17 can perform a programming verification operation (Verify) to ensure that the data has been correctly programmed into the memory cell 211 coupled to the selected word line WL. In yet another example, the column decoder / page buffer / sense amplifier 17 can also perform an operation of sensing a low-power signal from the bit line BL representing the data stored in the memory cell 211, and amplify the small voltage swing of the low-power signal to a recognizable logic level in a read operation.

[0077] The column decoder / page buffer / sense amplifier 17 may be configured to be controlled by the control logic unit 11 and select one or more memory cells 211 to be programmed or read by applying a bit line voltage generated from the voltage generator 13 .

[0078] The ECC operation module 18 is used for performing a data error correction operation on the data associated with the data storage block 210 , and the ECC associated with the data error correction operation is stored in the ECC storage block 220 .

[0079] The error correction code operation module 18 is also used to perform programming error correction operations during programming operations. The programming error correction operation receives the stack data from the column decoder / page buffer / detection amplifier (hereinafter referred to as: page buffer) 17, and corresponds to the stack data of the storage stack 210a, and determines the stack error correction code ECC[N] of the stack data, and outputs the stack data and the stack error correction code ECC[N].

[0080] The following further describes the error correction code operation module 18 in conjunction with the programming operation.

[0081] First, the error correction code operation module 18 is used to receive the stack data Bytes[N] corresponding to the size of the storage stack 210a in units of the storage stack 210a, and further determine whether to generate a stack error correction code ECC[N]. The stack error correction code ECC[N] includes an error correction code bit group ECC<8:0> and a flag bit group ECC<10:9>, wherein the error correction code bit group ECC<8:0> includes one of a stack error correction code (ECC-CODE) and a stack error correction preset code (1FFh) corresponding to the stack data, and the flag bit group ECC<10:9> is used to indicate the state attribute of the stack error correction code ECC[N], especially the valid state in some embodiments.

[0082] Specifically, Figure 5a As shown, Figure 5a The signal diagram of the input and output of the error correction code operation module. At the input of the error correction code operation module 18, an ECC EN signal representing whether the ECC function is activated, an ECC call signal ECC CAL, a signal PBOUT<127:0> from the page buffer 17, a signal SA<127:0> from the detection amplifier 17, and / or an error correction code detection signal ECCSA<10:0> are received according to the programming operation or the read operation. And the processed data signal SAP<127:0> and the processed error correction code signal ECCSAP<10:0> are output. The so-called "processed" will be explained in the following text in conjunction with the operation of various embodiments.

[0083] The signal PBOUT<127:0> from the page buffer 17 and the signal SA<127:0> from the detection amplifier 17 are equivalent to receiving the divided data Bytes[N] corresponding to the size of the storage stack 210a. During the programming operation, these data come from the signal PBOUT<127:0> input to the page buffer 17 from the outside, and during the reading operation, these data come from the signal SA<127:0> output from the storage array to the detection amplifier 17. Since a byte has 8 bits, 16 bytes have 128 bits, which are represented by <127:0>.

[0084] Further Figure 5b As shown, Figure 5bThe figure shows a schematic diagram of the setting of the error correction code during the programming process, and the right side of the table in the figure shows the stacked error correction code ECC[N] including the error correction code bit group ECC[8:0] and the flag bit group ECC[10:9] (i.e., ECCSAP <10> and ECCSAP <9> ). The error correction code bit group ECC[8:0] includes one of the stack error correction code ECC-CODE and the stack error correction preset code 1FFh corresponding to the stack data Bytes[N], and the flag bit group ECC[10:9] is used to indicate the status attribute of the effective state of the stack error correction code ECC[N]. Moreover, the stack error correction code ECC[N] includes two types, ECCSA<10:0> and ECCSAP<10:0>, wherein ECCSA<10:0> represents the stack error correction code originally set in the error correction code storage block or to be input into the error correction code operation module 18, and ECCSAP<10:0> represents the stack error correction code processed by the error correction code operation module 18.

[0085] Furthermore, the aforementioned stack error correction code ECC-CODE represents the calculated error correction code corresponding to the stack data Bytes[N*16:N*16+15], and the stack error correction preset code 1FFh represents the preset value originally set in the error correction code storage block. Figure 5b As shown in the table, when the error correction code storage location 220a has not been stored with the error correction code, ECCSA<10;9;8:0> are respectively <1;1;1FFh>, that is, 7FFh. When the error correction code storage location 220a has been stored with the error correction code, ECCSA<10;9;8:0> are respectively <1;0;ECC-CODE>, that is, 10-CODE.

[0086] According to some embodiments of the present application, the memory 10 also includes a page buffer 17, and the error correction code operation module 18 is also used to perform a programming error correction operation during a programming operation. The programming error correction operation receives the stack data PBOUT<127:0> from the page buffer 17 and corresponding to the storage stack 210a (because it is a programming state, PBOUT<127:0> is used to replace the aforementioned Bytes[N] to represent the stack data), and determines the stack error correction code ECCSAP<10:0> of the stack data PBOUT<127:0>, and outputs the stack data SAP<127:0> and the stack error correction code ECCSAP<10:0> that have been processed with the error correction code.

[0087] In some embodiments, the error correction code operation module 18 is also used to perform a first judgment, and the first judgment is used to determine whether the starting address and the ending address of the stack data PBOUT<127:0> cover the stack starting address and the stack ending address of the storage stack 210a. If the result of the first judgment is yes, the stack error correction code ECC-CODE is generated, and the error correction code bit group ECCSAP<8:0> is set to the stack error correction code ECC-CODE, and the flag bit group ECCSAP<10:9> is set to the presence of the stack error correction code <10> and storing the stacked error correction code and the flag bit group into the error correction code storage block or position 220a.

[0088] In some embodiments, if the result of the first judgment is no, the stack error correction code ECCSA<10:0> corresponding to the stack data PBOUT<127:0> in the error correction code storage block is not programmed, and the stack error correction code ECCSAP<10:0> maintains the stack error correction preset code 7FFh.

[0089] In some embodiments, the error correction code operation module is also used to receive the starting address and the ending address of the data to be stored from the page buffer 17 during the programming operation, and determine whether the ending address of the stack data PBOUT<127:0> has reached the ending address. If it has not reached the ending address, the next stack data is received from the page buffer 17, and the programming error correction operation is repeated.

[0090] For details, please refer to Figure 6 The various actions of the error correction code operation module 18 described above using programming as an example. Figure 6 The flowchart of the error correction code operation module 18 according to the embodiment of the present application when performing a programming operation is shown.

[0091] First, in step S100, a program command 02h with an ECC operation, a 24-bit address (N*16), and a data byte ([N*16:M*16+15, 0≦N≦M]) are received, and the data is stored in the page buffer 17. For specific signal operations, please refer to Figure 7 , wherein the signal CS# is used to enable the memory chip, the signal SCLK is a clock signal, and the signal SI is a serial input. In the serial input SI signal, the aforementioned command 02h, 24-bit address, and data bytes 1 to 256 are sequentially input according to the clock signal.

[0092] Next, programming with ECC operations begins, including:

[0093] Step S140: Set the starting address [N*16] and the ending address of the input data;

[0094] Step S150: read out 16 bytes each time, that is, a divided data PBOUT<127:0>;

[0095] Step S160: Calculate the ECC code for the divided data PBOUT<127:0>, set the processed divided data SAP<127:0> as PBOUT<127:0>, and output ECCSA<10:0> and SAP<127:0>;

[0096] Step S170: Perform the aforementioned first determination to determine whether the starting address of the processed stack data SAP<127:0> covers the starting address of the storage stack 210a, and whether the number of program bytes of the processed stack data SAP<127:0> is 16, that is, whether the end address is also the same; if not, let the stack error correction code ECCSAP<10:0> maintain the stack error correction preset code 7FFh;

[0097] Step S180: storing SAP<127:0> into the data storage block 210, and storing ECCSAP<10:0> into the ECC storage block 220; and,

[0098] Step S190: Receive the starting address and the ending address of the data to be stored from the page buffer 17, and determine whether the ending address of the divided data PBOUT<127:0> has reached the ending address. If it has not reached the ending address, receive the next divided data PBOUT<127:0> from the page buffer 17, and repeat the programming error correction operation steps S160 to S180.

[0099] Specifically, the so-called "processed" here means that the relevant judgment or operation of the error correction code has been performed, and the ECC calculation can be performed in this step, or it can be performed when necessary after the first judgment is made. This is just an example. In addition, in addition to the above description, you can also refer to Figure 5b Description of the table shown. Figure 5b The changes of the heap error correction code under the aforementioned first judgment are clearly listed. That is, the first row below the title row represents the situation where the first judgment is "no"; the second row below the title row represents the situation where the first judgment is "yes".

[0100] According to the above programming process, an example is given below to illustrate how to generate ECC according to the storage location. Figure 8 Schematic diagram of storage array storage location and ECC generation according to an embodiment of the present application. Figure 8 As shown, an example of sequentially performing three programming operations in a data storage block 210 and an error correction code storage block 220 with all null values ​​is shown.

[0101] The first programming is to store a page data with a start address of 0h and an end address of 12h. Since this first programming does not meet the first judgment in step S170, in addition to outputting the stack data SAP<127:0>, no ECC-CODE is output, but ECCSAP<10:0> is maintained at <7FFh>.

[0102] The second programming is to store a page data with a starting address of 13h and an ending address of 34h. Among them, since the address of a storage stack is 0h~15h, that is, the stack starting address is N*16, and the stack ending address is N*16+15, N is an integer greater than or equal to 0. Therefore, this data page needs to exist across three storage stacks, so there are three sub-stack data, namely bytes [13:15], bytes [16:31] and bytes [32:34]. Among them, the second sub-stack data [2*16:2*16+15] meets the result of the first judgment of the aforementioned step S170, that is, the result is "yes", so in addition to outputting SAP<127:0>, ECCSAP<10:0>=<1:0:ECC-CODE> is output, that is, ECC[1] is generated. However, the first divided data Bytes[13:15] and the third divided data Bytes[32:34] do not meet the first judgment in step S170, so in addition to outputting the first and third divided data SAP<127:0>, ECC-CODE is not output, but ECCSAP<10:0> is maintained at <7FF>.

[0103] The third programming is to store a page data with a start address of 35h and an end address of 47h. Since this first programming does not meet the first judgment in step S170, in addition to outputting the stack data SAP<127:0>, no ECC-CODE is output, but ECCSAP<10:0> is maintained at <7FFh>.

[0104] In the above embodiment, the first programming and the third programming do not generate the stacking error correction code ECC[N], which is still insufficient for the reliability of data storage. Therefore, according to some embodiments of the present application, a memory is further proposed to improve the problem that the stacking error correction code of some data is not generated.

[0105] Also refer to Figure 2 According to the embodiment of the present application, the memory 10 includes:

[0106] A storage array 10a, the storage array 10a comprising a data storage block 210 for storing data and an error correction code storage block 220 for storing an error correction code; and

[0107] Peripheral circuit 10b, the peripheral circuit 10b includes an error correction code operation module 18, the error correction code operation module 18 is used to receive data of a specific address and an error correction code corresponding to the specific address (that is, corresponding to the data) according to an error correction command SI (which can come from the outside), and detect the error correction code to determine whether to update the error correction code.

[0108] Regarding the aforementioned Figure 2 For specific operations of the error correction code operation module 18, please refer to Fig. 9 . Fig. 9 A specific flow chart showing the error correction code operation module 18 according to the embodiment of the present application performing the above-mentioned operation to strengthen the generation of the error correction code. First, in step S200, an ECC error correction reinforcement command (hereinafter referred to as the error correction command) 88h and a 24-bit address (N*16) are received, and then the ECC error correction reinforcement operation is started, and the steps include:

[0109] Step S250: Detect the stacked data [N*16:N*16+15] and the stacked error correction code ECC[N] through the detection amplifier 17 to obtain the stacked data SA<127:0> and the stacked error correction code ECCSA<10:0>; and

[0110] Step S260: Check whether the heap error correction code ECCSA<10:0> is equal to the preset null value (7FFh). Here, the so-called "preset null value" refers to the state that the storage unit is not programmed. If it is the preset null value (7FFh), it means that the heap error correction code corresponding to this storage stack has not been generated, but is still maintained at the preset value, so it can be updated. If it is not the preset null value (7FFh), it means that the heap error correction code has been generated, and there is no need to generate a new heap error correction code, and this command can be terminated.

[0111] In some embodiments, if the determination result of step S260 is that updating is required, the ECC operation module 18 will further calculate a new ECC for the data and store the new ECC in the ECC storage block 220 .

[0112] Specifically, Fig. 9 As shown in step S270 and step S280, the error correction code operation module 18 further calculates the ECC correction code ECCSAP<8:0> for the stacked data SA<127:0>, adds the flag bit group ECCSAP<10:9>, and outputs a new stacked error correction code ECCSAP<10:0>, and then ends.

[0113] Therefore, according to the foregoing, it can be understood that according to an embodiment of the present application, the memory may include:

[0114] A storage array 10a, the storage array 10a includes a data storage block 210 for storing data, and an error correction code storage block 220 for storing an error correction code; and the data storage block 210 includes at least one storage stack 210a, the storage stack 210a includes a plurality of storage cells 211 with specific head addresses and tail addresses in the data storage block 210; the data includes at least one stack data Bytes[N] corresponding to one of the storage stacks; the error correction code ECC includes at least one stack error correction code ECC[N] corresponding to one of the storage stacks; and,

[0115] The peripheral circuit 10b, the error correction code operation module 18 in the peripheral circuit 10b will enable and generate the heap error correction code ECCSAP<10:0> corresponding to the heap data Bytes[N] when the heap data Bytes[N] fills up the storage heap 210a.

[0116] Specifically, the full writing means that, as in the first judgment mentioned above, during programming, the head address and the tail address of the divided heap data cover the head address and the tail address of the storage heap 210a.

[0117] In some embodiments, the written data is stored in at least one of the storage stacks 210a, and when the previous storage stack is not full, it is determined whether the next storage stack is full, and when it is full, the stack error correction code ECCSAP<10:0> corresponding to the stack data of the next storage stack is generated and enabled. Specifically, for example, in the second programming mentioned above, a page data with a starting address of 13h and an ending address of 34h is stored. The second stack data [2*16:2*16+15] meets the result of the first judgment of the aforementioned step S170, that is, the result is "yes", so in addition to outputting SAP<127:0>, ECCSAP<10:0>=<1:0:ECC-CODE> is output, that is, ECC[1] is generated.

[0118] In other embodiments, the storage stack 210a stores at least one piece of data, and when the storage stack 210a is not filled with the previous piece of data, the next piece of data continues to be written in the storage stack 210a until the storage stack 210a is filled, and the stack error correction code ECCSAP<10:0> corresponding to the stack data in the storage stack 210a is generated and enabled. For example, in the aforementioned third programming, a page data with a starting address of 35h and an ending address of 47h is stored. In this case, with the addition of an error correction command, the stack error correction code ECCSAP<10:0> corresponding to the stack data in the storage stack 210a will be generated and enabled.

[0119] As for how to generate the pile error correction code, it is mainly based on the error correction command, receiving the data of the specific address and the error correction code corresponding to the specific address, and detecting the error correction code to determine whether to update the error correction code; and the detection includes detecting whether the pile error correction code ECC[N] is a preset null value. If the pile error correction code ECC[N] is the preset null value, a new pile error correction code ECCSAP<10:0> is generated for the pile data, and the new pile error correction code ECCSAP<10:0> replaces the pile error correction code ECC[N].

[0120] The specific content of the memory described in this embodiment can be understood based on the description of the previous figures, so no additional figures are prepared for repeated description.

[0121] Furthermore, in some embodiments, the error correction command is a first error correction command and the specific address includes a start address, the data received by the error correction code operation module is the heap data corresponding to the start address, and the received error correction code is the heap error correction code corresponding to the heap data. That is, the data covers the storage heap, and the storage heap covers the start address.

[0122] Specifically, Fig. 9 As shown, when the error correction command is the first error correction command 88h, and there is only a starting address (N*16) but no ending address, the error correction code check corresponding to one heap data is performed in step S260 and then the process ends. If the error correction code check corresponding to other heap data is to be performed, a first error correction command with another starting address must be issued again.

[0123] Fig.11a An example of using the aforementioned first error correction command 88h to perform an error correction code reinforcement operation is shown. Fig.11a As shown, after completing Figure 8 After the programming operation shown, only the error correction code ECC[1] corresponding to the storage stack of bytes 16 to 31 is generated. In order to strengthen the error correction code of each storage stack data, after the first error correction (reinforcement) command 88h with address 00 as the starting address, only the error correction code ECC[0] corresponding to the storage stack of bytes 0 to 15 is generated. After that, the second error correction (reinforcement) command 88h with address 32 as the starting address is required to generate the error correction code ECC[2] corresponding to the storage stack of bytes 32 to 47.

[0124] That is, under this error correction command, the address of each storage pile must be specified one by one to reinforce the generation of each sub-pile error correction code to increase the reliability of data storage or output. Incidentally, during this reinforcement error correction process, an error correction (reinforcement) command 88h with address 16 as the starting address can also be performed in sequence, but because the storage pile with address 16 as the starting address has already generated the sub-pile error correction code ECC[1], the sub-pile error correction code ECC[1] corresponding to the storage pile of byte 16 to byte 31 will not be generated again.

[0125] In some embodiments, the specific address includes the starting address and a specific range of addresses starting from the starting address, and the specific range of addresses includes at least one storage stack, and the error correction code includes each of the sub-stack error correction codes corresponding to the at least one storage stack.

[0126] Specifically, in the previous embodiment, an address within a storage stack range after the start address is used as the specific address, but in some embodiments, an address within a range of several storage stacks after the start address can also be used as the specific address. This range can be preset in advance, and the data of the specific address can be obtained based on the start address. Therefore, when the specific range of addresses includes at least one storage stack, the error correction code will include the error correction codes of each of the sub-stacks corresponding to the at least one storage stack.

[0127] Furthermore, in some embodiments, the error correction command is a second error correction command, and the specific address includes a start address and an end address, and the start address and the end address cover at least one of the storage stacks, and the error correction code includes each of the sub-stack error correction codes corresponding to the at least one storage stack. That is, after the error correction code operation module detects the sub-stack error correction code corresponding to the start address, it also includes determining whether the data has not reached the end address; if it has not reached, it continues to receive the next sub-stack data of the data, and the next sub-stack error correction code corresponding to the next sub-stack data, and detects the next sub-stack error correction code until the data has reached the end address.

[0128] Specifically, Fig.10 As shown, when the error correction command is the second error correction command, and the specific address includes a start address and an end address, that is, when the error correction command is the second error correction command, it is allowed to receive one more end address. Figure 7In the timing diagram, the signal received by the SI pin will have two groups of 24-bit address signals after the command, and then the data will be received. Then, as in the operation process of the first error correction command, a check of the stacking error correction code corresponding to the stacking data will be performed in step S260, as well as the calculation and storage in steps S270 and S280. The difference from the first error correction command is that the check of whether the stacking data has reached the end address is added in step S290. If the result is "yes", the operation of this command is terminated; if the result is "no", enter step S295, automatically add the checked address to the next round of storage stack, and then repeat steps S250 to S280, continue to receive the next stack data (N+1)*16: (N+1)*16+15) of the data, and the next stack error correction code ECC[N+1] corresponding to the next stack data, and detect the next stack error correction code (step S260), and further calculate a new error correction code for the next stack data, and store the new error correction code in the error correction code storage block 220 (steps S270 and S280), until the data has reached the end address.

[0129] Fig.11b An example of using the aforementioned second error correction command 89h to perform an error correction code reinforcement operation is shown. Fig.11b As shown, after completing Figure 8 After the programming operation shown, only the error correction code ECC[1] corresponding to the storage pile of byte 16 to byte 31 is generated. In order to strengthen the error correction code of each storage pile data, after the error correction (reinforcement) command 89h with 00 as the starting address and 32 as the ending address is executed, not only the error correction code ECC[0] corresponding to the storage pile of byte 0 to byte 15 is generated, but also the error correction code ECC[2] corresponding to the storage pile of byte 32 to byte 47 with 32 as the starting address will be generated. That is, under this error correction command, as long as the starting address and ending address of the error correction reinforcement are specified, the error correction code of each storage pile corresponding to the starting address and the ending address will be automatically reinforced to increase the reliability of data storage or output. Incidentally, during this enhanced error correction process, an error correction code check starting at address 16 can also be performed. However, since the storage stack starting at address 16 has already generated the heap error correction code ECC[1], the heap error correction code ECC[1] corresponding to the storage stack from byte 16 to byte 31 will not be generated.

[0130] Through the error correction code reinforcement operation brought about by the above two error correction commands, the reliability of stored data can be further improved and the errors in data reading can be reduced.

[0131] Furthermore, the aforementioned Fig. 9 and Fig.10 The commands used in the error correction reinforcement process use different command codes, but in some embodiments, error correction commands with the same command code can also be used, and the error correction code operation module is allowed to determine whether the specific address includes the end address to perform different operations and detect error correction codes corresponding to addresses in different ranges. Therefore, in some embodiments, the first error correction command and the second error correction command have the same command code, which is referred to as the third error correction command, and the error correction code operation module is also used to determine whether the specific address includes the end address and detect error correction codes corresponding to addresses in different ranges.

[0132] Specifically, Fig.12 As shown, the error correction command is set to the third error correction command 90h, and compared to Figure 7 The timing diagram shows that the signal received by the SI pin retains two 24-bit address signals after the command, and then starts to receive data. At this time, the specific address may include a start address and an end address, or only a start address. Next, after entering the error correction reinforcement operation of the error correction code operation module 18, first determine whether there is an end address in step S230. If so, in step S290', it will be determined whether the data checked in this round has reached the end address; if it is determined in step S230 that there is no end address, in step S290', it will be automatically set to no end address, and then after completing step S260, or steps S260 to S280, the operation of this command is terminated. It can be understood that steps S240 to S280 can be the same regardless of whether they are the first error correction command, the second error correction command, or the third error correction command, so their detailed description is omitted here, and these steps will not be repeated, and please refer to the previous description.

[0133] According to the memory with enhanced data error correction code provided in the above embodiments of the present application, by setting a data storage block for storing data and an error correction code storage block for storing error correction code inside the storage array, and setting an internal error correction code operation module in the peripheral circuit, so as to obtain an error code for each stacked data or storage stack in the data storage block, the bit error rate of the memory can be better reduced and the reliability of the memory can be improved.

[0134] In addition, according to an embodiment of the present application, a memory operation method with enhanced data error correction code is also provided. The memory operation method with data error correction operation is further described below.

[0135] Also refer to the above Figures 2 to 12 The memory operation method of the enhanced data error correction code disclosed in the embodiment of the present application includes: providing Figure 2The error correction code storage block 220 and the error correction code operation module 18 are shown, and a method is provided as follows Fig. 9 , 10 , and the memory operation method of the enhanced data error correction code shown in 12, the specific details and instructions have been described above, so the following only focuses on the storage operation method, and no longer repeats the specific details as mentioned above. For the relevant specific details of each key point, please refer to the corresponding instructions above.

[0136] According to the memory operation method provided in the embodiment of the present application, the memory 10 includes a memory array 10a and a peripheral circuit 10b, and the operation method includes:

[0137] A data storage block 210 for storing data and an error correction code storage block 220 for storing error correction codes are provided in the storage array 10a; and

[0138] An error correction code operation module 18 is provided in the peripheral circuit 10b, and the error correction code operation module 18 receives data of a specific address (00 / 16 / 32) and an error correction code (ECC[N]) corresponding to the specific address according to an error correction command (88h / 89h / 90h), and detects the error correction code to determine whether to update the error correction code.

[0139] In some embodiments, the operating method further includes disposing the storage array 10a and the error correction code operating module 18 in a serial interface flash memory.

[0140] In some embodiments, the operation further includes calculating a new error correction code ECC[N] or ECCSAP<10:0> for the data when the result of the judgment is that an update is required, and storing the new error correction code ECC[N] / ECCSAP<10:0> in the error correction code storage block 220.

[0141] In some embodiments, the operating method further includes:

[0142] The error correction code operation module 18 is configured to receive the chunk data Bytes[N] corresponding to the size of the storage pile based on the storage pile 210a; and the error correction code ECC is configured to include at least one chunk error correction code ECC[N], one chunk error correction code corresponds to a storage pile (chunk), and the storage pile includes the locations of multiple storage units with specific head and tail addresses in the data storage block for storing the data, and the data includes at least one chunk data stored in the storage pile, and the chunk data includes a specific number of bytes.

[0143] In some embodiments, Fig. 9As shown, the memory operation method also includes: detecting whether the pile-up error correction code is a preset null value (7FFh); if the pile-up error correction code is the preset null value, generating a new pile-up error correction code for the pile-up data, and storing the new pile-up error correction code in the error correction code storage position 220a of the error correction code storage block 220 to replace the pile-up error correction code.

[0144] In some embodiments, Fig. 9 As shown, the memory operation method further includes: according to a first error correction command, receiving the data at the specific address including a starting address and a specific range of addresses starting from the starting address, and the storage stack corresponding to the data covers the starting address.

[0145] That is, when the error correction command (which can come from the outside) is the first error correction command (88h) and the specific address (N*16) includes a starting address but no ending address, the data received by the error correction code operation module 18 is set to the stacked data corresponding to the starting address, and the received error correction code ECC[N] is set to the stacked error correction code corresponding to the stacked data.

[0146] Specifically, Fig. 9 As shown, when the error correction command is the first error correction command 88h, and there is only a starting address (N*16) but no ending address, the error correction code check corresponding to one heap data is performed in step S260 and then the process ends. If the error correction code check corresponding to other heap data is to be performed, a first error correction command with another starting address must be issued again.

[0147] In some embodiments, Fig.10 As shown, the memory operation method also includes: according to a second error correction command, receiving the data at the specific address including a starting address and an ending address, and the starting address and the ending address cover at least one of the storage stacks, and the error correction code includes each of the sub-stack error correction codes corresponding to the at least one storage stack.

[0148] That is, when the error correction command is the second error correction command (89h), and the specific address includes a start address (N*16) and an end address (N*16+M), the operation method further includes:

[0149] After detecting the heap error correction code corresponding to the start address, determining whether the data has not yet reached the end address (step S290); and,

[0150] If it has not arrived, continue to receive the next stack data ((N+1)*16) of the data, and the next stack error correction code ECC[N+1] corresponding to the next stack data ((N+1)*16), and detect the next stack error correction code until the data has reached the end address (N*16+M).

[0151] Specifically, Fig.10 As shown, when the error correction command is the second error correction command, and the specific address includes a start address and an end address, that is, when the error correction command is the second error correction command, it is allowed to receive one more end address. Figure 7 When the timing diagram is shown, the signal received by the SI pin will be followed by two 24-bit address signals after the command, and then the data will be received.

[0152] Next, as with the operation process of the first error correction command, a stack error correction code check corresponding to the stack data is performed in step S260, as well as calculation and storage in steps S270 and S280. The difference from the first command is that step S290 is added to check whether the stack data has reached the end address this time. If the result is "yes", the operation of this command is terminated; if the result is "no", enter step S295, automatically add the checked address to the next round of storage stack, and then repeat steps S250 to S280, continue to receive the next stack data (N+1)*16: (N+1)*16+15) of the data, and the next stack error correction code ECC[N+1] corresponding to the next stack data, and detect the next stack error correction code (step S260), and further calculate a new error correction code for the data, and store the new error correction code in the error correction code storage block 220 (steps S270 and S280), until the data has reached the end address.

[0153] The error correction code reinforcement operation brought about by the aforementioned two error correction commands (88h / 89h) can further enhance the reliability of stored data and reduce data reading errors.

[0154] Furthermore, the aforementioned Fig. 9 and Fig.10 The commands used in the error correction reinforcement process use different command codes, but in some embodiments, error correction commands with the same command code can also be used, but the error correction code operation module determines whether the specific address includes the end address, and detects the error correction codes corresponding to addresses in different ranges. Here, the starting address is regarded as an address that must be included, and is therefore not used as a basis for judgment, but it should be understood that the starting address is actually included. The relevant content can be understood by referring to the previous description, so it will not be repeated here.

[0155] Further, according to the above-mentioned embodiment, the embodiment of the present application also provides a memory operation method, the memory 10 includes a memory array 10a and a peripheral circuit 10b, and the operation method includes:

[0156] A data storage block for storing data and an error correction code storage block for storing error correction codes are arranged in a storage array; and the data storage block includes at least one storage stack, and the storage stack is a plurality of storage units with specific head addresses and tail addresses in the data storage block; the data includes at least one stack data corresponding to one of the storage stacks; the error correction code includes at least one stack error correction code corresponding to one of the storage stacks; and,

[0157] An error correction code operation module is provided in the peripheral circuit, and when one of the storage piles is fully written with the data in the pile, the pile-by-pile error correction code corresponding to the pile-by-pile data is enabled and generated through the error correction code operation module.

[0158] In some embodiments, the method also includes receiving data of a specific address and an error correction code corresponding to the specific address according to an error correction command, and detecting the error correction code, and the detection includes detecting whether the pile error correction code is a preset null value. If the pile error correction code is the preset null value, a new pile error correction code is generated for the pile data, and the pile error correction code is replaced by the new pile error correction code.

[0159] The specific operation steps of the aforementioned operation method can be understood by referring to the description of the previous embodiments. Therefore, in order to save space, no additional diagrams are prepared here for repeated description.

[0160] According to the memory operation method for strengthening the data error correction code provided in the above embodiment of the present application, a data storage block for storing data is set inside the storage array and is used to receive data of a specific address and an error correction code corresponding to the data according to an error correction command, and then the error correction code is detected to determine whether to update the error correction code; and if the result of the judgment is that an update is required, a new error correction code is calculated for the data and the new error correction code is stored in the error correction code storage block. Through such an operation method, the coverage of the error correction code can be strengthened, the bit error rate of the memory can be reduced, and the reliability of the memory can be improved.

[0161] The above is a detailed introduction to the memory and memory operation method of the enhanced data error correction code provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present application.

Claims

1. A memory, It is characterized in that The memory comprises: A storage array, the storage array comprising a data storage block for storing data and an error correction code storage block for storing error correction codes; and The peripheral circuit includes an error correction code operation module, which is used to receive data of a specific address and an error correction code corresponding to the specific address according to an error correction command, and detect the error correction code to determine whether to update the error correction code.

2. The memory according to claim 1, It is characterized in that The error correction code includes at least one stack error correction code, one of the stack error correction codes corresponds to a storage stack, the storage stack includes a plurality of storage units with specific head addresses and tail addresses in the data storage block, and the data includes at least one stack data corresponding to one of the storage stacks.

3. The memory according to claim 2, It is characterized in that The detection includes detecting whether the pile-up error correction code is a preset null value. If the pile-up error correction code is the preset null value, a new pile-up error correction code is generated for the pile-up data, and the new pile-up error correction code replaces the pile-up error correction code.

4. The memory according to claim 3, It is characterized in that The error correction command is a first error correction command, the specific address includes a start address, the data covers the storage stack, and the storage stack covers the start address.

5. The memory according to claim 4, It is characterized in that The specific address includes the start address and a specific range address starting from the start address, and the specific range address includes at least one storage stack, and the error correction code includes each of the sub-stack error correction codes corresponding to the at least one storage stack.

6. The memory according to claim 3, It is characterized in that The error correction command is a second error correction command, and the specific address includes a start address and an end address, and the start address and the end address cover at least one of the storage stacks, and the error correction code includes each of the sub-stack error correction codes corresponding to the at least one storage stack.

7. The memory according to claim 1, It is characterized in that The error correction command includes a first error correction command and a second error correction command, and the first error correction command and the second error correction command have different command codes.

8. The memory according to claim 1, It is characterized in that The error correction command includes a first error correction command and a second error correction command, the first error correction command and the second error correction command have the same command code, and the error correction code operation module is also used to determine whether the specific address includes an end address, and detect error correction codes corresponding to addresses in different ranges.

9. A memory, It is characterized in that The memory comprises: A storage array, the storage array comprising a data storage block for storing data, and an error correction code storage block for storing an error correction code; the data storage block comprises at least one storage stack, the storage stack comprises a plurality of storage cells having a specific head address and tail address in the data storage block; the data comprises at least one stacked data corresponding to one of the storage stacks; the error correction code comprises at least one stacked error correction code corresponding to one of the storage stacks; and, The peripheral circuit includes an error correction code operation module, and the error correction code operation module is used to enable and generate the heap error correction code corresponding to the heap data when the heap data fills up one of the storage heaps.

10. The memory according to claim 9, It is characterized in that The data is stored in at least one of the storage stacks, and when the previous storage stack is not full, it is determined whether the next storage stack is full, and when it is full, the stack error correction code corresponding to the stack data of the next storage stack is generated and enabled.

11. The memory according to claim 9, It is characterized in that The storage stack stores at least one piece of data, and when the storage stack is not full of the previous piece of data, continues to write the next piece of data into the storage stack until the storage stack is full, and generates and enables the partitioned error correction code corresponding to the partitioned data of the storage stack.

12. A memory according to claim 9, 10 or 11, It is characterized in that The error correction code operation module is also used to receive data of a specific address and an error correction code corresponding to the specific address according to an error correction command, and detect the error correction code to determine whether to update the error correction code.

13. The memory according to claim 2, It is characterized in that The detection includes detecting whether the pile-up error correction code is a preset null value. If the pile-up error correction code is the preset null value, a new pile-up error correction code is generated for the pile-up data, and the new pile-up error correction code replaces the pile-up error correction code.

14. A memory operation method, It is characterized in that The memory includes a storage array and a peripheral circuit, and the operation method includes: A data storage block for storing data and an error correction code storage block for storing error correction codes are arranged in the storage array; and, An error correction code operation module is provided in the peripheral circuit, through which data of a specific address and an error correction code corresponding to the specific address are received according to an error correction command, and the error correction code is detected to determine whether to update the error correction code.

15. The memory according to claim 14, It is characterized in that The operating method also includes configuring the error correction code to include at least one stack error correction code, one of the stack error correction codes corresponds to a storage stack, the storage stack is a plurality of storage units in the data storage block having a specific head address and tail address for storing the data, and the data includes at least one stack data corresponding to one of the storage stacks.

16. The memory operation method according to claim 15, It is characterized in that The operation method further includes detecting whether the pile-up error correction code is a preset null value. If the pile-up error correction code is the preset null value, a new pile-up error correction code is generated for the pile-up data, and the new pile-up error correction code replaces the pile-up error correction code.

17. The memory operation method according to claim 16, It is characterized in that The operating method further includes receiving the data at the specific address including a start address and a specific range of addresses starting from the start address according to a first error correction command, and the storage stack corresponding to the data covers the start address.

18. The memory operation method according to claim 16, It is characterized in that The operating method also includes receiving the data at the specific address including a starting address and an ending address according to a second error correction command, and the starting address and the ending address cover at least one of the storage stacks, and the error correction code includes each of the sub-stack error correction codes corresponding to the at least one storage stack.

19. A method for operating a memory, It is characterized in that The operation method comprises: A data storage block for storing data and an error correction code storage block for storing error correction codes are arranged in a storage array; and the data storage block includes at least one storage stack, and the storage stack is a plurality of storage units with specific head addresses and tail addresses in the data storage block; the data includes at least one stack data corresponding to one of the storage stacks; the error correction code includes at least one stack error correction code corresponding to one of the storage stacks; and, An error correction code operation module is provided in the peripheral circuit, and when one of the storage piles is fully written with the data in the pile, the pile-by-pile error correction code corresponding to the pile-by-pile data is enabled and generated through the error correction code operation module.

20. The operating method according to claim 19, It is characterized in that The method also includes receiving data of a specific address and an error correction code corresponding to the specific address according to an error correction command, and detecting the error correction code, and the detection includes detecting whether the pile error correction code is a preset null value. If the pile error correction code is the preset null value, a new pile error correction code is generated for the pile data, and the pile error correction code is replaced by the new pile error correction code.

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