Memory and memory operating method

Abstract

The invention discloses a memory with data error correction operation and a memory operation method, which are characterized in that a data storage block for storing data and an error correction code storage block for storing error correction codes are arranged in a storage array, and an error correction code operation module is arranged in a peripheral circuit; according to the invention, the data storage block is used for carrying out a data error correction operation on the data associated with the data storage block, and the error correction code associated with the data error correction operation is stored in the error correction code storage block, so that the bit error rate during the operation of the memory can be reduced, and the reliability of the memory can be improved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a memory with data error correction operation and a memory operation method. Background Art

[0002] In the process of verifying data, the verification technology of the verification data may be, for example, ECC (Error Correcting Code) technology, which usually requires corresponding external logic devices to implement the corresponding verification function. However, the more the number of these external logic devices, the larger the area they occupy. Therefore, how to ensure low bit error rate and high reliability during memory operation without increasing the area and design complexity is a long-standing problem. Summary of the invention

[0003] The present application provides a memory with data error correction operation and a memory operation method to improve the technical problems of bit error rate and reliability during memory operation.

[0004] In a first aspect, the present application provides a memory, the memory comprising:

[0005] A storage array, the storage array comprising a data storage block for storing data and an error correction code storage block for storing an error correction code; and

[0006] The peripheral circuit includes an error correction code operation module for performing a data error correction operation on the data associated with the data storage block, and the error correction code associated with the data error correction operation is stored in the error correction code storage block.

[0007] In some embodiments, the memory is a serial interface flash memory.

[0008] In some embodiments, the error correction code includes multiple heap error correction codes, each of which corresponds to a storage heap (chunk), and each storage heap is a location in the data storage block with a specific start address and end address for storing the data of a specific number of bytes.

[0009] In some embodiments, the error correction code operation module is also used to receive pile data corresponding to the size of the storage pile in units of the storage pile, and the pile error correction code includes an error correction code bit group and a flag bit group, the error correction code bit group includes one of a pile error correction correction code and a pile error correction preset code corresponding to the pile data, and the flag bit group is used to indicate the status attributes of the pile error correction code.

[0010] In some embodiments, the peripheral circuit further includes a detection amplifier, and the number of bytes of one of the storage stacks corresponds to the number of bytes detected by one of the detection amplifiers each time.

[0011] In some embodiments, the memory also includes a page buffer, and the error correction code operation module is also used to perform a programming error correction operation during a programming operation. The programming error correction operation receives the stack data from the page buffer and corresponding to the storage stack, determines the stack error correction code of the stack data, and outputs the stack data and the stack error correction code.

[0012] In some embodiments, the error correction code operation module is also used to perform a first judgment, and the first judgment is used to determine whether the first address and the last address of the pile data cover the first address and the last address of the storage pile. If the result of the first judgment is yes, the pile error correction code is generated, and the error correction code bit group is set to the pile error correction code, and the flag bit group is set to the presence of the pile error correction code, and the pile error correction code and the flag bit group are stored in the error correction code storage block.

[0013] In some embodiments, if the result of the first judgment is no, the pile-by-pile error correction code corresponding to the pile-by-pile data in the error correction code storage block is not programmed, and the pile-by-pile error correction code maintains the pile-by-pile error correction preset code.

[0014] In some embodiments, the error correction code operation module is also used to perform a second judgment, and the second judgment is used to determine whether the flag bit group in the pile error correction code corresponding to the pile data indicates that the corresponding pile error correction code already exists. If the result of the second judgment is yes, the error correction code bit group in the pile error correction code corresponding to the pile data is not programmed, and the flag bit group is programmed to indicate that the pile error correction code is invalid.

[0015] In some embodiments, the error correction code operation module is also used to perform a third judgment, and the third judgment is used to determine whether the original stored data in the storage stack is not all preset null values. If the result of the third judgment is yes, the error correction code bit group in the stack error correction code corresponding to the storage stack is not programmed, and the flag bit group is programmed to indicate that the stack error correction code is invalid.

[0016] In some embodiments, the error correction code operation module is also used to receive the starting address and ending address of the data to be stored from the page buffer during the programming operation, and determine whether the tail address of the stacked data has reached the ending address. If it has not reached the ending address, the next stacked data is received from the page buffer and the programming error correction operation is repeated.

[0017] In some embodiments, the error correction code operation module is also used to perform a read error correction operation when reading the data, and the read error correction operation receives the stack data and the stack error correction code corresponding to the storage stack from the data storage block, and outputs the processed stack data according to the stack error correction code.

[0018] In some embodiments, the error correction code operation module is also used to determine whether it is necessary to perform data error correction on the pile data based on the flag bit group in the pile error correction code. If necessary, the corrected pile data is used as the processed pile data. If not, the received pile data is directly used as the processed pile data.

[0019] In some embodiments, the error correction code operation module is further used to calculate a pile data error correction check code, and then output the corrected pile data as the processed pile data based on the pile error correction check code and the pile error correction code.

[0020] In some embodiments, the error correction code operation module is also used to receive the starting address and ending address of the data to be read during the read operation, and determine whether the tail address of the divided data has reached the ending address. If it has not reached the ending address, the next divided data is received from the data storage block and the read error correction operation is repeated.

[0021] In some embodiments, the error correction code operation module is further configured to enable the heap-wise error correction code of the heap-wise data when the heap-wise data fills up one of the storage heaps, and disable the heap-wise error correction code otherwise.

[0022] In some embodiments, the writing is performed based on a first judgment, and the first judgment is used to determine whether the first address and the last address of the divided heap data cover the first address and the last address of the storage heap.

[0023] In some embodiments, the error correction code operation module is further used to disable the heap error correction code when the heap error correction code already exists or when the original stored data in the storage heap is not all preset null values.

[0024] In a second aspect, the present application provides a memory operation method, wherein the memory includes a memory array and a peripheral circuit, and the operation method includes:

[0025] A data storage block for storing data and an error correction code storage block for storing error correction codes are arranged in the storage array; and

[0026] An error correction code operation module is set in the peripheral circuit, and a data error correction operation is performed on the data associated with the data storage block through the error correction code operation module, and the error correction code associated with the data error correction operation is stored in the error correction code storage block.

[0027] In some embodiments, the operating method includes placing the storage array and the error correction code operating module in a serial interface flash memory.

[0028] In some embodiments, the operation also includes configuring the error correction code into multiple stack error correction codes, and making one of the stack error correction codes correspond to a storage stack (chunk), and each of the storage stacks is a location in the data storage block with a specific start address and end address for storing a specific number of bytes of the data.

[0029] In some embodiments, the operating method further includes:

[0030] The error correction code operation module is configured to receive the divided heap data corresponding to the size of the storage heap in units of the storage heap; and

[0031] The pile error correction code is configured to include an error correction code bit group and a flag bit group, and the error correction code bit group is configured to correspond to one of a pile error correction code and a pile error correction preset code of the pile data, and the flag bit group is configured to indicate the valid state of the pile error correction code.

[0032] In some embodiments, the memory further includes a page buffer, and the operation method further includes a programming error correction operation, and the programming error correction operation includes:

[0033] receiving the divided heap data corresponding to the storage heap from the page buffer through the error correction code operation module; and

[0034] The pile error correction code of the pile data is determined, and the pile data and the pile error correction code are output.

[0035] In some embodiments, the programming error correction operation further includes: when the divided pile data fills up one of the storage piles, enabling the divided pile error correction code of the divided pile data, otherwise disabling the divided pile error correction code.

[0036] In some embodiments, the writing is performed based on a first judgment, and the first judgment is used to determine whether the first address and the last address of the divided heap data cover the first address and the last address of the storage heap.

[0037] In some embodiments, the programming error correction operation further includes: when the stack error correction code already exists, or when the original stored data in the storage stack is not all preset null values, disabling the stack error correction code.

[0038] In some embodiments, the programming error correction operation further includes:

[0039] Performing a first judgment by an error correction code operation module, wherein the first judgment is used to judge whether the first address and the last address of the divided data cover the first address and the last address of the storage heap;

[0040] If the result of the first judgment is yes, the sub-pile error correction code is generated, the error correction code bit group is set to the sub-pile error correction code, and the flag bit group is set to indicate the presence of the sub-pile error correction code; and,

[0041] The stacked error correction code and the flag bit group are stored in the error correction code storage block.

[0042] In some embodiments, the programming error correction operation further includes:

[0043] If the result of the first judgment is no, the pile-by-pile error correction code corresponding to the pile-by-pile data in the error correction code storage block is not programmed, and the pile-by-pile error correction code maintains the pile-by-pile error correction preset code.

[0044] In some embodiments, the programming error correction operation further includes:

[0045] A second judgment is performed through the error correction code operation module, and the second judgment is used to determine whether the flag bit group in the pile error correction code corresponding to the pile data indicates that the corresponding pile error correction code already exists; if the result of the second judgment is yes, the error correction code bit group in the pile error correction code corresponding to the pile data is not programmed, and the flag bit group is programmed to indicate that the pile error correction code is invalid.

[0046] In some embodiments, the programming error correction operation further includes:

[0047] A third judgment is performed through the error correction code operation module, and the third judgment is used to determine whether the original data stored in the storage stack is not all preset null values. If the result of the third judgment is yes, the error correction code bit group in the stack error correction code corresponding to the storage stack is not programmed, and the flag bit group is programmed to indicate that the error correction code is invalid.

[0048] In some embodiments, the programming error correction operation further includes:

[0049] The error correction code operation module receives the starting address and the ending address of the data to be stored from the page buffer, and determines whether the tail address of the divided data has reached the ending address; if it has not reached the ending address, the next divided data is received from the page buffer, and the programming error correction operation is repeated.

[0050] In some embodiments, the operation method further includes a read error correction operation, and the read error correction operation includes:

[0051] Receiving, through the error correction code operation module, the heap data and the heap error correction code corresponding to the storage heap in the data storage block; and

[0052] According to the heap error correction code, the processed heap data is output.

[0053] In some embodiments, the read error correction operation further includes:

[0054] In the error correction code operation module, whether it is necessary to perform data error correction on the pile data is determined based on the flag bit group in the pile error correction code; if necessary, the corrected pile data is used as the processed pile data; if not necessary, the received pile data is directly used as the processed pile data.

[0055] In some embodiments, the read error correction operation further includes:

[0056] Calculating a heap error correction check code for the heap data by the error correction code operation module; and

[0057] According to the pile-by error correction check code and the pile-by error correction code, the corrected pile-by data is output as the processed pile-by data.

[0058] In some embodiments, the read error correction operation further includes:

[0059] The error correction code operation module receives the starting address and the ending address of the data to be read, and determines whether the tail address of the divided data has reached the ending address; if it is determined that the tail address has not reached the ending address, the next divided data is received from the data storage block, and the read error correction operation is repeated.

[0060] According to the memory and memory operation method provided by the present application, by setting a data storage block for storing data and an error correction code storage block for storing error correction codes in a storage array, and setting an error correction code operation module in a peripheral circuit to perform a data error correction operation on the data associated with the data storage block, and the error correction code associated with the data error correction operation is stored in the error correction code storage block, the bit error rate during the memory operation can be reduced and the reliability of the memory can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0062] Figure 1 It is a schematic block diagram of an exemplary electronic system with a storage system disclosed according to an embodiment of the present application.

[0063] Figure 2 This is a system block diagram of a memory using flash memory as an example disclosed in an embodiment of the present application.

[0064] Figure 3 A schematic diagram of the arrangement and connection of storage units in a storage array.

[0065] Figure 4 Schematic diagram of data storage distribution in a storage array according to an embodiment of the present application.

[0066] Figure 5a It is a schematic diagram of signals at the input and output ends of the error correction code operation module according to an embodiment of the present application.

[0067] Figure 5b It is a schematic diagram of the setting of the error correction code during the programming process according to the embodiment of the present application.

[0068] Figure 6 The flowchart of the error correction code operation module according to the embodiment of the present application when performing a programming operation.

[0069] Figure 7a and Figure 7b They are respectively bus signal timing diagrams during programming and reading according to the embodiments of the present application.

[0070] Figure 8 It is a schematic diagram of storage locations and ECC generation of a storage array according to an embodiment of the present application.

[0071] Fig. 9 The flowchart of the error correction code operation module according to the embodiment of the present application when performing a read operation.

[0072] Fig.10The figure is a diagram showing the meaning of the flag bit of the stacking error correction code during a read operation according to an embodiment of the present application.

[0073] Fig.11 It is a comparison chart of the input and output signals of the error correction code operation module under programming and reading operations respectively according to the embodiment of the present application. DETAILED DESCRIPTION

[0074] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0075] The terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "one", "one" and "item" used herein are also intended to include plural numbers. It should also be understood that the terms "include" and / or "comprise" used herein specify the existence of stated features, integers, steps, operations, units and / or components, without excluding the existence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0076] Figure 1 A schematic block diagram of an exemplary electronic system 100 having a storage system 110 according to some embodiments of the present application is shown. The electronic system 100 may be, for example, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0077] like Figure 1 As shown, the electronic system 100 may include at least a storage system 110 and a host 120. The storage system 110 has a controller 111 and one or more memories 112. The host 120 may be a processor (e.g., a central processing unit, CPU) or a system on a chip (SoC) (e.g., an application processor, AP) of an electronic device. Specifically, the host 120 may be configured to send data to the memory 112 or receive data from the memory 112.

[0078] According to some embodiments, the controller 111 is coupled to the memory 112 and the host 120, and is configured to control the memory 112. Further, the controller 111 can manage the data stored in the memory 112 and communicate with the host 120. In some embodiments, the controller 111 is designed to control the memory used in electronic devices such as personal computers, digital cameras, mobile phones, etc., or a data or program storage device in a mobile device such as a smart phone, a tablet computer, a laptop computer, etc.

[0079] The controller 111 may be configured to control the operation of the memory 112, such as a read operation (Read), an erase operation (Erase), and a program operation (Program). The controller 111 may also be configured to manage various functions related to data stored or to be stored in the memory 112, such as but not limited to bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 111 is also configured to process error correction codes (ECC) related to data read from or written to the memory 112. In some embodiments, the controller 111 may also be configured to perform any other suitable functions, such as formatting the memory 112.

[0080] The controller 111 may communicate with an external device (e.g., the host 120) according to a specific communication protocol. For example, the controller 111 may communicate with an external device through at least one of various interface protocols, and the interface protocol may be, for example, a universal serial bus (USB) protocol, a multimedia (Multi Media Card, MMC) protocol, a peripheral component interconnect (Peripheral Component Interconnect, PCI) protocol, a high-speed PCI (Peripheral Component Interconnect Express, PCI-E) protocol, an advanced technology attachment (Advanced Technology Attachment, ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (Small Computer System Interface, SCSI) protocol, an enhanced small disk interface (Enhanced Small Device Interface, ESDI) protocol, an integrated drive electronics (Integrated Drive Electronics, IDE) protocol, and a FireWire protocol.

[0081] Figure 1The memory used can be various types of memory, including but not limited to EPROM, DRAM, NAND flash memory, parallel NOR flash memory, serial (SPI) NOR flash memory, PCRAM, FRAM, etc. Taking the comparison between EPROM and SPI NOR flash (SPINOR flash memory) as an example, EPROM usually uses IIC serial bus, which is low speed, single-duplex, and the communication rate is generally hundreds of KHz. SPI Flash uses SPI bus, which is high speed, full-duplex, and the communication rate is generally hundreds of MHz. SPI Flash belongs to Flash ROM flash memory. Compared with EPROM, it has faster reading and writing speed, and SPI Flash is usually used to store frequently read data, such as font files or program codes.

[0082] In some embodiments, the minimum unit of SPI Flash erasure is a sector. When writing data to a certain address, first read the data at this address to see if it is 0xFF. If it is not 0xFF, then the data writing fails. Therefore, the usual write operation is to directly erase the sector where the address is located before writing to a certain address, and then write the data. Of course, if all the contents of this sector are 0xFF, there is no need to erase it and it can be written directly. The capacity of SPI Flash is usually in MB level, such as 2MB to 512MB, or multiple SPI flashes are combined into a memory chip with a capacity of GB level. As for the comparison of other types of memory, I will not explain them one by one here.

[0083] In some memories (especially NAND flash memory), in order to further improve reliability, verification technology / functions (such as error correction code, ECC, error correction code) have become a necessary function. Common configurations include using single-bit correction SEC (Single Error Correction) or single-bit correction-double error detection SEC-DED (Single Error Correction-Double Error Detection) to perform data error correction. SEC-DED has the function of correcting one bit of data or detecting two bits of error. Common SEC-DED implementations include Hamming code and Hsiao code. Various ECC methods are widely used and will not be described in detail here.

[0084] However, the ECC operation of current memories is usually performed through a controller set outside the memory to perform programming and read and write error correction. Such a design usually makes signal and data transmission complicated, which not only increases the difficulty of system design, but also may affect the reliability of data.

[0085] Therefore, an embodiment of the present application provides a memory, the memory comprising: a memory array, the memory array comprising a data storage block for storing data and an error correction code storage block for storing an error correction code; and a peripheral circuit, the peripheral circuit comprising an error correction code operation module for performing a data error correction operation on the data associated with the data storage block, and the error correction code associated with the data error correction operation is stored in the error correction code storage block. Further, in some embodiments, the memory is a serial interface flash memory.

[0086] Specifically, Figure 2 As shown, Figure 2 The system block diagram of the memory disclosed in the embodiment of the present application using flash memory (especially SPI flash) as an example is shown. In addition, in order to facilitate the explanation of the technical concept of the present application, although only SPI flash is used as an example to represent the aforementioned various memories, it should be understood that the application scope of the technology disclosed in the present application is not limited to SPI flash, but can also be parallel NOR flash and other types of memories.

[0087] like Figure 2 As shown, the memory 10 includes a storage array 10a and a peripheral circuit 10b. The peripheral circuit 10b may include at least a control logic unit 11, a status register 12, a high voltage generator 13, a page address latch / counter 14, a byte address latch / counter 15, a write protection logic unit / row decoder 16, a column decoder / page buffer / sense amplifier 17, an ECC operation module 18, and various data buses IO3, CS#, SI, SO, etc. It should be understood that in some examples, the peripheral circuit 10b may also include other peripheral circuits not shown in FIG. Figure 2 Other circuits shown in FIG.

[0088] The storage array 10a includes a general data storage block 210 and an ECC storage block 220. The data storage block 210 is used to store general data, while the ECC storage block 220 is used to store an error correction code (ECC). The ECC storage block can be a special address block set according to each actual storage block or each storage page in the storage array 10a, and can be set in an extended position in each storage page or a storage stack of a specific size to store the error correction code (ECC) associated with the data error correction operation in the error correction code storage block.

[0089] Specifically, Figure 3 As shown, Figure 3 The configuration of the data storage block 210 and the ECC storage block 220 in the storage array 10a can be as follows: Figure 3The device includes memory cells 211 arranged in a matrix, and word lines WL 212 and bit lines BL 213 respectively connecting the memory cells 211 in a first direction and a second direction. The first direction and the second direction are usually perpendicular to each other.

[0090] Further, each memory cell 211 is provided in the form of a NOR flash array. Each memory cell 211 can maintain a continuous analog value, such as a voltage or a charge, which depends on the number of electrons captured by each memory cell 211 in the corresponding area. In some embodiments, each memory cell 211 may include a gate layer, and a channel structure composed of a tunneling insulating layer, a charge storage layer, a blocking insulating layer, and a polysilicon layer as a channel. The memory cell 211 may be a floating gate type memory cell including a floating gate transistor, or a charge trap type memory cell including a charge trap transistor.

[0091] In some embodiments, each storage cell 211 may be a single level cell (SLC), wherein the single level cell has two levels of threshold states, and therefore, each single level cell may store one bit (or referred to as "bit") of data, for example, the first level threshold state "0" may correspond to the first voltage range, and the second level threshold state "1" may correspond to the second voltage range. In other embodiments, each storage cell 211 may be a multi-level cell capable of storing more than one bit of data in more than two levels of multi-level threshold states, for example, each storage cell 211 may be a multi-level cell (MLC) capable of storing two bits of data, or a triple level cell (TLC) capable of storing three bits of data, or a quad level cell (QLC) capable of storing four bits of data. One of the multi-level threshold states of the storage cell 211 is an erased state. However, in the ECC storage block 220, each storage unit 211 is usually a single-level cell (SLC), but it can also adopt multi-level storage in accordance with the number of levels of the data storage block 210. In the embodiment of the present application, for ease of description, only a single-level cell will be used as an example.

[0092] In some embodiments, the error correction code disclosed according to the embodiments of the present application includes multiple stack error correction codes, one of the stack error correction codes corresponds to a storage stack (chunk), and each of the storage stacks is a location in the data storage block with a specific start address and end address for storing the data of a specific number of bytes.

[0093] Specifically, Figure 4 Further disclosed is a schematic diagram of data storage distribution in the storage array 10a according to some embodiments of the present application. Figure 4 As shown, the data storage location in the data storage block 210 is divided into a plurality of storage chunks 210a[N] according to address settings. The storage chunks 210a[N] may be 210a[0]-210a[N], where N is an integer greater than or equal to zero.

[0094] exist Figure 4 In order to avoid complexity, only one storage stack is labeled 210a, and the other storage stacks are parallel to 210a. In the following description, only 210a is used to represent one storage stack. Each storage stack 210a[N] has a specific first address and last address in the data storage block 210, and is used to store the data of a specific number of bytes. Figure 4 In the example shown, each storage heap 210a is set to 16 bytes. However, it should be understood that the size of each storage heap can be changed and is not limited to this number of bytes.

[0095] In some embodiments, the number of bytes of a storage stack 210a may correspond to the number of bytes detected by a detection amplifier 17 each time, so as to match the hardware design of the memory.

[0096] The error correction code ECC includes a plurality of sub-stack error correction codes ECC[N], each of which also has an error correction code storage position 220a corresponding to each data storage stack 210a. Therefore, one of the sub-stack error correction codes ECC[N] corresponds to one storage stack 210a[N] and also corresponds to one error correction code storage position 220a. Figure 4 In order to avoid complexity, only one error correction code storage position is marked with the label 220a, and the other error correction code storage positions are parallel to the position shown in 220a.

[0097] The above is a description of the storage array 10a disclosed in the embodiment of the present application. Figure 2 The peripheral circuit 10b will be further described.

[0098] First, the control logic unit 11 can be coupled with each circuit in the peripheral circuit 10b as described above (e.g., the status register 12, the high voltage generator 13, the page address latch / counter 14, the byte address latch / counter 15, the write protection logic unit / row decoder 16, the column decoder / page buffer / sense amplifier 17, the ECC operation module 18, and various data buses IO3, CS#, SI, SO), and control the operation of each circuit. In the SPI NOR flash, the control logic unit 11 is particularly a serial control logic unit.

[0099] The control logic unit 11 can also be coupled to an interface (not shown) externally, and the interface receives signals IO3, CS#, SI, SO, etc. from various data buses. The interface also acts as a control buffer to perform buffering from Figure 1 The controller receives the control command and relays the command to the control logic unit 11, and performs buffering of status information received from the control logic unit 11 and relays the command to the controller.

[0100] Furthermore, the interface shown can also be coupled to the write protection logic unit / row decoder 16, the column decoder / page buffer / sense amplifier 17 via various data buses, and act as a data I / O (Input / Output) interface and a data buffer to perform operations of buffering data and relaying the data to the storage array 10a, and to perform operations of relaying or buffering data from the storage array 10a. Among them, the aforementioned various operations on the data storage array 210 in the storage array 10a all include operations on the ECC storage block 220 in the storage array 10a.

[0101] The status register 12 is coupled to the control logic unit 11 and may include at least a status register, a command register and an address register to store status information, a command operation code (OP code) and a command address for controlling the operation of each of the above circuits.

[0102] The voltage generator 13 can be configured to be controlled by the control logic unit 11 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verification voltage, erase voltage, etc.), bit line voltages and source line voltages to be supplied to the memory array 10a.

[0103] The page address latch / counter 14 and the byte address latch / counter 15 are used to latch the data of a data page in conjunction with the received address each time programming is performed, so as to program the page data into the storage array 10a in sequence, and calculate the address of each programming and the number of programming times until a data page is completed and stored and then the next page is switched.

[0104] The write protection logic unit / row decoder 16 may be configured to be controlled by the control logic unit 11 to select / deselect the memory cells 211 in the memory array 10a. The write protection logic unit / row decoder 16 may also be configured to drive the word lines WL using the word line voltage generated from the voltage generator 13. As described in detail below, the write protection logic unit / row decoder 16 is configured to perform operations such as programming, erasing, and verifying on the memory cells 211 coupled to one or more selected word lines WL.

[0105] The column decoder / page buffer / sense amplifier 17 can be configured to read data from the memory array 10a and program (also referred to as "write") data to the memory array 10a according to the control signal from the control logic unit 11. Specifically, in one example, the column decoder / page buffer / sense amplifier 17 can store data to be programmed into a memory page of the memory array 10a, for example, 256 bytes. In another example, the column decoder / page buffer / sense amplifier 17 can perform a programming verification operation (Verify) to ensure that the data has been correctly programmed into the memory cell 211 coupled to the selected word line WL. In yet another example, the column decoder / page buffer / sense amplifier 17 can also perform an operation of sensing a low-power signal from the bit line BL representing the data stored in the memory cell 211, and amplify the small voltage swing of the low-power signal to a recognizable logic level in a read operation.

[0106] The column decoder / page buffer / sense amplifier 17 may be configured to be controlled by the control logic unit 11 and select one or more memory cells 211 to be programmed or read by applying a bit line voltage generated from the voltage generator 13 .

[0107] The ECC operation module 18 is used for performing a data error correction operation on the data associated with the data storage block 210 , and the error correction code (ECC) associated with the data error correction operation is stored in the ECC storage block 220 .

[0108] The error correction code operation module 18 is also used to perform programming error correction operations during programming operations. The programming error correction operation receives the stack data from the column decoder / page buffer / detection amplifier (hereinafter referred to as: page buffer) 17, and corresponds to the stack data of the storage stack 210a, and determines the stack error correction code ECC[N] of the stack data, and outputs the stack data and the stack error correction code ECC[N].

[0109] The error correction code operation module 18 is also used to perform a read error correction operation when reading the data. The read error correction operation receives the stack data and the stack error correction code ECC[N] corresponding to the storage stack 210a from the data storage block 210, and outputs the processed stack data according to the stack error correction code ECC[N].

[0110] The following will further describe the ECC operation module 18 in conjunction with the programming and reading operations.

[0111] First, the error correction code operation module 18 receives the stack data Bytes[N] corresponding to the size of the storage stack 210a in units of the storage stack 210a, and further determines whether to generate a stack error correction code ECC[N]. The stack error correction code ECC[N] includes an error correction code bit group ECC<8:0> and a flag bit group ECC<10:9>, wherein the error correction code bit group ECC<8:0> includes one of a stack error correction code (ECC-CODE) and a stack error correction preset code (1FFh) corresponding to the stack data, and the flag bit group ECC<10:9> is used to indicate the state attribute of the stack error correction code ECC[N], especially the valid state in some embodiments.

[0112] Specifically, Figure 5a As shown, Figure 5a The signal diagram of the input and output of the error correction code operation module. At the input of the error correction code operation module 18, an ECC EN signal representing whether the ECC function is activated, an ECC call signal ECC CAL, a signal PBOUT<127:0> from the page buffer 17, a signal SA<127:0> from the detection amplifier 17, and / or an error correction code detection signal ECCSA<10:0> are received according to the programming operation or the read operation. And the processed data signal SAP<127:0> and the processed error correction code signal ECCSAP<10:0> are output. The so-called "processed" will be explained in the following text in conjunction with the operation of various embodiments.

[0113] The signal PBOUT<127:0> from the page buffer 17 and the signal SA<127:0> from the sense amplifier 17 are equivalent to receiving the divided data Bytes[N] corresponding to the size of the storage stack 210a. During programming operation, these data come from the signal PBOUT<127:0> input to the page buffer 17 from the outside, and during reading operation, these data come from the signal SA<127:0> output from the storage array to the sense amplifier 17. Since a byte has 8 bits, 16 bytes have 128 bits, which are represented by <127:0>.

[0114] Further Figure 5b As shown, Figure 5bThe figure shows a schematic diagram of the setting of the error correction code during the programming process, and the right side of the table in the figure shows the stacked error correction code ECC[N] including the error correction code bit group ECC[8:0] and the flag bit group ECC[10:9] (i.e., ECCSAP <10> and ECCSAP <9> ). The error correction code bit group ECC[8:0] includes one of the stack error correction code ECC-CODE and the stack error correction preset code 1FFh corresponding to the stack data Bytes[N], and the flag bit group ECC[10:9] is used to indicate the valid status attribute of the stack error correction code ECC[N]. Moreover, the stack error correction code ECC[N] includes two types: ECCSA<10:0> and ECCSAP<10:0>, wherein ECCSA<10:0> represents the stack error correction code originally set in the error correction code storage block or to be input into the error correction code operation module 18, and ECCSAP<10:0> represents the processed stack error correction code that has been processed by the error correction code operation module 18.

[0115] Furthermore, the aforementioned stack error correction code ECC-CODE represents the calculated error correction code corresponding to the stack data Bytes[N*16:N*16+15], and the stack error correction preset code 1FFh represents the preset value originally set in the error correction code storage block. Figure 5b As shown in the table, when the error correction code storage location 220a has not been stored with the error correction code, ECCSA<10; 9; 8:0> are respectively <1; 1; 1FFh>, that is, 7FFh. When the error correction code storage location 220a has been stored with the error correction code, ECCSA<10; 9; 8:0> are respectively <1; 0; ECC-CODE>, that is, 10-CODE. When the error correction code in the error correction code storage location 220a is invalid, ECCSA<10; 9; 8:0> are respectively <0; 0; 1FFh>, that is, 00-1FFh. The specific relative relationship will be further described in the following description of the programming steps.

[0116] According to some embodiments of the present application, the memory 10 also includes a page buffer 17, and the error correction code operation module 18 is also used to perform a programming error correction operation during a programming operation. The programming error correction operation receives the stack data PBOUT<127:0> from the page buffer 17 and corresponding to the storage stack 210a (because it is a programming state, PBOUT<127:0> is used to replace the aforementioned Bytes[N] to represent the stack data), and determines the stack error correction code ECCSAP<10:0> of the stack data PBOUT<127:0>, and outputs the stack data SAP<127:0> and the stack error correction code ECCSAP<10:0> that have been processed with the error correction code.

[0117] In some embodiments, the error correction code operation module 18 is also used to perform a first judgment, and the first judgment is used to determine whether the first address and the tail address of the stack data PBOUT<127:0> cover the stack head address and the stack tail address of the storage stack 210a, and the coverage includes that the first address and the tail address of the stack data PBOUT<127:0> are respectively the same as the stack head address and the stack tail address of the storage stack 210a. If the result of the first judgment is yes, the stack error correction code ECC-CODE is generated, and the error correction code bit group ECCSAP<8:0> is set to the stack error correction code ECC-CODE, and the flag bit group ECCSAP<10:9> is set to the presence of the stack error correction code <10> and storing the stacked error correction code and the flag bit group into the error correction code storage block or position 220a.

[0118] In some embodiments, if the result of the aforementioned first judgment is no, the stack error correction code ECCSA<10:0> corresponding to the stack data PBOUT<127:0> in the error correction code storage block is not programmed, and the stack error correction code ECCSAP<10:0> maintains the stack error correction preset code 7FFh. In some embodiments, the error correction code operation module is also used to perform a second judgment, and the second judgment is used to determine whether the flag bit group ECCSA<10:9> in the pile error correction code corresponding to the pile data PBOUT<127:0> indicates that the corresponding pile error correction code ECC-CODE already exists. If the result of the second judgment is yes, the error correction code bit group ECCSAP<8:0> in the pile error correction code corresponding to the pile data PBOUT<127:0> is not programmed (1FF), and the flag bit group ECCSAP<10:9> is programmed to indicate that the pile error correction code is invalid ECCSAP<10:9=0:0>, that is, the error correction code is not enabled.

[0119] In some embodiments, the error correction code operation module is further used to perform a third judgment, and the third judgment is used to judge whether the original stored data SA<127:0> in the storage stack 210a is not all preset null values ​​(FFh). If the result of the third judgment is yes, that is, not all null values, the error correction code bit group ECCSAP<8:0> in the sub-stack error correction code ECCSA<10:0> corresponding to the storage stack 210a is not programmed (1FF), and the flag bit group ECCSAP<10:9> is programmed to indicate that the sub-stack error correction code is invalid ECCSAP<10:9=0:0>, that is, the error correction code is not enabled. The so-called "preset null value" here refers to the state in which the storage unit is not programmed.

[0120] The above three judgments, in simple terms, mean that the error correction code operation module 18 will enable the partitioned data error correction code ECC[N] when the partitioned data PBOUT<127:0> fills up one of the storage stacks 210a, otherwise the partitioned data error correction code will be disabled (not enabled). The full writing is performed based on the first judgment, that is, judging whether the first address and the last address of the partitioned data PBOUT<127:0> cover the first address and the last address of the storage stack 210a. If the judgment result is yes, it is full. The error correction code operation module 18 is also used to disable the partitioned data error correction code ECC[N] when the partitioned data error correction code ECC-CODE already exists (that is, the aforementioned second judgment), or when the original data stored in the storage stack 210a is not all preset null values ​​(FFh) (that is, the aforementioned third judgment).

[0121] In some embodiments, the error correction code operation module is also used to receive the starting address and the ending address of the data to be stored from the page buffer 17 during the programming operation, and determine whether the tail address of the stack data PBOUT<127:0> has reached the ending address. If it has not reached the ending address, the next stack data is received from the page buffer 17, and the programming error correction operation is repeated.

[0122] For details, please refer to Figure 6 The various actions of the error correction code operation module 18 described above using programming as an example. Figure 6 The flowchart of the error correction code operation module 18 according to the embodiment of the present application when performing a programming operation is shown.

[0123] First, in step S100, a program command 02h with an ECC operation, a 24-bit address (N*16), and a data byte ([N*16:M*16+15, 0≦N≦M]) are received, and the data is stored in the page buffer 17. For specific signal operations, please refer to Figure 7a , wherein the signal CS# is used to enable the memory chip, the signal SCLK is a clock signal, and the signal SI is a serial input. In the serial input SI signal, the aforementioned command 02h, 24-bit address, and data bytes 1 to 256 are sequentially input according to the clock signal.

[0124] Next, programming with ECC operations begins, including:

[0125] Step S140: Set the starting address [N*16] and the ending address of the input data;

[0126] Step S150: read out 16 bytes each time, that is, a divided data PBOUT<127:0>;

[0127] Step S160: Calculate the ECC code for the stacked data PBOUT<127:0>, set the processed stacked data SAP<127:0> to PBOUT<127:0>, and output ECCSA<10:0> and SAP<127:0>; the so-called "processed" here means that the relevant judgment or operation of the error correction code has been performed. Incidentally, the ECC calculation can be performed in this step, or it can be performed when necessary after the first, second, and third judgments are made below. This is just an example;

[0128] Step S170: Perform the aforementioned first judgment to determine whether the starting address of the processed partitioned data SAP<127:0> covers the starting address of the storage stack 210a, that is, whether the starting address of the processed partitioned data SAP<127:0> is the same as the starting address of the storage stack 210a, and whether the number of program bytes of the processed partitioned data SAP<127:0> is 16, that is, whether the tail address is also the same and covers the tail address of the storage stack 210a; if the result of the first judgment is no, then let the partitioned error correction code ECCSAP<10:0> maintain the partitioned error correction preset code 7FFh;

[0129] Step S171: If the result of the first judgment is yes, the second judgment or the third judgment is performed; the second judgment is used to judge whether the flag bit group ECCSA<10:9> in the sub-heap error correction code corresponding to the sub-heap data PBOUT<127:0> indicates that the corresponding sub-heap error correction code ECC-CODE already exists; the third judgment is used to judge whether the original storage data SA[127:0] originally stored in the storage stack 210a is not all preset null values ​​(FFh);

[0130] Step S180: storing SAP<127:0> in the data storage block 210, and storing ECCSAP<10:0> in the error correction code (ECC) storage block 220; and,

[0131] Step S190: Receive the starting address and the ending address of the data to be stored from the page buffer 17, and determine whether the tail address of the divided data PBOUT<127:0> has reached the ending address. If it has not reached the ending address, receive the next divided data PBOUT<127:0> from the page buffer 17, and repeat the programming error correction operation steps S160 to S180.

[0132] In step S171, if the result of the second judgment or the third judgment is yes, the error correction code bit group ECCSAP<8:0> in the stack error correction code corresponding to the stack data PBOUT<127:0> is not programmed (1FF, 1FF means that <8:0> is not programmed), and the flag bit group ECCSAP<10:9> is programmed to indicate that the stack error correction code is invalid ECCSAP<10:9=0:0>.

[0133] If the result of the second judgment or the third judgment is no, the error correction code bit group ECCSAP<8:0> is set to the stack error correction code ECC-CODE, and the flag bit group ECCSAP<10:9> is set to the presence of the stack error correction code

[10] and output ECCSAP<10:0>.

[0134] Specifically, regarding the first, second, and third judgments, in addition to the above descriptions, you can also refer to Figure 5b Description of the table shown. Figure 5b The changes of the stacking error correction code under the first, second, and third judgments are clearly listed. That is, the first row below the title row represents the situation where the first judgment is "no"; the second row below the title row represents the situation where the first judgment is "yes"; the third row below the title row represents the situation where the first judgment is "yes" but the second and third judgments are "yes".

[0135] According to the above programming process, an example is given below to illustrate how to generate ECC according to the storage location. Figure 8 Schematic diagram of storage array storage location and ECC generation according to an embodiment of the present application. Figure 8 As shown, it shows how to store a page data with a starting address (first address) of 13h and an ending address (last address) of 34h in a data storage block 210 with all null values ​​and an error correction code storage block 220. Among them, since the address of a storage stack is 0h~15h, that is, the stack head address is N*16, the stack tail address is N*16+15, and N is an integer greater than or equal to 0. Therefore, this data page needs to exist across three storage stacks, so there are three sub-stack data, namely bytes [13:15], bytes [16:31] and bytes [32:34]. Among them, the second sub-stack data [2*16:2*16+15] meets the result of the first judgment of the aforementioned step S170, that is, the result is "yes", so in addition to outputting SAP<127:0>, ECCSAP<10:0>=<1:0:ECC-CODE> is also output.

[0136] However, the first divided data Bytes[13:15] and the third divided data Bytes[32:34] do not meet the first judgment in step S170, that is, the judgment result is "No". Therefore, in addition to outputting the first and third divided data SAP<127:0>, ECC-CODE is not output, but ECCSAP<10:0> is maintained at <7FF>.

[0137] On the other hand, according to some embodiments of the present application, the error correction code operation module 18 is also used to perform a read error correction operation when reading the data, and the read error correction operation receives the stack data SA<127:0> corresponding to the storage stack 210a in the data storage block 210 (because it is a read state, SA<127:0> is used to replace the aforementioned Bytes[N] to represent the stack data) and the stack error correction code ECC[N], and outputs the processed stack data SAP<127:0> according to the stack error correction code ECC[N].

[0138] In some embodiments, the error correction code operation module 18 is also used to determine whether it is necessary to perform data error correction on the stack data SA<127:0> based on the flag bit group ECCSA<10:9> in the stack error correction code ECC[N]. If necessary, the corrected stack data is used as the processed stack data SAP<127:0>; if not necessary, the received stack data SA<127:0> is directly used as the processed stack data SAP<127:0>.

[0139] In some embodiments, the error correction code operation module 18 is further used to calculate the pile data SA<127:0>, and then output the corrected pile data as the processed pile data SAP<127:0> based on the pile error correction code ECC-CHECK and the pile error correction code ECC-CODE.

[0140] In some embodiments, the error correction code operation module 18 is also used to receive the starting address and the ending address of the data to be read during the read operation, and to determine whether the tail address of the stacked data SA<127:0> has reached the ending address. If it has not reached the ending address, the next stacked data SA<127:0> is received from the data storage block 210, and the read error correction operation is repeated.

[0141] For details, please refer to Fig. 9 The above-mentioned actions are described. Fig. 9The flowchart of the error correction code operation module 18 according to the embodiment of the present application is shown. First, in step S200, a read command with an ECC operation, such as 0Bh, a 24-bit address (N*16), is received, and then the reading with the ECC operation is started. The reading steps include:

[0142] Step S250: Detect the stacked data [N*16:N*16+15] and the stacked error correction code ECC[N] through the detection amplifier 17 to obtain the stacked data SA<127:0> and the stacked error correction code ECCSA<10:0>; and,

[0143] Step S260: The ECC check code is calculated for the stacked data SA<127:0> by the error correction code operation module 18, and the data is corrected by the ECC check code and the stacked error correction code ECCSA<10:0>, and SAP<127:0> is output. Incidentally, the data correction mentioned here can be the example method, or the ECC check code can be not calculated, and the stacked error correction code ECCSA<10:0> can be used to correct the data directly, or any other feasible correction method can be used to obtain the processed stacked data SAP<127:0>. Therefore, the correction example shown here is only an example and is not intended to limit the correction method.

[0144] Specifically, refer to Fig.10 , Fig.10 This is a chart showing the meaning of the flag bit of the stacking error correction code during the read operation according to the embodiment of the present application. Whether to perform error correction on the stacking data SA<127:0> will also be different depending on the value of the flag bit group ECCSAP<10:9> in the stacking error correction code ECCSA<10:0> corresponding to the stacking data SA<127:0>, including Fig.10 Three scenarios in the diagram shown:

[0145] The first type: ECCSAP<10:9>=11: When the flag bit value is detected to be 11, the ECC EN signal of the error correction code operation module 18 is set to No, and thus no ECC error correction check is performed, that is, correction is disabled, and the stack data SA<127:0> is directly output;

[0146] The second type: ECCSAP<10:9>=10: the flag bit value is detected to be 10, indicating that the error correction code exists, and the ECC EN signal of the error correction code operation module 18 is set to Yes, that is, the correction is enabled, so the aforementioned ECC error correction check is performed, and the processed stack data SAP<127:0> is output;

[0147] The third type: ECCSAP<10:9>=00: The flag bit value is detected to be 00, which means that the error correction code is invalid, and the ECC EN signal of the error correction code operation module 18 is set to No, so no ECC error correction check is performed, that is, correction is disabled, and the stack data SA<127:0> is directly output.

[0148] Furthermore, in step S260, the data SA<127:0> is stacked and the end address of the read data is checked. If the end address has not been reached, the process proceeds to step S280 to increase the address and perform the next round of stacked data reading.

[0149] In addition, the processed stack data SAP<127:0> is output to the latch in step S290 and then output via the interface and various data buses.

[0150] The entire read timing and specific bus Figure 7b As shown, Figure 7b Displays the read timing and specific bus signals. Figure 7b As shown, in step S200, a read command with an ECC operation, such as 0Bh and a 24-bit address (N*16), is received via SI, and after waiting for a period of time through a dummy byte, a data byte ([N*16:M*16+15, 0≦N≦M]) can be serially output via SO. Among them, the signal CS# is used to enable the memory chip, the signal SCLK is a clock signal, and the signal SI is a serial input. In the serial input SI signal, the aforementioned command 02h, the 24-bit address, and the dummy data byte are sequentially input according to the clock signal; and then the read data is output through the SO pin.

[0151] Summarizing the aforementioned programming and reading operations, and combining the aforementioned ECC EN signal, Fig.11 Show Figure 5a The output / input signals of the error correction code operation module 18 are shown as difference and comparison diagrams under programming and reading operations, respectively.

[0152] like Fig.11 As shown, depending on the signal ECC EN, the error correction code operation module 18 is enabled (H) or not enabled (L). During programming, the input is all the stack data PBOUT<127:0>, and there is no stack error correction code ECCSA<10:0> in the storage array. However, if the error correction code operation module 18 is enabled (H), the stack error correction code ECCSA<10:0> and the stack data PBOUT<127:0> will be output; if the error correction code operation module 18 is not enabled (L), the stack error correction code ECCSA<10:0> will maintain the preset 7FFh during output, and the stack data will still be PBOUT<127:0>.

[0153] When reading, the input signal includes the stack data SA<127:0> and the stack error correction code ECCSA<10:0>. However, if the error correction code operation module 18 is enabled (H), the output will have the stack error correction code ECCSAP<10:0> and the stack data SAP<127:0>; if the error correction code operation module 18 is not enabled (L), the stack error correction code ECCSA<10:0> is not used during output, and the stack data is still SA<127:0>.

[0154] According to the memory with data error correction operation provided by the above embodiments of the present application, by setting a data storage block for storing data and an error correction code storage block for storing error correction codes inside the storage array, and setting an internal error correction code operation module in the peripheral circuit to perform a data error correction operation on the data associated with the data storage block, and the error correction code associated with the data error correction operation is stored in the error correction code storage block, the bit error rate during the memory operation can be reduced, and the reliability of the memory can be improved.

[0155] Furthermore, according to an embodiment of the present application, a memory operation method with data error correction operation is also provided. The memory operation method with data error correction operation is further described below.

[0156] Also refer to the above Figures 2 to 10 The memory operation method with data error correction operation disclosed in the embodiment of the present application includes providing, in particular, Figure 2 The error correction code storage block 220 and the error correction code operation module 18 are shown, and a method is provided as follows Figure 6 A programming method with data error correction operation as shown, and a Fig. 9 The specific details and descriptions of the reading method with data error correction operation shown have been described above, so the following only focuses on the storage operation method, and no longer repeats the specific details as mentioned above. For the relevant specific details of each key point, please refer to the corresponding description above.

[0157] According to the memory operation method provided in the embodiment of the present application, the memory 10 includes a memory array 10a and a peripheral circuit 10b, and the operation method includes:

[0158] A data storage block 210 for storing data and an error correction code storage block 220 for storing error correction codes are provided in the storage array 10a; and

[0159] An error correction code operation module 18 is set in the peripheral circuit 10b, and the error correction code operation module 18 performs a data error correction operation on the data associated with the data storage block 210, and the error correction code associated with the data error correction operation is stored in the error correction code storage block 220.

[0160] In some embodiments, the operation method includes setting the storage array 10a and the error correction code operation module 18 in a serial interface flash memory. In some embodiments, the operation also includes configuring the error correction code into a plurality of sub-heap error correction codes ECC[N], and making one of the sub-heap error correction codes correspond to a storage chunk 210a, and each storage chunk 210a is a location in the data storage block 210 with a specific head address and tail address for storing a specific number of bytes of the data.

[0161] In some embodiments, the operating method further includes:

[0162] The error correction code operation module 18 is configured to receive the divided heap data Bytes[N] corresponding to the storage heap size in units of the storage heap 210a; and

[0163] The pile error correction code ECC[N] is configured to include an error correction code bit group ECC<8:0> and a flag bit group ECC<10:9>, and the error correction code bit group is configured to correspond to one of the pile error correction code (ECC-CODE) and the pile error correction preset code (1FFh) of the pile data, and the flag bit group ECC<10:9> is configured to indicate the status attribute of the pile error correction code.

[0164] In some embodiments, the memory further includes a page buffer 17, and the operation method further includes a programming error correction operation, and the programming error correction operation includes:

[0165] Receive the divided data PBOUT<127:0> corresponding to the storage pile 210a from the page buffer 17 through the error correction code operation module 18; and

[0166] The stacking error correction code ECCSAP<10:0> of the stacking data PBOUT<127:0> is determined, and the stacking data SAP<127:0> and the stacking error correction code ECCSAP<10:0> are output.

[0167] In some embodiments, the programming error correction operation further includes:

[0168] The first judgment is performed by the error correction code operation module 18, and the first judgment is used to determine whether the first address and the tail address of the divided pile data PBOUT<127:0> cover the pile head address and the pile tail address of the storage pile 210a; if the result of the first judgment is yes, the divided pile error correction code ECC-CODE is generated, and the error correction code bit group ECCSAP<8:0> is set to the divided pile error correction code ECC-CODE, and the flag bit group ECCSAP<10:9> is set to the existence of the divided pile error correction code <10> ;as well as,

[0169] The stacked error correction code and the flag bit group are stored in the error correction code storage block or location 220a.

[0170] In some embodiments, the programming error correction operation further includes:

[0171] If the result of the first judgment is no, the stack error correction code ECCSA<10:0> corresponding to the stack data PBOUT<127:0> in the error correction code storage block 220a is not programmed, and the stack error correction code ECCSAP<10:0> maintains the stack error correction preset code 7FFh.

[0172] In some embodiments, the programming error correction operation further includes:

[0173] A second judgment is performed by the error correction code operation module, and the second judgment is used to judge whether the flag bit group ECCSA<10:9> in the pile error correction code corresponding to the pile data PBOUT<127:0> indicates that the corresponding pile error correction code ECC-CODE already exists; if the result of the second judgment is yes, the error correction code bit group ECCSAP<8:0> in the pile error correction code corresponding to the pile data PBOUT<127:0> is not programmed (1FFh), and the flag bit group ECCSAP<10:9> is programmed to indicate that the pile error correction code is invalid ECCSAP<10:9=0:0>.

[0174] In some embodiments, the programming error correction operation further includes:

[0175] A third judgment is performed by the error correction code operation module, and the third judgment is used to determine whether the original stored data SA<127:0> originally stored in the storage stack 210a is not all preset null values. If the result of the third judgment is yes, the error correction code bit group ECCSAP<10:9> in the stack error correction code ECCSA<10:0> corresponding to the storage stack 210a is not programmed, and the flag bit group ECCSAP<10:9> is programmed to indicate that the error correction code is invalid ECCSAP<10:9=0:0>.

[0176] In some embodiments, the programming error correction operation further includes:

[0177] The error correction code operation module 18 receives the starting address and the ending address of the data to be stored from the page buffer 17, and determines whether the tail address of the divided data PBOUT<127:0> has reached the ending address; if it has not reached the ending address, the next divided data PBOUT<127:0> is received from the page buffer 17, and the programming error correction operation is repeated.

[0178] The above operation method, in simple terms, is that the error correction code operation module 18 will enable the partitioned data error correction code ECC[N] when the partitioned data PBOUT<127:0> fills up one of the storage stacks 210a, otherwise the partitioned data error correction code will be disabled. The full writing is performed based on the first judgment, that is, judging whether the first address and the last address of the partitioned data PBOUT<127:0> cover the first address and the last address of the storage stack 210a. If so, it is full. The programming error correction operation also includes disabling the partitioned data error correction code ECC[N] when the partitioned data ECC-CODE already exists (that is, the aforementioned second judgment), or when the original data stored in the storage stack 210a is not all preset null values ​​(FFh) (that is, the aforementioned third judgment). In some embodiments, the operation method also includes a read error correction operation, and the read error correction operation includes:

[0179] Receive the stack data SA<127:0> and the stack error correction code ECC[N] corresponding to the storage stack 210a in the data storage block 210 through the error correction code operation module 18; and

[0180] According to the stacking error correction code ECC[N], the processed stacking data SAP<127:0> is output.

[0181] In some embodiments, the read error correction operation further includes:

[0182] In the error correction code operation module 18, it is determined whether it is necessary to perform data error correction on the divided data SA<127:0> according to the flag bit group ECCSA<10:9> in the divided error correction code ECC[N]; and

[0183] If necessary, the corrected sorted data is used as the processed sorted data SAP<127:0>; if not necessary, the received sorted data SA<127:0> is directly used as the processed sorted data SAP<127:0>.

[0184] In some embodiments, the read error correction operation further includes:

[0185] The error correction code operation module 18 calculates the stack error correction check code ECC-CHECK based on the stack data SA<127:0>; and

[0186] According to the stacking error correction check code and the stacking error correction code ECC-CODE, the corrected stacking data SAP<127:0> is output as the processed stacking data.

[0187] In some embodiments, the read error correction operation further includes:

[0188] The error correction code operation module 18 receives the start address and the end address of the data to be read, and determines whether the tail address of the divided data SA<127:0> has reached the end address; and

[0189] If it is determined that the end address has not been reached, the next stack data SA<127:0> is received from the data storage block 210 and the read error correction operation is repeated.

[0190] According to the memory operation method with data error correction operation provided by the above embodiment of the present application, by setting a data storage block for storing data and an error correction code storage block for storing error correction code inside the storage array, and setting an internal error correction code operation module in the peripheral circuit to perform a data error correction operation on the data associated with the data storage block, and the error correction code associated with the data error correction operation is stored in the error correction code storage block, the bit error rate during the memory operation can be reduced, and the reliability of the memory can be improved.

[0191] The above is a detailed introduction to the memory with data error correction operation and the memory operation method provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present application.

Claims

1. A memory, It is characterized in that The memory comprises: A storage array, the storage array comprising a data storage block for storing data and an error correction code storage block for storing an error correction code; and The peripheral circuit includes an error correction code operation module for performing a data error correction operation on the data associated with the data storage block, and the error correction code associated with the data error correction operation is stored in the error correction code storage block.

2. The memory according to claim 1, It is characterized in that The error correction code includes a plurality of chunk error correction codes, one chunk error correction code corresponds to a storage chunk (chunk), each storage chunk is a location in the data storage block having a specific head address and tail address for storing the data of a specific number of bytes.

3. The memory according to claim 2, It is characterized in that The error correction code operation module is also used to receive the pile data corresponding to the size of the storage pile in units of the storage pile, and the pile error correction code includes an error correction code bit group and a flag bit group, the error correction code bit group includes one of a pile error correction correction code and a pile error correction preset code corresponding to the pile data, and the flag bit group is used to indicate the effective status of the pile error correction code.

4. The memory according to claim 3, It is characterized in that The memory also includes a page buffer, and the error correction code operation module is also used to perform a programming error correction operation during a programming operation. The programming error correction operation receives the stack data corresponding to the storage stack from the page buffer, determines the stack error correction code of the stack data, and outputs the stack data and the stack error correction code.

5. The memory according to claim 4, It is characterized in that The error correction code operation module is also used to perform a first judgment, and the first judgment is used to determine whether the first address and the last address of the pile data cover the pile head address and the pile tail address of the storage pile. If the result of the first judgment is yes, the pile error correction code is generated, and the error correction code bit group is set to the pile error correction code, and the flag bit group is set to the presence of the pile error correction code, and the pile error correction code and the flag bit group are stored in the error correction code storage block.

6. The memory according to claim 5, It is characterized in that If the result of the first judgment is no, the pile-by-pile error correction code corresponding to the pile-by-pile data in the error correction code storage block is not programmed, and the pile-by-pile error correction code maintains the pile-by-pile error correction preset code.

7. The memory according to claim 5, It is characterized in that The error correction code operation module is also used to perform a second judgment, and the second judgment is used to determine whether the flag bit group in the pile error correction code corresponding to the pile data indicates that the corresponding pile error correction code already exists. If the result of the second judgment is yes, the error correction code bit group in the pile error correction code corresponding to the pile data is not programmed, and the flag bit group is programmed to indicate that the pile error correction code is invalid.

8. The memory according to claim 5, It is characterized in that The error correction code operation module is also used to perform a third judgment, and the third judgment is used to determine whether the original stored data in the storage stack is not all preset null values. If the result of the third judgment is yes, the error correction code bit group in the stack error correction code corresponding to the storage stack is not programmed, and the flag bit group is programmed to indicate that the stack error correction code is invalid.

9. The memory according to claim 4, It is characterized in that The error correction code operation module is also used to receive the starting address and the ending address of the data to be stored from the page buffer during the programming operation, and to determine whether the tail address of the divided data has reached the ending address. If it has not reached the ending address, the next divided data is received from the page buffer and the programming error correction operation is repeated.

10. The memory according to claim 3, It is characterized in that The error correction code operation module is also used to perform a read error correction operation when reading the data. The read error correction operation receives the heap data and the heap error correction code corresponding to the storage heap from the data storage block, and outputs the processed heap data according to the heap error correction code.

11. The memory according to claim 10, It is characterized in that The error correction code operation module is also used to determine whether it is necessary to perform data error correction on the pile data according to the flag bit group in the pile error correction code. If necessary, the corrected pile data is used as the processed pile data. If not, the received pile data is directly used as the processed pile data.

12. The memory according to claim 11, It is characterized in that The error correction code operation module is further used to calculate a pile-by-pile error correction check code for the pile-by-pile data, and then output the corrected pile-by-pile data as the processed pile-by-pile data according to the pile-by-pile error correction check code and the pile-by-pile error correction code.

13. The memory according to claim 10, It is characterized in that The error correction code operation module is also used to receive the starting address and the ending address of the data to be read during the read operation, and determine whether the tail address of the divided data has reached the ending address. If it has not reached the ending address, the next divided data is received from the data storage block and the read error correction operation is repeated.

14. The memory according to claim 4, It is characterized in that The error correction code operation module is further configured to enable the heap-wise error correction code of the heap-wise data when the heap-wise data fills up one of the storage heaps, and disable the heap-wise error correction code otherwise.

15. The memory according to claim 14, It is characterized in that The writing is performed based on a first judgment, and the first judgment is used to judge whether the first address and the last address of the divided heap data cover the first address and the last address of the storage heap.

16. The memory according to claim 14, It is characterized in that The error correction code operation module is further used to disable the heap-based error correction code when the heap-based error correction code already exists or when the original stored data in the storage heap is not all preset null values.

17. A memory operation method, It is characterized in that The memory includes a storage array and a peripheral circuit, and the operation method includes: A data storage block for storing data and an error correction code storage block for storing error correction codes are arranged in the storage array; and An error correction code operation module is set in the peripheral circuit, and a data error correction operation is performed on the data associated with the data storage block through the error correction code operation module, and the error correction code associated with the data error correction operation is stored in the error correction code storage block.

18. The memory operation method according to claim 17, It is characterized in that The operation also includes configuring the error correction code into a plurality of stack error correction codes, and making one of the stack error correction codes correspond to a storage stack, and each storage stack is a location in the data storage block with a specific head address and tail address for storing a specific number of bytes of the data.

19. The memory operation method according to claim 18, It is characterized in that The operation method further includes: The error correction code operation module is configured to receive the divided heap data corresponding to the size of the storage heap in units of the storage heap; and The pile error correction code is configured to include an error correction code bit group and a flag bit group, and the error correction code bit group is configured to correspond to one of a pile error correction code and a pile error correction preset code of the pile data, and the flag bit group is configured to indicate the valid state of the pile error correction code.

20. The memory operation method according to claim 19, It is characterized in that The memory further includes a page buffer, and the operation method further includes a programming error correction operation, and the programming error correction operation includes: receiving the divided heap data corresponding to the storage heap from the page buffer through the error correction code operation module; and The pile error correction code of the pile data is determined, and the pile data and the pile error correction code are output.

21. The memory operation method according to claim 20, It is characterized in that The programming error correction operation further includes: when the divided pile data fills up one of the storage piles, enabling the divided pile error correction code of the divided pile data, otherwise disabling the divided pile error correction code.

22. The memory operation method according to claim 21, It is characterized in that The writing is performed based on a first judgment, and the first judgment is used to judge whether the first address and the last address of the divided heap data cover the first address and the last address of the storage heap.

23. The memory operation method according to claim 21, It is characterized in that The programming error correction operation further includes: when the stack error correction code already exists, or when the original stored data in the storage stack are not all preset null values, disabling the stack error correction code.

Images