Technological method for reducing pattern bridging
By using multi-layer hard mask layer and side wall process in semiconductor integrated circuit manufacturing process, adjusting the width and spacing of photoresist patterns, the graphical bridging problem caused by process node reduction is solved, maintaining device performance and simplifying the process.
Patent Information
- Application Number
- CN202510214718.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-06-06
AI Technical Summary
In the manufacturing process of semiconductor integrated circuits, due to the shrinkage of process nodes, the active interval is reduced, and graphics bridging is prone to occur, affecting device performance.
By forming a multi-layer hard mask layer on the underlying structure, and adjusting the width and spacing of the first photoresist pattern in the photolithography process, it is smaller than the width and spacing of the target pattern, and forming a side wall on the sides of the second hard mask layer pattern, increasing its width to match the width of the target pattern.
It effectively reduces the occurrence of graphics bridging and maintains device performance. At the same time, the process is simple and easy to perform and will not affect the front layer process.
Smart Images
Figure CN120109083A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a process method for reducing pattern bridging. Background Art
[0002] Since the smaller the process node, the higher the chip integration, the lower the production cost and the greater the market competitiveness. Smaller process nodes are mainly achieved by reducing the size, which has higher requirements for the process and narrows the process window. One of the problems is the active area (AA) bridge. The reason for the AA bridge is that the spacing (space) between the active areas is too small. Usually, in order to ensure the performance of the device, when scaling down proportionally, the width of AA needs to be maintained so that the performance of the semiconductor device can be maintained. In this way, the step can only be reduced by reducing the spacing between the active areas to achieve proportional reduction.
[0003] However, due to the reduction of the space, the photoresist (PR) is prone to not being opened during the AA layer exposure, which will cause the AA to connect where it should not be, i.e., AA bridge. Figure 1 As shown, it is a photo of the existing active area bridging defect; the spacing area 202 between the active areas 101 is usually isolated by shallow trenches. It can be seen that Figure 1 There are a plurality of bridging defects between different active regions indicated by dashed circles 103 . Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide a process method for reducing graphic bridging, which can overcome the bridging problem caused by the continuous reduction in the spacing between graphics. At the same time, the process is simple and easy and will not affect the previous layer process. It can maintain the target size and spacing of the graphics, so that the device performance is not affected.
[0005] In order to solve the above technical problems, the process method for reducing pattern bridging provided by the present invention comprises the following steps:
[0006] A first hard mask layer is formed on a top surface of an underlying structure for forming a target pattern.
[0007] A second hard mask layer is formed on the first hard mask layer.
[0008] Photolithography is performed to form a first photoresist pattern, wherein a step of the first photoresist pattern is equal to a step of the target pattern, a width of the first photoresist pattern is smaller than a width of the target pattern, a pitch of the first photoresist pattern is larger than a pitch of the target pattern, and bridging of the first photoresist pattern is prevented by increasing the pitch of the first photoresist pattern.
[0009] A first etching is performed, wherein the first etching transfers the first photoresist pattern into the second hard mask layer and forms a second hard mask layer pattern.
[0010] A sidewall process is used to form a sidewall on the side of the second hard mask layer pattern, and the total width of the second hard mask layer pattern and the sidewalls on both sides is equal to the width of the target pattern.
[0011] A second etching is performed, wherein the first hard mask layer and the underlying structure are sequentially etched to form grooves in the underlying structure, and the underlying structure between the grooves constitutes the target pattern.
[0012] A further improvement is that the material of the first hard mask layer is the same as the material of the second hard mask layer.
[0013] Before forming the second hard mask layer, the method further includes:
[0014] An etch stop layer is formed on the surface of the first hard mask layer, and a material of the etch stop layer is different from a material of the second hard mask layer.
[0015] The first etching stops on the etch stop layer.
[0016] A further improvement is that the underlying structure includes a semiconductor substrate.
[0017] A further improvement is that the semiconductor substrate comprises a silicon substrate.
[0018] A further improvement is that the target pattern is an active area.
[0019] A further improvement is that the material of the first hard mask layer is SiN.
[0020] A further improvement is that the material of the etch stop layer is an oxide layer.
[0021] A further improvement is that before forming the first hard mask layer, a step of forming a first oxide layer on the top surface of the underlying structure is also included.
[0022] A further improvement is that after the second etching is completed, the second hard mask layer is consumed, and a portion of the thickness of the etching stop layer is retained, and then the method further includes:
[0023] The etch stop layer is removed.
[0024] Further improvements include:
[0025] The target pattern and the size of the groove are monitored online.
[0026] A further improvement is that the material of the sidewall spacer is the same as the material of the second hard mask layer.
[0027] A further improvement is that the sidewall process includes the following steps:
[0028] A spacer material layer is formed.
[0029] The sidewall spacer material layer is fully etched to form the sidewall spacer in a self-aligned manner on the side of the second hard mask layer.
[0030] On the basis of the existing process, the present invention adds a hard mask layer, namely the second hard mask layer, and at the same time changes the photolithography process, reducing the width of the first photoresist pattern defined by the photolithography process and increasing the spacing, so that the bridging problem of the photoresist pattern caused by too small spacing when the photolithography is defined according to the width and spacing of the target pattern in the existing method can be solved. Therefore, the present invention can overcome the bridging problem caused by the continuous reduction of the spacing of the pattern.
[0031] At the same time, since the width of the first photoresist pattern defined by the photolithography process is smaller than the width of the target pattern, in order to compensate for the difference between the two, after the first photoresist pattern is transferred to the second hard mask layer, a sidewall process is further added to form sidewalls on the sides of the second hard mask layer pattern. In this way, the width of the second hard mask layer pattern with sidewalls formed on both sides will be increased and equal to the width of the target pattern. When etching is performed using the second hard mask layer pattern with sidewalls formed on both sides as a mask, the width and spacing of the target pattern finally formed can meet the target requirements. Therefore, the present invention can remain unchanged without changing the target size and spacing of the pattern, so that the device performance is not affected.
[0032] In addition, the present invention only needs to add a hard mask layer on the basis of the existing hard mask layer and change the photolithography process, which can be achieved by only changing the process of the current layer. The process is simple and easy and will not affect the process of the previous layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0034] Figure 1 This is a photo of an existing active area bridging defect;
[0035] Figure 2 is a flow chart of a process method for reducing pattern bridging according to an embodiment of the present invention;
[0036] Figure 3A-3H It is a schematic diagram of the device structure in each step of the process method for reducing pattern bridging according to an embodiment of the present invention. DETAILED DESCRIPTION
[0037] like Figure 2 As shown, it is a flow chart of a process method for reducing pattern bridging according to an embodiment of the present invention; FIG. 3A to FIG. 3H , which is a schematic diagram of the device structure in each step of the process method for reducing pattern bridging according to an embodiment of the present invention; the process method for reducing pattern bridging according to an embodiment of the present invention comprises the following steps:
[0038] Step S101: Figure 3A As shown, a first hard mask layer 203 is formed on the top surface of an underlying structure 201, wherein the underlying structure 201 is used to form a target pattern 201a.
[0039] In the embodiment of the present invention, the underlying structure 201 includes a semiconductor substrate. The target pattern 201a is an active area.
[0040] In some embodiments, the semiconductor substrate includes a silicon substrate. Figure 3A In the figure, the silicon substrate is also represented by Silicon.
[0041] The material of the first hard mask layer 203 is SiN. Figure 3A In FIG. 2 , the first hard mask layer 203 is also represented by SIN.
[0042] Before forming the first hard mask layer 203, the method further includes forming a first oxide layer 202 on the top surface of the bottom structure 201. The first oxide layer 202 is a pad oxide layer. Figure 3A In FIG. 1 , the first oxide layer 202 is also represented by POX.
[0043] Step S102: Figure 3A As shown, a second hard mask layer 205 is formed on the first hard mask layer 203 .
[0044] In the embodiment of the present invention, the material of the first hard mask layer 203 is the same as the material of the second hard mask layer 205 .
[0045] Before forming the second hard mask layer 205, the method further includes:
[0046] An etch stop layer 204 is formed on the surface of the first hard mask layer 203 , and the material of the etch stop layer 204 is different from that of the second hard mask layer 205 .
[0047] In some embodiments, the material of the second hard mask layer 205 is silicon nitride.
[0048] The material of the etch stop layer 204 is an oxide layer.
[0049] Figure 3A In the figure, the second hard mask layer 205 is also represented by SIN-1, and the etching stop layer 204 is also represented by OX.
[0050] Step S103: Figure 3B As shown, photolithography is performed to form a first photoresist pattern 206, the stepping of the first photoresist pattern 206 is equal to the stepping of the target pattern 201a, the width w1 of the first photoresist pattern 206 is smaller than the width w1' of the target pattern 201a, and the spacing w2 of the first photoresist pattern 206 is larger than the spacing w2' of the target pattern 201a, and the first photoresist pattern 206 is prevented from bridging by increasing the spacing w2 of the first photoresist pattern 206. The critical dimension of the first photoresist pattern 206, i.e., CD, is the width.
[0051] Figure 3B In the figure, the first photoresist pattern 206 is also represented by PR.
[0052] Step S104: Figure 3C As shown, a first etching is performed, and the first etching transfers the first photoresist pattern 206 into the second hard mask layer 205 and forms a second hard mask layer pattern 205a.
[0053] The first etching stops on the etch stop layer 204 .
[0054] Step S105: Figure 3E As shown, a sidewall spacer 207a process is used to form a sidewall spacer 207a on the side of the second hard mask layer pattern 205a, and the total width of the second hard mask layer pattern 205a and the sidewall spacers 207a on both sides is equal to the width w1' of the target pattern 201a.
[0055] In the embodiment of the present invention, the material of the sidewall spacer 207 a is the same as the material of the second hard mask layer 205 .
[0056] The sidewall 207a process includes the following steps:
[0057] like Figure 3D As shown, a spacer material layer 207 is formed.
[0058] like Figure 3E As shown, the sidewall material layer 207 is fully etched to form the sidewall 207 a in a self-aligned manner on the side of the second hard mask layer 205 .
[0059] In some embodiments, the material of the sidewall spacer 207 a is silicon nitride. Figure 3D In FIG. 1 , the spacer material layer 207 is also represented by SIN-2.
[0060] Step S106: Figure 3G As shown, a second etching is performed, wherein the first hard mask layer 203 and the underlying structure 201 are sequentially etched to form grooves 201b in the underlying structure 201, and the underlying structure 201 between the grooves 201b constitutes the target pattern 201a.
[0061] In the embodiment of the present invention, Figure 3F As shown, the second etching first sequentially etches the etch stop layer 204 and the first hard mask layer 203 and stops on the surface of the first oxide layer 202. In this way, the second hard mask layer pattern 205a with the sidewall 207a formed on the side is transferred downward to the first hard mask layer 203.
[0062] Afterwards, if Figure 3G As shown, the first oxide layer 202 and the semiconductor substrate 201 are continuously etched to form the trench 201b and the target pattern 201a between the trench 201b.
[0063] In the embodiment of the present invention, the target pattern 201a is an active area, and the trench 201b is generally a shallow trench.
[0064] After the second etching is completed, the second hard mask layer 205 is consumed, and a portion of the thickness of the etching stop layer 204 is retained, and then the following steps are further included:
[0065] like Figure 3H As shown, the etch stop layer 204 is removed.
[0066] Also includes:
[0067] The sizes of the target pattern 201a and the groove 201b are monitored online.
[0068] Later also includes:
[0069] A dielectric layer such as an oxide layer is filled in the trench 201b to form shallow trench isolation.
[0070] On the basis of the existing process, the embodiment of the present invention adds a hard mask layer, namely, the second hard mask layer 205, and at the same time changes the photolithography process, reduces the width w1 of the first photoresist pattern 206 defined by the photolithography process and increases the spacing, so that the bridging problem of the photoresist pattern caused by the excessively small spacing when the photolithography is defined according to the width w1' and spacing of the target pattern 201a in the existing method can be solved. Therefore, the embodiment of the present invention can overcome the bridging problem caused by the continuous reduction of the spacing of the pattern.
[0071] At the same time, since the width w1 of the first photoresist pattern 206 defined by the photolithography process is smaller than the width w1' of the target pattern 201a, in order to compensate for the difference between the two, after the first photoresist pattern 206 is transferred to the second hard mask layer 205, a sidewall 207a process is further added to form a sidewall 207a on the side of the second hard mask layer pattern 205a. In this way, the width of the second hard mask layer pattern 205a with the sidewalls 207a formed on both sides will be increased and equal to the width w1' of the target pattern 201a. When etching is performed using the second hard mask layer pattern 205a with the sidewalls 207a formed on both sides as a mask, the width w1' and spacing of the target pattern 201a finally formed can meet the target requirements. Therefore, the embodiment of the present invention can maintain the target size and spacing of the pattern without affecting the device performance.
[0072] In addition, the embodiment of the present invention only needs to add a hard mask layer on the basis of the existing hard mask layer and change the photolithography process, which can be achieved by only changing the process of the current layer. The process is simple and easy and will not affect the process of the previous layer.
[0073] In the prior art, due to the reduction of Space, the PR is easily not opened during AA layer photolithography exposure, resulting in AA bridge. The embodiment of the present invention proposes a method of increasing the space by reducing the critical dimension (CD) of AA exposure, CD is the width of AA, when the step of AA remains unchanged, the space will increase when CD is reduced, and the embodiment of the present invention effectively overcomes the Bridge problem during AA exposure by adding a hard mask layer (HM layer) and supplementing the AA CD with reference to the sidewall process, and ensures that the target size of the device is not affected.
[0074] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A process for reducing pattern bridging, characterized in that: The steps include: forming a first hard mask layer on a top surface of an underlying structure, the underlying structure being used to form a target pattern; forming a second hard mask layer on the first hard mask layer; Performing photolithography to form a first photoresist pattern, wherein a step of the first photoresist pattern is equal to a step of the target pattern, a width of the first photoresist pattern is smaller than a width of the target pattern, a pitch of the first photoresist pattern is larger than a pitch of the target pattern, and bridging of the first photoresist pattern is prevented by increasing the pitch of the first photoresist pattern; Performing a first etching, wherein the first etching transfers the first photoresist pattern into the second hard mask layer and forms a second hard mask layer pattern; Forming a sidewall on the side of the second hard mask layer pattern by a sidewall process, wherein the total width of the second hard mask layer pattern and the sidewalls on both sides is equal to the width of the target pattern; A second etching is performed, wherein the first hard mask layer and the underlying structure are sequentially etched to form grooves in the underlying structure, and the underlying structure between the grooves constitutes the target pattern.
2. The process for reducing pattern bridging according to claim 1, characterized in that: The material of the first hard mask layer is the same as the material of the second hard mask layer; Before forming the second hard mask layer, the method further includes: forming an etch stop layer on a surface of the first hard mask layer, wherein a material of the etch stop layer is different from a material of the second hard mask layer; The first etching stops on the etch stop layer.
3. The process for reducing pattern bridging according to claim 2, characterized in that: The underlying structure includes a semiconductor substrate.
4. The process for reducing pattern bridging according to claim 3, characterized in that: The semiconductor substrate includes a silicon substrate.
5. The process for reducing pattern bridging according to claim 3, characterized in that: The target pattern is an active area.
6. The process for reducing pattern bridging according to claim 3, characterized in that: The material of the first hard mask layer is SiN.
7. The process for reducing pattern bridging according to claim 6, characterized in that: The material of the etching stop layer is an oxide layer.
8. The process for reducing pattern bridging according to claim 6, characterized in that: Before forming the first hard mask layer, the method further includes forming a first oxide layer on the top surface of the underlying structure.
9. The process for reducing pattern bridging according to claim 7, characterized in that: After the second etching is completed, the second hard mask layer is consumed, and a portion of the thickness of the etching stop layer is retained, and then the method further includes: The etch stop layer is removed.
10. The process for reducing pattern bridging according to claim 9, characterized in that: Also includes: The target pattern and the size of the groove are monitored online.
11. The process for reducing pattern bridging according to claim 2, characterized in that: The material of the sidewall spacer is the same as that of the second hard mask layer.
12. The process for reducing pattern bridging according to claim 1, characterized in that: The sidewall process includes the following steps: forming a side wall material layer; The sidewall spacer material layer is fully etched to form the sidewall spacer in a self-aligned manner on the side of the second hard mask layer.