Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a storage system. The semiconductor structure includes a first semiconductor structure including a first bonding layer; and the second semiconductor structure comprises a second bonding layer bonded with the first bonding layer, and the first bonding layer and the second bonding layer are made of silicon oxycarbide.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a storage system. Background Art

[0002] In the field of integrated circuit design and manufacturing, with the continuous improvement of semiconductor manufacturing process level, process feature size is getting smaller and smaller, and the integration of integrated circuits is getting higher and higher. Usually, in the semiconductor formation process, different semiconductor structures are often required to be bonded together to improve the design freedom and integration of the semiconductor structure, increase the number of devices per unit area, and reduce the interconnection between different semiconductor structures to reduce power consumption and delay. However, if the bonding strength between different semiconductor structures is low, it will cause the different semiconductor structures to fall off. Summary of the invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0004] The present application provides a semiconductor structure, which includes: a first semiconductor structure including a first bonding layer; and a second semiconductor structure including a second bonding layer bonded to the first bonding layer, wherein the first bonding layer and the second bonding layer are made of silicon oxycarbide.

[0005] In one embodiment, the first surface of the first bonding layer and the second surface of the second bonding layer are bonded, wherein the first surface and / or the second surface comprises silicon-oxygen-silicon bonds.

[0006] In one embodiment, the surface roughness Ra value of the first surface and / or the second surface is less than 1 nanometer.

[0007] In one embodiment, the bonding strength between the first bonding layer and the second bonding layer is greater than 2.4 J / m 2 .

[0008] In one embodiment, the bonding method of the first bonding layer and the second bonding layer includes a hybrid bonding method.

[0009] In one embodiment, the first bonding layer includes a first bonding contact, and the second bonding layer includes a second bonding contact in contact with the first bonding contact, wherein materials of the first bonding contact and the second bonding contact include conductive materials.

[0010] In one embodiment, the first semiconductor structure includes a memory cell array, and the second semiconductor structure includes a peripheral circuit, wherein the peripheral circuit is coupled to the memory cell array through the second bonding layer and the first bonding layer.

[0011] Another aspect of the present application provides a method for manufacturing a semiconductor structure, which includes: providing a first semiconductor structure having a first bonding layer and a second semiconductor structure having a second bonding layer, wherein the first bonding layer and the second bonding layer are made of silicon oxycarbide; and performing face-to-face bonding of the first bonding layer and the second bonding layer.

[0012] In one embodiment, performing face-to-face bonding on the first bonding layer and the second bonding layer includes: performing activation treatment on a first surface of the first bonding layer and a second surface of the second bonding layer; and performing face-to-face bonding on the first surface and the second surface.

[0013] In one embodiment, the activated first surface and / or the second surface comprises silanol groups.

[0014] In one embodiment, the method further includes: before performing face-to-face bonding on the first surface and the second surface, planarizing the first surface and the second surface so that the surface roughness Ra value of the first surface and / or the second surface is less than 1 nanometer.

[0015] In one embodiment, the method further comprises: performing an annealing process on the bonded first surface and the second surface, wherein during the annealing process, silicon-oxygen-silicon bonds are formed on the first surface and / or the second surface.

[0016] In one embodiment, the first bonding layer includes a first bonding contact extending to the first surface, and the second bonding layer includes a second bonding contact extending to the second surface, wherein face-to-face bonding of the first surface and the second surface includes: bonding the first surface and the second surface using a hybrid bonding process so that the first bonding contact is in contact with the second bonding contact.

[0017] In one embodiment, the method further includes: forming a memory cell array connected to the first bonding layer in the first semiconductor structure; and forming a peripheral circuit connected to the second bonding layer in the second semiconductor structure.

[0018] On the other hand, the present application provides a storage system, which includes at least one three-dimensional memory, each three-dimensional memory including the semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the three-dimensional memory to store data.

[0019] In one or more embodiments of the present application, the material of the first bonding layer of the first semiconductor structure and the second bonding layer of the second semiconductor structure may include silicon oxycarbide. In this way, the bonded first bonding layer and the second bonding layer not only have a greater bonding strength, but also have fewer defects such as gaps on the interface where the two are in contact. In addition, the dielectric constants of the first bonding layer and the second bonding layer are low, which is conducive to reducing the delay of the electrical signal in the first bonding layer and the second bonding layer and improving the signal propagation speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0021] Figure 1 is a partial structural schematic diagram of a semiconductor structure provided according to an exemplary embodiment of the present application;

[0022] Figure 2 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0023] Figure 3 is a partial structural schematic diagram of forming a first semiconductor structure according to an exemplary embodiment of the present application;

[0024] Figure 4 is a partial structural schematic diagram of forming a second semiconductor structure according to an exemplary embodiment of the present application;

[0025] Figure 5 is a schematic diagram of the bonding strength test results of the first surface and the second surface after bonding in three groups of samples provided according to an exemplary embodiment of the present application;

[0026] FIG. 6A to FIG. 6C is a schematic diagram of defect scanning results of the first surface and / or the second surface after bonding in three groups of samples provided according to an exemplary embodiment of the present application;

[0027] Figure 7 is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application; and

[0028] Fig. 8A and Figure 8B is a schematic diagram of a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way.

[0030] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teachings of this application, the first semiconductor structure discussed in this application may also be referred to as the second semiconductor structure, and vice versa.

[0031] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0032] In addition, in this document, when describing that one part is located "on" another part, for example, the meaning of "on", "above" and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" does not absolutely mean being above based on the direction of gravity, nor does it only mean the meaning of "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0033] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0034] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but include various equivalent structures that can achieve the same functions and shape and size deviations caused by, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0036] As used in this article, the term "layer" refers to a material portion including an area with a height. A layer can be an area of ​​a uniform or non-uniform continuous structure, whose height is less than the height of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it and / or below it. A layer can include multiple layers.

[0037] In addition, in the present application, when “connected” or “coupled” is used, it may indicate that the corresponding components are in direct contact or indirect contact, unless otherwise clearly defined or can be inferred from the context.

[0038] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0039] Figure 1 is a schematic structural diagram of a semiconductor structure 1000 according to an exemplary embodiment of the present application.

[0040] The semiconductor structure 1000 may include a first semiconductor structure 1100 and a second semiconductor structure 1200 .

[0041] The first semiconductor structure 1100 may include a first bonding layer 1110. The second semiconductor structure 1200 may include a second bonding layer 1210 bonded to the first bonding layer 1110. Exemplarily, the material of the first bonding layer 1110 and the second bonding layer 1210 may include silicon oxycarbide (SiOC).

[0042] In an exemplary embodiment of the present application, the first surface 1111 of the first bonding layer 1110 may be bonded to the second surface 1211 of the second bonding layer 1210 to achieve bonding between the first bonding layer 1110 and the second bonding layer 1210. For example, the first surface 1111 and / or the second surface 1211 may include silicon-oxygen-silicon bonds.

[0043] In the exemplary embodiment of the present application, Figure 1As shown, the first bonding layer 1110 may include a plurality of first bonding contacts 1112 extending to the first surface 1111 of the first bonding layer 1110 and a dielectric isolating the first bonding contacts 1112. The second bonding layer 1210 may include a plurality of second bonding contacts 1212 extending to the second surface 1211 of the second bonding layer 1210 and a dielectric isolating the second bonding contacts 1212, wherein the second bonding contacts 1212 may contact the first bonding contacts 1112.

[0044] The first bonding contact 1112 and the second bonding contact 1212 may include a conductive material, such as copper (Cu). The remaining regions of the first bonding layer 1110 and the second bonding layer 1210 may be formed of a silicon oxycarbide material.

[0045] Exemplarily, the bonding method of the first bonding layer 1110 and the second bonding layer 1210 may include a hybrid bonding method. In other words, the first bonding contact 1112 and the surrounding dielectric in the first bonding layer 1110 may be used for hybrid bonding. The second bonding contact 1212 and the surrounding dielectric in the second bonding layer 1210 may also be used for hybrid bonding.

[0046] In the exemplary embodiment of the present application, Figure 1 As shown, the first semiconductor structure 1100 may further include a first interconnect layer 1120, wherein the first bonding layer 1110 may be located on one side of the first interconnect layer 1120. The first interconnect layer 1120 may include an interconnect structure (also referred to as a "contact structure", not shown) in a plurality of dielectric layers. For example, the first bonding contact 1112 may be connected to an interconnect structure (such as a bit line contact and / or a word line contact) in the first interconnect layer 1120.

[0047] The material of the interconnect structure in the first interconnect layer 1120 may include a conductive material, such as, but not limited to, tungsten (W), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. The dielectric layer may be formed of a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof.

[0048] Exemplarily, the first semiconductor structure 1100 may further include a memory cell array (not shown) connected to the first bonding layer 1110 . For example, the memory cell array may be located on the other side of the first interconnect layer 1120 and may be connected to the first bonding layer 1110 through the first interconnect layer 1120 .

[0049] The memory cell array may include any suitable memory cell with storage function in a plurality of memory cells such as NAND memory string cells, embedded DRAM memory cells (including transistors and capacitors), etc. The NAND memory string cell may include a source, a drain, and a plurality of memory cells at the intersection with the plurality of memory layers and between the source and the drain. The DRAM memory cell may include a capacitor for storing a data bit as a positive charge or a negative charge and one or more transistors (also referred to as a transfer transistor) for controlling (e.g., switching and selecting) access to the memory cell.

[0050] In the exemplary embodiment of the present application, Figure 1 As shown, the second semiconductor structure 1200 may further include a second interconnect layer 1220, wherein the second bonding layer 1210 may be located on one side of the second interconnect layer 1220. The second interconnect layer 1220 may include a plurality of interconnect structures (also referred to as "contact structures", not shown), wherein the interconnect structures may include lateral interconnect lines and interconnect contacts. The second interconnect layer 1220 may also include one or more dielectric layers for separating the plurality of interconnect lines and / or interconnect contacts. That is, the second interconnect layer 1220 may include interconnect lines and interconnect contacts in a plurality of dielectric layers.

[0051] Exemplarily, the second semiconductor structure 1200 may further include a peripheral circuit (not shown) connected to the second bonding layer 1210. For example, the peripheral circuit may be located on the other side of the second interconnect layer 1220. The peripheral circuit may be connected to the second bonding layer 1210 through the second interconnect layer 1220, and the peripheral circuit may be coupled to the memory cell array through the second bonding layer 1210 and the first bonding layer 1100, so as to realize the functional support of the peripheral circuit to the memory cell array, such as reading, writing and erasing the data of the storage cell.

[0052] The peripheral circuits (also referred to as control and sensing circuits) may include any suitable digital, analog, and / or mixed signal circuits for facilitating the operation of the memory cell array. For example, the peripheral circuits may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the above functional circuits, or any active or passive component of the circuit (e.g., a peripheral transistor, diode, resistor, or capacitor).

[0053] In the exemplary embodiment of the present application, the bonding strength of the first bonding layer 1110 and the second bonding layer 1210 may be greater than 2.4 J / m 2Specifically, the present application conducts bonding strength tests on the semiconductor structure 1000 in multiple groups of samples, and the test results of the multiple groups of samples are not much different. Figure 5 The schematic diagram of the bonding strength test results of the bonded first surface 1111 and / or second surface 1211 in three groups of samples is exemplarily shown. Figure 5 It can be seen that the bonding strengths of the first surface 1111 and the second surface 1211 bonded in the three groups of samples are 2.48 J / m 2 , 2.56J / m 2 , 2.44J / m 2 It can be seen that, in the present application, by at least setting the materials of the first bonding layer 1110 and the second bonding layer 1210 to include silicon oxycarbide, the bonding strength of the bonded first semiconductor structure 1100 and the second semiconductor structure 1200 can be improved.

[0054] In the exemplary embodiment of the present application, by setting the material of the first bonding layer 1110 and the second bonding layer 1210 to include silicon oxycarbide, the surface roughness Ra value of the first surface 1111 and / or the second surface 1211 can be less than 1 nanometer, which is conducive to reducing defects such as gaps at the bonding interface. The present application performs bonding interface defect scanning tests on the semiconductor structure 1000 in multiple groups of samples, and the test results of the multiple groups of samples are not much different. FIG. 6A to FIG. 6C The schematic diagram of defect scanning results of the bonded first surface 1111 and / or second surface 1211 (ie, bonding interface) in three groups of samples is exemplarily shown. FIG. 6A to FIG. 6C It can be seen that the bonded first surface 1111 and / or second surface 1211 are relatively clean and have fewer defects.

[0055] In addition, the present application sets the material of the first bonding layer 1110 and the second bonding layer 1210 to include silicon oxycarbide, so that the first bonding layer 1110 and the second bonding layer 1210 can have a lower dielectric constant, which is beneficial to reducing the delay of the electrical signal in the first bonding layer 1110 and the second bonding layer 1210 and improving the signal propagation speed. The first bonding layer 1110 and the second bonding layer 1210 have a lower dielectric constant, which is also beneficial to blocking the metal diffusion of the first bonding contact 1112 and the second bonding contact 1212 (such as Cu contact) in the first bonding layer 1110 and the second bonding layer 1210, thereby extending the electromigration life of the semiconductor structure.

[0056] Figure 2 is a flow chart of a method 2000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0057] like Figure 2As shown, the method 2000 for manufacturing a semiconductor structure may include: S2100, providing a first semiconductor structure having a first bonding layer and a second semiconductor structure having a second bonding layer, wherein the materials of the first bonding layer and the second bonding layer include silicon oxycarbide; and S2200, performing face-to-face bonding on the first bonding layer and the second bonding layer. Steps S2100 and S2200 will be described in detail below.

[0058] In the exemplary embodiment of the present application, Figure 3 and Figure 4 As shown, a first semiconductor structure 1100 having a first bonding layer 1110 and a second semiconductor structure 1200 having a second bonding layer 1210 may be provided, wherein the materials of the first bonding layer 1110 and the second bonding layer 1210 may include silicon oxycarbide (SiOC).

[0059] In the exemplary embodiment of the present application, Figure 3 As shown, the first bonding layer 1110 may include a plurality of first bonding contacts 1112 extending to the first surface 1111 of the first bonding layer 1110 and a dielectric isolating the first bonding contacts 1112. The first bonding contacts 1112 may include a conductive material, such as copper (Cu). The remaining area of ​​the first bonding layer 1110 may be formed of a silicon oxycarbide material. The first bonding contacts 1112 and the surrounding dielectric in the first bonding layer 1110 may be used for hybrid bonding.

[0060] In the exemplary embodiment of the present application, Figure 3 As shown, a first interconnect layer 1120 may be formed in the first semiconductor structure 1100, wherein the first bonding layer 1110 may be located on one side of the first interconnect layer 1120. The first interconnect layer 1120 may include an interconnect structure (also referred to as a "contact structure") in a plurality of dielectric layers. For example, the first bonding contact 1112 may be connected to an interconnect structure (such as a bit line contact and / or a word line contact) in the first interconnect layer 1120.

[0061] The material of the interconnect structure in the first interconnect layer 1120 may include a conductive material, such as, but not limited to, tungsten (W), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. The dielectric layer may be formed of a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof.

[0062] Exemplarily, the interconnect structure in the first interconnect layer 1120 may include a conductive material deposited by one or more thin film deposition processes (including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof). The manufacturing process for forming the interconnect may also include photolithography, chemical mechanical polishing (CMP), wet / dry etching, or any other suitable process. The dielectric layer may include a dielectric material deposited using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof).

[0063] For example, the first bonding layer 1110 may be formed by depositing, for example, a carbide oxide material on one side surface of the first interconnect layer 1120 through one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Then, a contact hole patterned through the first bonding layer 1110 and in contact with the interconnect structure in the first interconnect layer 1120 may be formed by using a patterning process (e.g., photolithography and dry / wet etching of the carbide oxide material in the first bonding layer 1110), and a conductive material such as metal copper may be filled in the contact hole to form a first bonding contact 1112 that passes through the first bonding layer 1110 and in contact with the interconnect structure in the first interconnect layer 1120.

[0064] For example, a memory cell array (not shown) connected to the first bonding layer 1110 may be formed in the first semiconductor structure 1100. For example, a memory cell array may be formed on the other side of the first interconnect layer 1120. The memory cell array may be connected to the first bonding layer 1110 through the first interconnect layer 1120.

[0065] The memory cell array may include any suitable memory cell with storage function in a plurality of memory cells such as NAND memory string cells, embedded DRAM memory cells (including transistors and capacitors), etc. The NAND memory string cell may include a source, a drain, and a plurality of memory cells at the intersection with the plurality of memory layers and between the source and the drain. The DRAM memory cell may include a capacitor for storing a data bit as a positive charge or a negative charge and one or more transistors (also referred to as a transfer transistor) for controlling (e.g., switching and selecting) access to the memory cell.

[0066] In the exemplary embodiment of the present application, Figure 4As shown, the second bonding layer 1210 may include a plurality of second bonding contacts 1212 extending to a second surface 1211 of the second bonding layer 1210 and a dielectric isolating the second bonding contacts 1212. The second bonding contacts 1212 may include a conductive material, such as copper (Cu). The remaining area of ​​the second bonding layer 1210 may be formed of silicon oxycarbide. The second bonding contacts 1212 and the surrounding dielectric in the second bonding layer 1210 may be used for hybrid bonding.

[0067] In the exemplary embodiment of the present application, Figure 4 As shown, a second interconnect layer 1220 may be formed in the second semiconductor structure 1200, wherein the second bonding layer 1210 may be located on one side of the second interconnect layer 1220. The second interconnect layer 1220 may include a plurality of interconnect structures (also referred to as "contact structures"), wherein the interconnect structures may include lateral interconnect lines and interconnect contacts. The second interconnect layer 1220 may also include one or more dielectric layers for separating the plurality of interconnect lines and / or interconnect contacts. That is, the second interconnect layer 1220 may include interconnect lines and interconnect contacts in a plurality of dielectric layers.

[0068] It should be understood that in the present application, the material and formation process of the second interconnection layer 1220 may be similar to the material and formation process of the first interconnection layer 1120, and to avoid redundancy, the present application will not introduce them here. In addition, the formation process of the second bonding layer 1210 may be similar to the formation process of the first bonding layer 1110, and to avoid redundancy, the present application will not introduce them here.

[0069] Exemplarily, a peripheral circuit (not shown) connected to the second bonding layer 1210 may also be formed in the second semiconductor structure 1200. For example, a peripheral circuit may be formed on the other side of the second interconnect layer 1220. The peripheral circuit may be connected to the second bonding layer 1210 through the second interconnect layer 1220. After the second bonding layer 1210 and the first bonding layer 1100 are subsequently bonded, the peripheral circuit may be coupled to the memory cell array through the second bonding layer 1210 and the first bonding layer 1100 to realize the functional support of the peripheral circuit to the memory cell array, such as reading, writing and erasing the data of the storage cell.

[0070] The peripheral circuits (also referred to as control and sensing circuits) may include any suitable digital, analog, and / or mixed signal circuits for facilitating the operation of the memory cell array. For example, the peripheral circuits may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the above functional circuits, or any active or passive component of the circuit (e.g., a peripheral transistor, diode, resistor, or capacitor).

[0071] In an exemplary embodiment of the present application, the first bonding layer 1110 and the second bonding layer 1210 may be bonded face to face to form a Figure 1 The structure shown.

[0072] Illustratively, face-to-face bonding of the first bonding layer 1110 and the second bonding layer 1210 may include: activating the first surface 1111 of the first bonding layer 1110 and the second surface 1211 of the second bonding layer 1210 ; and face-to-face bonding of the first surface 1111 and the second surface 1211 .

[0073] Illustratively, before the first surface 1111 and the second surface 1211 are activated, the first surface 1111 and the second surface 1211 may be planarized, such as polished, to improve the flatness and cleanliness of the first surface 1111 and the second surface 1211, thereby helping to reduce defects such as gaps on the first surface 1111 and the second surface 1211, and further helping to reduce bonding defects and improve bonding strength.

[0074] In the present application, the material of the first surface 1111 and the second surface 1211 may include silicon oxycarbide. After the first surface 1111 and the second surface 1211 are planarized, the surface roughness Ra value of the first surface 1111 and / or the second surface 1211 may be less than 1 nanometer.

[0075] In an exemplary embodiment of the present application, the activated first surface 1111 and / or the second surface 1211 may include silanol groups. For example, the first surface 1111 of the first bonding layer 1110 and the second surface 1211 of the second bonding layer 1210 may be activated by a plasma activation process to excite the first surface 1111 and / or the second surface 1211 to generate free radicals such as activated silicon ions Si + In the plasma activation process, the plasma may bombard the first surface 1111 and / or the second surface 1211 to break the silicon-silicon bonds, silicon-oxygen bonds, silicon-carbon bonds, etc. on the first surface 1111 and / or the second surface 1211, thereby forming activated silicon ions Si + .

[0076] For example, during the plasma activation process of the first surface 1111 and the second surface 1211, part of the water vapor in the air is also bombarded by the plasma to form hydroxide ions OH. - . Hydroxide ion OH - Can be activated with silicon ions Si +Combine to form silanol Si-OH. For example, water vapor can be ionized by a plasma activation process to form hydroxide ions OH - . Hydroxide ion OH - can be bombarded onto the first surface 1111 and the second surface 1211 and interact with the activated silicon ions Si on the first surface 1111 and the second surface 1211 + Combine to generate silanol Si-OH.

[0077] In an exemplary embodiment of the present application, face-to-face bonding of the first surface 1111 and the second surface 1211 may include: bonding the first surface 1111 and the second surface 1211 using a hybrid bonding process to bring the first bonding contact 1112 into contact with the second bonding contact 1212. For example, during the bonding process, pressure may be applied to the first semiconductor structure 1100 and the second semiconductor structure 1200 to bring the first surface 1111 and the second surface 1211 into physical contact.

[0078] It should be understood that after the first surface 1111 and the second surface 1211 are bonded (i.e., the first bonding layer 1110 and the second bonding layer 1210 are bonded), the first bonding contact 1112 is in contact with the second bonding contact 1212, and the dielectric in the first bonding layer 1110 that isolates the first bonding contact 1112 is in contact with the dielectric in the second bonding layer 1210 that isolates the second bonding contact 1212.

[0079] In an exemplary embodiment of the present application, the first surface 1111 and the second surface 1211 after bonding may be subjected to an annealing treatment, that is, the first semiconductor structure 1100 and the second semiconductor structure 1200 after bonding may be subjected to an annealing treatment. Exemplarily, during the annealing treatment, the silanol Si-OH on the first surface 1111 and the second surface 1211 may be dehydrated and condensed to form a silicon-oxygen-silicon bond (Si-O-Si bond), thereby bonding the first surface 1111 and the second surface 1211 together, that is, bonding the first semiconductor structure 1100 and the second semiconductor structure 1200 together. The dehydration condensation reaction formula may be: Si-OH+HO-Si→SiO 2 +H 2 O.

[0080] In the present application, the first surface 1111 and the second surface 1211 after bonding are annealed, which is beneficial to improve the bonding strength between the first surface 1111 and the second surface 1211. For example, the bonding strength of the first bonding layer 1110 and the second bonding layer 1210 may be greater than 2.4 J / m 2 .

[0081] Specifically, the present application performs bonding strength tests on the first semiconductor structure 1100 and the second semiconductor structure 1200 after bonding in multiple groups of samples, and the test results of the multiple groups of samples are not much different. Figure 5 The schematic diagram of the bonding strength test results of the first surface 1111 and / or the second surface 1211 after bonding in three groups of samples is exemplarily shown. Figure 5 It can be seen that the bonding strengths of the first surface 1111 and the second surface 1211 after bonding in the three groups of samples are 2.48 J / m 2 , 2.56J / m 2 , 2.44J / m 2 It can be seen that, in the present application, by at least setting the materials of the first bonding layer 1110 and the second bonding layer 1210 to include silicon oxycarbide, the bonding strength between the first semiconductor structure 1100 and the second semiconductor structure 1200 after bonding can be improved.

[0082] In addition, the present application also performs bonding interface defect scanning tests on the first semiconductor structure 1100 and the second semiconductor structure 1200 after bonding in multiple groups of samples, and the test results of the multiple groups of samples are not much different. FIG. 6A to FIG. 6C The schematic diagram of defect scanning results of the first surface 1111 and / or the second surface 1211 (ie, the bonding interface) after bonding in three groups of samples is exemplarily shown. FIG. 6A to FIG. 6C It can be seen that the first surface 1111 and / or the second surface 1211 after bonding is relatively clean and has fewer defects.

[0083] On the other hand, the present application sets the material of the first bonding layer 1110 and the second bonding layer 1210 to include silicon oxycarbide, so that the first bonding layer 1110 and the second bonding layer 1210 can have a lower dielectric constant, which is beneficial to reduce the delay of the electrical signal in the first bonding layer 1110 and the second bonding layer 1210 and improve the signal propagation speed. In addition, the first bonding layer 1110 and the second bonding layer 1210 have a lower dielectric constant, which is beneficial to block the metal diffusion of the first bonding contact 1112 and the second bonding contact 1212 (such as Cu contact) in the first bonding layer 1110 and the second bonding layer 1210, and prolong the electromigration life of the semiconductor structure.

[0084] Since the contents and structures involved in the above description of the semiconductor structure 1000 may be fully or partially applicable to the method 2000 for manufacturing a semiconductor structure described herein, the related or similar contents will not be described in detail herein.

[0085] Although the exemplary structure and method of making the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced or added from the method of making the semiconductor structure. In addition, the illustrated layers and materials thereof are merely exemplary.

[0086] Figure 7 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0087] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the storage system 12 located therein). Figure 7 As shown, the system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more memories (including a three-dimensional memory 14) and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memory 14.

[0088] The three-dimensional memory 14 may include the semiconductor structure 1000 described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media-card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate function may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0089] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig. 8AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Figure 7 The host 18 in the memory card connector 24 is coupled. Figure 8B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Figure 7 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0090] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A semiconductor structure, It is characterized in that include: A first semiconductor structure including a first bonding layer; and The second semiconductor structure includes a second bonding layer bonded to the first bonding layer, wherein the material of the first bonding layer and the second bonding layer includes silicon oxycarbide.

2. The semiconductor structure according to claim 1, It is characterized in that The first surface of the first bonding layer and the second surface of the second bonding layer are bonded, wherein the first surface and / or the second surface include silicon-oxygen-silicon bonds.

3. The semiconductor structure according to claim 2, It is characterized in that The surface roughness Ra value of the first surface and / or the second surface is less than 1 nanometer.

4. The semiconductor structure according to claim 1, It is characterized in that The bonding strength between the first bonding layer and the second bonding layer is greater than 2.4 J / m 2 .

5. The semiconductor structure according to claim 1, It is characterized in that The bonding method of the first bonding layer and the second bonding layer includes a mixed bonding method.

6. The semiconductor structure according to claim 5, It is characterized in that The first bonding layer includes a first bonding contact, and the second bonding layer includes a second bonding contact in contact with the first bonding contact, wherein materials of the first bonding contact and the second bonding contact include conductive materials.

7. The semiconductor structure according to any one of claims 1 to 6, It is characterized in that The first semiconductor structure includes a memory cell array, and the second semiconductor structure includes a peripheral circuit, wherein the peripheral circuit is coupled to the memory cell array through the second bonding layer and the first bonding layer.

8. A method of manufacturing a semiconductor structure, It is characterized in that The method comprises: Providing a first semiconductor structure having a first bonding layer and a second semiconductor structure having a second bonding layer, wherein the first bonding layer and the second bonding layer are made of silicon oxycarbide; and The first bonding layer and the second bonding layer are bonded face to face.

9. The method according to claim 8, It is characterized in that The step of performing face-to-face bonding on the first bonding layer and the second bonding layer comprises: performing activation treatment on the first surface of the first bonding layer and the second surface of the second bonding layer; and The first surface and the second surface are bonded face to face.

10. The method according to claim 9, It is characterized in that The first surface and / or the second surface after activation includes silanol groups.

11. The method according to claim 9, It is characterized in that The method further comprises: Before the first surface and the second surface are bonded face to face, the first surface and the second surface are planarized so that the surface roughness Ra value of the first surface and / or the second surface is less than 1 nanometer.

12. The method according to claim 9, It is characterized in that The method further comprises: The first surface and the second surface after bonding are subjected to an annealing treatment, wherein during the annealing treatment, silicon-oxygen-silicon bonds are formed on the first surface and / or the second surface.

13. The method according to any one of claims 9 to 12, It is characterized in that The first bonding layer includes a first bonding contact extending to the first surface, the second bonding layer includes a second bonding contact extending to the second surface, Wherein, performing face-to-face bonding on the first surface and the second surface comprises: The first surface and the second surface are bonded by a hybrid bonding process, so that the first bonding contact contacts the second bonding contact.

14. The method according to any one of claims 8 to 12, It is characterized in that The method further comprises: forming a memory cell array in the first semiconductor structure connected to the first bonding layer; and A peripheral circuit connected to the second bonding layer is formed in the second semiconductor structure.

15. A storage system, It is characterized in that include: At least one three-dimensional memory, each of the three-dimensional memory comprising a semiconductor structure as claimed in any one of claims 1 to 7; as well as The controller is coupled to the semiconductor structure and is used for controlling the three-dimensional memory to store data.

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