Semiconductor device, manufacturing method and testing method thereof, and storage system

Abstract

The present disclosure provides a semiconductor device, a manufacturing method and a testing method thereof, and a storage system. The semiconductor device includes a semiconductor layer, a first dielectric layer, and a second dielectric layer stacked in sequence along a first direction. A semiconductor structure is located in the semiconductor layer. A first conductive structure is located in the first dielectric layer. The first conductive structure is connected to the semiconductor structure. A second conductive structure extends through the second dielectric layer along the first direction and into the first dielectric layer, and the second conductive structure is connected to an end of the first conductive structure away from the semiconductor structure along the first direction. A pad structure is located in the second dielectric layer. The pad structure is connected to the second conductive structure and isolated from the first conductive structure. An opening is located in the second dielectric layer. The opening exposes the pad structure. Thus, the reliability of the semiconductor device can be improved, the difficulty of the manufacturing process can be reduced, the manufacturing rate can be increased, and the manufacturing cost can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method and a testing method thereof, and a storage system. Background Art

[0002] With the development of large-scale integrated circuits (ICs), semiconductor devices are entering the post-Moore era by moving towards three-dimensional fabrication to meet the demands of high integration, fast transmission speeds, and low power consumption. The vertical connection of multiple chips stacked in three dimensions in semiconductor devices is primarily achieved through silicon via (TSV) technology.

[0003] However, with the miniaturization of semiconductor devices, there are still many problems that need to be solved in the interconnection structure used to achieve vertical connection of semiconductor devices. Summary of the Invention

[0004] In view of this, in order to solve one or more of the existing technical problems, the embodiments of the present disclosure provide a semiconductor device, a manufacturing method and a testing method thereof, and a storage system; wherein the semiconductor device includes: a semiconductor layer, a first dielectric layer, and a second dielectric layer stacked in sequence along a first direction; a semiconductor structure located in the semiconductor layer; a first conductive structure located in the first dielectric layer; the first conductive structure is connected to the semiconductor structure; a second conductive structure penetrates the second dielectric layer along the first direction and extends into the first dielectric layer, the second conductive structure is connected to an end of the first conductive structure away from the semiconductor structure along the first direction; a pad structure located in the second dielectric layer; the pad structure is connected to the second conductive structure, and the pad structure and the first conductive structure are isolated from each other; an opening located in the second dielectric layer; the opening exposes the pad structure.

[0005] In some embodiments, when the material of the pad structure is copper, the semiconductor device further includes: a filling structure located at the opening; a top surface of the filling structure is flush with a top surface of the second dielectric layer along a second direction; and the second direction is perpendicular to the first direction.

[0006] In some embodiments, the semiconductor device further includes: a barrier layer; the barrier layer covers the sidewalls and bottom surface of the second conductive structure; wherein a portion of the barrier layer is located between the second conductive structure and the pad structure.

[0007] In some embodiments, the material of the barrier layer includes at least one of tantalum, tantalum nitride, titanium, and titanium nitride; and the material of the second conductive structure includes at least one of gold, silver, copper, iron, nickel, and tin.

[0008] In some embodiments, the semiconductor device further includes: a third conductive structure, which penetrates the second dielectric layer along the first direction and extends into the first dielectric layer, and the third conductive structure and the second conductive structure are arranged at intervals along the second direction; and a fourth conductive structure, which is located in the first dielectric layer; the fourth conductive structure is respectively connected to the third conductive structure and the semiconductor structure; and the fourth conductive structure and the first conductive structure are arranged at intervals along the second direction.

[0009] In some embodiments, the semiconductor device further includes: a first insulating layer, located in the first dielectric layer and located on a side of the first conductive structure away from the semiconductor structure in the first direction; wherein the second conductive structure penetrates the first insulating layer along the first direction and is connected to the first conductive structure.

[0010] In some embodiments, the semiconductor device further includes: a second insulating layer located on a side of the second dielectric layer away from the first dielectric layer along the first direction; the second insulating layer covers the top surface of the second conductive structure, and the top surface and the bottom surface are two opposite surfaces of the second conductive structure in the first direction.

[0011] In some embodiments, the semiconductor device further includes: a third dielectric layer located on a side of the second insulating layer away from the second dielectric layer along the first direction; and an interconnect structure penetrating the third dielectric layer and the second insulating layer along the first direction; the interconnect structure is connected to the second conductive structure.

[0012] A storage system proposed in an embodiment of the present disclosure includes the semiconductor device as described in the above embodiment of the present disclosure; and a memory controller coupled to the semiconductor device and configured to control the semiconductor device.

[0013] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising: forming a semiconductor layer, a first dielectric layer, and a second dielectric layer stacked in sequence along a first direction; forming a semiconductor structure in the semiconductor layer; forming a first conductive structure in the first dielectric layer, and connecting the first conductive structure to the semiconductor structure; forming a second conductive structure that penetrates the second dielectric layer along the first direction and extends into the first dielectric layer, and connecting the second conductive structure to an end of the first conductive structure that is away from the semiconductor structure along the first direction; forming a pad structure in the second dielectric layer, connecting the pad structure to the second conductive structure, and isolating the pad structure from the first conductive structure; and forming an opening in the second dielectric layer, and exposing the pad structure through the opening.

[0014] In some embodiments, the method further includes: when the material of the pad structure is copper, after testing the semiconductor structure using the pad structure, forming a filling structure at the opening.

[0015] In some embodiments, the method further includes: when the material of the pad structure is aluminum, removing the pad structure after testing the semiconductor structure using the pad structure; and forming a filling structure in situ on the pad structure and at the opening.

[0016] In some embodiments, forming a pad structure in the second dielectric layer includes: forming a pad structure on a portion of the surface of the first dielectric layer away from the semiconductor layer along the first direction; forming a dielectric material layer on the remaining surface of the first dielectric layer away from the semiconductor layer along the first direction, and on the surface of the pad structure; and planarizing the dielectric material layer to form a second dielectric layer.

[0017] In some embodiments, the forming of the second conductive structure that penetrates the second dielectric layer along the first direction and extends into the first dielectric layer includes: forming a groove that penetrates the second dielectric layer along the first direction and extends into the first dielectric layer; the groove exposes the top surface of the first conductive structure in the first direction and exposes a side surface of the pad structure in the second direction; the first direction is perpendicular to the second direction; and the second conductive structure is formed in the groove.

[0018] In some embodiments, forming the second conductive structure in the groove includes: forming a barrier layer on the sidewall and bottom of the groove; and forming the second conductive structure in the groove having the barrier layer formed thereon.

[0019] In some embodiments, the method further includes: forming a third conductive structure that penetrates the second dielectric layer along the first direction and extends into the first dielectric layer, and the third conductive structure and the second conductive structure are arranged at intervals along the second direction; and forming a fourth conductive structure in the first dielectric layer, and the fourth conductive structure is connected to the third conductive structure and the semiconductor structure respectively, and the fourth conductive structure and the first conductive structure are arranged at intervals along the second direction.

[0020] In some embodiments, the method further includes: forming a first insulating layer in the first dielectric layer and on a side of the first conductive structure away from the semiconductor structure along the first direction; wherein the second conductive structure penetrates the first insulating layer along the first direction and is connected to the first conductive structure.

[0021] In some embodiments, the method further includes: forming a second insulating layer on a side of the second dielectric layer away from the first dielectric layer along the first direction, and making the second insulating layer cover a top surface of the second conductive structure.

[0022] In some embodiments, the method further includes: forming a third dielectric layer on a side of the second insulating layer away from the second dielectric layer along the first direction; forming an interconnect structure penetrating the third dielectric layer and the second insulating layer along the first direction, and connecting the interconnect structure to the second conductive structure.

[0023] An embodiment of the present disclosure provides a method for testing a semiconductor device, wherein the semiconductor device includes the semiconductor device as described in the above embodiment of the present disclosure. The method includes: using a probe to contact a pad structure at an opening to test the semiconductor structure.

[0024] In an embodiment of the present disclosure, a semiconductor structure is formed in a semiconductor layer, a first conductive structure is formed in a first dielectric layer, and a second conductive structure is formed in the first and second dielectric layers, penetrating the first dielectric layer and extending into the second dielectric layer. The semiconductor structure is connected to one end of the first conductive structure, and the other end of the first conductive structure is connected to the second conductive structure. Then, a pad structure connected to the second conductive structure is formed in the second dielectric layer. In this manner, electrical testing of the semiconductor structure can be performed using the pad structure without affecting the reliability of the second conductive structure due to damage to the pad structure during testing. Furthermore, the pad structure and the second conductive structure are disposed in the same dielectric layer, thereby avoiding delamination problems caused by irreversible deformation during subsequent processing when the pad structure and the second conductive structure are disposed in multiple layers. Furthermore, while the pad structure and the first conductive structure can be electrically connected, the two can be electrically isolated from each other. Consequently, if the pad structure is removed, the first conductive structure will not be damaged, thereby improving the reliability of the semiconductor device, reducing the difficulty of the manufacturing process, increasing the manufacturing rate, and reducing the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of an electronic device provided in accordance with an embodiment of the present disclosure;

[0026] Figure 2a A schematic diagram of a semiconductor device provided in accordance with an embodiment of the present disclosure;

[0027] Figure 2b A schematic diagram of a semiconductor device provided in accordance with another embodiment of the present disclosure;

[0028] Figure 3 A schematic diagram of a manufacturing process of a semiconductor device provided in one embodiment of the present disclosure;

[0029] Figure 4 A schematic cross-sectional view of a semiconductor layer and a semiconductor structure provided in one embodiment of the present disclosure;

[0030] Figure 5 A schematic cross-sectional view of a first dielectric layer and a first conductive structure provided in one embodiment of the present disclosure;

[0031] Figure 6 A schematic cross-sectional view of a pad structure provided in one embodiment of the present disclosure;

[0032] Figure 7 A schematic cross-sectional view of a second dielectric layer provided in one embodiment of the present disclosure;

[0033] Figure 8 A schematic cross-sectional view of a first etched hole and a second etched hole provided in one embodiment of the present disclosure;

[0034] Figure 9 A schematic cross-sectional view of a groove and a contact hole provided in one embodiment of the present disclosure;

[0035] Figure 10 A schematic cross-sectional view of a barrier layer provided in one embodiment of the present disclosure;

[0036] Figure 11 A schematic cross-sectional view of a second conductive structure and a third conductive structure provided in one embodiment of the present disclosure;

[0037] Figure 12 A schematic cross-sectional view of a second insulating layer provided in one embodiment of the present disclosure;

[0038] Figure 13 A schematic cross-sectional view of an opening provided in one embodiment of the present disclosure;

[0039] Figure 14 A cross-sectional schematic diagram of testing a semiconductor structure using a testing device (such as a probe) according to an embodiment of the present disclosure;

[0040] Figure 15 A schematic cross-sectional view of a filling structure provided in one embodiment of the present disclosure;

[0041] Figure 16 A schematic cross-sectional view of a third dielectric layer and an interconnect structure provided in one embodiment of the present disclosure;

[0042] Figure 17 A cross-sectional schematic diagram of testing a semiconductor structure using a testing device (such as a probe) according to another embodiment of the present disclosure;

[0043] Figure 18 A schematic cross-sectional view of an opening and a window provided in one embodiment of the present disclosure;

[0044] Figure 19 A schematic cross-sectional view of a filling structure provided in another embodiment of the present disclosure;

[0045] Figure 20 A schematic cross-sectional view of a third dielectric layer and an interconnect structure provided in another embodiment of the present disclosure.

[0046] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0047] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0048] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0049] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0050] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0051] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both the above and below orientations. The device can be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0052] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0053] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure.

[0054] Figure 1 Schematic diagram of an electronic device according to an embodiment of the present disclosure. Electronic device 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device.

[0055] like Figure 1 As shown, electronic device 1 may include a memory system 10 and a host 20. Memory system 10 may include a memory controller 110 and a memory device 120. Host 20 may include a processor, such as a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)). Memory controller 110 is coupled to both host 20 and memory device 120. Memory controller 110 may be configured to communicate with host 20 and control memory device 120.

[0056] In some embodiments, the memory controller 110 may be configured to control operations of the memory device 120, such as read operations, write operations, erase operations, and refresh operations. In some embodiments, the memory controller 110 may also be configured to process error correction codes (ECC) on data read from or written to the memory device 120. In other embodiments, the memory controller 110 may also be configured to perform any other suitable operations, such as formatting the memory device 120.

[0057] In some embodiments, the memory controller 110 may receive data, commands, and addresses from the host 20, and may send the data, commands, and addresses to the memory device 120. Specifically, the memory controller 110 may include a command generator 111, an address generator 112, a device interface 113, and a host interface 114. The memory controller 110 may receive data, commands, and addresses from the host 20 via the host interface 114, decode the command received from the host 20 via the command generator 111 to generate an access command CMD, and provide the access command CMD to the memory device 120 via the device interface 113. The memory controller 110 may decode the address received from the host interface 114 via the address generator 112 to generate an address ADDR to be accessed in the memory cell array 121, and may provide the accessed address ADDR to the memory device 120 via the device interface 113. The access command CMD may be a signal instructing the memory device 120 to write or read data by accessing one or more memory cells in the memory cell array 121 corresponding to the address ADDR. In addition, the memory controller 110 may also send a refresh command to the memory device 120 . The refresh command may be a signal instructing the memory device 120 to read and rewrite data by accessing one or more memory cells in the memory cell array 121 corresponding to the address ADDR.

[0058] In some embodiments, reference Figure 1 Memory device 120 includes a memory cell array 121 and peripheral circuits 122. Memory cell array 121 may include multiple memory cells arranged in an array. Peripheral circuits 122 may include sense amplifier circuits, row decoders, column decoders, data input / output buffers, etc. Peripheral circuits 122 are configured to receive access commands CMD and addresses ADDR. Based on parsing the access commands CMD and ADDR, they may independently access each memory cell in memory cell array 121 and perform read operations, write operations, erase operations, or refresh operations on the data stored in the accessed memory cells.

[0059] In some specific examples, the memory device 120 may be a NAND Flash, a random access memory (RAM), such as a dynamic random access memory, a synchronous dynamic random access memory (SDRAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a double data rate SDRAM (DDR SDRAM), a phase-change random access memory (PRAM), a resistive random access memory (ReRAM), a magnetic random access memory (MRAM), etc.

[0060] With the advancement of semiconductor technology, the integration density of integrated circuit chips has reached hundreds of millions or even billions of semiconductor devices. Due to varying requirements, the wiring design of integrated circuit chips has become increasingly complex. To meet these requirements, multiple semiconductor devices in an integrated circuit can be interconnected using multi-layer interconnect structures. In practical applications, the design of interconnect structures is subject to various limitations, such as manufacturing processes and component materials.

[0061] In some embodiments, the interconnect structure can be made of various conductive materials, such as gold (Au), silver (Ag), copper (Cu), and aluminum (Al). Aluminum is widely used in the integrated circuit manufacturing industry due to its high electrical conductivity and excellent corrosion resistance. Compared to other metals like gold, silver, and copper, aluminum is relatively low in cost, making it more cost-effective for large-scale production. Furthermore, aluminum is relatively soft, making it more efficient and reliable during the bonding process, especially when used in conjunction with traditional bonding techniques such as gold wire ball bonding. Aluminum interconnect technology is a relatively mature technology, and its stable process and mature technology are suitable for widespread application in very large-scale integrated circuits.

[0062] However, while aluminum interconnects offer good stability, they suffer from relatively poor resistivity and interconnect density. Furthermore, due to their ease of etching, aluminum interconnects can be overetched, impacting the reliability of other connected structures. Furthermore, after probe testing, the subsequent removal of aluminum interconnects can often be incomplete due to issues like probe marks and lift, potentially leading to circuit failures such as open circuits.

[0063] Based on this, in order to solve one or more of the above problems, the present disclosure provides a semiconductor device, referring to Figure 2a , Figure 2a A schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown in FIG. Figure 2a As shown, the semiconductor device includes: a semiconductor layer 201, a first dielectric layer 202, and a second dielectric layer 203 stacked in sequence along a first direction; a semiconductor structure 204 located in the semiconductor layer 201; a first conductive structure 205 located in the first dielectric layer 202; the first conductive structure 205 is connected to the semiconductor structure 204; a second conductive structure 206 penetrates the second dielectric layer 203 along the first direction and extends into the first dielectric layer 202; here, the second conductive structure 206 is connected to an end of the first conductive structure 205 away from the semiconductor structure 204 along the first direction; a pad structure 207 located in the second dielectric layer 203; the pad structure 207 is connected to the second conductive structure 206 and isolated from the first conductive structure 205; and an opening 208 located in the second dielectric layer 203, the opening 208 exposing the pad structure 207.

[0064] Based on this, a semiconductor structure is formed in a semiconductor layer, a first conductive structure is formed in a first dielectric layer, and a second conductive structure is formed in the first dielectric layer and the second dielectric layer, penetrating the first dielectric layer and extending into the second dielectric layer. The semiconductor structure is connected to one end of the first conductive structure, and the other end of the first conductive structure is connected to the second conductive structure. Then, a pad structure connected to the second conductive structure is formed in the second dielectric layer. In this way, on the one hand, electrical testing of the semiconductor structure can be performed using the pad structure, and the reliability of the second conductive structure will not be affected by damage to the pad structure during testing. On the other hand, the pad structure and the second conductive structure are arranged in the same dielectric layer, avoiding the occurrence of problems such as delamination caused by irreversible deformation during subsequent processing when the pad structure and the second conductive structure are arranged in multiple layers. On the other hand, when the pad structure and the first conductive structure can be electrically connected, the two can be electrically isolated from each other. Then, if the pad structure is removed, the first conductive structure will not be damaged, thereby improving the reliability of the semiconductor device, reducing the difficulty of the manufacturing process, increasing the manufacturing rate, and reducing the manufacturing cost.

[0065] In addition, it should be explained in detail that the second conductive structure can be used to realize functional interaction between the semiconductor structure and external devices, such as bonding and signal interaction; the pad structure can be used to realize testing of the semiconductor structure at different operating speeds.

[0066] The following is a detailed introduction Figure 2aBefore illustrating a semiconductor device, various directions that may be used in the following description are defined. In this disclosure, the stacking direction of multiple layers in a semiconductor device is defined as a first direction (i.e., the Z-axis direction). A second direction (i.e., the X-axis direction) and a third direction (i.e., the Y-axis direction) intersecting with each other are defined in a plane perpendicular to the Z-axis direction. In some embodiments, the X-axis direction, the Y-axis direction, and the Z-axis direction may be perpendicular to each other.

[0067] refer to Figure 2a The material of the semiconductor layer 201 includes silicon (Si); the material of the first dielectric layer 202 includes silicon oxide (SiO2); and the material of the second dielectric layer 203 includes silicon oxide, silicon carbide (SiC), or silicon carbon nitride (SiCN). The thickness of the semiconductor layer 201, the first dielectric layer 202, and the second dielectric layer 203 along the Z-axis can be set according to actual needs and is not limited in this disclosure. The method for forming the semiconductor layer 201, the first dielectric layer 202, and the second dielectric layer 203 includes, but is not limited to, a deposition process, including chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0068] A semiconductor structure 204 is provided in the semiconductor layer 201. The semiconductor structure 204 may include peripheral circuits and / or a memory cell array. The peripheral circuits may include multiple CMOS transistors and control circuits associated with the CMOS transistors, such as control logic, sense amplifier circuits, row decoders, column decoders, data input / output buffers, drivers, and read / write circuits. When the control logic receives a read / write operation command and address data, the row decoder or column decoder, under the control of the control logic, may apply the corresponding voltage generated by the driver to the corresponding bit line or word line based on the decoded address to enable data reading or writing, and exchange data with external devices through the data input / output buffer. The memory cell array may include multiple memory cells, which may be NAND memory cells, PCM memory cells, DRAM memory cells, etc.

[0069] A first conductive structure 205 is provided in the first dielectric layer 202, and a second conductive structure 206 is provided in the first dielectric layer 202 and the second dielectric layer 203. One end of the first conductive structure 205 along the Z-axis is connected to one end of the semiconductor structure 204 along the Z-axis; the other end of the first conductive structure 205 along the Z-axis is connected to one end of the second conductive structure 206 along the Z-axis. In other words, the first conductive structure 205 is located between the semiconductor structure 204 and the second conductive structure 206. The first conductive structure 205 and the second conductive structure 206 can be used to lead electrical signals to and from the semiconductor structure 204. The shapes of the first conductive structure 205 and the second conductive structure 206 can be set according to actual needs and are not limited in this disclosure.

[0070] The materials of the first conductive structure 205 and the second conductive structure 206 can be the same or different. Exemplarily, the materials of the first conductive structure 205 and / or the second conductive structure 206 include a conductive material, such as at least one of gold (Au), silver (Ag), copper (Cu), iron (Fe), nickel (Ni), and tin (Sn). Methods for forming the first conductive structure 205 and the second conductive structure 206 include, but are not limited to, deposition processes, etching processes, and chemical mechanical polishing (CMP). Deposition processes include CVD, LPCVD, PECVD, PVD, and ALD processes. Etching processes include photolithography and etching.

[0071] A pad structure 207 is also provided in the second dielectric layer 203. The pad structure 207 is connected to the second conductive structure 206 and isolated from the first conductive structure 205. Here, one side of the pad structure 207 along the X-axis is connected to the second conductive structure 206. This allows electrical testing of the semiconductor structure to be performed using the pad structure without compromising the reliability of the second conductive structure due to damage to the pad structure during testing. Furthermore, the pad structure is electrically isolated from the first conductive structure, so that the first conductive structure is not damaged during removal of the pad structure. This improves the reliability of the semiconductor device, reduces the difficulty of the manufacturing process, increases manufacturing speed, and reduces manufacturing costs.

[0072] The material of the pad structure 207 includes, but is not limited to, conductive materials such as copper (Cu). The thickness of the pad structure 207 along the Z-axis ranges from 0.5 to 3.0 micrometers (um). The method of forming the pad structure 207 includes, but is not limited to, a deposition process.

[0073] refer to Figure 2aAn opening 208 is also provided in the second dielectric layer 203. Methods for forming the opening 208 include, but are not limited to, etching. The opening 208 exposes the pad structure 207. This allows for electrical testing of the semiconductor structure 204 by contacting the pad structure 207 with a probe through the opening 208. Furthermore, the pad structure enables various electrical tests to be performed on the semiconductor structure at different stages, allowing problematic semiconductor structures to be removed before packaging, saving packaging costs.

[0074] It should be noted that the number of semiconductor structures, first conductive structures, second conductive structures and pad structures in the semiconductor device can be one or more, and their arrangement can be set arbitrarily, which is not limited in this disclosure.

[0075] In some embodiments, reference Figure 2a The semiconductor device further includes a barrier layer 209 covering the sidewalls and bottom surface of the second conductive structure 206. A portion of the barrier layer 209 is located between the second conductive structure 206 and the liner structure 207. The barrier layer 209 has a lower etching rate than the liner structure 207. In other words, under the same etching conditions, the barrier layer 209 is less susceptible to etching than the liner structure 207. Thus, during the removal of the liner structure 207, the barrier layer 209 protects the second conductive structure 206 from etching, thereby ensuring the reliability of the second conductive structure 206.

[0076] Continue to refer Figure 2a The barrier layer 209 is also located between the second conductive structure 206 and the first conductive structure 205, thereby improving the conductivity of the second conductive structure 206 and the first conductive structure 205. The material of the barrier layer 209 includes at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN). Methods for forming the barrier layer 209 include, but are not limited to, deposition processes.

[0077] In some embodiments, reference Figure 2a The semiconductor device further includes a third conductive structure 210. The third conductive structure 210 extends through the second dielectric layer 203 along the Z-axis and into the first dielectric layer 202. The third conductive structure 210 and the second conductive structure 206 are spaced apart along the X-axis. The third conductive structure 210 and the second conductive structure 206 are made of the same material and formed using the same method, and can be formed using the same process, as previously described and will not be further described here.

[0078] In some embodiments, reference Figure 2aThe semiconductor device further includes: a fourth conductive structure 211; the fourth conductive structure 211 is located in the first dielectric layer 202; the fourth conductive structure 211 and the first conductive structure 205 are spaced apart along the X-axis direction; one end of the fourth conductive structure 211 along the Z-axis direction is connected to the third conductive structure 210, and the other end of the fourth conductive structure 211 along the Z-axis direction is connected to the semiconductor structure 204. The fourth conductive structure 211 and the first conductive structure 205 are made of the same material and formed in the same process, and can be formed in the same process, as previously described and will not be repeated here. Figure 2a The fourth conductive structure 211 is located between the third conductive structure 210 and the semiconductor structure 204. In this way, electrical signal communication of the semiconductor structure 204 can be achieved through the fourth conductive structure 211 and the third conductive structure 210.

[0079] In some embodiments, reference Figure 2a The sidewalls and bottom surface of the third conductive structure 210 are also conformally provided with a barrier layer 209 ; the barrier layer 209 can be used to increase the conductivity between the third conductive structure 210 and the fourth conductive structure 211 .

[0080] In some embodiments, reference Figure 2a The semiconductor device further includes a first insulating layer 213. The first insulating layer 213 is located in the first dielectric layer 202 and on a side of the first conductive structure 205 and the fourth conductive structure 211 that is away from the semiconductor structure 204 in the Z-axis direction. The second conductive structure 206 extends through the first insulating layer 213 along the Z-axis and connects to the first conductive structure 205. The third conductive structure 210 extends through the first insulating layer 213 along the Z-axis and connects to the fourth conductive structure 211. The first insulating layer 213 is used to prevent diffusion of materials from the first conductive structure 205 and the fourth conductive structure 211, thereby further improving the reliability of the semiconductor device. Materials for the first insulating layer 213 include, but are not limited to, silicon nitride (SiN). Methods for forming the first insulating layer 213 include, but are not limited to, deposition processes.

[0081] In some embodiments, reference Figure 2aThe semiconductor device further includes a second insulating layer 214. The second insulating layer 214 is located on a side of the second dielectric layer 203 away from the first dielectric layer 202 along the Z-axis. The second insulating layer 214 covers the top surfaces of the second conductive structure 206 and the third conductive structure 210. Here, the top surface of the second conductive structure 206 and the bottom surface of the second conductive structure 206 are two opposing surfaces of the second conductive structure 206 along the Z-axis, and the top surface of the third conductive structure 210 and the bottom surface of the third conductive structure 210 are two opposing surfaces of the third conductive structure 210 along the Z-axis. The second insulating layer 214 is used to prevent material diffusion from the second conductive structure 206 and the third conductive structure 210, thereby further improving the reliability of the semiconductor device. Here, the second insulating layer 214 also serves to form a dense buffer protection layer located above the pad structure 207, protecting the pad structure 207 from pressure damage. The material of the second insulating layer 214 includes, but is not limited to, silicon nitride. Methods for forming the second insulating layer 214 include, but are not limited to, deposition processes.

[0082] In other embodiments, reference Figure 2b The semiconductor device further includes a filling structure 212 located at the opening 208. The filling structure 212 covers the exposed surface of the pad structure 207 to enhance the reliability of the semiconductor device. When the second insulating layer 214 is not provided in the semiconductor structure, the top surface of the filling structure 212 can be flush with the top surface of the second dielectric layer 203 along the X-axis direction. When the second insulating layer 214 is provided in the semiconductor structure, the top surface of the filling structure 212 can be flush with the top surface of the second insulating layer 214 along the X-axis direction. The material of the filling structure 212 includes silicon oxide. Methods for forming the filling structure 212 include, but are not limited to, deposition processes.

[0083] In some embodiments, reference Figure 2b The semiconductor device further includes a third dielectric layer 215. The third dielectric layer 215 is located on a side of the second insulating layer 214 away from the second dielectric layer 203 along the Z-axis. The material of the third dielectric layer 215 can be the same as or different from the material of the filling structure 212. For example, the material of the third dielectric layer 215 can include silicon nitride, silicon oxide, silicon, or the like. Methods for forming the third dielectric layer 215 include, but are not limited to, deposition processes. It should be noted that when the material of the third dielectric layer 215 is the same as that of the filling structure 212, the filling structure 212 and the third dielectric layer 215 can be formed in the same process.

[0084] In some embodiments, reference Figure 2bThe semiconductor device further includes an interconnect structure 216. The interconnect structure 216 extends through the third dielectric layer 215 and the second insulating layer 214 along the Z-axis. The interconnect structure 216 is connected to one end of the second conductive structure 206 and the third conductive structure 210, respectively. The material of the interconnect structure 216 includes at least one of gold, silver, copper, iron, nickel-tin, and aluminum. Methods for forming the interconnect structure 216 include, but are not limited to, deposition processes. Thus, the interconnect structure 216 enables electrical signal communication between the semiconductor structure 204 and external devices.

[0085] Based on the above semiconductor device, the present disclosure also provides a method for manufacturing a semiconductor device. Figure 3 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure; FIG. Figure 3 As shown, the manufacturing method includes the following steps:

[0086] Step S301 : forming a semiconductor layer, a first dielectric layer, and a second dielectric layer stacked in sequence along a first direction.

[0087] Step S302: forming a semiconductor structure in the semiconductor layer.

[0088] Step S303 : forming a first conductive structure in the first dielectric layer, and connecting the first conductive structure to the semiconductor structure.

[0089] Step S304 : forming a second conductive structure penetrating the second dielectric layer along the first direction and extending into the first dielectric layer, and connecting the second conductive structure to an end of the first conductive structure away from the semiconductor structure along the first direction.

[0090] Step S305 : forming a liner structure in the second dielectric layer, connecting the liner structure to the second conductive structure, and isolating the liner structure from the first conductive structure.

[0091] Step S306 : forming an opening in the second dielectric layer, and exposing the pad structure through the opening.

[0092] It should be understood that Figure 3 The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown; Figure 3 The steps shown in the figure can be adjusted in sequence according to actual needs. Figures 4 to 20 The manufacturing process diagram of the semiconductor device provided in the embodiment of the present disclosure is shown below. Figures 3 to 20 The manufacturing method of the semiconductor device provided by the embodiment of the present disclosure is introduced. The first direction is the Z-axis direction, the second direction is the X-axis direction, and the third direction is the Y-axis direction. The X-axis direction, the Y-axis direction, and the Z-axis direction can be perpendicular to each other.

[0093] In some embodiments, reference Figure 4 The method includes: providing a semiconductor layer 401; and forming a semiconductor structure 402 in the semiconductor layer. Here, the semiconductor layer is made of silicon. The semiconductor structure includes peripheral circuits and / or a memory cell array. The peripheral circuits may include multiple CMOS transistors and control circuits associated with the CMOS transistors, such as control logic, sense amplifier circuits, row decoders, column decoders, data input / output buffers, drivers, and read / write circuits. When the control logic receives a read / write operation command and address data, the row decoder or column decoder, under the control of the control logic, can apply the corresponding voltage generated by the driver to the corresponding bit line or word line based on the decoded address to enable data reading or writing, and exchange data with external devices through the data input / output buffer. The memory cell array may include multiple memory cells, which may be NAND memory cells, PCM memory cells, DRAM memory cells, etc. Methods for forming peripheral circuits or memory cell arrays in semiconductor layers are relatively mature and will not be described in detail here.

[0094] The method further comprises: referring to Figure 5A first dielectric layer 403 is formed on one of two opposite sides of the semiconductor layer 401 along the Z-axis. A first conductive structure 404 and a fourth conductive structure 405 are formed in the first dielectric layer 403, and a first insulating layer 406 is formed in the first dielectric layer 403 on a side of the first conductive structure 404 and the fourth conductive structure 405 away from the semiconductor structure 402 in the Z-axis direction. Here, the first conductive structure 404 and the fourth conductive structure 405 are arranged along the X-axis; the first insulating layer 406 is used to prevent material diffusion of the first conductive structure 404 and the fourth conductive structure 405. The specific formation process includes: depositing a layer of dielectric material on the surface of the semiconductor layer 401, etching the layer of dielectric material to form a plurality of trenches arranged along the X-axis, and filling the plurality of trenches with conductive material to form the first conductive structure 404 and the fourth conductive structure 405 arranged along the X-axis. A first insulating layer 406 is formed on the top surfaces of the first conductive structure 404 and the fourth conductive structure 405, as well as on the surface of the dielectric material. Then, another layer of dielectric material is deposited on the surface of the first insulating layer 406 to form the first dielectric layer 403. Methods for depositing the first dielectric layer 403, the first conductive structure 404, the fourth conductive structure 405, and the first insulating layer 406 include, but are not limited to, deposition processes, including CVD, LPCVD, PECVD, PVD, ALD, and the like. The material of the first dielectric layer 403 includes silicon oxide, the material of the first insulating layer 406 includes silicon nitride, and the material of the first conductive structure 404 and the fourth conductive structure 405 includes a conductive material, such as at least one of gold, silver, copper, iron, nickel, and tin. The shapes of the first conductive structure 404 and the fourth conductive structure 405 may be the same or different, and this disclosure is not limited thereto.

[0095] It should be noted that both the first conductive structure 404 and the fourth conductive structure 405 may be connected to the semiconductor structure 402 to enable electrical signal communication between the semiconductor structure 402 and other devices.

[0096] In some embodiments, reference Figure 6 The method further includes depositing a conductive material layer on the surface of the first dielectric layer 403 on two opposing sides along the Z-axis, the side away from the semiconductor layer 401, and removing a portion of the conductive material layer through a photolithography and etching process to form a pad structure 407. The pad structure 407 is electrically isolated from the first conductive structure 404 and from the fourth conductive structure 405. Methods for forming the pad structure 407 include, but are not limited to, deposition processes, including CVD, LPCVD, PECVD, PVD, ALD, and the like. Here, the thickness of the pad structure 407 along the Z-axis ranges from 0.5 to 3.0 microns (μm). Materials for the pad structure 407 include conductive materials such as copper and aluminum.

[0097] It should be noted that aluminum pad structures can be used on a large scale in integrated circuits, but aluminum pad structures are easily damaged during testing. Based on this, after subsequent testing, the pad structure can choose a suitable retention method according to the different materials; there is a detailed description later, so I will not repeat it here.

[0098] In some embodiments, reference Figure 7 The method further includes forming a dielectric material layer on the remaining surface of the first dielectric layer 403 on the side away from the semiconductor layer 401 along the Z-axis direction and on the exposed surface of the pad structure 407. The dielectric material layer is planarized to form a second dielectric layer 408. The material of the second dielectric layer 408 includes silicon oxide, silicon carbide, or silicon carbon nitride. Methods for forming the second dielectric layer 408 include, but are not limited to, deposition processes, including CVD, LPCVD, PECVD, PVD, and ALD processes. Planarization processes include, but are not limited to, chemical mechanical polishing.

[0099] In some embodiments, reference Figure 8 The method further includes forming a first etching hole 409 and a second etching hole 410 that penetrate the second dielectric layer 408 along the Z-axis and extend into the first dielectric layer 403; the first etching hole 409 and the second etching hole 410 are spaced apart along the X-axis and / or the Y-axis; and the first etching hole 409 is closer to the pad structure 407 than the second etching hole 410. The formation process can use a Damascene copper wire process. The first insulating layer 406 can serve as an etch stop layer for the first etching hole 409 and the second etching hole 410.

[0100] In some embodiments, reference Figure 9 , the method further includes: using a first etching hole to remove a portion of the second dielectric layer 408 and a portion of the first insulating layer 406 to form a groove 411; the groove 411 exposes the top surface of the first conductive structure 404 in the Z-axis direction and exposes one side of the pad structure 407 in the X-axis direction. In other embodiments, the groove 411 may also expose a portion of the surface of the pad structure 407 in the Z-axis direction. At the same time, using a second etching hole to remove a portion of the second dielectric layer 408 and a portion of the first insulating layer 406 to form a contact hole 412. The contact hole 412 exposes the top surface of the fourth conductive structure 405 in the Z-axis direction. Here, the method of removing the second dielectric layer 408 and the first insulating layer 406 includes but is not limited to etching.

[0101] In some embodiments, reference Figure 10 The method further includes: forming a barrier layer 413 on the sidewalls and bottom of the groove 411 and the contact hole 412. A seed layer ( Figure 10(not shown), that is, the seed layer covers the surface of the barrier layer. Furthermore, a conductive material layer 414 is deposited in the recess 411 and contact hole 412 formed with the barrier layer 413 and seed layer, and on the surface of the second dielectric layer 408. The material of the barrier layer 413 includes, but is not limited to, at least one of tantalum, tantalum nitride, titanium, and titanium nitride; the material of the seed layer includes, for example, at least one of gold, silver, copper, iron, nickel, and tin; and the conductive material layer 414 includes at least one of gold, silver, copper, iron, nickel, and tin. Typically, the material of the seed layer is the same as that of the conductive material layer. Methods for forming the barrier layer 413, seed layer, and conductive material layer 414 include, but are not limited to, deposition processes, including CVD, LPCVD, PECVD, PVD, ALD, and the like.

[0102] In some embodiments, reference Figure 11 The method further includes planarizing the conductive material layer 414 to form a second conductive structure 415 in the groove where the barrier layer 413 and the seed layer are formed, and forming a third conductive structure 416 in the contact hole where the barrier layer 413 and the seed layer are formed. The second conductive structure 415 and the third conductive structure 416 are spaced apart along the X-axis, and the top surfaces of the second conductive structure 415 and the third conductive structure 416 are flush with the top surface of the second dielectric layer 408 along the X-axis. The second conductive structure 415 is connected to the first conductive structure 404 via the barrier layer 413, and the third conductive structure 416 is connected to the fourth conductive structure 405 via the barrier layer 413.

[0103] It should be noted that, in conjunction with the reference Figure 9 、 Figure 10 and Figure 11 In the above process, the groove 411 exposes a portion of the surface of the pad structure 407. Therefore, after the barrier layer 413 is formed, a portion of the barrier layer 413 covers the exposed surface of the pad structure 407. In other words, after the second conductive structure 415 is formed, the barrier layer 413 exists between the second conductive structure 415 and the pad structure 407. Due to the conductive properties of the barrier layer 413, the second conductive structure 415 and the pad structure 407 can be electrically connected.

[0104] In some embodiments, the etch rate of the barrier layer 413 is lower than that of the liner structure 407. In other words, under the same etching conditions, the barrier layer 413 is less susceptible to etching than the liner structure 407. Thus, during the removal of the liner structure 407, the barrier layer 413 protects the second conductive structure 415 from etching, thereby ensuring the reliability of the second conductive structure 415. Furthermore, the barrier layer 413 is used to enhance the electrical conductivity between the second conductive structure 415 and the first conductive structure 404, and to enhance the electrical conductivity between the third conductive structure 416 and the fourth conductive structure 405.

[0105] In some embodiments, reference Figure 12 The method further includes: forming a second insulating layer 417 on the top surfaces of the second conductive structure 415 and the third conductive structure 416 and the surface of the second dielectric layer 408. The second insulating layer 417 is used to prevent the diffusion of materials of the second conductive structure 415 and the third conductive structure 416. Based on the material properties of the second insulating layer 417, the second insulating layer 417 can also serve as a dense buffer protection layer to protect the pad structure, the second conductive structure, and the third conductive structure from damage. The material of the second insulating layer 417 includes, but is not limited to, silicon nitride. The method of forming the second insulating layer 417 includes, but is not limited to, a deposition process, including CVD, LPCVD, PECVD, PVD, ALD, etc.

[0106] In some embodiments, reference Figure 13 The method further includes: removing a portion of the second insulating layer 417 and a portion of the second dielectric layer 408 to form an opening 418. The opening 418 exposes the pad structure 407. The removal process includes but is not limited to dry etching. Based on this, in the above-mentioned semiconductor device of the present disclosure, reference Figure 14 The test device 500 (such as a probe) can be used to contact the pad structure 407 to perform an electrical test on the semiconductor structure 402 through the second conductive structure 415 and the first conductive structure 404. The electrical test includes but is not limited to a WAT ​​test (Wafer Acceptance Test) and a CP test (Chip Probing).

[0107] It should be noted that the reference Figure 13 or Figure 14 In this semiconductor device, both the pad structure 407 and the high-density metal wiring layer (including the second conductive structure 415 and the third conductive structure 416) are formed within the same dielectric layer. This allows the semiconductor device to meet subsequent testing and packaging requirements while maintaining a high wiring density. Furthermore, integrating the pad structure 407 and the metal wiring layer (including the second conductive structure 415 and the third conductive structure 416) within a single dielectric layer allows structures that would otherwise require wiring across two or more layers to be integrated onto a single layer, avoiding issues such as delamination between two or more layers due to irreversible deformation during subsequent processing. Furthermore, the overall dielectric layer thickness of the semiconductor device is reduced, which can also reduce the difficulty of managing warpage and the difficulty of the dicing process.

[0108] It should be noted that when the material of the pad structure 407 is copper, the damage caused to the pad structure 407 by the probe 500 during the test is small and can be ignored. In this way, after the semiconductor structure is tested using the pad structure, a filling structure can be directly formed at the opening 418, such as Figure 15 .

[0109] Specifically, refer to Figure 15 The method further includes: when the material of the liner structure 407 is copper, after testing the semiconductor structure 402 using the liner structure 407, forming a filling structure 419 at the opening. The top surface of the filling structure 419 is flush with the top surface of the second insulating layer 417 along the X-axis direction. The material of the filling structure 419 includes silicon oxide, and the method of forming the filling structure 419 includes, but is not limited to, a deposition process, including CVD, LPCVD, PECVD, PVD, ALD, etc.

[0110] In some embodiments, reference Figure 16 The method further includes forming a third dielectric layer 420 on a side of the second insulating layer 417 away from the second dielectric layer 408 along the Z-axis. The material of the third dielectric layer 420 includes silicon oxide. Methods for forming the third dielectric layer 420 include, but are not limited to, deposition processes, including CVD, LPCVD, PECVD, PVD, and ALD processes. In some embodiments, the filling structure 419 and the third dielectric layer 420 can be formed in the same process. This can reduce process steps and manufacturing time.

[0111] Continue to refer Figure 16 The method further includes forming an interconnect structure 421 that penetrates the third dielectric layer 420 and the second insulating layer 417 along the Z-axis direction, and connecting the interconnect structure 421 to the second conductive structure 415 and the third conductive structure 416, respectively. In this way, electrical signal communication between the semiconductor structure 402 and external devices can be achieved through the interconnect structure 421. The material of the interconnect structure 421 includes at least one of gold, silver, copper, iron, nickel, tin, and aluminum. Methods for forming the interconnect structure 421 include, but are not limited to, deposition processes, including CVD, LPCVD, PECVD, PVD, ALD processes, and the like.

[0112] In other embodiments, when the material of the pad structure 407 is aluminum, refer to Figure 17 During the test, the probe 500 may cause damage to the pad structure 407, such as warping 600, needle marks, etc. In this case, in order not to affect the subsequent formation of other structures, such as packaging, the damaged pad structure 407 needs to be removed, and then a filling structure is formed in the original position of the removed pad structure and the opening 418, such as Figure 18 、 Figure 19 .

[0113] Specifically: Reference Figure 18 and Figure 19 The method further includes: when the material of the pad structure is aluminum, after testing the semiconductor structure using the pad structure, removing the pad structure to form a window 422 in situ in the pad structure; then, forming a filling structure 423 in situ in the pad structure (i.e., at the window 422) and at the opening 418. Here, the removal process includes wet etching, and the etchant can be hydrofluoric acid (HF). It should be understood that after removing the pad structure, there is no risk of other failures in the etching process due to the pad structure; in addition, the etchant should be selected based on the principle of removing the pad structure (e.g., metal aluminum) while ensuring the integrity of the second conductive structure (e.g., metal copper) or the barrier layer.

[0114] In some embodiments, reference Figure 20 The method further includes forming a third dielectric layer 424 on a side of the second insulating layer 417 away from the second dielectric layer 408 along the Z-axis direction; and forming an interconnect structure 425 that penetrates the third dielectric layer 424 and the second insulating layer 417 along the Z-axis direction, and connecting the interconnect structure 425 to the second conductive structure 415 and the third conductive structure 416, respectively. Similarly, the third dielectric layer 424 and the filling structure 423 can be formed in the same process, thereby reducing process flow and manufacturing time.

[0115] The material and formation method of the filling structure 423 described herein are the same as those of the filling structure 419 described in the aforementioned embodiment. The third dielectric layer 424 described herein is the same as the third dielectric layer 420 described in the aforementioned embodiment. The interconnect structure 425 described herein is the same as the interconnect structure 421 described in the aforementioned embodiment. All of these have been described above and will not be repeated here. It should be noted that the method may further include: continuing to perform subsequent processes on the semiconductor device, such as a three-dimensional integrated hybrid bonding process, etc., which is not limited in this disclosure.

[0116] Based on this, in an embodiment of the present disclosure, a semiconductor structure is formed in a semiconductor layer, a first conductive structure is formed in a first dielectric layer, and a second conductive structure is formed in the first dielectric layer and the second dielectric layer, penetrating the first dielectric layer and extending into the second dielectric layer. The semiconductor structure is connected to one end of the first conductive structure, and the other end of the first conductive structure is connected to the second conductive structure. Then, a pad structure connected to the second conductive structure is formed in the second dielectric layer. In this way, on the one hand, electrical testing of the semiconductor structure can be achieved through the pad structure. On the other hand, the reliability of the second conductive structure will not be affected by damage to the pad structure during the test. On the other hand, when the pad structure and the first conductive structure can be electrically connected, the two can be electrically isolated from each other. Then, in the process of subsequently removing the pad structure, the first conductive structure will not be damaged, thereby improving the reliability of the semiconductor device, reducing the difficulty of the manufacturing process, increasing the manufacturing rate, and reducing the manufacturing cost.

[0117] Based on the above-mentioned semiconductor device and its manufacturing method, the embodiment of the present disclosure further provides a storage system, including the semiconductor device as described in the above-mentioned embodiment of the present disclosure; and a memory controller coupled to the semiconductor device and used to control the semiconductor device.

[0118] Based on the above-mentioned semiconductor device and its manufacturing method, an embodiment of the present disclosure also provides a method for testing a semiconductor device, wherein the semiconductor device includes the semiconductor device as described in the above-mentioned embodiment of the present disclosure; the method includes: using a probe to contact the pad structure at the opening to test the semiconductor structure.

[0119] It should be noted that "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In addition, the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0120] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor layer, a first dielectric layer, and a second dielectric layer are sequentially stacked along a first direction; a semiconductor structure located in the semiconductor layer; a first conductive structure, located in the first dielectric layer; The first conductive structure is connected to the semiconductor structure; a second conductive structure, penetrating the second dielectric layer along the first direction and extending into the first dielectric layer, the second conductive structure being connected to an end of the first conductive structure away from the semiconductor structure along the first direction; a liner structure located in the second dielectric layer; The pad structure is connected to the second conductive structure, and the pad structure is isolated from the first conductive structure; a barrier layer located between the second conductive structure and the liner structure; an opening located in the second dielectric layer; The opening exposes the pad structure.

2. The semiconductor device according to claim 1, wherein When the material of the pad structure is copper, the semiconductor device further includes: a filling structure located at the opening; a top surface of the filling structure is flush with a top surface of the second dielectric layer along a second direction; and the second direction is perpendicular to the first direction.

3. The semiconductor device according to claim 1, wherein The material of the barrier layer includes at least one of tantalum, tantalum nitride, titanium and titanium nitride; the material of the second conductive structure includes at least one of gold, silver, copper, iron, nickel and tin.

4. The semiconductor device according to claim 1, wherein The semiconductor device further includes: a third conductive structure, extending through the second dielectric layer along the first direction and into the first dielectric layer, the third conductive structure and the second conductive structure being spaced apart along a second direction perpendicular to the first direction; and A fourth conductive structure is located in the first dielectric layer; the fourth conductive structure is connected to the third conductive structure and the semiconductor structure respectively; the fourth conductive structure and the first conductive structure are spaced apart and arranged along the second direction.

5. The semiconductor device according to claim 4, wherein: The semiconductor device further includes: a first insulating layer located in the first dielectric layer and located on a side of the first conductive structure away from the semiconductor structure in the first direction; The second conductive structure penetrates the first insulating layer along the first direction and is connected to the first conductive structure.

6. The semiconductor device according to claim 5, wherein: The semiconductor device further includes: a second insulating layer located on a side of the second dielectric layer away from the first dielectric layer along the first direction; the second insulating layer covers the top surface of the second conductive structure.

7. The semiconductor device according to claim 6, wherein: The semiconductor device further includes: a third dielectric layer located on a side of the second insulating layer away from the second dielectric layer along the first direction; and An interconnection structure penetrates the third dielectric layer and the second insulating layer along the first direction; the interconnection structure is connected to the second conductive structure.

8. A storage system, characterized in that: comprising a semiconductor device according to any one of claims 1 to 7; and The memory controller is coupled to the semiconductor device and is used to control the semiconductor device.

9. A method for manufacturing a semiconductor device, characterized in that: The method comprises: forming a semiconductor layer, a first dielectric layer, and a second dielectric layer stacked in sequence along a first direction; forming a semiconductor structure in the semiconductor layer; forming a first conductive structure in the first dielectric layer, and connecting the first conductive structure to the semiconductor structure; forming a second conductive structure penetrating the second dielectric layer along the first direction and extending into the first dielectric layer, and connecting the second conductive structure to an end of the first conductive structure away from the semiconductor structure along the first direction; forming a pad structure in the second dielectric layer, connecting the pad structure to the second conductive structure and isolating the pad structure from the first conductive structure; forming a barrier layer between the second conductive structure and the pad structure; An opening is formed in the second dielectric layer, and the pad structure is exposed through the opening.

10. The manufacturing method according to claim 9, characterized in that: The method further comprises: When the material of the liner structure is copper, a filling structure is formed at the opening after the semiconductor structure is tested using the liner structure.

11. The manufacturing method according to claim 10, characterized in that: The method further comprises: When the material of the liner structure is aluminum, after the semiconductor structure is tested using the liner structure, the liner structure is removed; and a filling structure is formed at the original position of the liner structure and at the opening.

12. The manufacturing method according to claim 10 or 11, characterized in that: The forming of the liner structure in the second dielectric layer includes: forming a pad structure on a portion of the surface of the first dielectric layer away from the semiconductor layer along the first direction; forming a dielectric material layer on the remaining surface of the first dielectric layer away from the semiconductor layer along the first direction and on the surface of the pad structure; The dielectric material layer is planarized to form a second dielectric layer.

13. The manufacturing method according to claim 12, characterized in that: The forming of the second conductive structure penetrating the second dielectric layer along the first direction and extending into the first dielectric layer includes: forming a groove penetrating the second dielectric layer along the first direction and extending into the first dielectric layer; the groove exposing the top surface of the first conductive structure in the first direction and exposing a side surface of the pad structure in the second direction; the first direction is perpendicular to the second direction; The second conductive structure is formed in the groove.

14. The manufacturing method according to claim 13, characterized in that: The forming of the second conductive structure in the groove includes: forming a barrier layer on the sidewalls and bottom surface of the groove; The second conductive structure is formed in the groove where the barrier layer is formed.

15. The manufacturing method according to claim 14, characterized in that: The method further comprises: forming a third conductive structure penetrating the second dielectric layer along the first direction and extending into the first dielectric layer, and arranging the third conductive structure and the second conductive structure spaced apart along the second direction; and A fourth conductive structure is formed in the first dielectric layer, and the fourth conductive structure is connected to the third conductive structure and the semiconductor structure respectively. Furthermore, the fourth conductive structure and the first conductive structure are spaced apart and arranged along the second direction.

16. The manufacturing method according to claim 14, characterized in that: The method further comprises: A first insulating layer is formed in the first dielectric layer and on a side of the first conductive structure away from the semiconductor structure along the first direction; wherein the second conductive structure penetrates the first insulating layer along the first direction and is connected to the first conductive structure.

17. The manufacturing method according to claim 16, characterized in that: The method further comprises: A second insulating layer is formed on a side of the second dielectric layer away from the first dielectric layer along the first direction, and the second insulating layer covers a top surface of the second conductive structure.

18. The manufacturing method according to claim 17, characterized in that: The method further comprises: forming a third dielectric layer on a side of the second insulating layer away from the second dielectric layer along the first direction; An interconnection structure is formed along the first direction, penetrating the third dielectric layer and the second insulating layer, and the interconnection structure is connected to the second conductive structure.

19. A method for testing a semiconductor device, characterized in that: The semiconductor device comprises the semiconductor device as claimed in claim 1; the method comprises: The semiconductor structure is tested by contacting the pad structure at the opening with a probe.

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