Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and relates to the field of semiconductors. The semiconductor structure comprises a substrate, a conductive layer and a connecting piece, the conductive layer is arranged on the substrate; the connecting piece is arranged on one side, deviating from the substrate, of the conductive layer; the cross-sectional area of one side, close to the conductive layer, of the connecting piece is larger than that of one side, away from the conductive layer, of the connecting piece, and the cross section of the connecting piece is perpendicular to the thickness direction of the substrate. The area of the conducting layer can be increased, the resistance value of the conducting layer is reduced, the reliability of the connecting piece is improved, and the performance of the high-bandwidth memory is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Compared with traditional memory technology, High Bandwidth Memory (HBM) has the advantages of high bandwidth, low transmission power consumption and small size. It is widely used in video memory and high-end servers.

[0003] The high bandwidth memory includes a multi-layer substrate, with a conductive layer (Under-bumping Metallurgy, referred to as UBM) and a connector (ie, bump) disposed on the top surface of the conductive layer between two adjacent substrates to achieve stacking connection of the multi-layer substrates through the conductive layer and the connector.

[0004] However, the conductive layer has a large resistance and poor reliability, which affects the performance of high-bandwidth memory. Summary of the invention

[0005] The present disclosure provides a semiconductor structure and a preparation method thereof, which are used to solve the problem that the resistance of the conductive layer is large, the reliability is poor, and the performance of the high-bandwidth memory is affected.

[0006] In a first aspect, the present disclosure provides a semiconductor structure, including a substrate, a conductive layer, and a connector;

[0007] The conductive layer is disposed on the substrate;

[0008] The connecting member is arranged on a side of the conductive layer away from the substrate;

[0009] The cross-sectional area of ​​the connecting member on a side close to the conductive layer is larger than the cross-sectional area of ​​the connecting member on a side away from the conductive layer, wherein the cross-sectional area of ​​the connecting member is perpendicular to the thickness direction of the substrate.

[0010] In the above semiconductor structure, optionally, along the thickness direction of the substrate, the connecting member has a first surface and a second surface that are oppositely arranged, the first surface faces the conductive layer, and the second surface faces away from the conductive layer;

[0011] A first portion of the first surface is attached to the conductive layer, a second portion of the first surface is not attached to the conductive layer, and an area of ​​the first portion of the first surface is greater than or equal to an area of ​​the second surface.

[0012] In the above semiconductor structure, optionally, the area of ​​the second portion of the first surface is less than or equal to a set area;

[0013] The set area is greater than or equal to one fifth of the area of ​​the first part of the first surface, and less than or equal to one third of the area of ​​the first part of the first surface.

[0014] In the above semiconductor structure, optionally, the number of the connecting members and the number of the conductive layers are both multiple, and the multiple connecting members and the multiple conductive layers are arranged at intervals along a direction parallel to the substrate;

[0015] Each of the connecting members is correspondingly arranged on a side of the conductive layer facing away from the substrate;

[0016] In a direction parallel to the substrate, each of the connecting members has a maximum dimension, two adjacent connecting members have a spacing, and each of the maximum dimensions is greater than or equal to the spacing.

[0017] In the above semiconductor structure, optionally, it further includes a sacrificial layer, the sacrificial layer is located between the conductive layer and the connecting member, and the sacrificial layer electrically connects the conductive layer and the connecting member;

[0018] The metal activity of the sacrificial layer is higher than the metal activity of the conductive layer.

[0019] In the above semiconductor structure, optionally, along the thickness direction of the substrate, the connector has a first surface and a second surface that are oppositely and parallelly arranged, the first surface is attached to the conductive layer, and the second surface is away from the conductive layer;

[0020] In a plane perpendicular to the thickness direction of the substrate, an area of ​​the sacrificial layer is larger than an area of ​​the conductive layer and smaller than an area of ​​the first surface.

[0021] In a second aspect, the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0022] providing a substrate;

[0023] forming an initial conductive layer, wherein the initial conductive layer covers the substrate;

[0024] forming a connector, wherein the connector is located on a side of the initial conductive layer away from the substrate, and a cross-sectional area of ​​a side of the connector close to the conductive layer is larger than a cross-sectional area of ​​a side of the connector away from the initial conductive layer, wherein the cross-sectional area is perpendicular to a thickness direction of the substrate;

[0025] Using the connecting member as a mask, a portion of the initial conductive layer is removed by etching to form a conductive layer.

[0026] In the above-mentioned method for preparing a semiconductor structure, optionally, forming a connecting member includes:

[0027] forming a mask layer, wherein the mask layer covers the surface of the initial conductive layer away from the substrate, and the mask layer has an opening; the opening size of the opening close to the substrate is smaller than the opening size of the opening away from the substrate;

[0028] forming the connecting member, wherein the connecting member is filled in the opening;

[0029] The mask layer is removed.

[0030] In the above-mentioned method for preparing the semiconductor structure, optionally, forming the connecting member specifically includes: forming the connecting member in the opening by electroplating, wherein the connecting member is electrically connected to the initial conductive layer.

[0031] In the above-mentioned method for preparing the semiconductor structure, along the direction away from the substrate, the opening size of the opening gradually decreases, and the cross-sectional area of ​​the connecting member gradually decreases.

[0032] In the above-mentioned method for preparing the semiconductor structure, along the thickness direction of the substrate, the connecting member has a first surface and a second surface that are arranged opposite to each other, the first surface is attached to the conductive layer, and the second surface is away from the conductive layer;

[0033] Etching and removing part of the initial conductive layer specifically includes: etching the initial conductive layer with an etching solution, so that the side surface of the conductive layer is concave at the edge of the first surface;

[0034] The portion of the first surface that is in contact with the conductive layer forms a first portion of the first surface, and the portion of the first surface that is not in contact with the conductive layer forms a second portion of the first surface. The area of ​​the first portion of the first surface is greater than or equal to the area of ​​the second surface.

[0035] In the above-mentioned method for preparing a semiconductor structure, after forming the initial conductive layer and before forming the connecting member, the method further includes:

[0036] forming an initial sacrificial layer, the initial sacrificial layer covering the initial conductive layer, the metal activity of the initial sacrificial layer being higher than the metal activity of the initial conductive layer;

[0037] Forming the connecting member includes: the connecting member covers the surface of the initial sacrificial layer away from the substrate;

[0038] Etching the initial conductive layer also includes: using the connecting member as a mask to etch away a portion of the initial sacrificial layer to form a sacrificial layer.

[0039] The present disclosure provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure includes a substrate, a conductive layer and a connector, wherein the conductive layer is arranged on the substrate, the connector is arranged on a side of the conductive layer away from the substrate, and the cross-sectional area of ​​the connector close to the conductive layer is larger than the cross-sectional area of ​​the connector away from the conductive layer.

[0040] In the process of preparing the above-mentioned semiconductor structure, when an initial conductive layer is formed on a substrate and then a part of the initial conductive layer is removed to form a conductive layer, the connector covering the initial conductive layer can play a certain barrier role on the initial conductive layer, and the cross-sectional area of ​​the connector close to the conductive layer is larger than the cross-sectional area of ​​the connector away from the conductive layer, thereby increasing the area of ​​the conductive layer, reducing the resistance of the conductive layer, improving the reliability of the connector, and improving the performance of the high-bandwidth memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0042] Figure 1 It is a structural schematic diagram of a semiconductor structure including a cylindrical connector in a related art;

[0043] Figure 2 A schematic diagram of a structure in which a semiconductor structure including a cylindrical connector is removed from a portion of an initial conductive layer to form a conductive layer in a related art;

[0044] Figure 3 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0045] Figure 4 A schematic structural diagram of a semiconductor structure according to another embodiment of the present disclosure;

[0046] Figure 5 A top view of a semiconductor structure provided by an embodiment of the present disclosure;

[0047] Figure 6 A schematic structural diagram of a semiconductor structure in which the area of ​​the first portion of the first surface is larger than the area of ​​the second surface provided in an embodiment of the present disclosure;

[0048] Figure 7 A schematic structural diagram of a semiconductor structure in which the area of ​​the first portion of the first surface is equal to the area of ​​the second surface provided in an embodiment of the present disclosure;

[0049] Figure 8 A schematic diagram of a process for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0050] Fig. 9A schematic structural diagram of a substrate with a receiving groove provided in an embodiment of the present disclosure;

[0051] Fig.10 A schematic diagram of a structure for forming an initial conductive layer provided in an embodiment of the present disclosure;

[0052] Fig.11 A schematic diagram of a structure for forming an initial sacrificial layer provided in an embodiment of the present disclosure;

[0053] Fig.12 A schematic diagram of a structure for forming a mask layer with an opening provided in an embodiment of the present disclosure;

[0054] Fig.13 A schematic diagram of a structure of a connecting member provided in an embodiment of the present disclosure;

[0055] Fig.14 A schematic diagram of the structure for removing the mask layer provided in an embodiment of the present disclosure.

[0056] Description of reference numerals:

[0057] 100, substrate; 110, receiving groove; 200, conductive layer; 200a, initial conductive layer; 300, sacrificial layer; 300a, initial sacrificial layer; 400, connector; 400a, cylindrical connector; 500, mask layer; 510, opening; 600, solder.

[0058] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0059] Reference Figure 1 and Figure 2 The high bandwidth memory includes a multi-layer substrate 100, and a conductive layer 200 is arranged between two adjacent substrates 100. The conductive layer 200 may be an under-bumping metallurgy (UBM) and a connector 400 (i.e., a bump) arranged on the top surface of the conductive layer 200, so as to realize stacking connection of the multi-layer substrates 100 through the conductive layer 200 and the connector. In the preparation process of the above semiconductor structure, an initial conductive layer 200a is usually formed on the substrate 100, and then a connector 400 is formed on the side of the initial conductive layer 200a away from the substrate 100, and then a portion of the initial conductive layer 200a not covering the connector 400 is removed by etching, so that a portion of the initial conductive layer 200a covering the connector 400 forms a conductive layer 200, so that each connector 400 can be connected to the substrate 100 through a conductive layer 200.

[0060] In the related art, the connector 400 is set as a cylindrical connector 400a, and the cross-sectional area of ​​the cylindrical connector 400a on the side close to the initial conductive layer 200a is equal to the cross-sectional area of ​​the cylindrical connector 400a on the side away from the initial conductive layer 200a. When the part of the initial conductive layer 200a not covering the cylindrical connector 400a is removed by etching, part of the initial conductive layer 200a covering the cylindrical connector 400a will also be etched away, so that the contact area between the conductive layer 200 and the cylindrical connector 400a is reduced, the resistance of the conductive layer 200 is large, and the reliability of the cylindrical connector 400a connected to the conductive layer 200 is poor, which affects the performance of the high-bandwidth memory.

[0061] In view of this, the present disclosure provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure includes a substrate, a conductive layer and a connector, wherein the conductive layer is arranged on the substrate, the connector is arranged on a side of the conductive layer away from the substrate, and the cross-sectional area of ​​the connector close to the conductive layer is larger than the cross-sectional area of ​​the connector away from the conductive layer.

[0062] In the process of preparing the above-mentioned semiconductor structure, when an initial conductive layer is formed on a substrate and then a part of the initial conductive layer is etched away, relative to the cylindrical connector in the related art, the cross-sectional area of ​​the connector on the side close to the conductive layer is larger than the cross-sectional area of ​​the connector on the side away from the conductive layer, so that the area of ​​the initial conductive layer covering the connector is increased, thereby increasing the area of ​​the initial conductive layer remaining after etching and removal, increasing the contact area between the conductive layer and the connector, reducing the resistance of the conductive layer, and improving the reliability of the connector, thereby improving the performance of the high-bandwidth memory.

[0063] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0064] In order to make the purpose, technical solution and advantages of the present disclosure clearer, the technical solution in the embodiment of the present disclosure will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present disclosure. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limitations on the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure. The embodiments of the present disclosure are described in detail below in conjunction with the drawings.

[0065] Reference Figure 3 and Figure 4 In a first aspect, the present disclosure provides a semiconductor structure, including a substrate 100, a conductive layer 200 and a connector 400, wherein the conductive layer 200 is disposed on the substrate 100, and the connector 400 is disposed on a side of the conductive layer 200 away from the substrate 100, each connector 400 can be connected to the substrate 100 through a conductive layer 200, and a cross-sectional area of ​​a side of the connector 400 close to the conductive layer 200 is larger than a cross-sectional area of ​​a side of the connector 400 away from the conductive layer 200, wherein a cross-sectional area of ​​the connector 400 can be perpendicular to a thickness direction of the substrate 100.

[0066] As a feasible implementation manner, along the thickness direction of the substrate 100, the connector 400 may have a first surface and a second surface that are relatively arranged, wherein the first surface of the connector 400 faces the conductive layer 200, and the second surface of the connector 400 faces away from the conductive layer 200; the first portion of the first surface of the connector 400 is attached to the conductive layer 200, and the second portion of the first surface of the connector 400 is not attached to the conductive layer 200, and the area of ​​the first portion of the first surface of the connector 400 may be greater than or equal to the area of ​​the second surface of the connector 400.

[0067] In the process of preparing the semiconductor structure, an initial conductive layer 200a may be formed on the substrate 100, and then a connector 400 may be formed on a side of the initial conductive layer 200a away from the substrate 100, wherein a first surface of the connector 400 faces the initial conductive layer 200a, and a second surface of the connector 400 faces away from the initial conductive layer 200a;

[0068] Reference Figure 3 and Figure 4, and then remove the portion of the initial conductive layer 200a not covering the connector 400 by etching, so that the portion of the initial conductive layer 200a covering the connector 400 forms a conductive layer 200, so that each connector 400 can be connected to the substrate 100 through a conductive layer 200, and the area of ​​the first portion of the first surface of the connector 400 is greater than or equal to the area of ​​the second surface of the connector 400, that is, the area of ​​the conductive layer 200 is greater than or equal to the area of ​​the second surface of the connector 400.

[0069] It should be noted that, refer to Figure 1 and Figure 2 When the connector 400 is set as a cylindrical connector 400a, during the preparation process of the semiconductor structure, the cross-sectional area of ​​the cylindrical connector 400a on the side close to the initial conductive layer 200a is equal to the cross-sectional area of ​​the cylindrical connector 400a on the side away from the initial conductive layer 200a. When the portion of the initial conductive layer 200a not covering the cylindrical connector 400a is removed by etching, part of the initial conductive layer 200a covering the cylindrical connector 400a will also be etched away, so that the contact area between the conductive layer 200 and the cylindrical connector 400a is reduced, and the area of ​​the conductive layer 200 is smaller than the area of ​​the second surface of the connector 400.

[0070] With respect to the cylindrical connector 400a, the cross-sectional area of ​​the connector 400 on the side close to the conductive layer 200 is set to be larger than the cross-sectional area of ​​the connector 400 on the side away from the conductive layer 200, so that the area of ​​the conductive layer 200 can be greater than or equal to the area of ​​the second surface of the connector 400, thereby increasing the contact area between the conductive layer 200 and the cylindrical connector 400a, reducing the resistance of the conductive layer 200, and improving the reliability of the connector 400, thereby improving the performance of the high-bandwidth memory.

[0071] As a feasible implementation, the substrate 100 may include one or more grains (ie, dies), and the material of the substrate 100 may be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, or silicon-on-insulator (SOI), or other materials known to those skilled in the art.

[0072] The number of connectors 400 and conductive layers 200 can be set to multiple, multiple connectors 400 can be arranged at intervals in a direction parallel to the substrate 100, and multiple conductive members can be arranged at intervals in a direction perpendicular to the thickness of the substrate 100; each connector 400 can be connected to the substrate 100 through a conductive layer 200, and each connector 400 is correspondingly arranged on the side of the conductive layer 200 facing away from the substrate 100.

[0073] Reference Figure 5The area of ​​the first portion of the first surface of the connector 400 can be large, and the area of ​​the second surface of the connector 400 is parallel to the substrate 100. Each connector 400 has a maximum size (i.e. Figure 5 d), it should be noted that the maximum size can be used to represent the maximum distance between any two points on the edge of the connector 400 in a direction parallel to the substrate 100.

[0074] For example, in a plane parallel to the substrate 100, the connector 400 can be set to a circle, and the maximum size of the connector 400 is set to the diameter of the connector 400; or, in a plane parallel to the substrate 100, the connector 400 can be set to a rectangle or a square, and the maximum size of the connector 400 is set to the diagonal length of the connector 400.

[0075] In the direction parallel to the substrate 100, there is a distance between two adjacent connecting members 400 (ie Figure 5 w) in order to reduce the possibility of mutual conduction between two adjacent connectors 400; in two adjacent connectors 400, the spacing can be used to represent the distance between the edge of one connector 400 and the edge of the other connector 400, and the maximum size of each connector 400 is greater than or equal to the spacing.

[0076] As a feasible implementation, the conductive layer 200 can be directly disposed on the surface of the substrate 100, or the substrate 100 can be provided with a receiving groove 110, the receiving groove 110 is used to accommodate the conductive layer 200, and the receiving groove 110 can be coaxially arranged with the connector 400, and the number of receiving grooves 110 can be multiple, and the multiple receiving grooves 110 are arranged one-to-one with the multiple conductive layers 200.

[0077] The conductive layer 200 may include a first part and a second part connected to each other, wherein the first part of the conductive layer 200 is located in the receiving groove 110, and the second part of the conductive layer 200 is located outside the receiving groove 110, and in a plane parallel to the substrate 100, the second part of the conductive layer 200 surrounds the outer side of the first part of the conductive layer 200.

[0078] As a feasible implementation, in a plane parallel to the substrate 100, the connector 400 is configured to be circular, and multiple connectors 400 can be arranged in multiple rows and columns, and the spacing between connectors 400 in the same row can be equal to the spacing between connectors 400 in the same column. In two adjacent connectors 400 in the same row or two adjacent connectors 400 in the same column, the spacing can be used to indicate the distance between the edges of the two connectors 400 in the direction of the line connecting the centers of the two connectors 400.

[0079] It is easy to understand that, in a plane parallel to the substrate 100, the arrangement of the multiple connectors 400 can be adjusted according to the setting method of the substrate 100. For example, the multiple connectors 400 can form several connector 400 assemblies, and the maximum size of two adjacent connectors 400 in each connector 400 group is greater than or equal to the spacing, and the maximum size of two connectors 400 in different connector 400 groups can be less than the spacing, so as to make the arrangement of the multiple connectors 400 more flexible.

[0080] In the group of connectors 400, the number of connectors 400 can be set to one or several. When the number of connectors 400 is set to several, the several connectors 400 can be arranged in an array, and the spacing between two adjacent connectors 400 can be the same. Alternatively, the several connectors 400 can also be arranged irregularly, and the spacing between two adjacent connectors 400 can be different.

[0081] In a plane parallel to the substrate 100, several connectors 400 may have the same shape, for example, the shapes of several connectors 400 may all be set to be square or circular; or, several connectors 400 may have different shapes, for example, the shape of a first portion of connectors 400 among several connectors 400 may be set to be square, and the shape of a second portion of connectors 400 among several connectors 400 may be set to be circular.

[0082] As a feasible implementation manner, along the thickness direction of the substrate 100, the connector 400 may have a first surface and a second surface that are relatively arranged, wherein the first surface of the connector 400 faces the conductive layer 200, and the second surface of the connector 400 faces away from the conductive layer 200. The second surface of the connector 400 can be used to connect other substrates 100 or components and other structures. For example, the second surface of the connector 400 can be connected to other substrates 100 or components and other structures through solder 600.

[0083] The first portion of the first surface of the connector 400 is attached to the conductive layer 200, and the second portion of the first surface of the connector 400 is not attached to the conductive layer 200. Figure 6 , the area of ​​the first portion of the first surface of the connector 400 may be greater than the area of ​​the second surface of the connector 400; or, referring to Figure 7 , the area of ​​the first portion of the first surface of the connecting member 400 may also be equal to the area of ​​the second surface of the connecting member 400 .

[0084] The connector 400 may be a truncated cone connector 400 , the axis direction of which is parallel to the thickness direction of the substrate 100 , the first surface of which is a circular surface, and the second surface of which is a circular surface.

[0085] Reference Figure 4 and Figure 5 When the portion of the initial conductive layer 200a not covering the connector 400 is removed by etching to form the conductive layer 200 by the portion of the initial conductive layer 200a covering the connector 400, the portion of the initial conductive layer 200a covering the truncated cone-shaped connector 400 is circular in shape, and the diameter of the portion of the initial conductive layer 200a covering the truncated cone-shaped connector 400 is smaller than the diameter of the second surface of the truncated cone-shaped connector 400, so that the shape of the conductive layer 200 is circular, and the conductive layer 200 is coaxially arranged with the truncated cone-shaped connector 400.

[0086] The connector 400 can be set as a prism-shaped connector 400, the axial direction of the truncated cone-shaped connector 400 is parallel to the thickness direction of the substrate 100, and the first surface of the prism-shaped connector 400 is set as a polygonal surface, and the second surface of the prism-shaped connector 400 is set as a polygonal surface. For example, the polygonal surface can be set as one of a triangular surface, a quadrilateral surface, a pentagonal surface and a hexagonal surface.

[0087] When the portion of the initial conductive layer 200a not covering the connector 400 is removed by etching to form the conductive layer 200 with the portion of the initial conductive layer 200a covering the connector 400, the portion of the initial conductive layer 200a covering the prism-shaped connector 400 is polygonal in shape, and the size of the portion of the initial conductive layer 200a covering the prism-shaped connector 400 is smaller than the size of the second surface of the truncated cone-shaped connector 400, so that the shape of the conductive layer 200 is polygonal, and the conductive layer 200 is coaxially arranged with the truncated cone-shaped connector 400.

[0088] As a feasible implementation manner, the first portion of the first surface of the connector 400 is adhered to the conductive layer 200, and the second portion of the first surface of the connector 400 is not adhered to the conductive layer 200. The area of ​​the first portion of the first surface of the connector 400 may be greater than or equal to the area of ​​the second surface of the connector 400, that is, the area of ​​the conductive layer 200 may be greater than or equal to the area of ​​the second surface of the connector 400.

[0089] The area of ​​the second portion of the first surface may be less than or equal to a set area, wherein the set area may be greater than or equal to one fifth of the area of ​​the first portion of the first surface and less than or equal to one third of the area of ​​the first portion of the first surface.

[0090] For example, the set area can be equal to one-fifth of the area of ​​the first part of the first surface, the area of ​​the second part of the first surface is less than or equal to one-fifth of the area of ​​the first part of the first surface, and in the first surface of the connector 400, the area of ​​the second part can be set to one of one-fifth, one-sixth and one-seventh of the area of ​​the first part.

[0091] Alternatively, the set area can also be equal to one-fourth of the area of ​​the first part of the first surface, the area of ​​the second part of the first surface is less than or equal to one-fourth of the area of ​​the first part of the first surface, and in the first surface of the connecting member 400, the area of ​​the second part can be set to one of one-fourth, one-fifth and one-sixth of the area of ​​the first part.

[0092] Alternatively, the set area can also be equal to one third of the area of ​​the first part of the first surface, the area of ​​the second part of the first surface is less than or equal to one third of the area of ​​the first part of the first surface, and in the first surface of the connecting member 400, the area of ​​the second part can be set to one of one third, one quarter and one fifth of the area of ​​the first part.

[0093] It is easy to understand that when the connector 400 is set as a cylindrical connector 400a, the first surface of the cylindrical connector 400a is set the same as the second surface of the cylindrical connector 400a; the first part of the first surface of the cylindrical connector 400a is attached to the conductive layer 200, and the second part of the first surface of the cylindrical connector 400a is not attached to the conductive layer 200.

[0094] The area of ​​the first portion of the first surface of the cylindrical connector 400a is less than or equal to the area of ​​the second surface of the cylindrical connector 400a, the area of ​​the conductive layer 200 is equal to the area of ​​the first portion of the cylindrical connector 400a, and the area of ​​the conductive layer 200 is less than the area of ​​the second surface of the cylindrical connector 400a.

[0095] Relative to the cylindrical connector 400a, when the area of ​​the first surface of the connector 400 is greater than the area of ​​the second surface of the connector 400, the area of ​​the conductive layer 200 can be greater than or equal to the area of ​​the second surface of the connector 400, thereby increasing the contact area between the conductive layer 200 and the connector 400, reducing the resistance of the conductive layer 200, and improving the reliability of the connector 400, thereby improving the performance of the memory.

[0096] Reference Figure 6 and Figure 7 As a feasible implementation, the semiconductor structure may further include a sacrificial layer 300. The sacrificial layer 300 may be located between the conductive layer 200 and the connector 400. The sacrificial layer 300 electrically connects the conductive layer 200 and the connector 400. The metal activity of the sacrificial layer 300 is higher than the metal activity of the conductive layer 200. The sacrificial layer 300 can protect the conductive layer 200 to a certain extent and increase the area of ​​the conductive layer 200.

[0097] For example, when the material of the conductive layer 200 is set to metal copper (chemical formula is Cu), the metal activity of the sacrificial layer 300 is higher than that of metal copper, and the material of the sacrificial layer 300 can be set to metal nickel (chemical formula is Ni) or metal aluminum (chemical formula is Al).

[0098] When the portion of the initial conductive layer 200a not covering the connector 400 is removed by etching, the sacrificial layer 300 can form a primary battery with the conductive layer 200, and the sacrificial layer 300 forms the negative electrode of the primary battery, and the conductive layer 200 forms the positive electrode of the primary battery, so as to increase the area of ​​the conductive layer 200 by providing the sacrificial layer 300 to protect the portion of the initial conductive layer 200a covering the connector 400.

[0099] In a plane perpendicular to the thickness direction of the substrate 100 , the area of ​​the sacrificial layer 300 may be larger than the area of ​​the conductive layer 200 , and the area of ​​the sacrificial layer 300 may be smaller than the area of ​​the first surface of the connector 400 .

[0100] It is easy to understand that the first part of the sacrificial layer 300 can cover the surface of the conductive layer 200 facing away from the substrate 100, and the second part of the sacrificial layer 300 can surround the outside of the conductive layer 200 to increase the contact area between the sacrificial layer 300 and the conductive layer 200, thereby improving the protective effect of the sacrificial layer 300 on the conductive layer 200.

[0101] To sum up, in the process of preparing the above-mentioned semiconductor structure, a receiving groove 110 can be formed on the substrate 100, and an initial conductive layer 200a can be formed on the substrate 100, so that part of the initial conductive layer 200a is located in the receiving groove 110, and the rest of the initial conductive layer 200a is located outside the receiving groove 110; then when etching away part of the initial conductive layer 200a, relative to the cylindrical connector 400a in the related art, the cross-sectional area of ​​the connector 400 close to the conductive layer 200 is greater than the cross-sectional area of ​​the connector 400 away from the conductive layer 200, so that the area of ​​the initial conductive layer 200a covering the connector 400 is increased, thereby increasing the area of ​​the remaining part of the initial conductive layer 200a after etching and removal, increasing the contact area between the conductive layer 200 and the connector 400, reducing the resistance of the conductive layer 200, and improving the reliability of the connector 400, thereby improving the performance of the high-bandwidth memory.

[0102] In a second aspect, the present disclosure provides a method for preparing a semiconductor structure. Figure 8 A schematic diagram of a process for preparing a semiconductor structure provided by an embodiment of the present disclosure. Figure 8 As shown, the preparation method includes: S100, providing a substrate;

[0103] The substrate 100 may include one or more grains (ie, dies), and the material of the substrate 100 may be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, or silicon-on-insulator (SOI), or other materials known to those skilled in the art.

[0104] Reference Fig. 9 One or more receiving grooves 110 may be formed on the substrate 100. The receiving grooves 110 may be arranged in one-to-one correspondence with the connectors 400, and the receiving grooves 110 may be used to accommodate the subsequent conductive layer 200 and the connector 400 to make the connection between the connector 400 and the substrate 100 more stable.

[0105] After providing the substrate 100, the preparation method further includes: S200, forming an initial conductive layer, wherein the initial conductive layer covers the substrate;

[0106] As a feasible implementation, the initial conductive layer 200a can be formed by deposition, for example, the deposition method can be a chemical vapor deposition process (Chemical Vapor Deposition, referred to as CVD), a physical vapor deposition process (Physical Vapor Deposition, referred to as PVD) or an atomic layer deposition process (Atomic Layer Deposition, referred to as ALD).

[0107] Reference Fig. 9 and Fig.10 The material of the initial conductive layer 200a can be set to metal copper (chemical formula is Cu) or the like, and part of the initial conductive layer 200a can be located in the receiving groove 110, and the rest of the initial conductive layer 200a can be located outside the receiving groove 110. A depression is formed on the surface of the initial conductive layer 200a facing away from the substrate 100, and the depression is correspondingly arranged in the receiving groove 110, and the part of the initial conductive layer 200a located in the receiving groove 110 is electrically connected to the part of the initial conductive layer 200a located outside the receiving groove 110.

[0108] Reference Fig.10 and Fig.11 After the initial conductive layer 200a is formed, an initial sacrificial layer 300a can also be formed on the surface of the initial conductive layer 200a facing away from the substrate 100. For example, the initial sacrificial layer 300a can be formed by deposition or the like. The metal activity of the initial sacrificial layer 300a is higher than the metal activity of the initial conductive layer 200a. The initial sacrificial layer 300a can protect part of the initial conductive layer 200a to a certain extent, thereby increasing the area of ​​the conductive layer 200 formed subsequently.

[0109] For example, when the material of the initial conductive layer 200a is set to metal copper (chemical formula Cu), the metal activity of the initial sacrificial layer 300a is higher than the metal activity of metal copper, and the material of the initial sacrificial layer 300a can be set to metal nickel (chemical formula Ni) or metal aluminum (chemical formula Al). For example, when the material of the initial sacrificial layer 300a is set to metal aluminum, it can be formed by a physical vapor deposition process.

[0110] After forming the initial conductive layer 200a, the preparation method further includes: S300, forming a connector; the connector 400 is located on a side of the initial conductive layer 200a away from the substrate 100, and the cross-sectional area of ​​the connector 400 close to the conductive layer 200 is larger than the cross-sectional area of ​​the connector 400 away from the initial conductive layer 200a, wherein the cross section is perpendicular to the thickness direction of the substrate 100;

[0111] Reference Fig.11 and Fig.12 As a feasible implementation, forming the connector 400 may include: forming a mask layer 500, the mask layer 500 covers the surface of the initial conductive layer 200a facing away from the substrate 100, and the mask layer 500 has an opening 510, the opening 510 is a depression facing the initial conductive layer 200a, and each opening 510 is correspondingly arranged in a depression; the size of the opening 510 on the side of the opening 510 close to the substrate 100 is smaller than the size of the opening 510 on the side facing away from the substrate 100, and the size of the opening 510 on the side of the opening 510 close to the substrate 100 is larger than the size of the accommodating groove 110.

[0112] As a feasible implementation manner, the size of the opening 510 gradually decreases along the direction away from the substrate 100 , so that the cross-sectional area of ​​the connecting member 400 formed in the opening 510 gradually decreases.

[0113] Reference Fig.12 and Fig.13 After forming the mask layer 500, a connector 400 is formed, and the connector 400 is filled in the opening 510; illustratively, the connector 400 can be formed in the opening 510 by electroplating, so that the connector 400 is electrically connected to the initial conductive layer 200a, and a portion of the connector 400 is filled in the recess of the initial conductive layer 200a.

[0114] Alternatively, the opening 510 may be filled with a connection material by deposition or the like, so that the connection material fills the opening 510 , so that the connection material filled in the opening 510 can form a connection member 400 , and a portion of the connection member 400 fills the recess of the initial conductive layer 200 a .

[0115] The cross-sectional area of ​​the connector 400 on the side close to the initial conductive layer 200a may be greater than the cross-sectional area of ​​the connector 400 on the side facing away from the initial conductive layer 200a. For example, in a direction parallel to the thickness of the substrate 100, the connector 400 may have a first surface and a second surface relative to each other. The first surface of the connector 400 may be attached to the surface of the sacrificial layer 300 facing away from the substrate 100, and the second surface of the connector 400 faces away from the sacrificial layer 300.

[0116] The first surface of the connector 400 is electrically connected to the conductive layer 200 through the sacrificial layer 300, and the second surface of the connector 400 is used to connect components or other structures such as the substrate 100, and the area of ​​the first surface of the connector 400 is larger than the area of ​​the second surface of the connector 400. Along the direction away from the substrate 100, the cross-sectional area of ​​the connector 400 located outside the recess can gradually decrease.

[0117] It is easy to understand that the shape of the connecting member 400 can be the same as the shape of the corresponding opening 510. For example, the connecting member 400 can be set as a truncated cone-shaped connecting member 400 or a prism-shaped connecting member 400. The specific setting method of the connecting member 400 can refer to the above, and the embodiments of the present application will not be repeated here.

[0118] Reference Fig.13 and Fig.14 After forming the connector 400, the mask layer 500 is removed to expose the connector 400. For example, the mask layer 500 can be removed by etching or the like to expose the connector 400 located in the opening 510 of the mask layer 500, and the first surface of the connector 400 is electrically connected to the substrate 100 through the sacrificial layer 300.

[0119] Reference Fig.14 and Figure 6 After removing the mask layer 500 to expose the connector 400, the preparation method further includes: S400, using the connector as a mask, etching and removing part of the initial conductive layer to form a conductive layer; wherein the conductive layer 200 includes a first part and a second part that are connected to each other, the first part of the conductive layer 200 is located in the receiving groove 110, and the second part of the conductive layer 200 is located outside the receiving groove 110, and in a plane parallel to the substrate 100, the second part of the conductive layer 200 surrounds the outer side of the first part of the conductive layer 200.

[0120] Etching and removing part of the initial conductive layer 200a specifically includes: etching the initial conductive layer 200a with an etching solution to remove part of the initial conductive layer 200a between two adjacent connectors 400 through the etching solution, so that the remaining part of the initial conductive layer 200a forms a conductive layer 200, and the side surface of the formed conductive layer 200 is concave at the edge of the first surface of the connector 400.

[0121] It should be noted that, with the connector 400 as a mask, the etching liquid can flow from between adjacent connectors 400 toward the initial conductive layer 200a, so that the etching liquid can contact the portion of the initial conductive layer 200a between two adjacent connectors 400, so as to remove the portion of the initial conductive layer 200a not covering the connector 400 by the etching liquid, thereby forming a conductive layer 200 by covering the portion of the initial conductive layer 200a covering the connector 400.

[0122] When the etching liquid contacts the initial conductive layer 200a to remove part of the initial conductive layer 200a, part of the etching liquid will flow to the initial conductive layer 200a covering the connector 400, so that part of the initial conductive layer 200a covering the connector 400 will react with the etching liquid. The size of the initial conductive layer 200a covering the connector 400 is smaller than the size of the first surface of the connector 400, and the side of the conductive layer 200 formed is concave at the edge of the first surface of the connector 400.

[0123] Among them, the part of the first surface of the connector 400 that is attached to the conductive layer 200 forms the first part of the first surface, and the part of the first surface of the connector 400 that is not attached to the conductive layer 200 forms the second part of the first surface. The area of ​​the first part of the first surface is greater than or equal to the area of ​​the second surface, that is, the area of ​​the conductive layer 200 is greater than or equal to the area of ​​the second surface.

[0124] In the initial conductive layer 200a covered with the connector 400, the first portion of the initial conductive layer 200a is not in contact with the etching solution, and the first portion of the first surface facing the first portion of the initial conductive layer 200a is adhered to the first portion of the initial conductive layer 200a. When the first portion of the initial conductive layer 200a forms the conductive layer 200, the first portion of the first surface is adhered to the conductive layer 200.

[0125] The second initial conductive layer 200a contacts the etching solution, and the second portion of the first surface facing the second initial conductive layer 200a is exposed. When the first initial conductive layer 200a forms the conductive layer 200 , the second portion of the first surface is not attached to the conductive layer 200 .

[0126] It is easy to understand that the area of ​​the first surface of the connector 400 is greater than the area of ​​the second surface of the connector 400, so that the area of ​​the first part of the first surface of the connector 400 can be greater than or equal to the area of ​​the second surface of the connector 400, thereby making the area of ​​the conductive layer 200 greater than or equal to the area of ​​the second surface of the connector 400.

[0127] It should be noted that when the connector 400 is set as a cylindrical connector 400a, the first surface of the cylindrical connector 400a is set the same as the second surface of the cylindrical connector 400a; the first part of the first surface of the cylindrical connector 400a is attached to the conductive layer 200, and the second part of the first surface of the cylindrical connector 400a is not attached to the conductive layer 200.

[0128] In the initial conductive layer 200a covering the cylindrical connector 400a, the first portion of the initial conductive layer 200a does not react with the etching solution, and the first portion of the first surface facing the first portion of the initial conductive layer 200a is adhered to the first portion of the initial conductive layer 200a. When the first portion of the initial conductive layer 200a forms the conductive layer 200, the first portion of the first surface is adhered to the conductive layer 200.

[0129] The second initial conductive layer 200a reacts with the etching solution to expose the second portion of the first surface of the second initial conductive layer 200a. When the first initial conductive layer 200a forms the conductive layer 200, the second portion of the first surface is not attached to the conductive layer 200.

[0130] It is easy to understand that the area of ​​the first surface of the cylindrical connector 400a is equal to the area of ​​the second surface of the cylindrical connector 400a, so that the area of ​​the first part of the first surface of the connector 400 is smaller than the area of ​​the second surface of the connector 400, thereby making the area of ​​the conductive layer 200 smaller than the area of ​​the second surface of the connector 400;

[0131] When the area of ​​the second surface of the connector 400 is the same, relative to the cylindrical connector 400a, the area of ​​the first surface of the connector 400 is greater than the area of ​​the second surface of the connector 400, so that the area of ​​the conductive layer 200 can be greater than or equal to the area of ​​the second surface of the connector 400, thereby increasing the area of ​​the conductive layer 200, increasing the contact area between the conductive layer 200 and the connector 400, reducing the resistance of the conductive layer 200, and improving the reliability of the connector 400, thereby improving the performance of the high-bandwidth memory.

[0132] Furthermore, the second surface of the connector 400 is used to connect components or other structures such as the substrate 100, and a certain interval is required between the second surfaces of two adjacent connectors 400 to reduce the possibility of a short circuit between the two adjacent connectors 400;

[0133] By setting the area of ​​the first surface of the connector 400 to be larger than the area of ​​the second surface of the connector 400 , a larger interval is created between the second surfaces of two adjacent connectors 400 , and the area of ​​the conductive layer 200 can also be larger than or equal to the area of ​​the second surface of the connector 400 .

[0134] As a feasible implementation, in the first surface of the connector 400, the area of ​​the second portion of the first surface may be less than or equal to a set area, wherein the set area may be greater than or equal to one-fifth of the area of ​​the first portion of the first surface and less than or equal to one-third of the area of ​​the first portion of the first surface.

[0135] In the initial conductive layer 200a covered with the connector 400, the first portion of the initial conductive layer 200a is not in contact with the etching solution, and the second portion of the initial conductive layer 200a is in contact with the etching solution; when part of the initial conductive layer 200a is etched away, the area of ​​the second portion of the initial conductive layer 200a is less than or equal to the set area, the set area is greater than or equal to one-fifth of the area of ​​the first portion of the initial conductive layer 200a, and the set area is less than or equal to one-third of the area of ​​the first portion of the initial conductive layer 200a.

[0136] The process of etching the initial conductive layer 200 a with an etching solution also includes: using the connector 400 as a mask to etch away a portion of the initial sacrificial layer 300 a to form a sacrificial layer 300 .

[0137] In some embodiments, since the initial sacrificial layer 300a covers the surface of the initial conductive layer 200a facing away from the substrate 100, during the process of etching the initial conductive layer 200a with an etching solution, the etching solution will contact the initial sacrificial layer 300a, so that part of the initial sacrificial layer 300a is removed to form the sacrificial layer 300, and the initial conductive layer 200a is exposed, so that the etching solution can contact the initial conductive layer 200a.

[0138] It should be noted that, in the process of etching the initial conductive layer 200a with an etching solution, the etching solution contacts the initial sacrificial layer 300a and the initial conductive layer 200a, so that the initial sacrificial layer 300a can form a primary battery with the initial conductive layer 200a, and the metal activity of the initial sacrificial layer 300a is higher than the metal activity of the initial conductive layer 200a, so that the initial sacrificial layer 300a forms the negative electrode of the primary battery, and the initial conductive layer 200a forms the positive electrode of the primary battery, thereby increasing the area of ​​the conductive layer 200 by providing the initial sacrificial layer 300a to protect the portion of the initial conductive layer 200a covering the connector 400.

[0139] In summary, in the process of preparing the semiconductor structure, a receiving groove 110 may be first formed on the surface of the substrate 100, and then an initial conductive layer 200a may be formed on the surface of the substrate 100, a portion of the initial conductive layer 200a may be located in the receiving groove 110, and the remaining portion of the initial conductive layer 200a may be located outside the receiving groove 110, and a depression is formed on the surface of the initial conductive layer 200a away from the substrate 100; then, an initial sacrificial layer 300a is formed on the surface of the initial conductive layer 200a away from the substrate 100, and the metal activity of the initial sacrificial layer 300a is higher than the metal activity of the initial conductive layer 200a;

[0140] A mask layer 500 is formed on the surface of the initial sacrificial layer 300a away from the initial conductive layer 200a, and the mask layer 500 has an opening 510, the opening 510 is recessed toward the initial conductive layer 200a, the size of the opening 510 on the side of the opening 510 close to the substrate 100 is smaller than the size of the opening 510 on the side away from the substrate 100, and the size of the opening 510 on the side of the opening 510 close to the substrate 100 is larger than the size of the receiving groove 110; a connector 400 is formed in the opening 510 by electroplating or deposition, and the mask layer 500 is removed to expose the connector 400, and the cross-sectional area of ​​the connector 400 on the side close to the substrate 100 is larger than the cross-sectional area of ​​the connector 400 on the side away from the substrate 100;

[0141] Subsequently, the connector 400 is used as a mask to etch away the portion of the initial conductive layer 200a not covering the connector 400, and the portion of the initial conductive layer 200a covering the connector 400 forms the conductive layer 200. The initial sacrificial layer 300a can form a primary battery with the initial conductive layer 200a, the initial sacrificial layer 300a forms the negative electrode of the primary battery, and the initial conductive layer 200a forms the positive electrode of the primary battery. Thus, by providing the initial sacrificial layer 300a to protect the portion of the initial conductive layer 200a covering the connector 400, the area of ​​the conductive layer 200 is increased, so that the area of ​​the conductive layer 200 can be greater than or equal to the cross-sectional area of ​​the connector 400 facing away from the substrate 100, thereby increasing the contact area between the conductive layer 200 and the connector 400, reducing the resistance of the conductive layer 200, and improving the reliability of the connector 400, thereby improving the performance of the high-bandwidth memory.

[0142] In a third aspect, an embodiment of the present disclosure provides a memory, which may include the above-mentioned semiconductor structure. The memory may include, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), or a magnetoresistive random access memory (MRAM). The non-storage device may be a logic device (such as a microprocessor, a digital signal processor, or a microcontroller) or a device similar thereto.

[0143] The semiconductor structure in the memory in this embodiment is the same as that in the above-mentioned embodiment, and can achieve the same technical effects as those thereof, which will not be described in detail here.

[0144] In the description of the embodiments of the present disclosure, it should be understood that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances. The orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

[0145] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0146] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, It is characterized in that comprising a substrate, a conductive layer and a connecting member; The conductive layer is disposed on the substrate; The connecting member is arranged on a side of the conductive layer away from the substrate; The cross-sectional area of ​​the connecting member on a side close to the conductive layer is larger than the cross-sectional area of ​​the connecting member on a side away from the conductive layer, wherein the cross-sectional area of ​​the connecting member is perpendicular to the thickness direction of the substrate.

2. The semiconductor structure according to claim 1, It is characterized in that Along the thickness direction of the substrate, the connecting member has a first surface and a second surface that are arranged opposite to each other, the first surface faces the conductive layer, and the second surface faces away from the conductive layer; A first portion of the first surface is attached to the conductive layer, a second portion of the first surface is not attached to the conductive layer, and an area of ​​the first portion of the first surface is greater than or equal to an area of ​​the second surface; In a direction perpendicular to the thickness of the substrate, the cross-sectional area of ​​the first surface is larger than the cross-sectional area of ​​the surface of the conductive layer opposite to the first surface, and the cross-sectional area of ​​the second surface is not larger than the cross-sectional area of ​​the surface of the conductive layer opposite to the first surface.

3. The semiconductor structure according to claim 2, It is characterized in that The area of ​​the second portion of the first surface is less than or equal to a set area; The set area is greater than or equal to one fifth of the area of ​​the first portion of the first surface and less than or equal to one third of the area of ​​the first portion of the first surface; The first surface of the connector has a region not bonded to the conductive layer, and the area of ​​the region not bonded to the conductive layer in the first surface is no larger than one third to one fifth of the area of ​​the region of the first surface bonded to the conductive layer.

4. The semiconductor structure according to any one of claims 1 to 3, It is characterized in that The number of the connecting members and the number of the conductive layers are both multiple, and the multiple connecting members and the multiple conductive layers are arranged at intervals in a direction parallel to the substrate; Each of the connecting members is correspondingly arranged on a side of the conductive layer facing away from the substrate; In a direction parallel to the substrate, each of the connecting members has a maximum dimension, two adjacent connecting members have a spacing, and each of the maximum dimensions is greater than or equal to the spacing.

5. The semiconductor structure according to claim 1, It is characterized in that It also includes a sacrificial layer, the sacrificial layer is located between the conductive layer and the connecting member, and the sacrificial layer electrically connects the conductive layer and the connecting member; The metal activity of the sacrificial layer is higher than the metal activity of the conductive layer.

6. The semiconductor structure according to claim 5, It is characterized in that Along the thickness direction of the substrate, the connecting member has a first surface and a second surface which are arranged oppositely and in parallel, the first surface is attached to the conductive layer, and the second surface is away from the conductive layer; In a plane perpendicular to the thickness direction of the substrate, an area of ​​the sacrificial layer is larger than an area of ​​the conductive layer and smaller than an area of ​​the first surface.

7. A method for preparing a semiconductor structure, It is characterized in that include: providing a substrate; forming an initial conductive layer, wherein the initial conductive layer covers the substrate; forming a connector, wherein the connector is located on a side of the initial conductive layer away from the substrate, and a cross-sectional area of ​​a side of the connector close to the conductive layer is larger than a cross-sectional area of ​​a side of the connector away from the initial conductive layer, wherein the cross-sectional area is perpendicular to a thickness direction of the substrate; Using the connecting member as a mask, a portion of the initial conductive layer is removed by etching to form a conductive layer.

8. The method for preparing a semiconductor structure according to claim 7, It is characterized in that Forming a connection piece, including: forming a mask layer, wherein the mask layer covers the surface of the initial conductive layer away from the substrate, and the mask layer has an opening; the opening size of the opening close to the substrate is smaller than the opening size of the opening away from the substrate; forming the connecting member, wherein the connecting member is filled in the opening; The mask layer is removed.

9. The method for preparing a semiconductor structure according to claim 8, It is characterized in that The forming of the connecting member specifically includes: forming the connecting member in the opening by electroplating, wherein the connecting member is electrically connected to the initial conductive layer.

10. The method for preparing a semiconductor structure according to claim 8, It is characterized in that Along the direction away from the substrate, the opening size of the opening gradually decreases, and the cross-sectional area of ​​the connecting member gradually decreases.

11. The method for preparing a semiconductor structure according to claim 7, It is characterized in that Along the thickness direction of the substrate, the connecting member has a first surface and a second surface which are arranged opposite to each other, the first surface is attached to the conductive layer, and the second surface is away from the conductive layer; Etching and removing part of the initial conductive layer specifically includes: etching the initial conductive layer with an etching solution, so that the side surface of the conductive layer is concave at the edge of the first surface; The portion of the first surface that is in contact with the conductive layer forms a first portion of the first surface, and the portion of the first surface that is not in contact with the conductive layer forms a second portion of the first surface. The area of ​​the first portion of the first surface is greater than or equal to the area of ​​the second surface.

12. The method for preparing a semiconductor structure according to any one of claims 7 to 11, It is characterized in that After forming the initial conductive layer and before forming the connecting member, the method further includes: forming an initial sacrificial layer, the initial sacrificial layer covering the initial conductive layer, the metal activity of the initial sacrificial layer being higher than the metal activity of the initial conductive layer; Forming the connecting member includes: the connecting member covers the surface of the initial sacrificial layer away from the substrate; Etching the initial conductive layer also includes: using the connecting member as a mask to etch away a portion of the initial sacrificial layer to form a sacrificial layer.

Images