Short-circuit protection method and system for multi-thread integrated circuit

Abstract

The present invention discloses a short-circuit protection method and system for a multi-thread integrated circuit, specifically related to the field of circuit technology, including S1. Multi-source data acquisition: Through high-frequency sampling sensors integrated on each thread power supply pin, thread-level current waveforms, voltage fluctuations, and temperature gradient data are collected in real time, and the chip load status is obtained synchronously to construct a multi-dimensional original data stream. Anti-noise coding technology and fault-tolerant interpolation algorithms are used to ensure data integrity and robustness. By collecting multi-dimensional original data in real time and calculating the data influence coefficients of the current layer, thread layer, scheduling layer, and power supply network layer, the present invention constructs four types of core protection decision features, which can accurately locate specific thread or core faults, avoid forced interruption of non-fault areas, and achieve fine protection.

Description

Technical Field

[0001] The present invention relates to the field of circuit technologies, and more particularly, to a short - circuit protection method and system for multi - thread integrated circuits. Background Art

[0002] With the continuous development of integrated circuit technologies, multi - thread integrated circuits are increasingly widely used in various electronic devices. Multi - thread integrated circuits can process multiple tasks simultaneously, greatly improving the operating efficiency of the system.

[0003] Short - circuit faults are one of the common problems faced by integrated circuits. Once a short - circuit occurs, it may cause damage to the integrated circuit and even trigger faults in the entire electronic device. Traditional circuit short - circuit protection methods include connecting a fuse in series in the circuit, which melts when the current exceeds the rated value to cut off the circuit, or monitoring the current through a comparator and triggering a shutdown relay for circuit protection.

[0004] However, in actual use, there are still some disadvantages. For example, the protection is not precise. Traditional methods protect at the global or module level. The fuse will cut off the entire power network and cannot locate the specific thread or core, resulting in forced interruption of non - fault areas. The protection depends on static thresholds. Traditional methods rely on fixed thresholds and cannot dynamically adapt to transient load changes in multi - thread scenarios, and may misjudge normal peak currents as faults. The recovery ability is poor. Traditional protection actions are mostly irreversible operations and require manual intervention to restart, and cannot achieve automatic recovery after a fault.

[0005] Therefore, there is an urgent need to provide a short - circuit protection method and system for multi - thread integrated circuits to solve the problems of imprecise protection, dependence on static thresholds, and poor recovery ability of existing circuit short - circuit protection methods. Summary of the Invention

[0006] To overcome the above - mentioned defects of the prior art, embodiments of the present invention provide a short - circuit protection method and system for multi - thread integrated circuits, through the following solutions, to solve the problems raised in the above - mentioned background art.

[0007] To achieve the above object, the present invention provides the following technical solution: A short - circuit protection method for multi - thread integrated circuits, including:

[0008] S1. Multi - source data acquisition: Through high - frequency sampling sensors integrated on each thread power supply pin, real - time collect thread - level current waveforms, voltage fluctuations, and temperature gradient data, synchronously obtain the chip load status, and construct a multi - dimensional original data stream; adopt anti - noise coding technology and fault - tolerant interpolation algorithms to ensure data integrity and robustness;

[0009] S2. Index calculation: Based on the multi-source raw data collected in S1, through physical coupling modeling and non-linear function design, calculate the current layer data influence coefficient, thread layer data influence coefficient, scheduling layer data influence coefficient, and power supply network layer data influence coefficient respectively, and construct four types of core protection decision features;

[0010] S3. Short-circuit protection strategy generation: Based on the four types of core protection decision features obtained in S2, select the autonomous influence coefficient grading trigger mechanism to avoid the comprehensive value from obscuring the risk characteristics of each level, and then generate the short-circuit protection strategy;

[0011] S4. Self-healing recovery and status feedback: According to the protection strategy generated in S3, perform short-circuit protection, and then perform progressive recovery and model iteration. Feed the data related to the short-circuit event back to the LSTM dynamic threshold model, update the threshold parameters, and re-collect multi-source data for the circuit system after short-circuit protection;

[0012] S5. Data interaction: Transmit the data related to the short-circuit event and the generated short-circuit protection strategy to the user information section to provide reference data for the user to make adjustment measures.

[0013] Preferably, the multi-dimensional raw data stream includes current layer data, thread layer data, scheduling layer data, and power supply network layer data.

[0014] Preferably, the current layer data includes the power supply rail voltage drop, denoted as ΔVd; the effective current value, denoted as Ir; the measured impedance value at the resonant frequency, denoted as Z(fr); the duration of current over-standard, denoted as To; the thread layer data includes the core temperature gradient, denoted as ▽T; the hot spot diffusion rate, denoted as vh; the number of shared resource contentions, denoted as C; the scheduling layer data includes the task deadline, denoted as Td; the on-chip network bandwidth utilization rate, denoted as Un; the CPU resource dispersion, denoted as σc; the GPU resource dispersion, denoted as σg; the voltage perturbation caused by migration, denoted as ΔV; the power supply network layer data includes the number of effective power supply paths, denoted as Np; the path impedance matching degree, denoted as ρZ; the total number of power supply paths, denoted as Nt; the short-circuit current propagation speed, denoted as vf; the voltage coupling coefficient, denoted as kc, and the duration of current over-standard, denoted as To.

[0015] Preferably, the current layer data influence coefficient reflects the instantaneous power anomaly through the product of voltage drop and current. The impedance attenuation exponential term amplifies the low-impedance risk, and the square root of time term balances the influence of short-time spikes and continuous overloads, realizing the multi-physical field coupling modeling of current-voltage-impedance-time for quantifying the short-circuit risk of the current layer.

[0016] Preferably, the data influence coefficient of the thread layer characterizes the urgency of thermal runaway through the product of the temperature gradient and the hot spot diffusion rate. The logarithmic function of the number of resource contentions suppresses the numerical explosion in high-concurrency scenarios, and the thread-level risk is evaluated through the ternary relationship of heat-time-resource.

[0017] Preferably, the data influence coefficient of the scheduling layer measures the scheduling urgency through the ratio of the task deadline to the bandwidth utilization rate. The square root of the resource dispersion suppresses the fragmentation effect, and the hyperbolic tangent function constrains the voltage perturbation amplitude to achieve the collaborative optimization of real-time performance-resource efficiency-power supply stability.

[0018] Preferably, the data influence coefficient of the power supply network layer evaluates the network redundancy ability through the product of the effective path ratio and the impedance matching degree. The coupling term of the fault propagation speed and the square root of time quantifies the diffusion risk, and the path-impedance-speed ternary model is used to predict the reconstruction success rate.

[0019] Preferably, the specific steps of the short-circuit protection strategy generation are as follows:

[0020] First, set the hierarchical threshold and priority, and generate four groups of core thresholds, namely, the current layer data influence coefficient threshold, the thread layer data influence coefficient threshold, the scheduling layer data influence coefficient threshold, and the power supply network layer data influence coefficient threshold, based on historical data and experimental data. Then, perform priority sorting according to the priority of power supply network layer > current layer > thread layer > scheduling layer; then, perform real-time monitoring and parallel evaluation, and make parallel judgments based on the real-time values of the current layer data influence coefficient, the thread layer data influence coefficient, the scheduling layer data influence coefficient, and the power supply network layer data influence coefficient obtained in S2, and then generate a protection action strategy according to the priority.

[0021] The current layer data influence coefficient threshold is calculated by building a test environment, injecting a stepwise increasing short-circuit current, recording the critical point of the CLIF value and chip damage, taking 80% of the critical value to calculate the current layer data influence coefficient at this time, and then averaging it with the mean value of the historical current layer data influence coefficient as the current layer data influence coefficient threshold;

[0022] The thread layer data influence coefficient threshold is calculated by gradually increasing the core load until transistor leakage failure occurs in the high-temperature aging test, recording the TLIF critical value, calculating the thread layer data influence coefficient at this time, and then averaging it with the mean value of the historical thread layer data influence coefficient as the thread layer data influence coefficient threshold;

[0023] The scheduling layer data influence coefficient threshold is calculated by gradually increasing the task load until task timeout in the resource fragmentation scenario, recording the SLIF critical value, calculating the scheduling layer data influence coefficient at this time, and then averaging it with the mean value of the historical scheduling layer data influence coefficient as the scheduling layer data influence coefficient threshold;

[0024] The threshold of the power supply network layer data influence coefficient is obtained by artificially creating a short circuit in the power supply network, measuring the PLIF and the correlation fuse trigger point of system collapse, calculating the power supply network layer data influence coefficient at this time, and then averaging it with the mean value of the historical power network layer data influence coefficients as the threshold of the power supply network layer data influence coefficient.

[0025] Preferably, the parallel judgment is specifically as follows:

[0026] When the power supply network layer data influence coefficient < the threshold of the power supply network layer data influence coefficient, cut off the power supply of the faulty thread, inject reverse current, immediately cut off the global power supply of the chip, record the coordinates of the faulty area through the non-volatile memory; send an interrupt signal to the external controller and wait for manual intervention;

[0027] When the current layer data influence coefficient > the threshold of the current layer data influence coefficient, cut off the power supply of the faulty thread, inject reverse current, and turn off the GaN switch of the faulty thread within ≤ 10 ns; inject reverse current into the adjacent threads to cancel the short-circuit current; mark the faulty thread as the disabled state and continuously monitor the current layer data influence coefficient until < 20% of the threshold of the current layer data influence coefficient;

[0028] When the thread layer data influence coefficient > the threshold of the thread layer data influence coefficient, migrate the thread to the spare core, start active heat dissipation, pause the task of the faulty thread, and migrate the context to the spare core through the high-speed link of the silicon interposer; after the migration is completed, reset the temperature sensor of the original core and release the shared resource lock;

[0029] When the scheduling layer data influence coefficient > the threshold of the scheduling layer data influence coefficient, increase the task scheduling priority and optimize the resource allocation; dynamically increase the task priority and allocate it to the core with a resource dispersion < 0.2; limit the bandwidth occupancy rate of non-real-time tasks;

[0030] In other cases, maintain the monitoring state.

[0031] Preferably, the short-circuit protection system for a multi-thread integrated circuit specifically includes:

[0032] A multi-source data acquisition module, through high-frequency sampling sensors integrated on each thread power supply pin, real-time collects thread-level current waveforms, voltage fluctuations, and temperature gradient data, synchronously obtains the chip load status, and constructs a multi-dimensional original data stream; adopts anti-noise coding technology and fault-tolerant interpolation algorithm to ensure data integrity and robustness;

[0033] The index calculation module calculates the current layer data influence coefficient, thread layer data influence coefficient, scheduling layer data influence coefficient, and power supply network layer data influence coefficient respectively through physical coupling modeling and non-linear function design based on the multi-source raw data collected by the multi-source data collection module, and constructs four types of core protection decision features;

[0034] The short-circuit protection strategy generation module selects an independent influence coefficient hierarchical triggering mechanism based on the four types of core protection decision features obtained by the index calculation module to avoid the comprehensive value from obscuring the risk features of each layer, and then generates a short-circuit protection strategy;

[0035] The self-healing recovery and status feedback module performs short-circuit protection according to the protection strategy generated by the short-circuit protection strategy generation module, then performs progressive recovery and model iteration, feeds the data related to the short-circuit event back to the LSTM dynamic threshold model, updates the threshold parameters, and re-collects multi-source data for the circuit system after short-circuit protection;

[0036] The data interaction module transports the data related to the short-circuit event and the generated short-circuit protection strategy to the user information section to provide reference data for the user to make adjustment measures.

[0037] The technical effects and advantages of the present invention:

[0038] By collecting multi-dimensional raw data in real time, calculating the data influence coefficients of the current layer, thread layer, scheduling layer, and power supply network layer, and constructing four types of core protection decision features, the present invention can accurately locate specific threads or core faults, avoid forced interruption of non-fault areas, and achieve fine protection;

[0039] The present invention adopts anti-noise coding technology and fault-tolerant interpolation algorithm to ensure data integrity and robustness. Based on the collected multi-source raw data, it calculates various influence coefficients through physical coupling modeling and non-linear function design, and feeds the data related to the short-circuit event back to the LSTM dynamic threshold model to update the threshold parameters, which can dynamically adapt to the transient load changes in multi-thread scenarios and avoid misjudging normal peak current as a fault;

[0040] After performing short-circuit protection according to the short-circuit protection strategy, the present invention performs progressive recovery and model iteration at the same time to achieve automatic recovery after a fault, reduce manual intervention, and improve the recovery efficiency of the circuit system. Brief Description of the Drawings

[0041] Figure 1 It is a schematic diagram of the overall structure of the present invention.

[0042] Figure 2 It is a schematic diagram of the system structure of the present invention. Detailed Embodiment

[0043] Next, in combination with the accompanying drawings in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0044] As shown in the attached Figure 1 short-circuit protection method for a multi-threaded integrated circuit, including.

[0045] S1. Multi-source data acquisition: Through high-frequency sampling sensors integrated on each thread power supply pin, thread-level current waveforms, voltage fluctuations, and temperature gradient data are collected in real time, and the chip load status is synchronously obtained to construct a multi-dimensional original data stream; anti-noise coding technology and fault-tolerant interpolation algorithms are used to ensure data integrity and robustness.

[0046] In this embodiment, it should be specifically noted that the multi-dimensional original data stream includes current layer data, thread layer data, scheduling layer data, and power supply network layer data.

[0047] In this embodiment, it should be specifically noted that the current layer data includes power supply rail voltage drop, denoted as ΔVd; root mean square current, denoted as Ir; measured impedance value at the resonant frequency, denoted as Z(fr); duration of overcurrent, denoted as To; thread layer data includes core temperature gradient, denoted as ▽T; hot spot diffusion rate, denoted as vh; number of shared resource contentions, denoted as C; scheduling layer data includes task deadline, denoted as Td; on-chip network bandwidth utilization rate, denoted as Un; CPU resource dispersion, denoted as σc; GPU resource dispersion, denoted as σg; voltage perturbation caused by migration, denoted as ΔV; power supply network layer data includes number of effective power supply paths, denoted as Np; path impedance matching degree, denoted as ρZ; total number of power supply paths, denoted as Nt; short-circuit current propagation speed, denoted as vf; voltage coupling coefficient, denoted as kc, and duration of overcurrent, denoted as To.

[0048] In this embodiment, it should be specifically noted that the power supply rail voltage drop is obtained by deploying a high-precision differential voltage probe at the chip power supply pin, collecting voltage signals at a sampling rate of 2MS / s, synchronously recording the rated voltage feedback value of the power management unit, and calculating the deviation between the actual voltage and the rated value.

[0049] In this embodiment, it should be specifically noted that the root mean square current is obtained by collecting an instantaneous current sequence using a high-frequency current sensor and then performing calculations. Specifically: ;

[0050] where I(t) represents the instantaneous current sequence and T represents the current running time.

[0051] In this embodiment, specifically, the measured impedance value at the resonance frequency is directly acquired by injecting a swept signal from 1 MHz to 1 GHz into the power supply network using an impedance analyzer, measuring the impedance amplitude-frequency characteristic curve, and extracting the impedance amplitude at the resonance frequency point.

[0052] In this embodiment, specifically, the duration of the current exceeding the standard is directly acquired by starting the built-in hardware timer of the FPGA when the current sensor triggers an over-standard signal, continuously timing until the current drops below the threshold, and recording the time difference.

[0053] In this embodiment, specifically, the core temperature gradient is obtained by deploying digital thermal sensors at the four corners of the chip core, with a sampling rate of 100 kS / s, recording the temperature, and then calculating. Specifically: ;

[0054] where T i represents the core temperature of the i-th sensor, T j represents the core temperature of the j-th sensor, and d ij is the distance between the i-th sensor and the j-th sensor.

[0055] In this embodiment, specifically, the hot spot diffusion rate is obtained by collecting the chip surface temperature distribution image at a frame rate of 100 Hz using an infrared thermal imager, locating the hot spot coordinates, and then calculating. Specifically: ;

[0056] where (x(t), y(t)) represents the located hot spot coordinates, (x(t + Δt), y(t + Δt)) represents the located hot spot coordinates after Δt time, and Δt represents the time interval.

[0057] In this embodiment, specifically, the number of shared resource contentions is directly obtained by implanting hardware performance counters in the cache controller and the bus arbiter to count the number of access failures caused by resource conflicts per unit time.

[0058] In this embodiment, specifically, the task deadline is obtained by reading the real-time constraint parameters of the task from the real-time operating system scheduler or the hardware task management unit.

[0059] In this embodiment, specifically, the on-chip network bandwidth utilization rate is obtained by deploying a hardware traffic monitor in the NoC router, counting the number of valid data packets per unit time, and calculating in combination with the theoretical maximum bandwidth. Specifically: ;

[0060] Where Np represents the number of valid data packets, Lp represents the average data packet length, Bmax represents the theoretical maximum bandwidth, and Tz represents the statistical period.

[0061] In this embodiment, it should be specifically noted that the CPU resource dispersion and GPU resource dispersion are obtained by using a performance counter to record the proportion of idle cycles of each computing unit.

[0062] In this embodiment, it should be specifically noted that the voltage disturbance caused by the migration is obtained by using a high-speed voltage sensor to record the difference between the peak value and the steady-state value of the power supply network voltage at the moment when the task migration is triggered.

[0063] In this embodiment, it should be specifically noted that the number of effective power supply paths is obtained by using the programmable power supply network scanning module of the power supply network scanner to inject test current into each path and detect the number of paths with voltage response.

[0064] In this embodiment, it should be specifically noted that the path impedance matching degree is obtained by applying a constant current to each power supply path, measuring the voltage drop, calculating the impedance, and comparing it with the rated impedance. Specifically: ;

[0065] Where Z represents the impedance and Zn represents the rated impedance.

[0066] In this embodiment, it should be specifically noted that the total number of power supply paths is directly read according to the chip power supply network design specification.

[0067] In this embodiment, it should be specifically noted that the short-circuit current propagation speed is obtained by recording the short-circuit trigger timestamp and the voltage anomaly timestamp in the adjacent area, and calculating the physical distance between the fault point and the affected area from the layout data. Specifically: ;

[0068] Where d represents the physical distance between the fault point and the affected area, t0 represents the short-circuit trigger timestamp, and t1 represents the voltage anomaly timestamp in the adjacent area.

[0069] In this embodiment, it should be specifically noted that the voltage coupling coefficient is obtained by deploying voltage sensors in adjacent power supply areas, recording the voltage fluctuations in the two areas during the short-circuit event, and then calculating. Specifically: ;

[0070] Where ΔV1 represents the amplitude of the voltage fluctuation in the fault area and ΔV2 represents the amplitude of the voltage fluctuation in the adjacent area.

[0071] S2. Index calculation: Based on the multi-source raw data collected in S1, through physical coupling modeling and non-linear function design, calculate the current layer data influence coefficient, thread layer data influence coefficient, scheduling layer data influence coefficient, and power supply network layer data influence coefficient respectively, and construct four types of core protection decision features.

[0072] In this embodiment, it should be specifically noted that the current layer data influence coefficient reflects the instantaneous power anomaly through the product of voltage drop and current. The impedance attenuation exponential term amplifies the low impedance risk, and the square root term of time balances the influence of short-term spikes and continuous overloads, realizing the multi-physical field coupling modeling of current-voltage-impedance-time, and is used to quantify the short-circuit risk of the current layer. Specifically: ;

[0073] Where ΔVd represents the current layer data including the power supply rail voltage drop, Ir represents the effective current value, Z(fr) represents the measured impedance value at the resonant frequency, To represents the duration of current over-limit, Vn represents the rated voltage, Zn represents the rated impedance, and Ts represents the maximum allowable safety time.

[0074] In this embodiment, it should be specifically noted that the thread layer data influence coefficient characterizes the urgency of thermal runaway through the product of temperature gradient and hot spot diffusion rate. The logarithmic function of the number of resource contentions suppresses the numerical explosion in high-concurrency scenarios, and evaluates the thread-level risk through the thermal-time-resource ternary relationship. Specifically: ;

[0075] Where ▽T represents the core temperature gradient, vh represents the hot spot diffusion rate, C represents the number of shared resource contentions, Ts represents the maximum safety temperature, τ represents the thermal diffusion time constant, and Ct represents the maximum allowable number of contentions.

[0076] In this embodiment, it should be specifically noted that the scheduling layer data influence coefficient measures the scheduling urgency through the ratio of task deadline to bandwidth utilization. The square root of resource dispersion suppresses the fragmentation effect, and the hyperbolic tangent function restricts the voltage perturbation amplitude, realizing the collaborative optimization of real-time performance-resource efficiency-power supply stability. Specifically: ;

[0077] Where Td represents the task deadline; Un represents the on-chip network bandwidth utilization; σc represents the CPU resource dispersion; σg represents the GPU resource dispersion; ΔV represents the voltage perturbation caused by migration, and Vn represents the power supply noise tolerance;

[0078] In this embodiment, it should be specifically noted that the power supply network layer data influence coefficient evaluates the network redundancy ability through the product of the effective path ratio and impedance matching degree. The coupling term of fault propagation speed and square root of time quantifies the diffusion risk, and predicts the reconstruction success rate through the path-impedance-speed ternary model. Specifically: ;

[0079] where Np represents the number of effective power supply paths, ρZ represents the path impedance matching degree, Nt represents the total number of power supply paths, vf represents the short-circuit current propagation speed, kc represents the voltage coupling coefficient, To represents the duration of overcurrent, and v max represents the maximum propagation speed.

[0080] S3. Short-circuit protection strategy generation: Based on the four types of core protection decision features obtained in S2, select the independent influence coefficient hierarchical triggering mechanism to avoid the comprehensive value from obscuring the risk features of each layer, and then generate the short-circuit protection strategy.

[0081] In this embodiment, specifically, the specific steps of the short-circuit protection strategy generation are as follows:

[0082] First, set the hierarchical thresholds and priorities, generate four groups of core thresholds, namely, the current layer data influence coefficient threshold, the thread layer data influence coefficient threshold, the scheduling layer data influence coefficient threshold, and the power supply network layer data influence coefficient threshold, based on historical data and experimental data, and then perform priority sorting according to the priority of the power supply network layer > current layer > thread layer > scheduling layer; then perform real-time monitoring and parallel evaluation, make parallel judgments based on the real-time values of the current layer data influence coefficient, thread layer data influence coefficient, scheduling layer data influence coefficient, and power supply network layer data influence coefficient obtained in S2, and then generate the protection action strategy according to the priority.

[0083] In this embodiment, specifically, the current layer data influence coefficient threshold is calculated by building a test environment, injecting a stepwise increasing short-circuit current, recording the critical point of the CLIF value and chip damage, taking 80% of the critical value to calculate the current layer data influence coefficient at this time, and then averaging it with the mean value of the historical current layer data influence coefficient as the current layer data influence coefficient threshold.

[0084] In this embodiment, specifically, the thread layer data influence coefficient threshold is calculated by gradually increasing the core load until transistor leakage failure occurs in the high-temperature aging test, recording the TLIF critical value, calculating the thread layer data influence coefficient at this time, and then averaging it with the mean value of the historical thread layer data influence coefficient as the thread layer data influence coefficient threshold.

[0085] In this embodiment, specifically, the scheduling layer data influence coefficient threshold is calculated by gradually increasing the task load until task timeout in the resource fragmentation scenario, recording the SLIF critical value, calculating the scheduling layer data influence coefficient at this time, and then averaging it with the mean value of the historical scheduling layer data influence coefficient as the scheduling layer data influence coefficient threshold.

[0086] In this embodiment, it should be specifically noted that the threshold of the power supply network layer data influence coefficient is obtained by artificially creating a short circuit in the power supply network, measuring the correlation melting trigger point between the PLIF and the system crash, calculating the power supply network layer data influence coefficient at this time, and then averaging it with the mean value of the historical power network layer data influence coefficient as the threshold of the power supply network layer data influence coefficient.

[0087] In this embodiment, it should be specifically noted that the parallel judgment is specifically as follows:

[0088] When the power supply network layer data influence coefficient < the threshold of the power supply network layer data influence coefficient, cut off the power supply of the faulty thread, inject reverse current, immediately cut off the global power supply of the chip, and record the coordinates of the faulty area through the non-volatile memory; send an interrupt signal to the external controller and wait for manual intervention;

[0089] When the current layer data influence coefficient > the threshold of the current layer data influence coefficient, cut off the power supply of the faulty thread, inject reverse current, and turn off the GaN switch of the faulty thread within ≤ 10 ns; inject reverse current into the adjacent threads to cancel the short-circuit current; mark the faulty thread as the disabled state and continuously monitor the current layer data influence coefficient until < 20% of the threshold of the current layer data influence coefficient;

[0090] When the thread layer data influence coefficient > the threshold of the thread layer data influence coefficient, migrate the thread to the spare core, start active heat dissipation, pause the task of the faulty thread, and migrate the context to the spare core through the high-speed link of the silicon interposer; after the migration is completed, reset the temperature sensor of the original core and release the shared resource lock;

[0091] When the scheduling layer data influence coefficient > the threshold of the scheduling layer data influence coefficient, increase the task scheduling priority and optimize the resource allocation; dynamically increase the task priority and allocate it to the core with a resource dispersion < 0.2; limit the bandwidth occupancy rate of non-real-time tasks.

[0092] In other cases, maintain the monitoring state.

[0093] S4. Self-healing recovery and status feedback: Perform short-circuit protection according to the protection strategy generated in S3, then perform progressive recovery and model iteration, feedback the data related to the short-circuit event to the LSTM dynamic threshold model, update the threshold parameters, and re-collect multi-source data for the circuit system after short-circuit protection.

[0094] In this embodiment, it should be specifically noted that the progressive recovery is specifically to gradually restore the voltage of the faulty area at a step size of 10% after the short circuit is eliminated, with an interval of 1 μs for each step.

[0095] S5. Data interaction: Transmit the data related to the short-circuit event and the generated short-circuit protection strategy to the user information segment to provide reference data for the user to make adjustment measures.

[0096] As shown in the appendix Figure 2 This embodiment provides a short - circuit protection system for a multi - thread integrated circuit, including:

[0097] A multi - source data acquisition module, through high - frequency sampling sensors integrated on each thread power supply pin, real - time collects thread - level current waveforms, voltage fluctuations, and temperature gradient data, synchronously obtains the chip load status, and constructs a multi - dimensional original data stream; adopts anti - noise coding technology and fault - tolerant interpolation algorithm to ensure data integrity and robustness;

[0098] An index calculation module, based on the multi - source original data collected by the multi - source data acquisition module, through physical coupling modeling and non - linear function design, calculates the current - layer data influence coefficient, thread - layer data influence coefficient, scheduling - layer data influence coefficient, and power supply network - layer data influence coefficient respectively, and constructs four types of core protection decision features;

[0099] A short - circuit protection strategy generation module, based on the four types of core protection decision features obtained by the index calculation module, selects an autonomous influence coefficient hierarchical triggering mechanism to avoid the comprehensive value blurring the risk characteristics of each level, and then generates a short - circuit protection strategy;

[0100] A self - healing recovery and status feedback module, according to the protection strategy generated by the short - circuit protection strategy generation module, conducts short - circuit protection, then performs progressive recovery and model iteration, feeds back the data related to the short - circuit event to the LSTM dynamic threshold model, updates the threshold parameters, and re - conducts multi - source data acquisition on the circuit system after short - circuit protection;

[0101] A data interaction module, transports the data related to the short - circuit event and the generated short - circuit protection strategy to the user information section, and provides reference data for the user to make adjustment measures.

[0102] Secondly: In the attached drawings of the disclosed embodiments of the present invention, only the structures related to the disclosed embodiments are involved. Other structures can refer to the general design. Without conflict, the same embodiment and different embodiments of the present invention can be combined with each other;

[0103] Finally: The above - mentioned are only the preferred embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A short-circuit protection method for a multi-threaded integrated circuit, characterized in that, Including: S1. Multi-source data acquisition: High-frequency sampling sensors integrated on each thread power supply pin are used to collect thread-level current waveforms, voltage fluctuations, and temperature gradient data in real time, synchronously obtain the chip load status, and construct a multi-dimensional raw data stream. Anti-noise coding technology and fault-tolerant interpolation algorithms are adopted to ensure data integrity and robustness; The multi-dimensional raw data stream includes current layer data, thread layer data, scheduling layer data, and power supply network layer data; The current layer data includes power rail voltage drop, denoted as ΔVd; root mean square current, denoted as Ir; measured impedance value at the resonant frequency, denoted as Z(fr); duration of overcurrent, denoted as To; Thread layer data includes core temperature gradient, denoted as ∇T; hot spot diffusion rate, denoted as vh; number of shared resource contentions, denoted as C; Scheduling layer data includes task deadline, denoted as Td; on-chip network bandwidth utilization rate, denoted as Un; CPU resource dispersion, denoted as σc; GPU resource dispersion, denoted as σg; voltage disturbance caused by migration, denoted as ΔV; Power supply network layer data includes the number of effective power supply paths, denoted as Np; path impedance matching degree, denoted as ρZ; total number of power supply paths, denoted as Nt; short-circuit current propagation speed, denoted as vf; voltage coupling coefficient, denoted as kc, duration of overcurrent, denoted as To; S2. Index calculation: Based on the multi-source raw data collected in S1, through physical coupling modeling and non-linear function design, the influence coefficients of current layer data, thread layer data, scheduling layer data, and power supply network layer data are calculated respectively, and four types of core protection decision features are constructed; The influence coefficient of the current layer data reflects the instantaneous power abnormality through the product of voltage drop and current. The impedance attenuation exponential term amplifies the low-impedance risk, and the time square root term balances the influence of short-term spikes and continuous overloads, realizing the multi-physical field coupling modeling of current-voltage-impedance-time, and is used to quantify the short-circuit risk of the current layer; The influence coefficient of the thread layer data characterizes the urgency of thermal runaway through the product of temperature gradient and hot spot diffusion rate. The logarithmic function of the number of resource contentions suppresses the numerical explosion in high-concurrency scenarios, and evaluates the thread-level risk through the ternary relationship of heat-time-resources; The influence coefficient of the scheduling layer data measures the scheduling urgency through the ratio of task deadline to bandwidth utilization rate. The square root of resource dispersion suppresses the fragmentation effect, and the hyperbolic tangent function restricts the voltage disturbance amplitude, realizing the collaborative optimization of real-time-resource efficiency-power supply stability; The influence coefficient of the power supply network layer data evaluates the network redundancy ability through the product of the ratio of effective paths and impedance matching degree. The coupling term of fault propagation speed and time square root quantifies the diffusion risk, and predicts the reconstruction success rate through the path-impedance-speed ternary model; S3. Short-circuit protection strategy generation: Based on the four types of core protection decision features obtained in S2, an autonomous influence coefficient hierarchical triggering mechanism is selected to avoid the comprehensive value from obscuring the risk characteristics of each level, and then a short-circuit protection strategy is generated; S4, Self-healing recovery and status feedback: According to the protection strategy generated in S3, short-circuit protection is performed, and then progressive recovery and model iteration are carried out. The data related to the short-circuit event is fed back to the LSTM dynamic threshold model to update the threshold parameters, and multi-source data acquisition is restarted for the circuit system after short-circuit protection; S5, Data interaction: The data related to the short-circuit event and the generated short-circuit protection strategy are sent to the user information section to provide reference data for the user to make adjustment measures.

2. The short-circuit protection method for a multi-thread integrated circuit according to claim 1, characterized in that: The specific steps for generating the short-circuit protection strategy are as follows: First, set hierarchical thresholds and priorities. Four groups of core thresholds, namely the current layer data influence coefficient threshold, thread layer data influence coefficient threshold, scheduling layer data influence coefficient threshold, and power supply network layer data influence coefficient threshold, are generated based on historical data and experimental data, and then priority sorting is performed according to the priority of power supply network layer > current layer > thread layer > scheduling layer; Then, real-time monitoring and parallel evaluation are carried out. Parallel judgments are made based on the real-time values of the current layer data influence coefficient, thread layer data influence coefficient, scheduling layer data influence coefficient, and power supply network layer data influence coefficient obtained in S2, and then a protection action strategy is generated according to the priority; The current layer data influence coefficient threshold is calculated by building a test environment, injecting a stepwise increasing short-circuit current, recording the critical point of the CLIF value and chip damage, taking 80% of the critical value to calculate the current layer data influence coefficient at this time, and then averaging it with the mean value of the historical current layer data influence coefficient as the current layer data influence coefficient threshold; The thread layer data influence coefficient threshold is calculated by gradually increasing the core load in a high-temperature aging test until transistor leakage failure occurs, recording the TLIF critical value, calculating the thread layer data influence coefficient at this time, and then averaging it with the mean value of the historical thread layer data influence coefficient as the thread layer data influence coefficient threshold; The scheduling layer data influence coefficient threshold is calculated by gradually increasing the task load in a resource fragmentation scenario until the task times out, recording the SLIF critical value, calculating the scheduling layer data influence coefficient at this time, and then averaging it with the mean value of the historical scheduling layer data influence coefficient as the scheduling layer data influence coefficient threshold; The power supply network layer data influence coefficient threshold is calculated by artificially creating a power supply network short circuit, measuring the PLIF and the associated fuse trigger point of system collapse, calculating the power supply network layer data influence coefficient at this time, and then averaging it with the mean value of the historical power supply network layer data influence coefficient as the power supply network layer data influence coefficient threshold.

3. The short-circuit protection method for a multi-thread integrated circuit according to claim 2, wherein: The specific parallel judgment is as follows: When the power supply network layer data influence coefficient < the power supply network layer data influence coefficient threshold, cut off the power supply of the faulty thread, inject a reverse current, immediately cut off the global power supply of the chip, and record the coordinates of the faulty area through non-volatile memory; Send an interrupt signal to the external controller and wait for manual intervention; When the current layer data influence coefficient > the current layer data influence coefficient threshold, cut off the power supply of the faulty thread, inject a reverse current, and turn off the GaN switch of the faulty thread within ≤10 ns; Inject a reverse current into the adjacent thread to cancel the short-circuit current; Mark the faulty thread as disabled and continuously monitor the current layer data impact coefficient until it is less than 20% of the current layer data impact coefficient threshold; When the thread layer data impact coefficient > the thread layer data impact coefficient threshold, migrate the thread to the spare core, start active cooling, pause the faulty thread task, and migrate the context to the spare core through the high-speed link of the silicon interposer; after the migration is completed, reset the original core temperature sensor and release the shared resource lock; When the scheduling layer data impact coefficient > the scheduling layer data impact coefficient threshold, increase the task scheduling priority and optimize the resource allocation; dynamically increase the task priority and allocate it to the core with a resource dispersion < 0.2; limit the bandwidth occupancy rate of non-real-time tasks; In other cases, maintain the monitoring status.

4. A short-circuit protection system for a multi-threaded integrated circuit, which is used to implement the short-circuit protection method for a multi-threaded integrated circuit according to any one of the above claims 1-3, characterized in that, Including: A multi-source data acquisition module that uses high-frequency sampling sensors integrated on each thread power supply pin to collect thread-level current waveforms, voltage fluctuations, and temperature gradient data in real time, synchronously obtains the chip load status, and constructs a multi-dimensional raw data stream; uses anti-noise coding technology and fault-tolerant interpolation algorithms to ensure data integrity and robustness; An index calculation module that calculates the current layer data impact coefficient, thread layer data impact coefficient, scheduling layer data impact coefficient, and power supply network layer data impact coefficient respectively based on the multi-source raw data collected by the multi-source data acquisition module through physical coupling modeling and non-linear function design, and constructs four types of core protection decision features; A short-circuit protection strategy generation module that selects an independent impact coefficient grading trigger mechanism based on the four types of core protection decision features obtained by the index calculation module to avoid the comprehensive value blurring the risk characteristics of each layer, and then generates a short-circuit protection strategy; A self-healing recovery and status feedback module that performs short-circuit protection according to the protection strategy generated by the short-circuit protection strategy generation module, then performs progressive recovery and model iteration, feeds the data related to the short-circuit event back to the LSTM dynamic threshold model, updates the threshold parameters, and re-performs multi-source data acquisition on the circuit system after short-circuit protection; A data interaction module that transports the data related to the short-circuit event and the generated short-circuit protection strategy to the user information section to provide reference data for the user to make adjustment measures.

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