Control circuit, converter and system

Abstract

The invention discloses a control circuit, a converter and a system, and relates to the field of integrated circuits, and the control circuit comprises a logic control module, a timing module and a timing expansion module. Outputting a first signal to an upper field-effect tube of the buck converter, wherein the first signal is used for starting the upper field-effect tube; the timing module is connected with the logic control module; the timing expansion module comprises a first switch, a second switch, a first current source, a first capacitor and a first comparator, one end of the first current source is connected with the first switch, the other end of the first current source is connected with the second switch, the positive input end of the first comparator and the first capacitor, and the output end of the first comparator is connected with the logic control module. And by arranging the timing expansion module, the starting time of the upper field effect transistor is prolonged, the load response speed is further improved, and the stability of the equipment is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a control circuit, a converter and a system. Background Art

[0002] In the prior art, for a traditional buck converter, when a load instantaneous change occurs, the difference between the feedback voltage and the preset reference voltage is too large, so it takes a long time to adjust the voltage, causing the buck converter to respond slowly, thereby affecting the stability of the device. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a control circuit, a converter and a system that can quickly respond to instantaneous changes in load, adjust the voltage in time, and improve the stability of the device.

[0004] The control circuit of the first embodiment of the present application includes:

[0005] According to the control circuit of the embodiment of the present application, at least the following beneficial effects are achieved: by setting a logic control module, it is convenient to output a first signal when it is detected that the feedback voltage is less than a preset reference voltage to control the opening of the upper field effect tube; by setting a timing module, it is convenient to output a second signal to the logic control module after the upper field effect tube is turned on for a required time; and the setting of the timing expansion module, by setting a first switch, is convenient to control the closing of the first switch when it is detected that the timing module outputs the second signal, so as to keep the first current source and the first capacitor and the positive input terminal of the first comparator in a conducting state, so that the first current source continuously charges the first capacitor, so that when the first current source stops inputting current, the first capacitor can still maintain a stable voltage for a period of time; when the voltage at the positive input terminal of the first comparator is less than the preset voltage, the first comparator outputs a third signal to the logic control module, and the timing module The block outputs the second signal, prompting the logic control module to continue to maintain the state of outputting the first signal. When the first comparator does not output the third signal and only the timing module outputs the second signal, the logic control module stops outputting the first signal, prompting the closure of the upper field effect tube. In the prior art, the timing module outputs the second signal, and then controls the closure of the upper field effect tube through the logic control module, and there is no setting of the timing extension module. However, the present application sets the timing extension module. When the timing module outputs the second signal, the timing extension module also outputs the third signal, so as to maintain the continuous output of the first signal of the logic control module until the timing extension module no longer outputs the third signal, thereby extending the opening time of the upper field effect tube, reducing the difference between the feedback voltage and the preset reference voltage, facilitating the rapid adjustment of the voltage, and then achieving rapid response to instantaneous changes in the load, thereby improving the stability of the device.

[0006] According to some embodiments of the present application, the timing module includes a second current source, a third switch, a fourth switch and a second comparator, the second current source is respectively connected to the positive input terminal, the third switch and the fourth switch of the second comparator, the reverse input terminal of the second comparator is connected to the output voltage of the buck converter, and the output terminal of the second comparator is connected to the logic control module.

[0007] According to some embodiments of the present application, the timing module also includes a second capacitor, one end of the second capacitor is connected to the positive input end of the second comparator, and the other end is grounded, and the second capacitor is connected in parallel with the third switch and the fourth switch.

[0008] According to some embodiments of the present application, the logic control module includes a first OR gate, a NOR gate, a second OR gate, a first AND gate, a NAND gate, a second AND gate and a third comparator, wherein the first input end of the first OR gate is connected to the output end of the second comparator, the second input end of the first OR gate is connected to the output end of the first comparator, the output end of the first OR gate is connected to the first input end of the NOR gate, the second input end of the NOR gate is connected to the output end of the second OR gate, the output end of the NOR gate is connected to the first input end of the second OR gate, the first input end of the first AND gate is connected to the output end of the first comparator, and the third comparator comprises a first AND gate and a second AND gate. The output end of an AND gate is connected to the second input end of the second OR gate, the first input end of the NAND gate is connected to the output end of the second OR gate, the output end of the second OR gate is also connected to the buck converter, the output end of the NAND gate is connected to the second input end of the second AND gate, the output end of the second AND gate is respectively connected to the second input end of the first AND gate and the second input end of the NAND gate, the output end of the third comparator is connected to the first input end of the second AND gate, the first positive input end of the third comparator is used to access the preset reference voltage, and the first negative input end of the third comparator is used to access the feedback voltage.

[0009] According to some embodiments of the present application, the logic control module also includes a trigger, a NOT gate and a third OR gate, the output end of the second AND gate is connected to the second input end of the NAND gate through the trigger, the output end of the NAND gate is connected to the first input end of the third OR gate, the output end of the third OR gate is connected to the second input end of the second AND gate, the second input end of the third OR gate is used to access the preset blank voltage of the logic control module, the zeroing end of the trigger is used to access the overcurrent voltage of the control circuit, and the clock end of the trigger is used to access the overcurrent voltage through the NOT gate.

[0010] According to some embodiments of the present application, the logic control module also includes an error amplifier, the positive input terminal of the error amplifier is used to connect to the preset reference voltage, the reverse input terminal of the error amplifier is used to connect to the feedback voltage, and the output terminal of the error amplifier is connected to the second positive input terminal of the third comparator.

[0011] According to some embodiments of the present application, the second inverting input terminal of the third comparator is connected to the ramp signal of the logic control module.

[0012] According to some embodiments of the present application, the trigger is a data trigger.

[0013] A converter according to an embodiment of the second aspect of the present application includes:

[0014] The control circuit of the first embodiment of the present application.

[0015] The converter according to the embodiment of the present application has at least the following beneficial effects: by setting a logic control module, it is convenient to output a first signal when it is detected that the feedback voltage is less than a preset reference voltage to control the opening of the upper field effect tube; by setting a timing module, it is convenient to output a second signal to the logic control module after the upper field effect tube is turned on for the required time; and the setting of the timing expansion module, by setting a first switch, is convenient to control the closing of the first switch when it is detected that the timing module outputs the second signal, so as to prompt the first current source and the first capacitor and the positive input terminal of the first comparator to remain in a conductive state, so that the first current source continuously charges the first capacitor, so that when the first current source stops inputting current, the first capacitor can still maintain a stable voltage for a period of time; when the voltage at the positive input terminal of the first comparator is less than the preset voltage, the first comparator outputs a third signal to the logic control module, and the timing module outputs a second signal, prompting the logic control module The block continues to maintain the state of outputting the first signal, and when the first comparator does not output the third signal and only the timing module outputs the second signal, the logic control module stops outputting the first signal, prompting the closure of the upper field effect tube. In the prior art, the timing module outputs the second signal, and then controls the closure of the upper field effect tube through the logic control module, and there is no setting of the timing extension module. However, the present application sets the timing extension module. When the timing module outputs the second signal, the timing extension module also outputs the third signal, so as to maintain the continuous output of the first signal of the logic control module until the timing extension module no longer outputs the third signal, thereby extending the opening time of the upper field effect tube, reducing the difference between the feedback voltage and the preset reference voltage, facilitating the rapid adjustment of the voltage, and then realizing a rapid response to the instantaneous change of the load, thereby improving the stability of the equipment, and by introducing the control circuit of the present application, it can respond to the instantaneous change of the load in a timely manner.

[0016] A system according to an embodiment of the third aspect of the present application includes:

[0017] A converter according to the second aspect of the present application.

[0018] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0020] Figure 1 A schematic diagram of a control circuit according to an embodiment of the present application;

[0021] Figure 2 This is a waveform diagram of the control circuit before and after overcurrent occurs in the embodiment of the present application;

[0022] Figure 3 This is a waveform diagram of the control circuit before and after a rapid load change occurs in the embodiment of the present application.

[0023] Reference numerals:

[0024] Timing expansion module 100; timing module 101; logic control module 102. DETAILED DESCRIPTION

[0025] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0026] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0027] In the description of this application, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0028] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0029] At present, in the prior art, some conventional buck converters with a constant on-time architecture have a fixed on-time of the upper tube. During a transient load change, the speed index of the buck converter load response is mainly determined by the voltage drop of its output voltage, that is, the difference between the feedback voltage and the preset reference voltage. The smaller the voltage drop, the faster the load response. If the load response is too slow, more time is required to adjust the voltage, which can easily cause instability in the device circuit.

[0030] Based on this, the present application proposes a control circuit, a converter and a system, which aims to extend the turn-on time of the upper field effect tube by setting a timing expansion module 100, reduce the voltage drop, and thereby increase the speed of load response and maintain the stability of the equipment.

[0031] The following references Figure 1 The control circuit of the embodiment of the present application is described.

[0032] It can be understood that: the control circuit of the embodiment of the present application includes a logic control module 102, a timing module 101 and a timing expansion module 100, the output end of the logic control module 102 is used to connect to the buck converter, the logic control module 102 is used to output a first signal to the upper field effect transistor of the buck converter when it is detected that the feedback voltage of the buck converter is less than the preset reference voltage, and the first signal is used to turn on the upper field effect transistor; the timing module 101 is connected to the logic control module 102, and the timing module 101 is used to output a second signal to the logic control module 102; the timing expansion module 100 includes a first switch, a second switch, a first current source, a first capacitor and a first comparator, one end of the first current source is connected to the first switch, and the other end is respectively connected to the second switch, the positive input end of the first comparator, and the first comparator. A capacitor is connected, the first switch is used to close when the second signal output is detected, and the second switch is used to close when the second signal output is not detected, the reverse input terminal of the first comparator is used to access the preset voltage of the timing expansion module 100, and the output terminal of the first comparator is connected to the logic control module 102. The first comparator is used to output a third signal to the logic control module 102 when it is detected that the voltage at the positive input terminal of the first comparator is less than the preset voltage; the logic control module 102 is also used to maintain the state of outputting the first signal when it is detected that the timing module 101 outputs the second signal and the timing expansion module 100 outputs the third signal; the logic control module 102 is also used to stop outputting the first signal when it is detected that the timing module 101 outputs the second signal and the timing expansion module 100 does not output the third signal.

[0033] The beneficial effects of the control circuit of the embodiment of the present application can be manifested as follows: by setting the logic control module 102, it is convenient to output the first signal when it is detected that the feedback voltage is less than the preset reference voltage to control the opening of the upper field effect tube, and by setting the timing module 101, it is convenient to output the second signal to the logic control module 102 after the upper field effect tube is turned on for the required time. The setting of the timing expansion module 100, by setting the first switch, is convenient to control the first switch to close when it is detected that the timing module 101 outputs the second signal, so as to keep the first current source and the first capacitor and the positive input terminal of the first comparator in the on state, so that the first current source continuously charges the first capacitor, so that when the first current source stops inputting current, the first capacitor can still maintain a stable voltage for a period of time, and when the voltage at the positive input terminal of the first comparator is less than the preset voltage, the first comparator outputs a third signal to the logic control module 102, and the timing module 101 outputs a second signal. The logic control module 102 is prompted to continue to maintain the state of outputting the first signal. When the first comparator does not output the third signal and only the timing module 101 outputs the second signal, the logic control module 102 stops outputting the first signal, prompting the closure of the upper field effect tube. In the prior art, the timing module 101 outputs the second signal, and then controls the closure of the upper field effect tube through the logic control module 102, and there is no setting of the timing extension module 100. However, the present application sets the timing extension module 100. When the timing module 101 outputs the second signal, the timing extension module 100 also outputs the third signal, so as to maintain the continuous output of the first signal of the logic control module 102 until the timing extension module 100 no longer outputs the third signal, thereby extending the opening time of the upper field effect tube, reducing the difference between the feedback voltage and the preset reference voltage, facilitating rapid voltage regulation, and then achieving rapid response to instantaneous changes in the load, thereby improving the stability of the device.

[0034] For example, in some embodiments, reference Figure 1In this embodiment, K1 is a first switch, K2 is a second switch, IChange is a first current source, C2 is a first capacitor, M1 is a first comparator, VIN is a preset voltage, ONESHOT is a signal output by the timing module 101 to the logic control module 102, SHOT_ETD is a signal output by the first comparator to the logic control module 102, when the logic control module 102 detects that the feedback voltage of the buck converter is less than the preset reference voltage, that is, when a rapid load change occurs, a first signal is output to the upper field effect transistor of the buck converter, and the first signal controls the upper field effect transistor to turn on, wherein the first signal is a high level, and the timing module 101 is used to output a second signal, wherein the second signal is also a high level, when the timing module 101 outputs the second signal, the first switch is closed, and the second switch is opened, so that the first current source can start to charge the first capacitor, so that when the first capacitor stops charging, the first capacitor can continue to maintain the voltage value for a period of time, similarly, when the timing module 101 does not output the second signal, that is, when the timing module 101 outputs a low level, the first switch is closed. The switch is turned off and the second switch is closed. At this time, the first current source stops charging the first capacitor. The reverse input terminal of the first comparator is connected to the preset voltage, and the positive input terminal is connected between the first current source and the first capacitor. While the first current source charges the first capacitor, the voltage at the positive input terminal of the first comparator is gradually rising. When the voltage at the positive input terminal of the first comparator is less than the preset voltage, the output terminal of the first comparator outputs a third signal to the logic control module 102, wherein the third signal is a low level. At this time, under the joint action of the second output signal and the third output signal, the logic control module 102 is controlled to keep outputting the first signal continuously, so as to cause the upper field effect tube to be continuously turned on. When the voltage at the positive input terminal of the first comparator is greater than the preset voltage, the output terminal of the first comparator no longer outputs the third signal, that is, it starts to output a high level to the logic control module 102. At this time, the logic control module 102 stops outputting the first signal, so as to cause the upper field effect tube to be turned off, thereby extending the turn-on time of the upper field effect tube, so as to cause the difference between the feedback voltage and the preset voltage not to be too large, so as to shorten the circuit adjustment time and improve the stability of the device.

[0035] It can be understood that: the timing module 101 includes a second current source, a third switch, a fourth switch and a second comparator, the second current source is respectively connected to the positive input terminal, the third switch and the fourth switch of the second comparator, the reverse input terminal of the second comparator is connected to the output voltage of the buck converter, and the output terminal of the second comparator is connected to the logic control module 102.

[0036] For example, in some embodiments, reference Figure 1In this embodiment, VIN / R is the second current source, K3 is the third switch, K4 is the fourth switch, M2 is the second comparator, and VOUT is the output voltage. When the voltage at the positive input terminal of the second comparator is greater than the output voltage, the output terminal of the second comparator outputs the second signal to the logic control module 102. At this time, the third switch is closed, causing the second current source to be directly grounded, thereby causing the voltage at the positive input terminal of the second comparator to drop, so that the output terminal of the second comparator is switched from the second signal to a low level, and the fourth switch is controlled by the logic control module 102. When the logic control module 102 outputs the first signal, the fourth switch is disconnected. Conversely, when the logic control module 102 does not output the first signal, the fourth switch is closed, causing the second current source to be directly grounded, so that the voltage at the positive input terminal of the second comparator will not gradually increase, so as to prevent the timing module 101 from outputting the second signal when the upper field effect tube is not turned on.

[0037] It can be understood that: the timing module 101 further includes a second capacitor, one end of the second capacitor is connected to the positive input end of the second comparator, the other end is grounded, and the second capacitor is connected in parallel with the third switch and the fourth switch.

[0038] For example, in some embodiments, reference Figure 1 In this embodiment, C1 is the second capacitor. When the second current source is not directly grounded, the second current source continuously charges the second capacitor. When the second current source is directly grounded, the current no longer flows to the second capacitor and the second comparator. At this time, the second capacitor can still keep the voltage at the positive input terminal of the second comparator unchanged for a period of time, thereby keeping the voltage at the positive input terminal of the second comparator greater than the output voltage, so that the second comparator can continuously output the second signal to the logic control module 102 within a certain period of time, which is more conducive to signal transmission and response.

[0039] It can be understood that: the logic control module 102 includes a first OR gate, a NOR gate, a second OR gate, a first AND gate, a NAND gate, a second AND gate and a third comparator, the first input end of the first OR gate is connected to the output end of the second comparator, the second input end of the first OR gate is connected to the output end of the first comparator, the output end of the first OR gate is connected to the first input end of the NOR gate, the second input end of the NOR gate is connected to the output end of the second OR gate, the output end of the NOR gate is connected to the first input end of the second OR gate, the first input end of the first AND gate is connected to the output end of the first comparator, the output end of the first AND gate is connected to the second input end of the second OR gate, the first input end of the NAND gate is connected to the output end of the second OR gate, the output end of the second OR gate is also connected to the buck converter, the output end of the NAND gate is connected to the second input end of the second AND gate, the output end of the second AND gate is respectively connected to the second input end of the first AND gate and the second input end of the NAND gate, the output end of the third comparator is connected to the first input end of the second AND gate, the first positive input end of the third comparator is used to access the preset reference voltage, and the first negative input end of the third comparator is used to access the feedback voltage.

[0040] For example, in some embodiments, reference Figure 1 In this embodiment, A1 is the first OR gate, A2 is the NOR gate, A3 is the second OR gate, A4 is the first AND gate, A5 is the NAND gate, A6 is the second AND gate, M3 is the third comparator, HSON is the output signal of the second OR gate, PWM is the output signal of the second AND gate, the output signal SHOT_ETD of the output end of the first comparator takes the negation value and is connected to the first input end of the first AND gate, the output end of the second OR gate is connected to the upper field effect transistor of the buck converter, when the output end of the second OR gate outputs the first signal, that is, a high level, the upper field effect transistor is turned on, when the output end of the second OR gate outputs a low level, the upper field effect transistor is turned off, and at the same time, the lower field effect transistor of the buck converter is turned on.

[0041] It can be understood that: the logic control module 102 also includes a trigger, a NOT gate and a third OR gate, the output end of the second AND gate is connected to the second input end of the NAND gate through the trigger, the output end of the NAND gate is connected to the first input end of the third OR gate, the output end of the third OR gate is connected to the second input end of the second AND gate, the second input end of the third OR gate is used to access the preset blank voltage of the logic control module 102, the zeroing end of the trigger is used to access the overcurrent voltage of the control circuit, and the clock end of the trigger is used to access the overcurrent voltage through the NOT gate.

[0042] For example, in some embodiments, reference Figure 1In this embodiment, A7 is a NOT gate, A8 is a third OR gate, D is a trigger, LSBLank is a preset blank voltage, the zeroing end of the trigger is connected to the overcurrent voltage of the control circuit of the present application, and at the same time, the overcurrent voltage signal takes a negation value and is connected to the clock end of the trigger. The trigger is a rising edge trigger. Since the output end of the second AND gate is connected to the second input end of the NAND gate through the trigger, that is, when the electrical signal received by the clock end of the trigger changes from a low level to a high level and generates a rising edge, the trigger will transmit the signal at the output end of the second AND gate to the second input end of the NAND gate, so as to facilitate monitoring of the overcurrent voltage.

[0043] It should be noted that the preset blank voltage can be freely set as needed.

[0044] It is understandable that the logic control module 102 also includes an error amplifier, the positive input terminal of the error amplifier is used to access the preset reference voltage, the negative input terminal of the error amplifier is used to access the feedback voltage, and the output terminal of the error amplifier is connected to the second positive input terminal of the third comparator.

[0045] For example, in some embodiments, reference Figure 1 In this embodiment, EAO is the output signal of the error amplifier. Since the feedback voltage follows the value of the bottom of the preset reference voltage, there will be an error voltage between the feedback voltage and the reference voltage, so that an error may occur when the comparison is performed by the third comparator. Therefore, an error amplifier is set, and the output signal of the error amplifier is connected to the second positive input terminal of the third comparator, that is, the error voltage is also added to the input terminal of the third comparator, so as to reduce the error and improve the accuracy of the circuit.

[0046] It can be understood that the second inverting input terminal of the third comparator is connected to the ramp signal of the logic control module 102 .

[0047] For example, in some embodiments, reference Figure 1 and Figure 2 In this embodiment, RAMP is a ramp signal. By connecting the ramp signal to the second inverting input terminal of the third comparator, it is easy to solve the problem of time delay change of the circuit periodic signal caused by noise, that is, the signal edge has a slight offset on the time axis, thereby improving the stability of the circuit.

[0048] It can be understood that: the trigger is a data trigger.

[0049] For example, in some embodiments, reference Figure 1In this embodiment, the trigger is a data trigger. The setting of the trigger is convenient for the timing expansion module 100 to extend the opening time of the upper field effect tube to fail when the control circuit has an overcurrent, that is, the circuit exceeds the rated value of normal operation, until the current returns to the normal range. The specific principle is as follows: Figure 2 , wherein the dotted waveform represents the waveform of the related art without the timing expansion module 100 to extend the opening time of the upper field effect tube, and the solid waveform is the waveform reflected by the control circuit of the present application. When the load is in a fast response, that is, the feedback voltage is less than the preset reference voltage and no overcurrent is generated, since the overcurrent voltage passes through the NOT gate, that is, it is connected to the trigger after taking the NOT value, when the rising edge of the trigger is triggered, that is, when the overcurrent voltage VALLEY_OC changes from a high level to a low level, the output terminal signal PWM of the second AND gate is a low level at this time, so the signal transmitted to the second input terminal of the NAND gate is a low level. Therefore, the fifth logic gate outputs a high level, and the preset blank voltage at this stage is consistent with the overcurrent voltage waveform, and also outputs a low level, prompting the output end of the third OR gate to output a high level, so that the output signal PWM of the second AND gate output end is a high level and is output to the second input end and trigger of the first AND gate. At this time, the first comparator does not output the third signal, so the output of the first comparator is a low level, and the low level is inverted to become a high level and then connected to the first input end of the first AND gate. Therefore, the output signal of the first AND gate is a high level, prompting the second OR gate to continue to output the first signal, thereby extending the opening time of the upper field effect tube. When the load changes rapidly and overcurrent occurs, it can be seen that when the overcurrent voltage VALLEY_OC changes from a high level to a low level, the output signal PWM of the second AND gate is a high level at this time, so the second input terminal of the NAND gate is connected to a high level, and then the output terminal of the NAND gate outputs a low level. At the same time, the blank preset voltage at this time is in a low level state, prompting the third OR gate to output a low level, so that the second AND gate outputs a low level at this time, so that when the second comparator outputs the third signal and the first comparator outputs the second signal, the output signal HSON of the second OR gate is low, that is, the timing expansion module 100 fails, and the opening time of the upper field effect tube is no longer extended until the overcurrent state ends.

[0050] For example, reference Figure 1 , Figure 2 and Figure 3 , the operating principle of the control circuit of the present application is described in detail through specific embodiments:

[0051] The waveform of PART1 is in the normal state, the waveform of PART2 is under rapid load change, IL is the inductor current waveform, FB is the waveform of the feedback voltage, VREF is the waveform of the preset reference voltage, undershoot is the maximum voltage difference between the feedback voltage and the preset voltage. The dashed waveform represents the waveform without the timing extension module 100 in the related art to extend the turn-on time of the upper MOSFET, and the solid waveform is the waveform reflected by the control circuit of the present application. When FB + RAMP < VREF + EAO without rapid load change and overcurrent in the circuit, the third comparator outputs a high level. Since the upper MOSFET is initially in the off state, that is, the output of the second OR gate should be low, so the output of the NAND gate should be high, and the output of the third OR gate should be high, making both the first input terminal and the second input terminal of the second AND gate high level, and then the second AND gate outputs a high-level signal PWM. At the same time, the first comparator outputs a third signal, that is, a low level. After the low level is inverted to a high level, it is input to the first input terminal of the first AND gate. The second input terminal of the first AND gate is connected to the output signal PWM of the second AND gate, so the first AND gate outputs a high level. And at this time, the second comparator outputs a low level, which together with the low level output by the first comparator, makes the first OR gate output a low level. Then it can be known that the NOR gate outputs a low level, and the output signal HSON of the second OR gate is high level. Then the output signal HSON controls the turn-on of the upper MOSFET of the buck converter, which promotes the slow rise of the output voltage and drives the rise of the feedback voltage. When FB + RAMP > VREF + EAO, the third comparator outputs a low-level signal, which makes the output signal PWM of the second AND gate low level, and promotes the output of the first AND gate to become low level. At this time, the output signal HSON of the second OR gate will continuously output the first signal until the voltage at the positive input terminal of the second comparator is greater than the output voltage, and the second comparator outputs a second signal, that is, ONESHOT turns high level, making the first OR gate output high level, promoting the NOR gate to output low level, and the second OR gate to output low level, that is, the second OR gate stops outputting the first signal and turns to output low level. Therefore, the upper MOSFET turns off, and at the same time, the lower MOSFET of the buck converter is turned on. From Figure 2 It can be seen that in the normal state, the turn-on time of the upper MOSFET is the time period from when the PWM signal starts to be high level to when the ONESHOT signal starts to be high level. Its specific time can be calculated by the following formula:

[0052]

[0053] Among them, in this formula, TON is the conduction time of the upper MOSFET, C1 is the capacitance of the second capacitor, VIN / R is the current of the second current source, and VOUT is the value of the output voltage.

[0054] When the control circuit is in a state of rapid load change and no overcurrent occurs, the difference between the feedback voltage and the preset reference voltage is large. Therefore, during this period of time, the value of the feedback voltage is always less than the preset reference voltage. Therefore, the third comparator will continue to output a high level, so that the output signal PWM of the second AND gate will not be a low level due to the low level output of the third comparator during the rapid load change process. When the second comparator outputs a high level, the second AND gate can still maintain a high level output, and then the second OR gate still maintains the output of the first signal, that is, keeps the upper field effect tube turned on, until the voltage of the positive input of the first comparator is greater than the preset voltage, the first comparator outputs a high level, so that the first OR gate outputs a high level and the first AND gate outputs a low level, prompting the second OR gate to output a low level, so that the upper field effect tube is turned off, and the lower field effect tube is turned on, thereby extending the opening time of the upper field effect tube, so that the output voltage rises faster, and then drives the feedback voltage to rise faster until it is greater than the preset reference voltage. Among them, the extended opening time of the upper field effect tube can be obtained by the following formula:

[0055]

[0056] Wherein, in this formula, TON_EXTEND is the on-time extension of the upper field effect tube, and TON_EXTEND is equal to TON, C2 is the capacity of the first capacitor, VTH is the value of the preset voltage, and I Charge is the current of the first current source.

[0057] When an overcurrent phenomenon occurs during the rapid load change, since the overcurrent voltage passes through the NOT gate, that is, it is connected to the trigger after taking the NOT value, when the trigger is triggered by the rising edge, that is, when the overcurrent voltage VALLEY_OC changes from a high level to a low level, the output signal PWM of the second AND gate is a low level at this time, so the signal transmitted by the trigger to the second input terminal of the NAND gate is a low level, so the fifth logic gate outputs a high level, and since the preset blank voltage at this stage is consistent with the overcurrent voltage waveform, it also outputs a high level, prompting the output terminal of the third OR gate to output a high level, so that the output signal PWM of the second AND gate output terminal is a high level output to the second input terminal of the first AND gate and the trigger, at this time the first comparator does not output the third signal, so the first comparator outputs a low level, and the low level is taken NOT to become a high level and connected to the first input terminal of the first AND gate, so the output signal of the first AND gate is a high level, prompting the second OR gate to continue to output the first signal, thereby extending the opening time of the upper field effect tube. When the load changes rapidly and overcurrent occurs, it can be seen that when the overcurrent voltage VALLEY_OC changes from a high level to a low level, the output signal PWM of the second AND gate is a high level at this time, prompting the trigger to transmit the high level to the second input terminal of the NAND gate, and then the output terminal of the NAND gate outputs a low level. At the same time, the blank preset voltage at this time is in a low level state, prompting the third OR gate to output a low level, so that the second AND gate outputs a low level at this time, so that when the second comparator outputs the third signal and the first comparator outputs the second signal, the output signal HSON of the second OR gate is low, that is, the timing expansion module 100 fails, and the opening time of the upper field effect tube is no longer extended until the overcurrent state ends.

[0058] The converter according to the embodiment of the second aspect of the application includes the control circuit of the embodiment of the first aspect of the application.

[0059] According to the converter of the embodiment of the present application, by setting the logic control module 102, it is convenient to output the first signal when it is detected that the feedback voltage is less than the preset reference voltage to control the opening of the upper field effect tube, and by setting the timing module 101, it is convenient to output the second signal to the logic control module 102 after the upper field effect tube is turned on for the required time. The setting of the timing expansion module 100, by setting the first switch, is convenient to control the closing of the first switch when it is detected that the timing module 101 outputs the second signal, so as to prompt the first current source and the first capacitor and the positive input terminal of the first comparator to remain in the on state, so that the first current source continues to charge the first capacitor, so that when the first current source stops inputting current, the first capacitor can still maintain a stable voltage for a period of time, and when the voltage at the positive input terminal of the first comparator is less than the preset voltage, the first comparator outputs a third signal to the logic control module 102, and the timing module 101 outputs the second signal, prompting the logic control module 102 to continue to output the first The state of the signal, and when the first comparator does not output the third signal and only the timing module 101 outputs the second signal, the logic control module 102 stops outputting the first signal, prompting the closure of the upper field effect tube. In the prior art, the timing module 101 outputs the second signal, and then controls the closure of the upper field effect tube through the logic control module 102, and there is no setting of the timing extension module 100. However, the present application sets the timing extension module 100. When the timing module 101 outputs the second signal, the timing extension module 100 also outputs the third signal, so as to maintain the continuous output of the first signal of the logic control module 102 until the timing extension module 100 no longer outputs the third signal, thereby extending the opening time of the upper field effect tube, reducing the difference between the feedback voltage and the preset reference voltage, facilitating the rapid adjustment of the voltage, and then realizing a rapid response to the instantaneous change of the load, thereby improving the stability of the equipment. By introducing the control circuit of the present application, it can respond to the instantaneous change of the load in a timely manner.

[0060] Since the converter includes the control circuit of the first aspect embodiment, the corresponding contents of the control circuit in the first aspect embodiment are all applicable to the converter of the second aspect and have the same implementation principles and technical effects. In order to avoid redundant description, it will not be described in detail here.

[0061] The system according to the third aspect embodiment of the application includes the converter of the second aspect embodiment of the application.

[0062] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0063] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0064] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0065] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0066] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0067] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0068] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0069] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0070] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0071] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0072] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A control circuit, characterized in that: include: A logic control module, wherein the output end of the logic control module is used to connect to the buck converter, and the logic control module is used to output a first signal to the upper field effect transistor of the buck converter when detecting that the feedback voltage of the buck converter is less than a preset reference voltage, wherein the first signal is used to turn on the upper field effect transistor; a timing module, the timing module being connected to the logic control module and configured to output a second signal to the logic control module; A timing expansion module, the timing expansion module includes a first switch, a second switch, a first current source, a first capacitor and a first comparator, one end of the first current source is connected to the first switch, and the other end is respectively connected to the second switch, the positive input end of the first comparator, and the first capacitor, the first switch is used to close when the second signal output is detected, and the second switch is used to close when the second signal output is not detected, the reverse input end of the first comparator is used to access the preset voltage of the timing expansion module, the output end of the first comparator is connected to the logic control module, and the first comparator is used to output a third signal to the logic control module when it is detected that the voltage at the positive input end of the first comparator is less than the preset voltage. The logic control module is also used to maintain the state of outputting the first signal when it is detected that the timing module outputs the second signal and the timing extension module outputs the third signal; the logic control module is also used to stop outputting the first signal when it is detected that the timing module outputs the second signal and the timing extension module does not output the third signal.

2. The control circuit according to claim 1, characterized in that: The timing module includes a second current source, a third switch, a fourth switch and a second comparator. The second current source is respectively connected to the positive input terminal, the third switch and the fourth switch of the second comparator. The reverse input terminal of the second comparator is connected to the output voltage of the buck converter. The output terminal of the second comparator is connected to the logic control module.

3. The control circuit according to claim 2, characterized in that: The timing module further includes a second capacitor, one end of which is connected to the positive input end of the second comparator, and the other end of which is grounded, and the second capacitor is connected in parallel to the third switch and the fourth switch.

4. The control circuit according to claim 2, characterized in that: The logic control module includes a first OR gate, a NOR gate, a second OR gate, a first AND gate, a NAND gate, a second AND gate and a third comparator. The first input end of the first OR gate is connected to the output end of the second comparator, the second input end of the first OR gate is connected to the output end of the first comparator, the output end of the first OR gate is connected to the first input end of the NOR gate, the second input end of the NOR gate is connected to the output end of the second OR gate, the output end of the NOR gate is connected to the first input end of the second OR gate, the first input end of the first AND gate is connected to the output end of the first comparator, the output end of the first AND gate is connected to the second input end of the second OR gate, the first input end of the NAND gate is connected to the output end of the second OR gate, the output end of the second OR gate is also connected to the buck converter, the output end of the NAND gate is connected to the second input end of the second AND gate, the output end of the second AND gate is respectively connected to the second input end of the first AND gate and the second input end of the NAND gate, the output end of the third comparator is connected to the first input end of the second AND gate, the first positive input end of the third comparator is used to access the preset reference voltage, and the first negative input end of the third comparator is used to access the feedback voltage.

5. The control circuit according to claim 4, characterized in that: The logic control module also includes a trigger, a NOT gate and a third OR gate, the output end of the second AND gate is connected to the second input end of the NAND gate through the trigger, the output end of the NAND gate is connected to the first input end of the third OR gate, the output end of the third OR gate is connected to the second input end of the second AND gate, the second input end of the third OR gate is used to access the preset blank voltage of the logic control module, the zeroing end of the trigger is used to access the overcurrent voltage of the control circuit, and the clock end of the trigger is used to access the overcurrent voltage through the NOT gate.

6. The control circuit according to claim 4, characterized in that: The logic control module also includes an error amplifier, the positive input terminal of the error amplifier is used to access the preset reference voltage, the negative input terminal of the error amplifier is used to access the feedback voltage, and the output terminal of the error amplifier is connected to the second positive input terminal of the third comparator.

7. The control circuit according to claim 4, characterized in that: The second inverting input terminal of the third comparator is connected to the ramp signal of the logic control module.

8. The control circuit according to claim 5, characterized in that: The trigger is a data trigger.

9. A converter, characterized in that: include: A control circuit as claimed in any one of claims 1 to 8.

10. A system, characterized in that: include: A converter as claimed in claim 9.

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