A method for recovering fault-encapsulated waves in a T-type three-level circuit

Abstract

The present application discloses a method for processing fault wave sealing and recovery in a T-type three-level circuit, comprising the following steps: increasing the drive signal response time and / or wave sealing recovery signal response time of the vertical pipe relative to the horizontal pipe, so that the vertical pipe is turned on after the horizontal pipe during wave sealing recovery. Alternatively, only the vertical pipe is subjected to hardware wave sealing processing, and the horizontal pipe is always in a conducting state; and then, when wave sealing recovery is performed, the vertical pipe is turned on after the horizontal pipe based on the hardware wave sealing structure. The beneficial effects of the present application: Compared with the traditional method, the normally closed horizontal pipe can be ensured to be turned on before the high-frequency vertical pipe during the wave sealing recovery process of the system, thereby avoiding the risk of overvoltage of the high-frequency cross pipe and improving the stability of the system.

Description

Technical Field

[0001] The present application relates to the field of renewable energy power generation technology, and in particular to a method for recovering a fault-encapsulated wave in a T-type three-level circuit. Background Art

[0002] The T-type three-level circuit is a widely used circuit structure in power electronics, particularly in inverter design. Its basic structure consists of four switching transistors and associated components such as diodes and capacitors. These switches are arranged in a specific pattern to form a shape similar to the letter "T."

[0003] When a fault occurs in a T-type three-level circuit, its inherent fault protection measures control the switching transistors into a blocking mode. Once the fault is resolved, the switching transistors can resume oscillation. However, during the blocking recovery process in conventional T-type three-level circuits, there are no specific restrictions on the switching transistor recovery sequence; it is determined solely by the timing corresponding to conventional modulation. Therefore, during the blocking recovery process, the high-frequency risers corresponding to the positive and negative current cycles may resume conduction before the normally closed cross-circuit transistors, exposing the high-frequency cross-circuit transistors to overvoltage and potentially causing system failure. Summary of the Invention

[0004] One of the objectives of the present application is to provide a method for recovering a fault envelope of a T-type three-level circuit that can solve at least one of the defects in the above-mentioned background technology.

[0005] In order to achieve at least one of the above-mentioned purposes, the technical solution adopted in the present application is: a T-type three-level circuit fault wave sealing recovery processing method, comprising the following steps: increasing the drive signal response time and / or wave sealing recovery signal response time of the vertical tube relative to the horizontal tube, so that when the vertical tube performs wave sealing recovery, the vertical tube is turned on after the horizontal tube.

[0006] Preferably, the vertical tube responds to the driving signal through the vertical tube driving circuit, and the horizontal tube responds to the driving signal through the horizontal tube driving circuit; by increasing the response time of the vertical tube driving circuit to the driving signal and / or shortening the response time of the horizontal tube driving circuit to the driving signal, the vertical tube is turned on after the horizontal tube when the vertical tube performs wave sealing recovery.

[0007] Preferably, the vertical tube driving circuit and the horizontal tube driving circuit both include a driving chip, an on-resistor and a gate capacitor; the driving chip is connected in series with the on-resistor, and the gate capacitor is connected in parallel with the on-resistor to form an RC control circuit; by adjusting the resistance of the on-resistor and / or the capacitance of the gate capacitor, the response time of the driving signal is controlled.

[0008] Preferably, the wave encapsulation recovery signal is generated by a wave encapsulation system, which includes a wave encapsulation signal generating module, a latch module, a horizontal pipe wave encapsulation unit and a vertical pipe wave encapsulation unit; the wave encapsulation signal generating module is suitable for outputting the wave encapsulation recovery signal, the input end of the vertical pipe wave encapsulation unit is signal-connected with the wave encapsulation signal generating module through the latch module, the output end of the vertical pipe wave encapsulation unit is suitable for sending a conduction signal to the vertical pipe, and the latch module is suitable for delaying the wave encapsulation recovery signal sent by the wave encapsulation signal generating module; the input end of the horizontal pipe wave encapsulation unit is signal-connected with the wave encapsulation signal generating module, and the output end of the horizontal pipe wave encapsulation unit is suitable for sending a conduction signal to the horizontal pipe.

[0009] Preferably, the latch module includes a latch unit and a delay unit; the output of the horizontal pipe wave sealing unit serves as the input of the delay unit, and the output of the delay unit and the output of the wave sealing signal generating module both serve as the input of the latch unit, and then the latch unit sends the delayed wave sealing recovery signal to the vertical pipe wave sealing unit.

[0010] Preferably, the delay unit adopts an RC circuit structure.

[0011] Preferably, the latch module includes a comparison unit and a latch unit; the midpoint voltage of the horizontal pipe and the preset reference voltage serve as inputs of the comparison unit, and the output of the comparison unit and the output of the wave-enclosing signal generating module serve as inputs of the latch unit, and then the latch unit sends the delayed wave-enclosing recovery signal to the vertical pipe wave-enclosing unit.

[0012] Preferably, when the wave is restored to the positive half cycle of the current, the preset reference voltage V ref ≤[(V BUS / 2)+ΔV] / N; When the wave is restored to the negative half cycle of the current, the preset reference voltage V ref ≤ΔV / N; where V BUS represents the bus voltage, ΔV represents the voltage margin, and N represents the midpoint voltage sampling divider ratio of the cross tube.

[0013] Preferably, the latch unit is an AND gate unit.

[0014] A T-type three-level circuit fault wave sealing recovery processing method includes the following steps: performing hardware wave sealing processing only on the vertical pipe, and the horizontal pipe is always in the conductive state; and then, when performing wave sealing recovery, the vertical pipe is conductive after the horizontal pipe based on the hardware wave sealing structure.

[0015] Compared with the prior art, the present invention has the following advantages:

[0016] Compared with the traditional method, the present application can ensure that the normally closed cross pipe is turned on before the high-frequency vertical pipe during the system's wave blocking recovery process, thereby avoiding the overvoltage risk of the high-frequency cross pipe and improving the stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the circuit structure of an existing T-type three-level three-phase inverter.

[0018] Figure 2 for Figure 1 Current diagram of the middle a-phase bridge arm during normal operation in the negative half cycle of current.

[0019] Figure 3 for Figure 1 Current diagram of the middle phase a bridge arm when the surge protection is triggered during the negative half-cycle of the current.

[0020] Figure 4 for Figure 1 Schematic diagram of the current flow through the left tube Qa3 in the middle a-phase bridge arm when the surge protection is triggered during the negative half-cycle of the current.

[0021] Figure 5 for Figure 1 Schematic diagram of the current flow in the middle a-phase bridge arm, where the upper tube Qa1 turns on first when the blocking wave of the current is restored in the negative half-cycle.

[0022] Figure 6 for Figure 1 Schematic diagram of the current flow in the middle a-phase bridge arm, where the lower tube Qa2 turns on first when the blocking wave of the current is restored in the negative half-cycle.

[0023] Figure 7 for Figure 1 Voltage stress waveform of the right tube Qa4 in the middle a-phase bridge arm when the blocking wave is restored in the negative half cycle of the current.

[0024] Figure 8 for Figure 1 Schematic diagram of the current flow in the middle a-phase bridge arm, where the left tube Qa3 turns on first when the blocking wave of the current is restored in the negative half-cycle.

[0025] Figure 9 for Figure 1 Schematic diagram of the current flow in which the right tube Qa4 is turned on first when the middle a-phase bridge arm recovers from the blocking wave of the current negative half cycle.

[0026] Figure 10 for Figure 1 Current diagram of the middle a-phase bridge arm during normal operation in the positive half cycle of current.

[0027] Figure 11 for Figure 1 Schematic diagram of the current flow through the right tube Qa3 in the middle a-phase bridge arm when the surge protection is triggered during the positive half-cycle of the current.

[0028] Figure 12 for Figure 1 Schematic diagram of the current flow in the middle a-phase bridge arm, where the upper tube Qa1 turns on first when the current waveform is restored in the positive half-cycle.

[0029] Figure 13 for Figure 1 Schematic diagram of the current flow in the middle a-phase bridge arm, where the lower tube Qa2 turns on first when the current waveform is restored in the positive half-cycle.

[0030] Figure 14 for Figure 1 Schematic diagram of the current flow in which the left tube Qa3 in the middle a-phase bridge arm turns on first when the blocking wave of the current is restored in the positive half cycle.

[0031] Figure 15 for Figure 1 Schematic diagram of the current flow in which the right tube Qa4 is turned on first when the middle a-phase bridge arm recovers from the current surge in the positive half-cycle.

[0032] Figure 16 This is a schematic diagram of the workflow of this application.

[0033] Figure 17 This is a schematic diagram of the layout of the drive circuit of the a-phase bridge arm in this application.

[0034] Figure 18 for Figure 17 Specific circuit topology diagram of the driving circuit in FIG.

[0035] Figure 19 Schematic diagram of the structure of the existing wave enclosing system.

[0036] Figure 20 This is a structural diagram of the wave-sealing system after adding a latch module in this application.

[0037] Figure 21 This is a structural diagram of one example of the latch module in this application.

[0038] Figure 22 This is a structural diagram of another example of the latch module in this application.

[0039] Figure 23 This is a structural diagram of the wave sealing system for independently sealing the vertical pipe in this application.

[0040] In the figure: an encapsulation signal generating module 100 , a vertical pipe encapsulation unit 210 , a horizontal pipe encapsulation unit 220 , a vertical pipe driving circuit 310 , a horizontal pipe driving circuit 320 , a latch module 400 , a latch unit 401 , a delay unit 402 , and a comparison unit 403 . DETAILED DESCRIPTION

[0041] Below, the present application is further described in conjunction with specific implementation methods. It should be noted that, in the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like are intended to mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0042] In the description of this application, it should be noted that for directional words, such as the terms "center", "horizontal", "longitudinal", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and so on, indicating the orientation and position relationship are based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and cannot be understood as limiting the specific scope of protection of this application.

[0043] It should be noted that the terms "first", "second", etc. in the description and claims of this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0044] In this application, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they may refer to connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0045] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0046] The terms "comprises" and "having" and any variations thereof in the specification and claims of this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to such process, method, product or apparatus.

[0047] In order to facilitate the understanding of the technical solution of the present application, a circuit analysis of the fault wave recovery of the T-type three-level circuit may be first performed below.

[0048] like Figure 1 Figure 2 shows the circuit architecture of a traditional T-type three-level three-phase inverter. It primarily consists of three bridge arms: phase a, phase b, and phase c. Each arm includes four switching transistors. Taking phase a as an example, these four switching transistors are top transistor Qa1, bottom transistor Qa2, left transistor Qa3, and right transistor Qa4. Based on the layout of the switching transistors, top transistor Qa1 and bottom transistor Qa2 are defined as vertical transistors, while left transistor Qa3 and right transistor Qa4 are defined as horizontal transistors.

[0049] It should be noted that there are many specific types of switching tubes, which can be MOSFET devices, IGBT devices, or their series and parallel forms; for the convenience of subsequent description, this application will use the switching tube using MOSFET devices as an example for explanation.

[0050] The top tube Qa1's C-pole is connected to the positive busbar BUS+, and its E-pole is connected to the C-pole of the bottom tube Qa2. The E-pole of the bottom tube Qa2 is connected to the negative busbar BUS-. The C-pole of the left tube Qa3 is connected to the C-pole of the right tube Qa4, and its E-pole is connected to the busbar midpoint BUSN. The E-pole of the right tube Qa4 is connected to the E-pole of the top tube Qa1 (and the C-pole of the bottom tube Qa2).

[0051] The two risers need to withstand the full bus voltage V when working. BUS, that is, the voltage difference between the positive bus BUS+ and the negative bus BUS-, and the two cross tubes only need to withstand half the bus voltage V BUS / 2, that is, the voltage difference between the positive bus BUS+ and the bus midpoint BUSN or the negative bus BUS- and the bus midpoint BUSN. For the convenience of explanation, the subsequent content takes the bus midpoint BUSN as the 0 potential reference point, and the potential of the positive bus BUS+ is V BUS / 2, the potential of the negative bus BUS- is -V BUS / 2.

[0052] When an inverter fault occurs, it may trigger a surge protection. In some cases, the inverter may proactively attempt to restore normal operation by re-energizing the switches within a short period of time after the fault occurs, such as through wave-by-wave current limiting. In scenarios where the inverter re-energizes and resumes normal operation within the short surge protection period, the T-type three-level circuit has certain requirements for the turn-on timing of each switch. Due to the different current cycles during which surge recovery occurs, the conduction states of the horizontal and vertical switches may differ. The following analysis uses the scenario where the phase a bridge arm is in the negative and positive half-cycles of the current during surge recovery.

[0053] 1. The wave blocking recovery is in the negative half cycle of the current.

[0054] like Figure 2 As shown, before the wave is sealed, the upper tube Qa1 is normally open, the left tube Qa3 is normally closed, and the lower tube Qa2 and the right tube Qa4 are alternately turned on. Note that the current direction of the inductor La is assumed to be as follows: Figure 2 As shown, it flows from the right end to the left end. After the wave blocking protection is triggered, the switch tubes Qa1-Qa4 are all turned off. Due to the effect of the inductor La, the body diode of the upper tube Qa1 can form the following Figure 3 The freewheeling path shown. At this time, the e-pole potential of the right tube Qa4 is clamped to V BUS / 2+V F1 , V F1 is the forward voltage drop of the body diode in the vertical tube.

[0055] like Figure 4 As shown, the inductor La charges the parasitic capacitor C3 of the left tube Qa3 through the body diode of the right tube Qa4. At this time, the voltage drop borne by the left tube Qa3 is approximately half the bus voltage V BUS / 2, the voltage drop on the right tube Qa4 is the body diode conduction voltage drop V F2 .

[0056] Scenario 1: The upper tube Qa1 resumes conduction first.

[0057] like Figure 5 As shown, if the upper tube Qa1 is turned on first when the wave is restored, the inductor current i LFlows to the positive busbar BUS+ through the main channel of the upper tube Qa1. At this time, the e-pole potential of the right tube Qa4 is clamped to V BUS / 2+V on1 , where V on1 is the conduction voltage drop of the vertical tube, and the voltage drop borne by the left tube Qa3 is about half the bus voltage V BUS / 2, the pressure drop on the right tube Qa4 is approximately 0, so there is no overpressure risk for both the left tube Qa3 and the right tube Qa4.

[0058] Scenario 2: The lower tube Qa2 resumes conduction first.

[0059] like Figure 6 As shown in the figure, if the lower tube Qa2 turns on first when the wave is restored, the cathode potential of the body diode of the right tube Qa4 will be higher than the anode potential, and the body diode of the right tube Qa4 will enter the reverse recovery state. The parasitic capacitance C3 of the left tube Qa3 discharges to the lower tube Qa2 through the body diode of the right tube Qa4, and the discharge amount Q is equal to the reverse recovery charge of the diode. At this time, the c-pole potential V C =V BUS / 2-Q / C3, C3 represents the capacitance value of parasitic capacitor C3; the voltage drop on the left tube Qa3 is V C -V BUS / 2, the pressure drop on the right tube Qa4 is V C +V BUS / 2. The withstand voltage of the left tube Qa3 and the right tube Qa4 is half the bus voltage V BUS Therefore, under certain operating conditions, such as when the bus voltage is high and the reverse recovery charge of the body diode of the right transistor Qa4 is small, there is a risk of overvoltage on the right transistor Qa4.

[0060] Specifically, such as Figure 7 The figure shows the voltage stress waveform of the right tube Qa4. The waveform is blocked at time t1 and re-transmitted at time t2. Before time t1, the voltage stress on the right tube Qa4 is half the bus voltage V BUS / 2, after the wave is blocked at time t1, the e-pole potential of the right tube Qa4 is clamped to the bus voltage V BUS , the body diode of the right tube Qa4 is turned on. At this time, the voltage stress on the right tube Qa4 is the body diode conduction voltage drop V F2 .

[0061] At time t2, the lower tube Qa2 is turned on, and the e-pole potential of the right tube Qa4 is clamped to the negative bus voltage V BUS- , the body diode of the right tube Qa4 reverse recovers, and the parasitic capacitance C3 of the left tube Qa3 is discharged through the body diode of the right tube Qa4. At this time, the voltage stress V C =V BUS-Q / C3. If the reverse recovery charge of the body diode of the right tube Qa4 is small, it may cause Figure 6 As shown in V C Greater than half bus voltage V BUS / 2, the right tube Qa4 will have voltage stress risk.

[0062] Scenario 3: The left tube Qa3 resumes conduction first.

[0063] like Figure 8 As shown, if the left tube Qa3 is turned on first when the wave is restored, the inductor current i L The current flows through the body diode of the right tube Qa4 and the main channel of the left tube Qa3 to the busbar midpoint BUSN. The voltage drop on the left tube Qa3 is the transverse tube conduction voltage drop V on2 , where V on2 is the conduction voltage drop of the horizontal tube, and the voltage drop borne by the right tube Qa4 is the conduction voltage drop of the body diode of the horizontal tube V F2 Therefore, there is no overpressure risk in the left tube Qa3 and the right tube Qa4.

[0064] Scenario 4: The right tube Qa4 resumes conduction first.

[0065] like Figure 9 As shown, if the right tube Qa4 is turned on first when the wave is restored, the inductor current i L The voltage drops to the negative bus BUS+ through the body diode of the upper tube Qa1. The voltage drop on the left tube Qa3 is about half the bus voltage V BUS / 2, the voltage drop on the right tube Qa4 is the transverse tube conduction voltage drop V on2 Therefore, there is no overpressure risk in the left tube Qa3 and the right tube Qa4.

[0066] 2. The wave sealing recovery is in the positive half cycle of the current.

[0067] like Figure 10 As shown in the figure, before the wave blocking, the lower tube Qa2 is normally open, the right tube Qa4 is normally closed, and the upper tube Qa1 and the left tube Qa3 are alternately turned on. At this time, the current direction of the inductor La flows from the left end to the right end. After the wave blocking protection is triggered, the switch tubes Qa1-Qa4 are all turned off. Due to the effect of the inductor La, the body diode of the lower tube Qa2 forms the following Figure 3 The freewheeling path shown. At this time, the e-pole potential of the right tube Qa4 is clamped to -V BUS / 2-V F1 .

[0068] like Figure 11 As shown, the bus midpoint BUSN charges the parasitic capacitance of the right tube Qa4 through the body diode of the left tube Qa3. At this time, the voltage drop borne by the right tube Qa4 is about half the bus voltage V BUS / 2, the voltage drop on the left tube Qa3 is the body diode conduction voltage drop VF2 .

[0069] Scenario 5: The upper tube Qa1 resumes conduction first.

[0070] like Figure 12 As shown in the figure, if the upper tube Qa1 is turned on first when the wave is restored, the cathode potential of the body diode of the left tube Qa3 is higher than the anode potential, and the body diode of the left tube Qa3 enters the reverse recovery state. The parasitic capacitance C4 of the right tube Qa4 discharges the upper tube Qa1 through the body diode of the left tube Qa3, and the discharge amount Q is equal to the reverse recovery charge of the diode. At this time, the c-pole potential V C =V BUS / 2-Q / C4, C4 represents the capacitance value of parasitic capacitor C4; the voltage drop on the right tube Qa4 is V BUS / 2-V C , the pressure drop on the left tube Qa3 is V C +V BUS Therefore, under certain operating conditions, such as when the bus voltage is high and the reverse recovery charge of the body diode of the right tube Qa4 is small, there is an overvoltage risk for the left tube Qa3.

[0071] Scenario 6: The lower tube Qa2 resumes conduction first.

[0072] like Figure 13 As shown, if the lower tube Qa2 is turned on first when the wave is restored, the inductor current i L The voltage flows from the negative bus BUS- to the inductor through the lower tube Qa2. At this time, the e-pole potential of the right tube Qa4 is clamped to -V BUS / 2-V on1 , then the voltage drop on the left tube Qa3 is approximately 0, and the voltage drop on the right tube Qa4 is approximately half the bus voltage V BUS / 2, so there is no overpressure risk for the left tube Qa3 and the right tube Qa4.

[0073] Scenario 7: The left tube Qa3 resumes conduction first.

[0074] like Figure 14 As shown, if the left tube Qa3 is turned on first when the wave is restored, the inductor current i L The current flows from the negative bus BUS- to the inductor through the body diode of the lower tube Qa2. Then the e-pole potential of the right tube Qa4 is clamped to -V BUS / 2-V F1 The voltage drop on the left tube Qa3 is the transverse tube conduction voltage drop V on2 The voltage drop on the right tube Qa4 is about half the bus voltage V BUS / 2, so there is no overpressure risk for the left tube Qa3 and the right tube Qa4.

[0075] Scenario 8: The right tube Qa4 resumes conduction first.

[0076] like Figure 15 As shown, if the right tube Qa4 is turned on first when the wave is restored, the inductor current i L The current flows from the busbar midpoint BUSN to the inductor through the body diode of the left tube Qa3 and the right tube Qa4. At this time, the voltage drop borne by the left tube Qa3 is the body diode conduction voltage drop V F2 The voltage drop on the right tube Qa4 is the transverse tube conduction voltage drop V on2 Therefore, there is no overpressure risk in the left tube Qa3 and the right tube Qa4.

[0077] For ease of understanding, the horizontal pipe pressures under the above eight scenarios can be summarized in a table; among them, the vertical pipe conduction voltage drop V on1 and the conduction voltage drop of the horizontal tube V on2 Since the value is small and can be regarded as 0, the specific summary table is as follows:

[0078]

[0079] As can be seen from the table above, when recovering from a surge, only when the horizontal pipe is connected before the vertical pipe can both pipes avoid overvoltage hazards. Therefore, the core concept of this application is to control the vertical pipe to be connected after the horizontal pipe during surge recovery. There are many specific implementation methods that can achieve this requirement. For ease of understanding, the following will provide a detailed description using three specific examples.

[0080] Example 1:

[0081] like Figure 16 As shown, a T-type three-level circuit fault wave sealing recovery processing method includes the following steps: increasing the drive signal response time of the vertical tube relative to the horizontal tube, so that the vertical tube is turned on later than the horizontal tube when the vertical tube performs wave sealing recovery.

[0082] For ease of understanding, we can first briefly describe the T-type three-level circuit's wave recovery architecture. Figure 16 and Figure 17 As shown, the wave envelope recovery architecture of the T-type three-level circuit mainly includes a wave envelope system, a vertical pipe driving circuit 310, and a horizontal pipe driving circuit 320. When performing wave envelope recovery, the wave envelope system can output wave envelope recovery signals to the vertical pipe driving circuit 310 and the horizontal pipe driving circuit 320 respectively. Then, after receiving the wave envelope recovery signals, the vertical pipe driving circuit 310 and the horizontal pipe driving circuit 320 can process them and generate driving signals for controlling the vertical pipe and the horizontal pipe to conduct.

[0083] Based on the basic working process of the aforementioned T-type three-level circuit's wave-enclosure recovery architecture, this embodiment adjusts the response time of the drive signals when the vertical tube drive circuit 310 and the horizontal tube drive circuit 320 respectively send drive signals to the vertical tube and the horizontal tube, so that the vertical tube receives the drive signal after the horizontal tube. This ensures that the vertical tube is turned on later than the horizontal tube, thereby avoiding the risk of overvoltage on the horizontal tube.

[0084] It should be noted that for a single-phase bridge arm, the number of both horizontal and vertical tubes is two, so the number of both horizontal tube driving circuits 320 and vertical tube driving circuits 310 is two; each driving circuit is independently controlled and connected to the corresponding switch tube.

[0085] In this embodiment, Figure 16 As shown, based on the layout of the drive circuit architecture, there are three main specific implementation methods for increasing the response time of the vertical tube drive signal relative to the horizontal tube. The first is to increase the response time of the vertical tube drive circuit 310 to the drive signal, that is, to delay the output of the drive signal; the second is to shorten the response time of the horizontal tube drive circuit 320 to the drive signal, that is, to advance the output of the drive signal; the third is a combination of the first and second methods, that is, to increase the response time of the vertical tube drive circuit 310 to the drive signal while shortening the response time of the horizontal tube drive circuit 320 to the drive signal. All three of the above methods can meet the actual needs of this application, and those skilled in the art can choose according to their actual needs.

[0086] It is understandable that there are various specific structures of the driving circuit that can delay and advance the driving signal. For ease of understanding, a detailed description will be given below using specific examples.

[0087] Specifically, such as Figure 18 As shown, both the vertical tube drive circuit 310 and the horizontal tube drive circuit 320 include a driver chip, an on-resistance Ron, a diode D1, a gate capacitor Cge, and a voltage-stabilizing diode D2. The on-resistance Ron and the diode D1 are connected in parallel to form a protection branch. The input end of the driver chip is connected to the wave-sealing system, the output end of the driver chip is connected to the first end of the protection branch, and the second end of the protection branch is connected to the corresponding switch tube. The gate capacitor Cge and the voltage-stabilizing diode D2 are both connected in parallel between the second end of the protection branch and the bridge arm circuit, so that the gate capacitor Cge and the on-resistance Ron are connected in parallel to form an RC control circuit.

[0088] When the response time of the horizontal pipe driving circuit 320 to the driving signal needs to be shortened, the resistance of the on-resistor Ron and the capacitance of the gate-source capacitor Cge in the horizontal pipe driving circuit 320 can be reduced simultaneously. When the response time of the vertical pipe driving circuit 310 to the driving signal needs to be increased, the resistance of the on-resistor Ron and the capacitance of the gate-source capacitor Cge in the vertical pipe driving circuit 310 can be increased simultaneously.

[0089] It should be noted that whether reducing the delay of the RC control circuit in the horizontal tube drive circuit 320 or increasing the delay of the RC control circuit in the vertical tube drive circuit 310, the values of the turn-on resistor Ron and the gate-source capacitor Cge must be appropriately set based on the device performance of the vertical tube and the horizontal tube and the actual circuit differences. Too small values may cause voltage spikes or oscillations in the drive signal; too large values may cause the switch tube to conduct slowly, thus affecting normal control. Generally speaking, the difference in conduction time between the horizontal tube and the vertical tube is much smaller than the switching period of the T-type three-level circuit. Therefore, properly adjusting the delay of the drive circuit will not affect the control process of the entire system.

[0090] Example 2:

[0091] like Figure 16 As shown, a T-type three-level circuit fault wave sealing recovery processing method includes the following steps: increasing the wave sealing recovery signal response time of the vertical pipe relative to the horizontal pipe, so that the vertical pipe is turned on later than the horizontal pipe when performing wave sealing recovery.

[0092] For ease of understanding, we can first explain the traditional method of fault wave recovery in T-type three-level circuits. Figure 19 FIG. 1 is a schematic diagram of the circuit architecture of an existing conventional wave encapsulation system, which mainly includes a wave encapsulation signal generating module 100, a horizontal pipe wave encapsulation unit 220, and a vertical pipe wave encapsulation unit 210. The output end of the wave encapsulation signal generating module 100 is connected to the input ends of the horizontal pipe wave encapsulation unit 220 and the vertical pipe wave encapsulation unit 210, respectively. The output ends of the horizontal pipe wave encapsulation unit 220 and the vertical pipe wave encapsulation unit 210 are connected to the input ends of the horizontal pipe driving circuit 320 and the vertical pipe driving circuit 310, respectively.

[0093] Taking the a-phase bridge arm as an example, the number of the horizontal pipe wave-enclosing unit 220 and the vertical pipe wave-enclosing unit 210 are both two, so as to respectively connect the signals with the driving circuits of the corresponding switching tubes. Figure 19 As shown, the PWM signal generating module 100 can output a LOCK signal. When the LOCK signal is at a low level, it is a fault PWM signal. When the LOCK signal is at a high level, it is a PWM signal. Qa1 The control signal of the upper tube Qa1 of the main control output; PWM Qa2 The control signal of the lower tube Qa2 of the main control output; PWM Qa3The control signal of the left tube Qa3 of the main control output; PWM Qa4 It is the control signal of the right tube Qa4 of the main control output. CTL Qa1 CTL is the input signal of the driving circuit corresponding to the upper tube Qa1; Qa2 CTL is the input signal of the driving circuit corresponding to the lower tube Qa2; Qa3 It is the input signal of the driving circuit corresponding to the left tube Qa3; CTL Qa4 The horizontal pipe wave encapsulation unit 220 and the vertical pipe wave encapsulation unit 210 may be of various types. For ease of understanding, this embodiment uses an AND gate unit as an example for description.

[0094] When the system operates normally, the signal LOCK output by the wave encapsulation signal generating module 100 is at a high level, and the wave encapsulation unit corresponding to each switch tube will output the corresponding control signal PWM output by the master control.

[0095] When a system failure occurs and blocking is required, the blocking signal generating module 100 outputs a low-level signal LOCK, which is sent to each blocking unit and each blocking unit outputs a low-level signal, so that each switch is in a driving blocking state.

[0096] When the wave envelope recovery is required, the wave envelope signal generating module 100 outputs the signal LOCK as a high level. Qa1 or PWM Qa2 ) and the normally closed cross-tube control signal (PWM Qa3 or PWM Qa4 ) are both high. Due to differences in the opening timing and drive circuit parameters of the riser and cross tubes, the high-frequency riser may turn on before the normally closed cross tube, exposing the high-frequency cross tube to overvoltage risk. However, this embodiment delays the response time of the wave-envelope recovery signal output by the wave-envelope signal generation module 100 to the riser wave-envelope unit 210, ensuring that the riser turns on after the cross tube when the wave-envelope is restored.

[0097] In order to achieve the above functions, this embodiment improves the traditional wave encapsulation system. There are many specific ways to improve it. For the sake of easy understanding, a specific example will be used to illustrate it in detail below. Figure 20As shown, the wave encapsulation system includes a wave encapsulation signal generating module 100, a latch module 400, a horizontal pipe wave encapsulation unit 220, and a vertical pipe wave encapsulation unit 210. The wave encapsulation signal generating module 100 can output a wave encapsulation recovery signal. The input end of the vertical pipe wave encapsulation unit 210 is signal-connected to the wave encapsulation signal generating module 100 via the latch module 400. The output end of the vertical pipe wave encapsulation unit 210 can send a conduction signal to the vertical pipe. The latch module 400 can delay the wave encapsulation recovery signal sent by the wave encapsulation signal generating module 100. The input end of the horizontal pipe wave encapsulation unit 220 is signal-connected to the wave encapsulation signal generating module 100, and the output end of the horizontal pipe wave encapsulation unit 220 can send a conduction signal to the horizontal pipe.

[0098] It is understood that the conduction signal sent by the vertical tube wave sealing unit 210 to the vertical tube is the input signal corresponding to the vertical tube drive circuit 310, and the conduction signal sent by the horizontal tube wave sealing unit 220 to the horizontal tube is the input signal corresponding to the horizontal tube drive circuit 320. The function of the latch module 400 is to control the vertical tube to maintain the wave sealing state until the normally closed horizontal tube is opened or the high-frequency horizontal tube has no overvoltage risk during the wave sealing recovery, and then release the wave sealing state. There are many specific structures of the latch module 400 that can realize the above functions. For the sake of convenience, two specific examples will be used to illustrate in detail below.

[0099] Example 1: Figure 21 As shown, the latch module 400 includes a latch unit 401 and a delay unit 402. For a single-phase bridge arm, there are two latch units 401 and two delay units 402, respectively, to form two latch delay circuits connected to the corresponding riser drive circuit 310. The output of the horizontal pipe encapsulation unit 220 serves as the input of the delay unit 402, and the output of the delay unit 402 and the output of the encapsulation signal generation module 100 serve as the input of the latch unit 401. The latch unit 401 then sends the delayed encapsulation recovery signal to the riser encapsulation unit 210.

[0100] It is understood that there are various specific structural types for the latch unit 401 and the delay unit 402. In this example, an AND gate unit is preferably used for the latch unit 401, and an RC circuit structure is preferably used for the delay unit 402. For ease of understanding, the specific working process of Example 1 will be described in detail below using the a-phase bridge arm as an example.

[0101] Specifically, such as Figure 21 As shown, the driver chip input signal CTL of the right tube Qa4 Qa4 The delay unit 402 corresponding to the upper tube Qa1 is connected to one input end of the latch unit 401 corresponding to the upper tube Qa1. The other input end of the latch unit 401 corresponding to the upper tube Qa1 is connected to the output of the envelope signal generating module 100. The driver chip input signal CTL of the left tube Qa3Qa3 The delay unit 402 corresponding to the lower tube Qa2 is connected to one input end of the latch unit 401 corresponding to the lower tube Qa2. The other input end of the latch unit 401 corresponding to the lower tube Qa2 is connected to the output of the envelope signal generating module 100.

[0102] When the system recovers the wave blocking, the wave blocking signal generating module 100 outputs the signal LOCK as high level, and the horizontal pipe wave blocking unit 220 is immediately controlled by the main control. The two outputs of the latch module 400 are controlled by the driver chip input signal CTL of the left pipe Qa3. Qa3 And the right tube Qa4 driver chip input signal CTL Qa4 control.

[0103] When the a-phase bridge arm is in the positive half cycle of the current, the right tube Qa4 is normally closed, and the signal CTL output by the horizontal tube wave blocking unit 220 corresponding to the right tube Qa4 is restored at the first time. Qa4 The control signal PWM output by the master Qa4 At this time, the signal CTL output by the horizontal pipe wave-sealing unit 220 corresponding to the right pipe Qa4 is Qa4 The capacitor C is charged by the current limiting resistor R in the delay unit 402 corresponding to the upper tube Qa1. When the voltage of the capacitor C rises to the input threshold voltage of the latch unit 401 corresponding to the upper tube Qa1, the latch unit 401 corresponding to the upper tube Qa1 outputs a high level. At this time, the signal CTL output by the riser wave blocking unit 210 corresponding to the upper tube Qa1 is Qa1 The control signal PWM output by the master Qa1 Since the left tube Qa3 is a high-frequency switch and the lower tube Qa2 is normally closed, the output of the latch unit 401 corresponding to the lower tube Qa2 does not affect the output of the vertical tube wave-enclosing unit 210 corresponding to the lower tube Qa2.

[0104] When the a-phase bridge arm is in the negative half cycle of the current, the left tube Qa3 is normally closed, and the signal CTL output by the horizontal tube wave blocking unit 220 corresponding to the left tube Qa3 is restored at the first time. Qa3 The control signal PWM output by the master Qa3 At this time, the signal CTL output by the horizontal pipe wave blocking unit 220 corresponding to the left pipe Qa3 is Qa3 The capacitor C is charged by the current limiting resistor R in the delay unit 402 corresponding to the lower tube Qa2. When the voltage of the capacitor C rises to the input threshold voltage of the latch unit 401 corresponding to the lower tube Qa2, the latch unit 401 corresponding to the lower tube Qa2 outputs a high level. At this time, the signal CTL output by the vertical tube wave blocking unit 210 corresponding to the lower tube Qa2 is Qa2 The control signal PWM output by the master Qa2Since the right tube Qa4 is a high-frequency switch and the upper tube Qa1 is normally closed, the output of the latch unit 401 corresponding to the upper tube Qa1 does not affect the output of the vertical tube wave-enclosing unit 210 corresponding to the upper tube Qa1.

[0105] Example 2: For example Figure 22 As shown, the latch module 400 includes a comparison unit 403 and a latch unit 401. For a single-phase bridge arm, the number of the latch unit 401 and the comparison unit 403 are both two, so as to form two latch delay circuits connected to the corresponding vertical tube driving circuit 310. ref As input of the comparison unit 403 , the output of the comparison unit 403 and the output of the envelope signal generating module 100 are used as inputs of the latch unit 401 , and then the latch unit 401 sends the delayed envelope recovery signal to the riser envelope unit 210 .

[0106] It is understood that the specific structures and operating principles of the latch unit 401 and the comparison unit 403 are well known to those skilled in the art and are therefore not elaborated on in detail here. In this example, an AND gate unit is preferably used for the latch unit 401, and a comparator is preferably used for the comparison unit 403. For ease of understanding, the specific operating process of Example 2 will be described in detail below using the a-phase bridge arm as an example.

[0107] Specifically, from the above analysis process, it can be seen that the upper tube Qa1 and the lower tube Qa2 have overvoltage risks in the positive half cycle and negative half cycle of the current respectively. Therefore, the input terminal reference voltage V ref1 is the reference voltage of the positive half cycle of the current, and the reference voltage V ref2 It is the reference voltage of the negative half cycle of current.

[0108] In the positive half cycle of the current, Figure 20 and Figure 22 As shown, the output of the comparison unit 403 corresponding to the upper tube Qa1 is connected to one input terminal of the corresponding latch unit 401, and the other input terminal of the latch unit 401 is connected to the output terminal of the wave-encapsulation signal generating module 100. The output of the latch unit 401 is connected to one input terminal of the vertical tube wave-encapsulation unit 210 corresponding to the upper tube Qa1. The other input terminal of the vertical tube wave-encapsulation unit 210 corresponding to the upper tube Qa1 is connected to the control signal PWM output by the main control. Qa1 .

[0109] During the negative half cycle of the current, the output of the comparison unit 403 corresponding to the lower tube Qa2 is connected to one input terminal of the corresponding latch unit 401, and the other input terminal of the latch unit 401 is connected to the output terminal of the wave-encapsulation signal generating module 100. The output of the latch unit 401 is connected to one input terminal of the vertical tube wave-encapsulation unit 210 corresponding to the lower tube Qa2. The other input terminal of the vertical tube wave-encapsulation unit 210 corresponding to the lower tube Qa2 is connected to the control signal PWM output by the main control. Qa2 .

[0110] When the wave is restored during the positive half cycle of the current, the above analysis shows that if the upper tube Qa1 is turned on before the right tube Qa4, the left tube Qa3 may be exposed to overvoltage risk. At this time, the e-pole potential of the left tube Qa3 is the potential of the busbar midpoint BUSN, that is, 0 potential; the c-pole potential is the cross tube midpoint potential V1. Therefore, during the positive half cycle of the current, the positive input terminal reference voltage V ref1 Need to meet: V ref1 ≤[(V BUS / 2)+ΔV] / N.

[0111] When the wave is restored in the negative half cycle of the current, it can be seen from the above analysis process that if the lower tube Qa2 is turned on before the left tube Qa3, the right tube Qa4 may be exposed to overvoltage risk. At this time, the e-pole potential of the right tube Qa4 is the potential of the negative half bus BUS-, that is, -V BUS / 2 potential; the C-pole potential is the midpoint potential V1 of the horizontal tube. Therefore, in the negative half cycle of the current, the positive input reference voltage V ref2 Need to meet: V ref2 ≤ΔV / N.

[0112] Among them, V BUS represents the bus voltage, ΔV represents the voltage margin, and N represents the sampling voltage divider ratio of the cross-pipe midpoint voltage V1. The voltage margin ΔV and the sampling voltage divider ratio N of the cross-pipe midpoint voltage V1 should be reasonably set according to the actual operating conditions.

[0113] It is understandable that the above-mentioned embodiment 1 and embodiment 2 can be used separately or in combination, and the specific selection can be made according to the actual needs of those skilled in the art.

[0114] Example 3:

[0115] like Figure 23 As shown, a T-type three-level circuit fault wave sealing recovery processing method includes the following steps: only the vertical pipe is subjected to hardware wave sealing processing, and the horizontal pipe is always in the conductive state; then, when performing wave sealing recovery, the vertical pipe is conductive after the horizontal pipe based on the hardware wave sealing structure.

[0116] For ease of understanding, the specific working process of this embodiment will be described in detail below by taking the a-phase bridge arm as an example.

[0117] like Figure 23 As shown, only the upper tube Qa1 and the lower tube Qa2 are blocked by hardware. The control signal PWM output by the main control Qa3 Directly connected to the drive input signal CTL of the left tube Qa3 Qa3 ; The control signal PWM output by the master Qa4 Directly connected to the drive input signal CTL of the right tube Qa4 Qa4 .

[0118] When the system is blocking the wave, the blocking signal generating module 100 outputs the signal LOCK as low level, and the vertical tube blocking unit 210 outputs the low level, so that the upper tube Qa1 and the lower tube Qa2 are both blocking the wave. At this time, the horizontal tube is in normal wave discharge, and the inductor current can be freewheeled through the main channel or body diode of the right tube Qa4 and the main channel of the left tube Qa3. The specific flow direction of the inductor current can be referred to Figure 8 Therefore, hardware blocking of only the risers can achieve the same goal as hardware blocking of both the crossbars and risers, that is, disconnecting the DC bus from the output while also avoiding the risk of overcurrent in the high-frequency crossbar when blocking is restored.

[0119] The above describes the basic principles, main features, and advantages of the present application. Those skilled in the art should understand that the present application is not limited to the above-described embodiments. The above-described embodiments and the specification merely illustrate the principles of the present application. Various changes and improvements may be made to the present application without departing from the spirit and scope of the present application. These changes and improvements fall within the scope of the present application for which protection is sought. The scope of protection claimed by the present application is defined by the appended claims and their equivalents.

Claims

1. A method for recovering a faulty T-type three-level circuit, characterized in that: The method comprises the following steps: increasing the driving signal response time and / or the wave envelope recovery signal response time of the vertical tube relative to the horizontal tube, so that when the vertical tube performs wave envelope recovery, the vertical tube is turned on later than the horizontal tube; The wave encapsulation recovery signal is generated by a wave encapsulation system, which includes a wave encapsulation signal generating module, a latch module, a horizontal pipe wave encapsulation unit and a vertical pipe wave encapsulation unit; The wave encapsulation signal generating module is adapted to output a wave encapsulation recovery signal; the input end of the riser wave encapsulation unit is signal-connected to the wave encapsulation signal generating module via the latch module; the output end of the riser wave encapsulation unit is adapted to send a conduction signal to the riser; and the latch module is adapted to delay the wave encapsulation recovery signal sent by the wave encapsulation signal generating module; The input end of the cross-pipe wave-sealing unit is signal-connected to the wave-sealing signal generating module, and the output end of the cross-pipe wave-sealing unit is adapted to send a conduction signal to the cross-pipe; The latch module includes a comparison unit and a latch unit; the midpoint voltage of the horizontal pipe and the preset reference voltage serve as the input of the comparison unit, and the output of the comparison unit and the output of the wave envelope signal generation module serve as the input of the latch unit, and then the latch unit sends the delayed wave envelope recovery signal to the vertical pipe wave envelope unit.

2. The T-type three-level circuit fault encapsulation recovery processing method according to claim 1, characterized in that: The vertical tube responds to the driving signal through the vertical tube driving circuit, and the horizontal tube responds to the driving signal through the horizontal tube driving circuit; By increasing the response time of the vertical tube driving circuit to the driving signal and / or shortening the response time of the horizontal tube driving circuit to the driving signal, the vertical tube is turned on later than the horizontal tube when the vertical tube performs wave envelope recovery.

3. The T-type three-level circuit fault encapsulation recovery processing method according to claim 2, characterized in that: The vertical tube driving circuit and the horizontal tube driving circuit both include a driving chip, an on-resistor and a gate capacitor; the driving chip is connected in series with the on-resistor, and the gate capacitor and the on-resistor are connected in parallel to form an RC control circuit; The response time of the driving signal is controlled by adjusting the resistance of the turn-on resistor and / or the capacitance of the gate capacitor.

4. The T-type three-level circuit fault encapsulation recovery processing method according to claim 1, characterized in that: When the wave is restored to the positive half cycle of the current, the preset reference voltage ; When the wave is restored to the negative half cycle of the current, the preset reference voltage ; Among them, V BUS represents the bus voltage, represents the voltage margin, and N represents the midpoint voltage sampling divider ratio of the cross tube.

5. The T-type three-level circuit fault encapsulation recovery processing method according to claim 1, characterized in that: The latch unit is an AND gate unit.

6. A T-type three-level circuit fault wave recovery processing method, characterized in that: The method comprises the following steps: performing hardware wave sealing processing only on the vertical pipe, and the horizontal pipe is always in a conducting state; and then when wave sealing recovery is performed, the vertical pipe is conducted after the horizontal pipe based on the hardware wave sealing structure.

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