Operational amplifier clamping circuit

Abstract

The invention provides an operational amplifier clamping circuit. The operational amplifier clamping circuit comprises an operational amplifier and a clamping voltage control circuit. The operational amplifier comprises a cascode current mirror and a first differential input transistor. Wherein the first end of the first differential input transistor is connected with a connection node of a first common-gate tube and a first common-source tube in the cascode current mirror; the second end of the first differential input transistor is grounded; the control end of the first differential input transistor and the clamping voltage control circuit both receive a first differential input signal; the clamping voltage control circuit is connected with the control end of the first common-gate tube and is configured to output a first bias voltage to the first common-gate tube and adjust the first bias voltage based on a first differential input signal; wherein the first bias voltage is in positive correlation with the voltage of the first differential input signal. Therefore, the reliability of the operational amplifier clamping circuit is improved, and faults caused by overvoltage or abnormal signals are reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an operational amplifier clamping circuit. Background Art

[0002] The op amp clamp circuit mainly uses the characteristics of the operational amplifier to "clamp" or "limit" the input signal to ensure that the signal remains within the preset range. This circuit structure is widely used in various electronic devices to improve the stability and reliability of the circuit. Summary of the invention

[0003] In view of this, an embodiment of the present disclosure provides an operational amplifier clamping circuit to improve the reliability of the operational amplifier in an extreme working state.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows: An embodiment of the present disclosure provides an operational amplifier clamp circuit, comprising: an operational amplifier and a clamp voltage control circuit; wherein the operational amplifier comprises: a common-source common-gate current mirror and a first differential input transistor; wherein the first end of the first differential input transistor is connected to the connection node between the first common-gate transistor and the first common-source transistor in the common-source common-gate current mirror; the second end of the first differential input transistor is grounded; the control end of the first differential input transistor and the clamp voltage control circuit both receive a first differential input signal; the clamp voltage control circuit is connected to the control end of the first common-gate transistor, and is configured to output a first bias voltage to the first common-gate transistor, and to adjust the first bias voltage based on the first differential input signal; wherein the first bias voltage is positively correlated with the voltage of the first differential input signal.

[0005] In the above scheme, the clamping voltage control circuit includes: a first transistor; wherein the control end of the first transistor receives the first differential input signal, and the first end of the first transistor is connected to the control end of the first common-gate tube; the first differential input signal is used to control the conduction degree of the first transistor; wherein the voltage of the first differential input signal is positively correlated with the conduction degree of the first transistor.

[0006] In the above scheme, when the difference between the voltage of the first differential input signal and the power supply voltage is less than or equal to a first preset value, the first transistor is turned on; or, when the difference between the voltage of the first differential input signal and the power supply voltage is greater than a second preset value, the first transistor is turned off; wherein the first preset value is less than the second preset value.

[0007] In the above scheme, the clamping voltage control circuit also includes: a second transistor, a first buck element, a second buck element and a first current source; wherein the first end of the second transistor receives the power supply end; the second end and the control end of the second transistor are both connected to the first end of the first buck element; the second end of the first buck element and the first end of the second buck element are both connected to the second end of the first transistor; the second end of the second buck element and the first end of the first transistor are connected to the first end of the first current source; the second end of the first current source is grounded.

[0008] In the above solution, the equivalent sizes of the second transistor, the first common-source transistor and the first common-gate transistor, and the first common-source transistor and the second common-gate transistor are equal.

[0009] In the above scheme, the op amp clamp circuit also includes: a clamp circuit; wherein the clamp circuit is configured to isolate the first differential input transistor when the voltage of the first differential input signal and the power supply voltage are less than a third preset value; wherein the third preset value is greater than the first preset value.

[0010] In the above scheme, the clamping circuit includes: a third transistor; wherein the first end of the third transistor is connected to the first end of the first differential input transistor; the second end of the third transistor is connected to the second end of the second differential input transistor; and the control end of the third transistor receives a second bias voltage.

[0011] In the above scheme, the operational amplifier clamping circuit also includes: a second clamping circuit; wherein the second clamping circuit is connected to the operational amplifier, configured to receive a first differential input signal, and adjust the first differential input signal from a first voltage to a second voltage; the clamping voltage control circuit is connected to the second clamping circuit, and is also configured to adjust the voltage difference between the first voltage and the second voltage.

[0012] In the above scheme, the clamping circuit includes: a third transistor; wherein the first end of the third transistor is connected to the first end of the first differential input transistor; the second end of the third transistor is connected to the second end of the second differential input transistor; and the control end of the third transistor receives a second bias voltage.

[0013] In the above scheme, the operational amplifier also includes: a second differential input transistor; wherein the control end of the second differential input transistor receives a second differential input signal; the first end of the second differential input transistor is grounded; and the second end of the second differential input transistor is connected to the connection node of the second common-gate transistor and the second common-source transistor in the common-source common-gate current mirror.

[0014] In the above scheme, the first ends of the first common-source tube and the second common-source tube are both connected to the power supply end; the second end of the first common-source tube is connected to the first end of the first common-gate tube, and the second end of the second common-source tube is connected to the first end of the second common-gate tube; the control end of the first common-source tube is respectively connected to the control end of the second common-source tube and the second end of the first common-gate tube; the control end of the second common-gate tube is connected to the clamping voltage control circuit to receive the first bias voltage; the second ends of the first common-gate tube and the second common-gate tube are both grounded.

[0015] In the above scheme, the operational amplifier clamp circuit is applied to a current mirror circuit; wherein the current mirror circuit includes: a first current mirror, a second current source and a load circuit; wherein the output end of the operational amplifier is respectively connected to the control ends of the input transistor and the output transistor in the first current mirror; the first differential input end of the operational amplifier is respectively connected to the second end of the input transistor in the first current mirror and the first end of the second current source; the second differential input end of the operational amplifier is respectively connected to the second end of the output transistor in the first current mirror and the first end of the load circuit; the first ends of the input transistor and the output transistor in the first current mirror receive the power supply voltage; the second ends of the load circuit and the second current source are grounded. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the structure of the operational amplifier clamp circuit provided in the embodiment of the present disclosure Figure 1 ; Figure 2 The structure of the operational amplifier provided in the embodiment of the present disclosure is shown in FIG. Figure 1 ; Figure 3 A schematic diagram of the structure of a clamping voltage control circuit provided in an embodiment of the present disclosure; Figure 4 A schematic diagram of the structure of a clamping circuit provided in an embodiment of the present disclosure; Figure 5 The structure of the operational amplifier provided in the embodiment of the present disclosure is shown in FIG. Figure 2 ; Figure 6 A schematic diagram of the structure of the operational amplifier clamp circuit provided in the embodiment of the present disclosure Figure 2 ; Figure 7 A schematic diagram of the structure of the current mirror circuit provided in the embodiment of the present disclosure Figure 1 ; Figure 8 A schematic diagram of the structure of the current mirror circuit provided in the embodiment of the present disclosure Figure 2 . DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0018] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0019] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0021] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0022] Figure 1 is a schematic diagram of an optional operational amplifier clamp circuit 100 provided in an embodiment of the present disclosure, with reference to Figure 1 The operational amplifier clamp circuit 100 includes an operational amplifier 10. The operational amplifier 10 may be any one of a two-stage operational amplifier, a folded cascode operational amplifier, a fully differential operational amplifier, and the like.

[0023] It should be noted that the reference Figure 1, the operational amplifier 10 receives a first differential input signal and a second differential input signal. The operational amplifier 10 is used to amplify the voltage difference between the first differential input signal and the second differential input signal. Under the influence of power supply fluctuations or external interference, the first differential input signal may have an excessively high voltage, for example, the first differential input signal is close to the power supply voltage VDD. However, the operational amplifier 10 has certain limitations on the input range of voltage. The voltage of the first differential input signal exceeds the input voltage range allowed by the operational amplifier 10, which affects the normal operation of the operational amplifier 10 and may cause output distortion and other abnormalities.

[0024] Figure 2 is a schematic diagram of the structure of an optional operational amplifier 10 provided in an embodiment of the present disclosure, Figure 2 The operational amplifier 10 only illustrates the cascode current mirror 11 and transistors M1 and M2 of the input stage of the operational amplifier 10. The remaining structure of the operational amplifier 10 can be understood by referring to any one of the corresponding two-stage operational amplifiers, folded cascode operational amplifiers, and fully differential operational amplifiers. Figure 2 The example shows that the first differential input transistor M1 and the second differential input transistor M2 are both NMOS transistors, the first common source transistor M4, the second common source transistor M3, the first common gate transistor M6 and the first common source transistor M5 are all PMOS transistors, and M1~M6 can also be other types of transistors such as bipolar transistors, which is not limited here.

[0025] In the embodiments of the present disclosure, reference Figure 2 The operational amplifier 10 includes a first differential input transistor M1, a second differential input transistor M2 and a common-source current mirror 11. The control end of the first differential input transistor M1 receives the first differential input signal Vn. The first end of the first differential input transistor M1 is connected to a connection node A of the first common-gate transistor M6 and the first common-source transistor M4 in the common-source current mirror 11. That is, the voltage of the connection node A of the first common-gate transistor M6 and the first common-source transistor M4 is the same as the voltage of the first end of the first differential input transistor M1.

[0026] In the embodiments of the present disclosure, reference Figure 1 The operational amplifier clamping circuit 100 further includes a clamping voltage control circuit 30. The clamping voltage control circuit 30 is connected to the control terminal of the first common-gate transistor M6 and is configured to output a first bias voltage Vb1 to the first common-gate transistor M6. In this way, the first bias voltage Vb1 output by the clamping voltage control circuit 30 can control the gate voltage of the first common-gate transistor M6. Since the common-gate transistor works in the saturation region, the present disclosure can adjust the voltage (V of the connection node A) of the first common-gate transistor M6 and the first common-source transistor M4 by adjusting the gate voltage of the first common-gate transistor M6. A =Vb1+V GS), and then, adjust the drain-source voltage V of the first differential input transistor M1 DS .

[0027] It should also be noted that the reference Figure 3 , when the voltage of the first differential input signal is within the normal operating range of the operational amplifier 10, if the clamping voltage control circuit 30 is continued to control the drain-source voltage V DS , the drain-source voltage of the first common source tube / the second common source tube V DS It may be too small, so that the first common source tube M4 or the second common source tube M3 leaves the saturation region, resulting in a decrease in gain and poor anti-mismatching.

[0028] In the embodiments of the present disclosure, reference Figure 1 The clamp voltage control circuit 30 is further configured to adjust the first bias voltage Vb1 based on the first differential input signal. For example, the clamp voltage control circuit 30 may include a transistor. The first differential input signal may adjust the gate voltage of the transistor in the clamp voltage control circuit 30 to change the conduction degree of the transistor, thereby adjusting the first bias voltage Vb1 output by the clamp voltage control circuit 30. In this way, when the first differential input signal is close to the power supply voltage VDD, the clamp voltage control circuit 30 may increase the first bias voltage Vb1 to increase the drain-source voltage V of the first differential input transistor M1. DS , thereby preventing the first differential input transistor M1 of the operational amplifier from entering the linear region and causing a decrease in gain. When the voltage of the first differential input signal is within the allowable range of the first differential input transistor M1, the first bias voltage Vb1 output by the clamp voltage control circuit 30 will not change with the voltage of the first differential input signal, thereby keeping the voltage at point A constant, that is, the V of the first common source transistor M4 is DS Maintaining a constant appropriate value makes the op amp bias point better.

[0029] In some embodiments of the present disclosure, reference Figure 2 , the control end of the second differential input transistor M2 receives the second differential input signal Vp. The first end of the second differential input transistor M2 is connected to the connection node B of the second common-gate transistor M5 and the second common-source transistor M3 in the common-source current mirror 11. In other words, the voltage of the connection node B of the second common-gate transistor M5 and the second common-source transistor M3 is the same as the voltage of the first end of the second differential input transistor M2. In this way, the first bias voltage Vb1 output by the clamping voltage control circuit 30 can control the gate voltage of the second common-gate transistor M5 to adjust the voltage of the connection node B of the second common-gate transistor M5 and the second common-source transistor M3, thereby adjusting the drain-source voltage V of the second differential input transistor M2. DS , to prevent the second differential input transistor M2 of the operational amplifier from entering the linear region and causing a decrease in gain.

[0030] Figure 3 is a schematic structural diagram of an optional clamping voltage control circuit 30 provided in an embodiment of the present disclosure.

[0031] In some embodiments of the present disclosure, reference Figure 3 , the clamping voltage control circuit 30 includes a first transistor M7. The second end of the first transistor M7 is connected to the control end of the first common-gate transistor M6. The control end of the first transistor M7 receives a first differential input signal. The first differential input signal is used to control the conduction degree of the first transistor M7. For example, when the first differential input signal is close to the power supply voltage VDD, the first transistor M7 is turned on. For another example, when the second differential input signal is within the allowable range of the first differential input transistor M1, the first transistor M7 is turned off.

[0032] That is, the first bias voltage Vb1 in the clamp voltage control circuit 30 controls the drain voltage of the first differential input transistor M1. In this way, when the voltage of the first differential input signal is close to the power supply voltage VDD, the first bias voltage Vb1 can turn on the first transistor M7, so that the drain voltage of the first differential input transistor M1 can establish a sufficient V DS , preventing the voltage of the first differential input signal from exceeding the allowable range of the operational amplifier 10, thereby reducing faults caused by overvoltage or abnormal signals.

[0033] In addition, when the voltage of the first differential input signal is within the range allowed by the first differential input transistor M1, the first transistor M7 is in the off state. In this way, the embodiment of the present disclosure can prevent the first bias voltage Vb1 from affecting the drain voltage of the first common source transistor M3, and prevent the first common source transistor from leaving the saturation region.

[0034] It should be noted that the voltage of the first differential input signal is positively correlated with the conduction degree of the first transistor M7. That is, when the first differential input signal is getting closer to the power supply voltage VDD, the conduction degree of the first transistor M7 increases, and the first bias voltage Vb1 increases.

[0035] In some embodiments of the present disclosure, reference Figure 3 , when the difference between the voltage of the first differential input signal and the power supply voltage is less than or equal to the first preset value, the first transistor M7 is turned on. For example, the voltage of the power supply voltage VDD can be 3~5V, and the first preset value can be 100~200mV. When the difference between the voltage of the first differential input signal and the power supply voltage VDD is less than or equal to the first preset value, that is, the voltage of the first differential input signal is close to the power supply voltage VDD, at this time, the clamping voltage control circuit 30 can turn on the first transistor M7. In this way, the present disclosure can increase the drain-source voltage VDS , thereby preventing the first differential input transistor M1 of the operational amplifier from entering the linear region and causing a significant gain drop.

[0036] In the embodiments of the present disclosure, reference Figure 3 , the first transistor M7 is turned on when the voltage difference between the voltage of the first differential input signal and the power supply voltage VDD is less than the first preset value, or is turned off when it is greater than or equal to the second preset value. For example, the voltage of the power supply voltage VDD can be 3-5V, the first preset value can be 100-200mV, and the second preset value can be 300mV. In this way, when the first transistor M7 is turned off, the voltage of the first differential input signal will not affect the value of the first bias voltage Vb1, thereby avoiding the first bias voltage Vb1 from affecting the drain voltage of the first differential input transistor M1.

[0037] In some embodiments of the present disclosure, reference Figure 3 The clamping voltage control circuit 30 further includes a second transistor M8, a first voltage drop element 31, a second voltage drop element 32 and a first current source 33. For example, the first voltage drop element 31 may include a first resistor R1, and the second voltage drop element 32 may include a second resistor R2. A first end of the second transistor M8 receives a power supply voltage VDD. A second end of the second voltage drop element 32 and a first end of the first transistor M7 are connected to a first end of the first current source 33. A second end of the first current source 33 is grounded.

[0038] In the embodiments of the present disclosure, reference Figure 2 , the first current source 33 is used to provide a bias current I bias The second end and the control end of the second transistor M8 are both connected to the first end of the first voltage-reducing element 31. The second end of the first voltage-reducing element 31 and the first end of the second voltage-reducing element 32 are both connected to the second end of the first transistor M7. When the voltage of the first differential input signal is close to the power supply voltage VDD, the bias voltage provided by the first differential input signal can turn on the first transistor M7 and short-circuit the second voltage-reducing element 32. Thus, the first transistor M7 can adjust the first bias voltage Vb1 according to the voltage of the first differential input signal. Further, adjusting the drain voltage of the first differential input transistor M1 can establish a sufficient V DS , preventing the voltage of the first differential input signal from exceeding the allowable range of the operational amplifier 10, thereby reducing faults caused by overvoltage or abnormal signals.

[0039] In addition, when the voltage of the first differential input signal is far from the power supply voltage VDD, the first transistor M8 is completely turned off. In this way, when the first transistor M7 is turned off, no current flows through the first transistor M7, thereby preventing the voltage of the first differential input signal from affecting the first bias voltage Vb1. It should be noted that Figure 3 The first voltage drop element 31 and the second voltage drop element 32 are both resistors. The first voltage drop element 31 and the second voltage drop element 32 may also be transistors, which is not limited here. In some embodiments, the clamping voltage control circuit 30 may only include the second voltage drop element 32.

[0040] In some embodiments of the present disclosure, reference Figure 3 , the equivalent sizes of the second transistor M8, the first common-gate transistor M4 and the second common-gate transistor M3 are equal. In this way, if the currents flowing through the second transistor M8, the first common-gate transistor M4 and the second common-gate transistor M3 are equal, then the gate-source voltage V GS equal.

[0041] Figure 4 It is a schematic diagram of the structure of an optional clamping circuit provided in an embodiment of the present disclosure.

[0042] In some embodiments of the present disclosure, reference Figure 4 The operational amplifier clamp circuit 100 further includes a clamp circuit 20. The clamp circuit 20 is configured to isolate the first differential input transistor M1 when the difference between the voltage of the first differential input signal and the power supply voltage VDD is less than a third preset value, wherein the third preset value is greater than the second threshold value.

[0043] It should be noted that the reference Figure 4 , when the difference between the voltage of the first differential input signal and the power supply voltage VDD is greater than the third preset value, the voltage of the first differential input signal may cause damage to the first differential input transistor. For example, the voltage of the power supply voltage VDD may be 3-5V, the third preset value may be 2.5V, and the voltage of the first differential input signal may be 500mV. In this way, the voltage of the first differential input signal is close to the ground voltage, and the first differential input transistor M1 may be damaged due to the drain-source voltage V DS If it is too large, it may deviate from normal working condition or even be damaged.

[0044] In the embodiments of the present disclosure, reference Figure 4, when the voltage of the first differential input signal is too low, the embodiment of the present disclosure can isolate the first differential input transistor M1 by the clamping circuit 20, that is, the clamping circuit 20 short-circuits the first differential input transistor M1. For example, multiple diode strings in opposite directions are connected in parallel between the source and the drain of the first differential input transistor M1, and then the voltage clamping is achieved by the low impedance characteristics of the diode when it is turned on. For another example, the clamping circuit 20 may include a transistor, and when the first differential input signal is too low, the transistor replaces the first differential input transistor M1 and becomes the differential input stage of the operational amplifier 10. In this way, when the voltage of the first differential input signal is too low, the embodiment of the present disclosure can isolate the first differential input transistor M1 by using the clamping circuit 20. Thereby, it is possible to avoid the voltage of the first differential input signal being too low, so that the differential input transistor VDS is too large and deviates from the normal working range.

[0045] In some embodiments of the present disclosure, reference Figure 4 The clamp circuit 20 includes a third transistor M20. A first end of the third transistor M20 is connected to a first end of the first differential input transistor M1. A second end of the third transistor M20 is connected to a second end of the first differential input transistor M1. A control end of the third transistor M20 receives a second bias voltage Vb2.

[0046] In the embodiments of the present disclosure, reference Figure 4 In the case where the voltage of the first differential input signal is too low (for example, the voltage of the first differential input signal is close to the ground voltage), the third transistor M20 is in a conducting state after receiving the second bias voltage Vb2, and then the clamping circuit 20 can short-circuit the first differential input transistor M1. Thus, it is possible to prevent the differential input transistor VDS from being too large and deviating from the normal working range or even being damaged. It should also be noted that the control end of the first differential input transistor M2 can receive the second bias voltage Vb2, thereby preventing the drain-source voltage of the second differential input transistor M2 from being too large.

[0047] Figure 5 is a schematic structural diagram of an optional folded cascode operational amplifier provided in an embodiment of the present disclosure, Figure 6 Specific examples are given Figure 5 FIG. 1 is a diagram showing a connection relationship between the folded cascode operational amplifier, the clamp circuit 20 and the clamp voltage control circuit 30. FIG.

[0048] It should be noted that Figure 5 The functions of the transistors M13, M14, M9, M10, M11 and M12 can be understood with reference to the first current source, which is used to provide tail current. The bias voltages Vb3 and Vb4 drive the corresponding transistors respectively.

[0049] Below Figure 5 and Figure 6 Taking the illustrated folded cascode operational amplifier as an example, the principles of the operational amplifier 10, the clamping circuit 20 and the clamping voltage control circuit 30 are explained: In the present disclosure, Figure 5 and Figure 6 In an ideal case, the two input terminals Vp and Vn of the operational amplifier have the same voltage to produce zero output. However, due to the mismatch in the actual circuit, such as differences in transistor size, threshold voltage, etc., there will be an input offset voltage ΔVoffset. In the case where the voltage of the first differential input signal is close to the power supply voltage VDD, the first differential input transistor M1 and the second differential input transistor M2 may be in the linear region, and their transconductance (gm) will decrease significantly, which will further increase the impact of the input offset voltage. As a result, the operational amplifier 10 will have problems such as decreased open-loop gain and poor stability.

[0050] Furthermore, the clamp voltage control circuit 30 can control the source-drain voltage V of the first differential input transistor M1 when the voltage of the first differential input signal is close to the power supply voltage VDD. DS Adjustments are made to prevent the first differential input transistor M1 and the second differential input transistor M2 from entering the linear region, thereby improving the reliability of the operational amplifier clamping circuit and reducing faults caused by overvoltage or abnormal signals.

[0051] In addition, when the voltage of the first differential input signal is far from the power supply voltage VDD, the clamping voltage control circuit 30 can turn off the first transistor M7 to prevent the first common-gate transistor M6 from affecting the drain voltage of the first differential input transistor M1, thereby ensuring signal integrity and avoiding signal clipping or distortion caused by improper clamping.

[0052] Figure 7 is a schematic diagram of a structure of an operational amplifier clamp circuit 100 provided in an embodiment of the present disclosure applied to a current mirror circuit 200. It should be noted that: Figure 7 The example shows that the operational amplifier clamp circuit 100 is applied to the current mirror circuit 200. The operational amplifier clamp circuit 100 can also be applied to other types of circuits, such as interface circuits, etc., which is not limited here.

[0053] Figure 8 is a schematic diagram of a structure of an optional current mirror circuit 200 provided in an embodiment of the present disclosure. Figure 8 The current mirror circuit 200 is exemplified to explain the principle of the operation of the operational amplifier clamp circuit 100 on the current mirror circuit 200: In the present disclosure, Figure 7 and Figure 8The current mirror circuit 200 includes a first current mirror 201, a second current source 202, and a load circuit 203. The output terminal Vo of the operational amplifier 10 is respectively connected to the control terminals of the input transistor M31 and the output transistor M32 in the first current mirror 201. The first differential input terminal of the operational amplifier 10 is respectively connected to the second terminal of the input transistor M31 in the first current mirror 201 and the first terminal of the second current source 202. The second differential input terminal of the operational amplifier 10 is respectively connected to the second terminal of the output transistor M32 in the first current mirror 201 and the first terminal of the load circuit 203. The first terminals of the input transistor M31 and the output transistor M32 in the first current mirror 201 receive the power supply voltage VDD. The second terminals of the second current source 202 and the load circuit 203 are grounded.

[0054] In the present disclosure, Figure 7 and Figure 8 , the inverting input terminal of the op amp clamp circuit 100 can receive the first differential input signal Vn. The non-inverting input terminal of the op amp clamp circuit 100 can receive the second differential input signal Vp. When the voltage of the first differential input signal Vn is close to the power supply voltage VDD, the loop gain decreases significantly, and the differential input transistor in the op amp clamp circuit 100 may be close to its linear region, resulting in a decrease in transconductance and an increase in offset voltage. As a result, the mirror current Iout output by the first current mirror 201 in the current mirror circuit 200 will be amplified due to ΔVoffset in the op amp clamp circuit 100. The closer the voltage of the first differential input signal is to the power supply voltage VDD, the greater the amplification factor of the mirror current Iout, and as a result, the excessive output current will damage the subsequent circuit. In other words, random mismatch (such as mismatch of transistor size) will cause the mirror ratio of the current mirror circuit 200 to deviate from the ideal value. When the loop gain of the current mirror circuit 200 drops to a certain level, the current mirror circuit 200 may not be able to effectively adjust to offset the random mismatch, causing the loop of the current mirror circuit 200 to enter a locked state.

[0055] Furthermore, when the voltage of the first differential input signal is close to the power supply voltage VDD, the clamp circuit in the operational amplifier clamp circuit 100 can clamp the VDD of the transistor in the operational amplifier clamp circuit 100 that receives the first differential input signal. DS Adjustments are made to prevent the transistor from entering the linear region. In this way, the disclosed embodiment can prevent the current mirror circuit 200 from entering an extreme operating condition (such as too low loop gain, too large offset voltage), thereby improving the reliability of the current mirror circuit 200 under extreme operating conditions.

[0056] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0057] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. An operational amplifier clamp circuit, characterized in that: include: Operational amplifier and clamp voltage control circuit; wherein, The operational amplifier comprises: a common-source common-gate current mirror and a first differential input transistor; wherein the first end of the first differential input transistor is connected to the connection node of the first common-gate transistor and the first common-source transistor in the common-source common-gate current mirror; and the second end of the first differential input transistor is grounded; The control terminal of the first differential input transistor and the clamping voltage control circuit both receive a first differential input signal; The clamping voltage control circuit is connected to the control end of the first common-gate tube, and is configured to output a first bias voltage to the first common-gate tube, and to adjust the first bias voltage based on the first differential input signal; wherein the first bias voltage is positively correlated with the voltage of the first differential input signal.

2. The operational amplifier clamp circuit according to claim 1, characterized in that: The clamping voltage control circuit comprises: a first transistor; wherein, The control end of the first transistor receives the first differential input signal, and the first end of the first transistor is connected to the control end of the first common-gate transistor; The first differential input signal is used to control the conduction degree of the first transistor; wherein the voltage of the first differential input signal is positively correlated with the conduction degree of the first transistor.

3. The operational amplifier clamp circuit according to claim 2, characterized in that: When the difference between the voltage of the first differential input signal and the power supply voltage is less than or equal to a first preset value, the first transistor is turned on; or, when the difference between the voltage of the first differential input signal and the power supply voltage is greater than a second preset value, the first transistor is turned off; wherein the first preset value is less than the second preset value.

4. The operational amplifier clamp circuit according to claim 3, characterized in that: The clamping voltage control circuit further includes: a second transistor, a first voltage-dropping element, a second voltage-dropping element and a first current source; wherein, The first end of the second transistor receives a power supply voltage; the second end and the control end of the second transistor are both connected to the first end of the first step-down element; the second end of the first step-down element and the first end of the second step-down element are both connected to the second end of the first transistor; the second end of the second step-down element and the first end of the first transistor are connected to the first end of the first current source; the second end of the first current source is grounded.

5. The operational amplifier clamp circuit according to claim 4, characterized in that: The operational amplifier clamping circuit further comprises: a clamping circuit; wherein, The clamp circuit is configured to isolate the first differential input transistor when the difference between the voltage of the first differential input signal and the power supply voltage is less than a third preset value; wherein the third preset value is greater than the first preset value.

6. The operational amplifier clamp circuit according to claim 5, characterized in that: The clamping circuit comprises: a third transistor; wherein, The first end of the third transistor is connected to the first end of the first differential input transistor; the second end of the third transistor is connected to the second end of the first differential input transistor; and the control end of the third transistor receives a second bias voltage.

7. The operational amplifier clamp circuit according to claim 4, characterized in that: The operational amplifier further includes: a second differential input transistor; wherein, The control terminal of the second differential input transistor receives a second differential input signal; The first end of the second differential input transistor is grounded; the second end of the second differential input transistor is connected to the connection node between the second common-gate transistor and the second common-source transistor in the common-source common-gate current mirror.

8. The operational amplifier clamp circuit according to claim 7, characterized in that: The first ends of the first common source transistor and the second common source transistor both receive a power supply voltage; The second end of the first common-source transistor is connected to the first end of the first common-gate transistor, and the second end of the second common-source transistor is connected to the first end of the second common-gate transistor; the control end of the first common-source transistor is respectively connected to the control end of the second common-source transistor and the second end of the first common-gate transistor; the control end of the second common-gate transistor is connected to the clamping voltage control circuit to receive the first bias voltage; The second ends of the first common-gate transistor and the second common-gate transistor are both grounded.

9. The operational amplifier clamp circuit according to claim 8, characterized in that: The equivalent sizes of the second transistor, the first common-gate transistor, and the second common-gate transistor are equal.

10. The operational amplifier clamp circuit according to claim 1, characterized in that: The operational amplifier clamp circuit is applied to a current mirror circuit; wherein, The current mirror circuit comprises: a first current mirror, a second current source and a load circuit; wherein, The output end of the operational amplifier is connected to the control end of the input transistor and the output transistor in the first current mirror respectively; The first differential input terminal of the operational amplifier is connected to the second terminal of the input transistor in the first current mirror and the first terminal of the second current source respectively; The second differential input terminal of the operational amplifier is connected to the second terminal of the output transistor in the first current mirror and the first terminal of the load circuit respectively; The first ends of the input transistor and the output transistor in the first current mirror are connected to the power supply end; the second ends of the load circuit and the second current source are grounded.

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