High-precision pulse width modulator supporting adaptive calibration and application method thereof

Abstract

The invention discloses a high-precision pulse width modulator supporting self-adaptive calibration and an application method thereof.The high-precision pulse width modulator comprises a delay and calibration unit used for generating a high-precision PWM waveform, the delay and calibration unit comprises a delay line, a first selector, a second selector and a calibration module, the delay line is composed of N-1 levels of delay units, and the first selector is connected with the second selector; the first selector and the second selector are one-out-of-N selectors, and are used for gating one path from N paths of input according to a delay unit selection signal to obtain high-precision PWM waveform output; and the calibration module is used for calibrating the high-precision PWM waveform output by the second selector to generate an actual calibration value representing the delay unit series required for delaying a clock period at present. According to the method, a user can directly observe the precision of the delay unit, calculation is carried out without an additional mode, the precision calculation process of the delay unit can be removed, errors caused by additional calculation are avoided, and the use efficiency is improved.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit design, and in particular relates to a high-precision pulse width modulator supporting adaptive calibration and an application method thereof. Background Art

[0002] With the rapid development of semiconductor technology, digital control technology has become more and more mature and widely used in power management, automatic control and other fields, and pulse width modulation technology in digital control technology is an important component. In integrated circuit design, eHRPWM (enhanced High-Resolution Pulse Width Modulator) is a key component in power electronic systems. It can realize complex waveform output, including high-precision PWM waveforms (pulse width modulation waveforms) with adjustable frequency and duty cycle. It is widely used in measurement, communication, power control and conversion and other fields. With the increase in application requirements, the requirements for PWM waveform output accuracy are also increasing. When using delay units to achieve high-precision PWM waveform output, since users cannot directly observe the accuracy of the delay unit, they need to calculate it through additional methods, which can easily lead to errors in the calculation of the delay unit accuracy, and the process is cumbersome, affecting the efficiency of use.

[0003] A delay line composed of delay units is a major method for implementing pulse width modulation. The pulse width modulator implemented by the delay line can achieve more accurate PWM waveform output and obtain a PWM waveform with a higher precision duty cycle output. Combined with calibration technology, the accuracy of the delay unit can be observed in real time, improving the efficiency of use. At present, some research on technologies related to high-precision pulse width modulation based on delay units has also emerged. For example: (1) Patent application document No. WO2022 / 121389A1 discloses a high-resolution pulse width modulation signal generation circuit, which aims to solve the problem that the accuracy of PWM signals in the prior art is limited by the clock frequency. The circuit improves the resolution of the PWM signal without changing the counting clock; through the multiple relationship between the counting clock and the delay chain, the delay module is regarded as a lower-level extension of the PWM counting module, which is convenient for control and improves the accuracy of the PWM signal; using MUX as the minimum delay unit and delay selection logic of the delay chain reduces the inherent delay, which is conducive to reducing the error of the delay chain. However, the disadvantage of this circuit is that the calibration circuit measures the multiple relationship between the counting clock and the delay chain. Its focus is to solve the problem that the accuracy of PWM signals is limited by the clock frequency in the prior art, and it does not consider directly mapping the current delay unit accuracy to the register. When outputting a high-precision PWM waveform, the user cannot directly observe the current delay unit accuracy. (2) The patent application document with publication number CN106612111A discloses a system and method for high-precision delay clock calibration, the purpose of which is to solve the technical problem of delay clock calibration. Its implementation scheme includes a NAND gate, an AND gate, a delay chip, a multiplexer and a processing module, wherein the multiplexer includes a calibration output terminal and a clock output terminal, and the processing module includes a delay control terminal, a selection control terminal and a control switch terminal. However, the disadvantage of this scheme is that it only realizes high-precision delay calibration for clock input. It focuses on solving the technical problem of delay clock calibration and realizes clock delay calibration by introducing a delay chip. The premise of the system is that the clock input is a fixed duty cycle, and the output of other complex waveforms is not considered. (3) The patent application document with publication number CN112187229A discloses a high-resolution pulse width modulation system with multi-phase delays, the purpose of which is to achieve high-precision modulation of pulse width signals. The implementation scheme includes a multi-phase delay locked loop system and a PWM signal post-processor, which can achieve pulse rising edge and falling edge modulation. However, after achieving high-precision pulse width modulation, the scheme does not mention the calibration method. Its focus is on proposing a high-precision pulse width modulation method for pulse signals, without considering the calibration method, and the user cannot directly observe the accuracy of the delay unit.(4) The patent application document with publication number CN102386916A discloses a high-digital pulse width modulation circuit, which aims to solve the problem of high power consumption and large area of ​​digital pulse width modulators implemented by traditional delay units. The implementation scheme includes a ring oscillator, a digital phase-locked loop controller and a pulse output circuit. The rising delay and falling delay of the delay unit are used to segmentally implement the high-bit precision and low-bit precision of pulse width modulation, and the phase difference between the rising delay and the falling delay is corrected by the digital phase-locked loop, so that all falling edge delays are equal to one rising edge delay, thereby greatly reducing the number of delay units required, achieving the purpose of reducing power consumption and chip area. However, the scheme does not mention the calibration method. Its focus is on realizing a pulse width modulator based on a delay unit to reduce power consumption and chip area. The calibration method is not considered, and it is not applied to high-precision pulse width waveform output. Summary of the invention

[0004] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a high-precision pulse width modulator supporting adaptive calibration and an application method thereof are provided. The present invention aims to generate a high-precision PWM waveform based on an ordinary PWM waveform. Through calibration, the user can directly observe the accuracy of the delay unit without the need for additional calculations, thereby eliminating the delay unit accuracy calculation process, avoiding errors caused by additional calculations, and improving usage efficiency.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A high-precision pulse width modulator supporting adaptive calibration comprises a delay and calibration unit for generating a high-precision PWM waveform from an input ordinary PWM waveform, the delay and calibration unit comprising a delay line, a first selector, a second selector and a calibration module, the delay line is composed of N-1 levels of delay units, the input end of each level of delay unit in the delay line and the output end of the last level of delay unit are respectively connected to N input ends of the first selector and N input ends of the second selector, the first selector and the second selector are both N-to-one selectors, both of the first selector and the second selector are used to select one path from N input paths according to a delay unit selection signal to obtain a high-precision PWM waveform output, the input end of the calibration module is connected to the output end of the second selector to calibrate the high-precision PWM waveform output by the second selector in combination with the input ordinary PWM waveform to generate an actual calibration value representing the number of delay unit levels required for the current delay of one clock cycle.

[0006] Optionally, the calibration module includes a first D flip-flop, a first edge detection module, a second D flip-flop, a third D flip-flop, a second edge detection module, a calibration state judgment module, a summing module and a fourth D flip-flop. The high-precision PWM waveform output by the first selector passes through the first D flip-flop and the first edge detection module in sequence to obtain a first edge detection result. The ordinary PWM waveform passes through the second D flip-flop, the third D flip-flop and the second edge detection module in sequence to obtain a second edge detection result. The first edge detection result and the second edge detection result are used as inputs of the calibration state judgment module to compare the two edge detection results through the calibration state judgment module to determine whether the state of the current calibration value is increasing, decreasing or maintaining. The summing module is used to update the current calibration value according to the state of the current calibration value and output it through the fourth D flip-flop until the actual calibration value tends to be stable to obtain an actual calibration value representing the number of delay unit stages required for the current delay of one clock cycle. The output of the fourth D flip-flop is connected to the input end of the summing module to provide the current calibration value.

[0007] Optionally, the summation module is used to update the current calibration value according to the state of the current calibration value, including: if the state of the current calibration value is increasing, the actual calibration value is increased by 1; if the state of the current calibration value is decreasing, the actual calibration value is reduced by 1; if the state of the current calibration value is unchanged, the actual calibration value remains unchanged.

[0008] Optionally, the delay line is composed of 255 levels of delay units, and the summing module adopts a calibration default value as the current calibration value when the fourth D flip-flop has not output a current calibration value, and the calibration default value is 128.

[0009] Optionally, the present invention also includes a PWM register module for providing a delay unit selection signal to achieve selection of high-precision PWM waveform output, processing register read and write requests from the CPU, and register output control logic, the PWM register module includes four registers: a configuration register HRCNFG, used to achieve output mode selection of high-precision PWM waveform, the output mode includes a duty cycle control mode and a phase control mode; a duty cycle extension register CMPAHR, used to provide a delay unit selection signal under the duty cycle control mode; a phase extension register TBPHSHR, used to provide a delay unit selection signal under the phase control mode; a calibration register HRREF, used to indicate the actual calibration value of the number of delay unit levels required to delay one clock cycle when the PWM waveform is output.

[0010] Optionally, the field in the configuration register HRCNFG includes a 2-bit edge mode bit EDGMODE, a 1-bit control mode bit CTLMODE and a 1-bit mapping mode bit HRLOAD, the edge mode bit EDGMODE is used to configure the edge detection mode to be one of high-precision PWM waveform output enable, edge-controlled rising edge, edge-controlled falling edge, edge-controlled rising edge and falling edge, the control mode bit CTLMODE is used to configure the output mode to be a duty cycle control mode or a phase control mode, and the mapping mode bit HRLOAD is used to configure the mapping value loading event of the delay unit selection signal in the duty cycle control mode to be the counter equal to zero or a preset period PRD.

[0011] Optionally, the value range of the duty cycle extension register CMPAHR is 1 to N-1 for implementing 1 to N-1 levels of adjustable delay line in duty cycle control mode, where N-1 is the number of delay units in the delay line.

[0012] Optionally, the value range of the phase expansion register TBPHSHR is 1 to N-1 for realizing 1 to N-1 levels of adjustable delay line in phase control mode, where N-1 is the number of delay units in the delay line.

[0013] Optionally, the input end of the delay and calibration unit is also connected to a common PWM waveform generator for generating a common PWM waveform.

[0014] In addition, the present invention also provides an application method of the aforementioned high-precision pulse width modulator supporting adaptive calibration, comprising the following steps: S1, read the edge mode bit EDGMODE of the configuration register HRCNFG through the PWM register module to see if the high-precision PWM waveform output function is disabled. If the high-precision PWM waveform output function is not disabled, jump to step S2; otherwise, directly output the ordinary PWM waveform, end and exit; S2, determining the output mode of the high-precision PWM waveform according to the control mode bit CTLMODE of the configuration register HRCNFG, if the output mode of the high-precision PWM waveform is the duty cycle control mode, selecting the duty cycle extension register CMPAHR to provide a delay unit selection signal in the duty cycle control mode; if the output mode of the high-precision PWM waveform is the phase control mode, selecting the phase extension register TBPHSHR to provide a delay unit selection signal in the phase control mode; S3, performing delay and calibration processing through the delay and calibration unit, including: delaying the input common PWM waveform through the N-1-stage delay unit in the delay line, and selecting one path from the N-path inputs through the first selector and the second selector in combination with the mapping mode bit HRLOAD and the delay unit selection signal to obtain a high-precision PWM waveform output; calibrating the high-precision PWM waveform output by the second selector in combination with the input common PWM waveform through the calibration module in combination with the edge detection mode configured by the edge mode bit EDGMODE to generate an actual calibration value representing the number of delay unit stages required for the current delay of one clock cycle and writing it into the calibration register HRREF until the actual calibration value is stable; S4, responding to the user's read request through the PWM register module, returning the actual calibration value written into the calibration register HRREF indicating the number of delay unit stages required for the current delay of one clock cycle.

[0015] Compared with the prior art, the present invention mainly has the following advantages: on the basis of realizing high-precision PWM waveform output, the present invention combines a calibration module to realize a high-precision pulse width modulation method that supports adaptive calibration. Through adaptive calibration, while outputting a high-precision PWM waveform, an actual calibration value representing the number of delay unit levels required for the current delay of one clock cycle is instantly generated. The user can instantly observe the number of delay unit levels required for a delay of one clock cycle, eliminate the delay unit accuracy calculation process, avoid errors caused by additional calculations, and improve usage efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the overall structure of a high-precision pulse width modulator in an embodiment of the present invention.

[0017] Figure 2 Schematic diagram of the structure of the delay and calibration unit in an embodiment of the present invention.

[0018] Figure 3 Schematic diagram of the structure of the calibration module in an embodiment of the present invention.

[0019] Figure 4 Schematic diagram of the working process of the high-precision pulse width modulator in an embodiment of the present invention.

[0020] Legend: 1. Delay line; 2. First selector; 3. Second selector; 4. Calibration module; 41. First D flip-flop; 42. First edge detection module; 43. Second D flip-flop; 44. Third D flip-flop; 45. Second edge detection module; 46. Calibration status judgment module; 47. Summation module; 48. Fourth D flip-flop. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0022] like Figure 1 As shown, the high-precision pulse width modulator supporting adaptive calibration in this embodiment includes a delay and calibration unit for generating a high-precision PWM waveform from an input ordinary PWM waveform. The high-precision pulse width modulator supporting adaptive calibration in this embodiment combines the delay line and the calibration technology, and designs a high-precision pulse width modulator supporting adaptive calibration (eHRPWM component) including two parts: an ordinary PWM waveform generator and a delay and calibration unit, as shown in FIG. Figure 1 As shown, the input end of the delay and calibration unit is connected to a common PWM waveform generator for generating a common PWM waveform. The high-precision pulse width modulator supporting adaptive calibration in this embodiment is a key component in the power electronic system. With the characteristics of realizing a higher-precision PWM waveform with adjustable frequency and duty cycle, it is widely used in measurement, communication, power control and conversion and other fields.

[0023] like Figure 2 As shown, the delay and calibration unit of this embodiment includes a delay line 1, a first selector 2, a second selector 3 and a calibration module 4. The delay line 1 is composed of N-1 levels of delay units, so as to realize a higher precision PWM waveform output. The input end of each level of delay unit in the delay line 1 and the output end of the last level of delay unit are respectively connected to the N input ends of the first selector 2 and the N input ends of the second selector 3. The first selector 2 and the second selector 3 are both N-to-one selectors, and the structures of the two are consistent. The first selector 2 and the second selector 3 are both used to select one path from N input paths according to the delay unit selection signal select[7:0] to obtain a high-precision PWM waveform output. The input end of the calibration module 4 is connected to the output end of the second selector 3 to calibrate the high-precision PWM waveform output by the second selector 3 in combination with the input ordinary PWM waveform to generate an actual calibration value REF[7:0] representing the number of delay unit levels required for the current delay of one clock cycle.

[0024] like Figure 3As shown, the calibration module 4 of this embodiment includes a first D flip-flop 41, a first edge detection module 42, a second D flip-flop 43, a third D flip-flop 44, a second edge detection module 45, a calibration state judgment module 46, a summing module 47 and a fourth D flip-flop 48. The high-precision PWM waveform output by the first selector 2 passes through the first D flip-flop 41 and the first edge detection module 42 in sequence to obtain a first edge detection result, and the ordinary PWM waveform passes through the second D flip-flop 43, the third D flip-flop 44 and the second edge detection module 45 in sequence to obtain a second edge detection result. The first edge detection result and the second edge detection result are used as inputs of the calibration state judgment module 46 to compare the two edge detection results through the calibration state judgment module 46 to determine whether the state of the current calibration value is increasing, decreasing or maintaining. The summing module 47 is used to update the current calibration value according to the state of the current calibration value and output it through the fourth D flip-flop 48 until the actual calibration value tends to be stable to obtain an actual calibration value representing the number of delay unit stages required for the current delay of one clock cycle. The output of the fourth D flip-flop 48 is connected to the input end of the summing module 47 to provide the current calibration value. When the ordinary PWM waveform is input, it enters the second D flip-flop 43 and the third D flip-flop 44 in turn, and the edge detection of the current input waveform can be performed. At the same time, the high-precision PWM waveform processed by the delay unit enters the first D flip-flop 41 for edge detection. The edge detection results of the two are compared to determine the state of the current calibration value (incrementing, decrementing and holding). Based on the calibration default value and the state of the current calibration value, the current actual calibration value can be obtained and written into the HRREF register. The HRREF register will be automatically updated at the rising and falling edges of the ordinary PWM input signal. Calibration starts after reset, and the time from reset to calibration completion is less than 256 clock cycles, and calibration is performed on both the rising and falling edges of the input, and the calibration rate is fast. While outputting a high-precision PWM waveform, the user can obtain the number of delay unit levels required for the current delay of one clock cycle by reading the value of the HRREF register.

[0025] In this embodiment, the summing module 47 updates the current calibration value according to the state of the current calibration value, including: if the state of the current calibration value is increasing, then the actual calibration value is added by 1, that is, the actual calibration value = the original actual calibration value + 0x1; if the state of the current calibration value is decreasing, then the actual calibration value is reduced by 1, that is, the actual calibration value = the original actual calibration value - 0x1; if the state of the current calibration value is unchanged, then the actual calibration value is kept unchanged, that is, the actual calibration value = the original actual calibration value. Until the actual calibration value tends to be stable, that is, the actual value of the delay unit stage required for the current delay unit to delay one clock cycle.

[0026] As an optional implementation, in this embodiment, the delay line 1 is composed of 255 delay units (i.e., N=256). To improve the efficiency of the calibration module, the summing module 47 uses the calibration default value as the current calibration value when the fourth D flip-flop 48 has not yet output the current calibration value, and the calibration default value is 128 (0x80). The calibration is started according to the current delay unit accuracy, and approaches the actual value of the delay unit level required to delay one clock cycle. When N=256, the first selector 2 and the second selector 3 are both N-to-one selectors, i.e., 256 / 1 selectors. When a normal PWM waveform is input, the delay line implemented based on the 255-level delay unit processes the input normal PWM waveform according to the delay unit selection in the first 256 / 1 selector to obtain a high-precision PWM output waveform; the second 256 / 1 selector also obtains a high-precision PWM output waveform according to the delay unit selection, and enters the calibration module at the same time.

[0027] As an optional implementation, this embodiment also includes a PWM register module for providing a delay unit selection signal to achieve the selection of high-precision PWM waveform output, processing register read and write requests from the CPU, and register output control logic, and the PWM register module includes four registers: a configuration register HRCNFG, used to achieve the output mode selection of the high-precision PWM waveform, and the output mode includes a duty cycle control mode and a phase control mode; a duty cycle extension register CMPAHR, used to provide a delay unit selection signal under the duty cycle control mode; a phase extension register TBPHSHR, used to provide a delay unit selection signal under the phase control mode; a calibration register HRREF, used to indicate the actual calibration value of the number of delay unit levels required to delay one clock cycle when the PWM waveform is output. According to the configuration register HRCNFG, the output mode selection of high-precision PWM waveform can be realized. The output mode includes duty cycle control mode and phase control mode. In the duty cycle control mode, the duty cycle expansion register CMPAHR is selected to provide a delay unit selection signal; in the phase control mode, the phase expansion register TBPHSHR is selected to provide a delay unit selection signal; in addition to realizing complex waveform output, the high-precision PWM waveform output control of the high-precision pulse width modulator supporting adaptive calibration in this embodiment includes duty cycle expansion (including rising edge control, falling edge control) and phase control (i.e., double-edge control). The calibration module automatically starts after reset, and the time from reset to calibration completion is less than 256 clock cycles. Calibration is performed on both the rising and falling edges of the input signal to ensure the correctness of the calibration value. The user can read the actual calibration value instantly by reading the calibration register HRREF.

[0028] In this embodiment, the field in the configuration register HRCNFG includes a 2-bit edge mode bit EDGMODE, a 1-bit control mode bit CTLMODE and a 1-bit mapping mode bit HRLOAD. The edge mode bit EDGMODE is used to configure the edge detection mode to be one of high-precision PWM waveform output enable, edge-controlled rising edge, edge-controlled falling edge, edge-controlled rising edge and falling edge. The control mode bit CTLMODE is used to configure the output mode to be a duty cycle control mode or a phase control mode. The mapping mode bit HRLOAD is used to configure the mapping value loading event of the delay unit selection signal in the duty cycle control mode to be the counter equal to zero or a preset period PRD. The mapping value loading event is selected according to the mapping mode bit HRLOAD. According to this bit field, the condition for mapping and loading the duty cycle extension register CMPAHR can be selected. If the mapping mode bit HRLOAD is 0x0, it means that the duty cycle extension register CMPAHR is loaded when the counter is 0x0; if the mapping mode bit HRLOAD is 0x1, it means that the duty cycle extension register CMPAHR is loaded when the counter is equal to the period value. In addition, the domain in the configuration register HRCNFG in this embodiment also includes 12 reserved bits. In this embodiment, the information table of the domain in the configuration register HRCNFG is specifically shown in Table 1.

[0029] Table 1: Information table of fields in configuration register HRCNFG

[0030] In Table 1, R in the domain control field indicates read-only, and R / W indicates read-write. The default state of the edge mode bit EDGMODE is 0x0, indicating that the high-precision PWM function is disabled, and the output is a normal PWM waveform; when the bit field is not 0, it indicates that the high-precision PWM function is enabled, and the output is a high-precision PWM waveform.

[0031] In this embodiment, the value range of the duty cycle extension register CMPAHR is 1 to N-1 to realize 1 to N-1 levels of adjustable delay line 1 in the duty cycle control mode, where N-1 is the number of delay units in the delay line 1. In this embodiment, the information table of the fields in the duty cycle extension register CMPAHR is specifically shown in Table 2.

[0032] Table 2: Information table of the fields in the duty cycle extension register CMPAHR

[0033] In this embodiment, the value range of the phase expansion register TBPHSHR is 1 to N-1 for realizing 1 to N-1 levels of adjustable delay line 1 in the phase control mode, where N-1 is the number of delay units in the delay line 1. In this embodiment, the information table of the fields in the phase expansion register TBPHSHR is specifically shown in Table 3.

[0034] Table 3: Information table of fields in the phase extension register TBPHSHR

[0035] The calibration register HRREF is used to indicate the actual calibration value of the number of delay unit stages required to delay one clock cycle when the PWM waveform is output. In this embodiment, the information table of the fields in the calibration register HRREF is specifically shown in Table 4.

[0036] Table 4: Information table of fields in calibration register HRREF

[0037] like Figure 4 As shown, this embodiment also provides an application method of the aforementioned high-precision pulse width modulator supporting adaptive calibration, comprising the following steps: S1, read the edge mode bit EDGMODE of the configuration register HRCNFG through the PWM register module to see if the high-precision PWM waveform output function is disabled (i.e., whether it is equal to 0x0). If the high-precision PWM waveform output function is not disabled, jump to step S2; otherwise, directly output the ordinary PWM waveform, end and exit; S2, determining the output mode of the high-precision PWM waveform according to the control mode bit CTLMODE of the configuration register HRCNFG, if the output mode of the high-precision PWM waveform is the duty cycle control mode, selecting the duty cycle extension register CMPAHR to provide a delay unit selection signal in the duty cycle control mode; if the output mode of the high-precision PWM waveform is the phase control mode, selecting the phase extension register TBPHSHR to provide a delay unit selection signal in the phase control mode; S3, performing delay and calibration processing through the delay and calibration unit, including: delaying the input common PWM waveform through the N-1-stage delay unit in the delay line 1, and selecting one path from the N-path inputs through the first selector 2 and the second selector 3 in combination with the mapping mode bit HRLOAD and the delay unit selection signal to obtain a high-precision PWM waveform output; calibrating the high-precision PWM waveform output by the second selector 3 and the input common PWM waveform through the calibration module 4 in combination with the edge detection mode configured by the edge mode bit EDGMODE to generate an actual calibration value representing the number of delay unit stages required for the current delay of one clock cycle and writing it into the calibration register HRREF until the actual calibration value is stable; S4, responding to the user's read request through the PWM register module, returning the actual calibration value written into the calibration register HRREF indicating the number of delay unit stages required for the current delay of one clock cycle.

[0038] In summary, the high-precision pulse width modulator supporting adaptive calibration in this embodiment realizes high-precision pulse width modulation through a delay line, and combines calibration technology to realize instant calibration of the delay unit. After the user selects the high-precision control mode by configuring the register HRCNFG, the duty cycle extension register CMPAHR / phase extension register TBPHSHR is selected as the delay unit selection. The delay unit is adjustable from 1 to 255 levels. When the ordinary PWM waveform is input, the high-precision PWM waveform output can be obtained. At the same time, the HRREF register can be read to read the number of delay unit levels required for the current delay of one clock cycle. The high-precision mode of the high-precision pulse width modulator supporting adaptive calibration in this embodiment is divided into a duty cycle mode and a phase control mode. The user can configure the delay unit register according to the high-precision mode selection. The configuration is simple, and the delay unit can be adjusted from 0 to 255 levels. The configuration is flexible. While outputting a high-precision PWM waveform, the actual delay unit accuracy can be read to avoid additional calculation errors. The use flexibility is high and the use efficiency is improved. The default value of the actual calibration value of the high-precision pulse width modulator that supports adaptive calibration in this embodiment is 128. The calibration is automatically started after reset. The time from reset to calibration completion is less than 256 PWM cycles, and calibration is performed on both the rising and falling edges of the input. The calibration value is incremented / decremented / held according to the actual calibration situation to instantly update the actual calibration value until the calibration value is stable, which can improve the calibration efficiency. The user can instantly obtain the number of delay unit levels that are currently delayed by one clock cycle.

[0039] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A high-precision pulse width modulator supporting adaptive calibration, characterized in that: The invention comprises a delay and calibration unit for generating a high-precision PWM waveform from an input ordinary PWM waveform, the delay and calibration unit comprising a delay line (1), a first selector (2), a second selector (3) and a calibration module (4), the delay line (1) being composed of N-1 levels of delay units, the input end of each level of delay unit in the delay line (1) and the output end of the last level of delay unit being respectively connected to N input ends of the first selector (2) and N input ends of the second selector (3), the first selector (2) and the second selector (3) being both N-to-one selectors, the first selector (2) and the second selector (3) both being used to select one path from N input paths according to a delay unit selection signal to obtain a high-precision PWM waveform output, the input end of the calibration module (4) being connected to the output end of the second selector (3) to calibrate the high-precision PWM waveform output by the second selector (3) in combination with the input ordinary PWM waveform to generate an actual calibration value representing the number of delay unit levels required for the current delay of one clock cycle.

2. The high-precision pulse width modulator supporting adaptive calibration according to claim 1, characterized in that: The calibration module (4) comprises a first D flip-flop (41), a first edge detection module (42), a second D flip-flop (43), a third D flip-flop (44), a second edge detection module (45), a calibration state judgment module (46), a summing module (47) and a fourth D flip-flop (48); the high-precision PWM waveform output by the first selector (2) passes through the first D flip-flop (41) and the first edge detection module (42) in sequence to obtain a first edge detection result; the ordinary PWM waveform passes through the second D flip-flop (43), the third D flip-flop (44) and the second edge detection module (45) in sequence to obtain a second edge detection result. As a result, the first edge detection result and the second edge detection result are used as inputs of the calibration state judgment module (46) to compare the two edge detection results through the calibration state judgment module (46) to determine whether the state of the current calibration value is increasing, decreasing or maintaining. The summing module (47) is used to update the current calibration value according to the state of the current calibration value and output it through the fourth D flip-flop (48) until the actual calibration value tends to be stable to obtain an actual calibration value representing the number of delay unit stages required for the current delay of one clock cycle. The output of the fourth D flip-flop (48) is connected to the input end of the summing module (47) to provide the current calibration value.

3. The high-precision pulse width modulator supporting adaptive calibration according to claim 2, characterized in that: The summing module (47) is used to update the current calibration value according to the state of the current calibration value, including: if the state of the current calibration value is increasing, then the actual calibration value is increased by 1; if the state of the current calibration value is decreasing, then the actual calibration value is decreased by 1; if the state of the current calibration value is unchanged, then the actual calibration value is kept unchanged.

4. The high-precision pulse width modulator supporting adaptive calibration according to claim 3, characterized in that: The delay line (1) is composed of 255 levels of delay units. When the fourth D flip-flop (48) has not yet output a current calibration value, the summing module (47) uses a calibration default value as the current calibration value, and the calibration default value is 128.

5. The high-precision pulse width modulator supporting adaptive calibration according to any one of claims 1 to 4, characterized in that: It also includes a PWM register module for providing a delay unit selection signal to achieve the selection of high-precision PWM waveform output, processing register read and write requests from the CPU, and register output control logic. The PWM register module includes four registers: a configuration register HRCNFG, which is used to achieve the output mode selection of the high-precision PWM waveform, and the output mode includes a duty cycle control mode and a phase control mode; a duty cycle extension register CMPAHR, which is used to provide a delay unit selection signal in the duty cycle control mode; The phase expansion register TBPHSHR is used to provide a delay unit selection signal in the phase control mode; the calibration register HRREF is used to indicate the actual calibration value of the number of delay unit stages required to delay one clock cycle when the PWM waveform is output.

6. The high-precision pulse width modulator supporting adaptive calibration according to claim 5, characterized in that: The domain in the configuration register HRCNFG includes a 2-bit edge mode bit EDGMODE, a 1-bit control mode bit CTLMODE and a 1-bit mapping mode bit HRLOAD. The edge mode bit EDGMODE is used to configure the edge detection mode to be one of high-precision PWM waveform output enable, edge-controlled rising edge, edge-controlled falling edge, edge-controlled rising edge and falling edge. The control mode bit CTLMODE is used to configure the output mode to be a duty cycle control mode or a phase control mode. The mapping mode bit HRLOAD is used to configure the mapping value loading event of the delay unit selection signal in the duty cycle control mode to be a counter equal to zero or a preset period PRD.

7. The high-precision pulse width modulator supporting adaptive calibration according to claim 5, characterized in that: The duty cycle extension register CMPAHR has a value range of 1 to N-1 for implementing 1 to N-1 level adjustable delay line (1) in a duty cycle control mode, wherein N-1 is the number of delay units in the delay line (1).

8. The high-precision pulse width modulator supporting adaptive calibration according to claim 5, characterized in that: The phase expansion register TBPHSHR has a value range of 1 to N-1 for realizing 1 to N-1 level adjustable delay line (1) in phase control mode, wherein N-1 is the number of delay units in the delay line (1).

9. The high-precision pulse width modulator supporting adaptive calibration according to claim 1, characterized in that: The input end of the delay and calibration unit is also connected to a common PWM waveform generator for generating a common PWM waveform.

10. An application method of the high-precision pulse width modulator supporting adaptive calibration as claimed in claim 6, characterized in that: The steps include: S1, read the edge mode bit EDGMODE of the configuration register HRCNFG through the PWM register module to see if the high-precision PWM waveform output function is disabled. If the high-precision PWM waveform output function is not disabled, jump to step S2; otherwise, directly output the ordinary PWM waveform, end and exit; S2, determining the output mode of the high-precision PWM waveform according to the control mode bit CTLMODE of the configuration register HRCNFG, if the output mode of the high-precision PWM waveform is the duty cycle control mode, selecting the duty cycle extension register CMPAHR to provide a delay unit selection signal in the duty cycle control mode; If the output mode of the high-precision PWM waveform is the phase control mode, the phase extension register TBPHSHR is selected to provide a delay unit selection signal in the phase control mode; S3, performing delay and calibration processing through the delay and calibration unit, including: delaying the input common PWM waveform through the N-1-stage delay unit in the delay line (1), and selecting one path from the N-path inputs through the first selector (2) and the second selector (3) in combination with the mapping mode bit HRLOAD and the delay unit selection signal to obtain a high-precision PWM waveform output; calibrating the high-precision PWM waveform output by the second selector (3) and the input common PWM waveform through the calibration module (4) in combination with the edge detection mode configured by the edge mode bit EDGMODE to generate an actual calibration value representing the number of delay unit stages required for the current delay of one clock cycle and writing it into the calibration register HRREF until the actual calibration value is stable; S4, responding to the user's read request through the PWM register module, returning the actual calibration value written into the calibration register HRREF indicating the number of delay unit stages required for the current delay of one clock cycle.

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