Digital driver based on GaAs technology

Abstract

The invention relates to the technical field of microelectronics, semiconductors and communication, and discloses a GaAs process-based digital driver, which comprises a power supply protection circuit, an input level protection circuit, a level shift circuit, a power supply buffer stage circuit, an inverting circuit 1 and an inverting circuit 2, the power supply protection circuit and the input level protection circuit are both obtained by designing a Schottky ESD protection diode provided by a GaAs pHEMT technology. The negative level complementary output digital driving circuit for negative voltage power supply under the GaAs technology is realized, the circuit reliability is improved, the problem of wrong level conversion under different temperature technology pins is solved, in addition, the monolithic integration level is improved, unnecessary port control is reduced, the power consumption of a driver is greatly reduced, and the usability is improved.

Description

Technical Field

[0001] The invention relates to the field of microwave integrated circuits, and in particular to a digital driver based on GaAs technology. Background Art

[0002] In microwave integrated circuits, digital drivers are often used in various amplitude and phase control circuits, such as digitally controlled phase shifters, digitally controlled attenuators, and switch filter groups. The main function of a digital driver is to convert conventional transistor-transistor logic level signals into a pair of complementary level signals, making it easier to turn on and off transistors in RF circuits, avoiding the use of more control power supply branches, and reducing chip area and circuit complexity.

[0003] At present, the current GaAs process is different from the classic silicon-based process. It lacks intrinsically stable GaAs oxide, and therefore lacks the P-type field effect transistors necessary for CMOS digital logic. The CMOS process digital circuit design is mature, but when used in cascade with GaAs microwave chips, integration and radiation resistance become limiting factors. And because most GaAs chips use depletion-type transistors, negative level output is more convenient for RF circuit control, reducing unnecessary positive voltage design in the circuit. Therefore, it has become an urgent need to develop a digital drive circuit that can be integrated with GaAs microwave chips and is mature and highly reliable. Summary of the invention

[0004] Based on this, it is necessary to address the problem of the lack of digital driving circuit technology that can be integrated with GaAs microwave chips and mature with high reliability in the prior art, and propose a digital driver based on GaAs technology, the circuit includes: a power protection circuit, an input level protection circuit, a level shift circuit, a power buffer stage circuit and an inverter circuit 1, an inverter circuit 2;

[0005] The power protection circuit is connected to the power supply, and the input level protection circuit is connected to the input level port, wherein the power protection circuit and the input level protection circuit are both designed using Schottky ESD protection diodes provided by GaAs pHEMT technology;

[0006] The input level port is connected to the input port of the level shift circuit, the output port of the level shift circuit is connected to one end of the power buffer stage circuit, and the other end of the power buffer stage circuit is connected to the power supply;

[0007] The output port of the level shift circuit is also connected to the input port of the inverter circuit 1, the output port of the inverter circuit 1 outputs the level signal 1, the input port of the inverter circuit 2 is connected to the inverter circuit 1, and the output port of the inverter circuit 2 outputs the level signal 2, wherein the power supply adopts a negative level signal, the level signal 1 and the level signal 2 are a pair of complementary negative level signals, and the control signal of the input level port is a positive level.

[0008] Further, the power protection circuit includes a Schottky ESD protection diode D11, a Schottky ESD protection diode D12, a Schottky ESD protection diode D13, a Schottky ESD protection diode D1n, a resistor R1, and a capacitor C1, wherein the cathode end of the Schottky ESD protection diode D11 is connected to the ground, the anode end of the Schottky ESD protection diode D11 is connected to the power supply voltage input terminal Vee, one end of the resistor R1 is connected to the power supply voltage input terminal Vee, the other end of the resistor R1 is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, the cathode of the Schottky ESD protection diode D1n is connected to the anode of the Schottky ESD protection diode D13, the anode of the Schottky ESD protection diode D1n is connected to the ground end, the cathode of the Schottky ESD protection diode D13 is connected to the anode of the Schottky ESD protection diode D12, and the cathode of the Schottky ESD protection diode D12 is connected to the power supply voltage input terminal Vee.

[0009] Furthermore, the input level protection circuit includes a Schottky ESD protection diode D21, a Schottky ESD protection diode D31, a Schottky ESD protection diode D32, and a Schottky ESD protection diode D3n, wherein the cathode of the Schottky ESD protection diode D21 is connected to the input level port, the anode of the Schottky ESD protection diode D21 is grounded, the anode of the Schottky ESD protection diode D31 is connected to the input level port, the cathode of the Schottky ESD protection diode D31 is connected to the anode of the Schottky ESD protection diode D32, the cathode of the Schottky ESD protection diode D32 is connected to the anode of the Schottky ESD protection diode D3n, and the cathode of the Schottky ESD protection diode D3n is grounded.

[0010] Further, the level shift circuit includes a resistor R2 and n forward series-connected diodes D41 to D4n, the first end of the resistor R2 is connected to the input level port, the second end of the resistor R2 is connected to the anode end of the diode D41, the anode of the first forward diode D41 among the n forward series-connected diodes is connected to the second end of the resistor R2, the cathode of the last forward diode D4n among the n forward series-connected diodes is connected to the first end of the resistor R3 in the power buffer circuit, and the cathode of the last forward diode D4n among the n forward series-connected diodes is connected to the gate end of the field effect transistor T2 in the reverse circuit 1.

[0011] Furthermore, the power buffer stage circuit includes a D-type field effect transistor T1 and a resistor R3, wherein one end of the source of the D-type field effect transistor T1 is connected to the power supply voltage input end Vee, the gate of the D-type field effect transistor T1 is connected to the first end of the resistor R3, and the drain of the D-type field effect transistor T1 is connected to the second end of the resistor R3.

[0012] Further, the inverter circuit 1 includes an E-type field effect transistor T2, an E-type field effect transistor T4, a D-type field effect transistor T3, a D-type field effect transistor T5, a D-type field effect transistor T6, and a resistor R4;

[0013] The drain of the E-type field effect transistor T2 is connected to the power supply voltage input terminal Vee, one end of the source of the E-type field effect transistor T2 is connected to one end of the resistor R4, the source of the E-type field effect transistor T2 is connected to the gate of the D-type field effect transistor T3, the drain of the D-type field effect transistor T3 is connected to the other end of the resistor R4, and the source of the D-type field effect transistor T3 is grounded;

[0014] The drain of the field effect transistor T4 is connected to the power supply voltage input terminal Vee, the gate of the field effect transistor T4 is connected to the source of the field effect transistor T2, the source of the field effect transistor T4 is connected to the drain of the field effect transistor T5, and the source of the field effect transistor T4 outputs a level signal 1;

[0015] The gate of the field effect transistor T5 is connected to the drain of the field effect transistor T5 and the gate of the field effect transistor T6 respectively, the source of the field effect transistor T5 is connected to the drain of the field effect transistor T6, and the source of the field effect transistor T6 is grounded.

[0016] Further, the inverting circuit 2 includes an E-type field effect transistor T7, an E-type field effect transistor T9, a D-type field effect transistor T8, a D-type field effect transistor T10, a D-type field effect transistor T11, and a resistor R5;

[0017] The drain of the E-type field effect transistor T7 is connected to the power supply voltage input terminal Vee, and the gate of the E-type field effect transistor T7 is connected to the source of the field effect transistor T2;

[0018] One end of the source of the E-type field effect transistor T7 is connected to one end of the resistor R5, the source of the E-type field effect transistor T7 is connected to the gate of the D-type field effect transistor T8, the drain of the D-type field effect transistor T8 is connected to the other end of the resistor R5, and the source of the D-type field effect transistor T8 is grounded;

[0019] The drain of the field effect transistor T9 is connected to the power supply voltage input terminal Vee, the gate of the field effect transistor T9 is connected to the source of the field effect transistor T7, the source of the field effect transistor T9 is connected to the drain of the field effect transistor T10, and the source of the field effect transistor T9 outputs a level signal 1;

[0020] The gate of the field effect transistor T10 is connected to the drain of the field effect transistor T10 and the gate of the field effect transistor T11 , respectively. The source of the field effect transistor T10 is connected to the drain of the field effect transistor T11 , and the source of the field effect transistor T11 is grounded.

[0021] The digital driver based on GaAs process proposed by the present invention comprises: a power protection circuit, an input level protection circuit, a level shift circuit, a power buffer stage circuit and an inverter circuit 1 and an inverter circuit 2; the power protection circuit is connected to a power supply, and the input level protection circuit is connected to an input level port, wherein the power protection circuit and the input level protection circuit are both designed by using a Schottky ESD protection diode provided by a GaAs pHEMT process; the input level port is connected to an input port of a level shift circuit, an output port of the level shift circuit is connected to one end of a power buffer stage circuit, and the other end of the power buffer stage circuit is connected to a power supply; the output port of the level shift circuit is also connected to an input port of an inverter circuit 1, the output port of the inverter circuit 1 outputs a level signal 1, the input port of the inverter circuit 2 is connected to the inverter circuit 1, and the output port of the inverter circuit 2 outputs a level signal 2, wherein the power supply adopts a negative level signal, the level signal 1 and the level signal 2 are a pair of complementary negative level signals, and the control signal of the input level port is a positive level. The present application realizes a negative level complementary output digital driving circuit with negative voltage power supply under GaAs process, while improving the circuit reliability and solving the problem of incorrect conversion level under different temperature process feet. In addition, it also improves the single-chip integration, reduces unnecessary port control, greatly reduces the power consumption of the driver and improves ease of use. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] in:

[0024] Figure 1 A schematic diagram of the circuit structure of a digital driver based on GaAs technology in one embodiment;

[0025] Figure 2 The power consumption of the digital driver example based on GaAs technology of the present invention after testing;

[0026] Figure 3 The output level after testing of the digital driver example based on GaAs technology of the present invention;

[0027] Figure 4 This is a traditional GaAs DCFL inverter circuit. DETAILED DESCRIPTION

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "including" and "having" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0029] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] See also Figure 1 As shown, Figure 1 A circuit diagram of a digital driver based on GaAs technology provided by an embodiment of the present invention includes: a power protection circuit, an input level protection circuit, a level shift circuit, a power buffer stage circuit, and an inverter circuit 1 and an inverter circuit 2;

[0032] The power protection circuit is connected to the power supply, and the input level protection circuit is connected to the input level port, wherein the power protection circuit and the input level protection circuit are both designed using Schottky ESD protection diodes provided by GaAs pHEMT technology;

[0033] The input level port is connected to the input port of the level shift circuit, the output port of the level shift circuit is connected to one end of the power buffer stage circuit, and the other end of the power buffer stage circuit is connected to the power supply;

[0034] The output port of the level shift circuit is also connected to the input port of the inverter circuit 1, the output port of the inverter circuit 1 outputs the level signal 1, the input port of the inverter circuit 2 is connected to the inverter circuit 1, and the output port of the inverter circuit 2 outputs the level signal 2, wherein the power supply adopts a negative level signal, the level signal 1 and the level signal 2 are a pair of complementary negative level signals, and the control signal of the input level port is a positive level.

[0035] In one embodiment, the power protection circuit includes a Schottky ESD protection diode D11, a Schottky ESD protection diode D12, a Schottky ESD protection diode D13, a Schottky ESD protection diode D1n, a resistor R1, and a capacitor C1, wherein the cathode terminal of the Schottky ESD protection diode D11 is connected to the ground, the anode terminal of the Schottky ESD protection diode D11 is connected to the power supply voltage input terminal Vee, one end of the resistor R1 is connected to the power supply voltage input terminal Vee, the other end of the resistor R1 is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, the cathode of the Schottky ESD protection diode D1n is connected to the anode of the Schottky ESD protection diode D13, the anode of the Schottky ESD protection diode D1n is connected to the ground terminal, the cathode of the Schottky ESD protection diode D13 is connected to the anode of the Schottky ESD protection diode D12, and the cathode of the Schottky ESD protection diode D12 is connected to the power supply voltage input terminal Vee.

[0036] In this embodiment, the specific values ​​of the resistor R1 and the capacitor C1 can be set according to needs. Through the ESD protection diode circuit of the power protection circuit, when an electrostatic pulse comes, the power clamp circuit can provide a low-resistance current path to prevent the core circuit from being impacted by the ESD pulse and causing failure; through the resistor and capacitor series filter circuit, a certain impurity ripple signal of the power supply can be filtered out to prevent the RF circuit signal from being affected by modulation and coupling.

[0037] In one embodiment, the input level protection circuit includes a Schottky ESD protection diode D21, a Schottky ESD protection diode D31, a Schottky ESD protection diode D32, and a Schottky ESD protection diode D3n, wherein the cathode of the Schottky ESD protection diode D21 is connected to the input level port, the anode of the Schottky ESD protection diode D21 is grounded, the anode of the Schottky ESD protection diode D31 is connected to the input level port, the cathode of the Schottky ESD protection diode D31 is connected to the anode of the Schottky ESD protection diode D32, the cathode of the Schottky ESD protection diode D32 is connected to the anode of the Schottky ESD protection diode D3n, and the cathode of the Schottky ESD protection diode D3n is grounded.

[0038] In this embodiment, the number n of the ESD protection diodes can be set according to specific needs. Similar to the above-mentioned ESD protection diode circuit, the input level protection circuit is used to prevent the core circuit from being impacted by ESD pulses and causing failure.

[0039] In one embodiment, the level shift circuit includes a resistor R2 and n forward series-connected diodes D41 to D4n, the first end of the resistor R2 is connected to the input level port, the second end of the resistor R2 is connected to an anode end of the diode D41, the anode of the first forward diode D41 among the n forward series-connected diodes is connected to the second end of the resistor R2, the cathode of the last forward diode D4n among the n forward series-connected diodes is connected to the first end of the resistor R3 in the power buffer circuit, and the cathode of the last forward diode D4n among the n forward series-connected diodes is connected to a gate end of the field effect transistor T2 in the reverse circuit 1.

[0040] In this embodiment, the level shift circuit mainly functions to shift the 0V and 5V electrical signals at the input level end to a negative level and a level signal close to 0V; the function of the resistor R2 is mainly to cooperate with the diode circuit to adjust the displacement level and reduce the overall power consumption of the driving circuit.

[0041] In one embodiment, the power buffer stage circuit includes a D-type field effect transistor T1 and a resistor R3, wherein one end of the source of the D-type field effect transistor T1 is connected to the power supply voltage input end Vee, the gate of the D-type field effect transistor T1 is connected to the first end of the resistor R3, and the drain of the D-type field effect transistor T1 is connected to the second end of the resistor R3.

[0042] In this embodiment, the resistance of the resistor R3 is generally 1 to 3KΩ; further, the power buffer stage circuit is connected to the drain and source of the D-type field effect transistor T1 and is connected in series with the resistor R3, which can be regarded as a resistor with a large resistance value, so as to stabilize the voltage signal and ensure that each input node of the reverse circuit has a fixed voltage signal.

[0043] In one embodiment, the inverter circuit 1 includes an E-type field effect transistor T2, an E-type field effect transistor T4, a D-type field effect transistor T3, a D-type field effect transistor T5, a D-type field effect transistor T6, and a resistor R4;

[0044] The drain of the E-type field effect transistor T2 is connected to the power supply voltage input terminal Vee, one end of the source of the E-type field effect transistor T2 is connected to one end of the resistor R4, the source of the E-type field effect transistor T2 is connected to the gate of the D-type field effect transistor T3, the drain of the D-type field effect transistor T3 is connected to the other end of the resistor R4, and the source of the D-type field effect transistor T3 is grounded;

[0045] The drain of the field effect transistor T4 is connected to the power supply voltage input terminal Vee, the gate of the field effect transistor T4 is connected to the source of the field effect transistor T2, the source of the field effect transistor T4 is connected to the drain of the field effect transistor T5, and the source of the field effect transistor T4 outputs a level signal 1;

[0046] The gate of the field effect transistor T5 is connected to the drain of the field effect transistor T5 and the gate of the field effect transistor T6 respectively, the source of the field effect transistor T5 is connected to the drain of the field effect transistor T6, and the source of the field effect transistor T6 is grounded.

[0047] In one embodiment, the inverter circuit 2 includes an E-type field effect transistor T7, an E-type field effect transistor T9, a D-type field effect transistor T8, a D-type field effect transistor T10, a D-type field effect transistor T11, and a resistor R5;

[0048] The drain of the E-type field effect transistor T7 is connected to the power supply voltage input terminal Vee, and the gate of the E-type field effect transistor T7 is connected to the source of the field effect transistor T2;

[0049] One end of the source of the E-type field effect transistor T7 is connected to one end of the resistor R5, the source of the E-type field effect transistor T7 is connected to the gate of the D-type field effect transistor T8, the drain of the D-type field effect transistor T8 is connected to the other end of the resistor R5, and the source of the D-type field effect transistor T8 is grounded;

[0050] The drain of the field effect transistor T9 is connected to the power supply voltage input terminal Vee, the gate of the field effect transistor T9 is connected to the source of the field effect transistor T7, the source of the field effect transistor T9 is connected to the drain of the field effect transistor T10, and the source of the field effect transistor T9 outputs a level signal 1;

[0051] The gate of the field effect transistor T10 is connected to the drain of the field effect transistor T10 and the gate of the field effect transistor T11 , respectively. The source of the field effect transistor T10 is connected to the drain of the field effect transistor T11 , and the source of the field effect transistor T11 is grounded.

[0052] In this embodiment, the T2, T3, T7, T8 field effect transistors in the inverter circuit 1 and the inverter circuit 2 constitute the first and second stage inverter circuits, and R4 and R5 are generally resistors with a resistance of 1 to 3KΩ; the present invention is based on the traditional GaAs DCFL inverter circuit (see reference Figure 4 ) is improved; in the traditional GaAs DCFL inverter circuit, Q1 is a D-type field effect transistor, and Q2 is an E-type field effect transistor; its working principle is that the drain end of Q1 is connected to the high-level power supply voltage end; its gate end is connected to the drain end and connected to the output level signal with the drain end of Q2; since the gate-source of Q1 is connected, it is always in the on state; when the input end inputs a low level, Q2 is in the off state, so the OUT end outputs a high level; when the input end inputs a high level, Q2 is in the on state, so the OUT end outputs a low level; further, in the inverter circuit 1 and the inverter circuit 2, T4, T5, T6, T9, T10, and T11 also constitute the third and fourth level inverter circuits respectively;

[0053] Furthermore, since the conduction voltage of a general E-type field effect transistor is 0.7V, and the gate-drain connection of the D-type field effect transistors T3 and T8 is established, they are always in the on state and can be equivalent to a resistor; and by connecting R4 and R5 with the T3 and T8 tubes, the equivalent resistance can be further increased, thereby reducing the power consumption of the circuit; by adjusting the resistance values ​​of R4 and R5, the voltage of the input node of the inverter circuit can be adjusted according to specific needs; further, T5, T6 and T10, T11 can all be used as equivalent resistors through the gate-drain connection mode, and the use of a multi-tube cascade mode helps to reduce the layout area of ​​the inverter compared to using resistors with the same resistance value.

[0054] Furthermore, when the input level signal is a low level of 0V, the signal can be shifted to near -5V through the level shift circuit. When the shifted signal enters the gate end of the T2 tube in the inverter circuit 1, the T2 tube is in a cut-off state at this time, so a signal near 0V can be output to the gate end of the T7 tube and the gate end of the T4 tube in the inverter circuit 2; further, the T4 tube is in a conducting state at this time, so the Vo1 port outputs a signal near -5V; similarly, the T7 tube is in an open state because the gate inputs a signal near 0V, and can transmit a level signal near -5V to the T9 tube; at this time, the T9 tube is in a cut-off state, so the Vo2 port outputs a low level signal near 0V.

[0055] In the present invention, when the input level signal is a high level of 5V, its working principle and the effects produced are the same as those described above. The specific analysis and understanding can be referred to above, and no repeated description will be given here.

[0056] The present invention improves the traditional GaAs driving circuit powered by positive power supply voltage, and can realize the use of negative voltage power supply, the input control voltage is 0 / +5V, and finally outputs a pair of complementary negative voltage control level digital driving circuits. Compared with the traditional circuit, the present invention reduces the circuit layout area and adds a protection circuit, which greatly improves the protection performance of the circuit and enhances the reliability of the application in the radio frequency circuit; at the same time, the present invention greatly reduces the circuit power consumption through resistance adjustment, such as Figure 2 As shown, the current consumption is only 1.4mA; further, the actual test results of the present invention are as follows Figure 3 As shown, the complementary level output of 0V / -5V can be completed.

[0057] This application mainly improves the traditional GaAs digital driver circuit design and improves the traditional positive voltage powered GaAs DCFL (Direct Coupling Fie ld Effect Transistor The structure of the inverter of GaAs RF circuit is improved so that it can be applied to negative voltage power supply and output complementary negative level control signal, which greatly increases the convenience of use in GaAs RF circuit; by adding power protection circuit and input level protection circuit, and combining Schottky ESD protection diode; when the normal working voltage is input at the voltage input end and the power input end, the ESD protection diode will not be turned on, and the working voltage can enter the working circuit normally; in addition, the power port is additionally added with RC series circuit, which can filter out the noise carried by the power voltage signal, and further improve the reliability of the circuit; compared with the traditional GaAs digital driver circuit, the present application realizes the negative level complementary output digital driver circuit with negative voltage power supply under GaAs process, and at the same time improves the circuit reliability and solves the problem of incorrect conversion level under different temperature process feet; in addition, the monolithic integration is improved, unnecessary port control is reduced, the power consumption of the driver is greatly reduced and the usability is improved, and the static power consumption current of the circuit of the present application is only 1mA.

[0058] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A digital driver based on GaAs technology, characterized in that: The digital driver based on GaAs technology includes: a power protection circuit, an input level protection circuit, a level shift circuit, a power buffer stage circuit and an inverter circuit 1 and an inverter circuit 2; The power protection circuit is connected to the power supply, and the input level protection circuit is connected to the input level port, wherein the power protection circuit and the input level protection circuit are both designed using Schottky ESD protection diodes provided by GaAs pHEMT technology; The input level port is connected to the input port of the level shift circuit, the output port of the level shift circuit is connected to one end of the power buffer stage circuit, and the other end of the power buffer stage circuit is connected to the power supply; The output port of the level shift circuit is also connected to the input port of the inverter circuit 1, the output port of the inverter circuit 1 outputs the level signal 1, the input port of the inverter circuit 2 is connected to the inverter circuit 1, and the output port of the inverter circuit 2 outputs the level signal 2, wherein the power supply adopts a negative level signal, the level signal 1 and the level signal 2 are a pair of complementary negative level signals, and the control signal of the input level port is a positive level.

2. The GaAs-based digital driver according to claim 1, characterized in that: The power protection circuit includes a Schottky ESD protection diode D11, a Schottky ESD protection diode D12, a Schottky ESD protection diode D13, a Schottky ESD protection diode D1n, a resistor R1, and a capacitor C1. The cathode terminal of the Schottky ESD protection diode D11 is connected to the ground, the anode terminal of the Schottky ESD protection diode D11 is connected to the power supply voltage input terminal Vee, one end of the resistor R1 is connected to the power supply voltage input terminal Vee, the other end of the resistor R1 is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, the cathode of the Schottky ESD protection diode D1n is connected to the anode of the Schottky ESD protection diode D13, the anode of the Schottky ESD protection diode D1n is connected to the ground terminal, the cathode of the Schottky ESD protection diode D13 is connected to the anode of the Schottky ESD protection diode D12, and the cathode of the Schottky ESD protection diode D12 is connected to the power supply voltage input terminal Vee.

3. The GaAs-based digital driver according to claim 2, characterized in that: The input level protection circuit includes a Schottky ESD protection diode D21, a Schottky ESD protection diode D31, a Schottky ESD protection diode D32, and a Schottky ESD protection diode D3n. The cathode of the Schottky ESD protection diode D21 is connected to the input level port, the anode of the Schottky ESD protection diode D21 is grounded, the anode of the Schottky ESD protection diode D31 is connected to the input level port, the cathode of the Schottky ESD protection diode D31 is connected to the anode of the Schottky ESD protection diode D32, the cathode of the Schottky ESD protection diode D32 is connected to the anode of the Schottky ESD protection diode D3n, and the cathode of the Schottky ESD protection diode D3n is grounded.

4. The GaAs-based digital driver according to claim 3, characterized in that: The level shift circuit includes a resistor R2 and n forward series-connected diodes D41 to D4n, wherein the first end of the resistor R2 is connected to the input level port, the second end of the resistor R2 is connected to the anode end of the diode D41, the anode of the first forward diode D41 among the n forward series-connected diodes is connected to the second end of the resistor R2, the cathode of the last forward diode D4n among the n forward series-connected diodes is connected to the first end of the resistor R3 in the power buffer circuit, and the cathode of the last forward diode D4n among the n forward series-connected diodes is connected to the gate end of the field effect transistor T2 in the reverse circuit 1.

5. The GaAs-based digital driver according to claim 4, characterized in that: The power buffer stage circuit includes a D-type field effect transistor T1 and a resistor R3, wherein one end of the source of the D-type field effect transistor T1 is connected to the power supply voltage input end Vee, the gate of the D-type field effect transistor T1 is connected to the first end of the resistor R3, and the drain of the D-type field effect transistor T1 is connected to the second end of the resistor R3.

6. The GaAs-based digital driver according to claim 5, characterized in that: The inverter circuit 1 includes an E-type field effect transistor T2, an E-type field effect transistor T4, a D-type field effect transistor T3, a D-type field effect transistor T5, a D-type field effect transistor T6, and a resistor R4; The drain of the E-type field effect transistor T2 is connected to the power supply voltage input terminal Vee, one end of the source of the E-type field effect transistor T2 is connected to one end of the resistor R4, the source of the E-type field effect transistor T2 is connected to the gate of the D-type field effect transistor T3, the drain of the D-type field effect transistor T3 is connected to the other end of the resistor R4, and the source of the D-type field effect transistor T3 is grounded; The drain of the field effect transistor T4 is connected to the power supply voltage input terminal Vee, the gate of the field effect transistor T4 is connected to the source of the field effect transistor T2, the source of the field effect transistor T4 is connected to the drain of the field effect transistor T5, and the source of the field effect transistor T4 outputs a level signal 1; The gate of the field effect transistor T5 is connected to the drain of the field effect transistor T5 and the gate of the field effect transistor T6 respectively, the source of the field effect transistor T5 is connected to the drain of the field effect transistor T6, and the source of the field effect transistor T6 is grounded.

7. The GaAs-based digital driver according to claim 6, characterized in that: The inverter circuit 2 includes an E-type field effect transistor T7, an E-type field effect transistor T9, a D-type field effect transistor T8, a D-type field effect transistor T10, a D-type field effect transistor T11, and a resistor R5; The drain of the E-type field effect transistor T7 is connected to the power supply voltage input terminal Vee, and the gate of the E-type field effect transistor T7 is connected to the source of the field effect transistor T2; One end of the source of the E-type field effect transistor T7 is connected to one end of the resistor R5, the source of the E-type field effect transistor T7 is connected to the gate of the D-type field effect transistor T8, the drain of the D-type field effect transistor T8 is connected to the other end of the resistor R5, and the source of the D-type field effect transistor T8 is grounded; The drain of the field effect transistor T9 is connected to the power supply voltage input terminal Vee, the gate of the field effect transistor T9 is connected to the source of the field effect transistor T7, the source of the field effect transistor T9 is connected to the drain of the field effect transistor T10, and the source of the field effect transistor T9 outputs a level signal 1; The gate of the field effect transistor T10 is connected to the drain of the field effect transistor T10 and the gate of the field effect transistor T11 , respectively. The source of the field effect transistor T10 is connected to the drain of the field effect transistor T11 , and the source of the field effect transistor T11 is grounded.

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