Analog-to-digital conversion device and method with data storage mechanism

Abstract

An analog-to-digital conversion device with a data storage mechanism comprises an analog-to-digital conversion circuit. The analog-to-digital conversion circuit comprises a conversion circuit, a comparison result storage circuit and a correction circuit. The conversion circuit comprises a capacitor array circuit, a comparison circuit and a capacitor control circuit. The capacitor array circuit receives an analog input voltage corresponding to a sampling stage of a conversion program, and performs a capacitor switching operation to generate an analog output voltage. The comparison circuit sequentially generates comparison results according to the analog output voltage. And the capacitor control circuit controls the capacitor array circuit to perform capacitor switching operation through a gradual approximation register mechanism according to the comparison result. The comparison result storage circuit stores the comparison result. The correction circuit obtains the comparison result from the comparison result storage circuit to carry out digital error correction so as to generate a digital output signal.

Description

Technical Field

[0001] The present invention relates to analog-to-digital conversion technology, and in particular to an analog-to-digital conversion device and method with a data storage mechanism. Background Art

[0002] An analog-to-digital converter is a circuit that converts a continuous analog signal or physical quantity (usually voltage) into a digital signal. The analog-to-digital converter can be implemented using a variety of different architectures, among which the successive-approximation register (SAR) analog-to-digital converter is a common one.

[0003] However, some analog-to-digital conversion circuits implemented with a successive approximation register mechanism have a redundant architecture, and require additional correction processing of the conversion result to generate a correct digital output signal. In the case of an analog-to-digital conversion circuit operating at an increasingly high frequency, the conversion result generated by a conversion process may be replaced by the conversion result of the next conversion process before the correction processing is completed, causing an error in the digital output signal. Summary of the invention

[0004] In view of the problems in the prior art, one of the objectives of the present invention is to provide an analog-to-digital conversion device and method with a data storage mechanism to improve the prior art.

[0005] The present invention includes an analog to digital conversion device (ADC) with a data storage mechanism, including: at least one analog to digital conversion circuit. The analog to digital conversion circuit includes: a conversion circuit, a comparison result storage circuit and a correction circuit. The conversion circuit includes: a capacitor array circuit, a comparison circuit and a capacitor control circuit. The capacitor array circuit is configured to receive a pair of analog input voltages in a sampling phase corresponding to a conversion procedure, and to perform a capacitor switching operation in a conversion phase corresponding to the conversion procedure to generate a pair of analog output voltages. The comparison circuit is configured to sequentially generate a plurality of comparison results according to the pair of analog output voltages in the conversion phase. The capacitor control circuit is configured to sequentially control the capacitor array circuit to perform a capacitor switching operation according to the comparison results through a successive-approximation register (SAR) mechanism in the conversion phase. The comparison result storage circuit is configured to store the comparison results. The correction circuit is configured to obtain the comparison results from the comparison result storage circuit, and then perform digital error correction (DEC) according to a plurality of weights to generate a digital output signal having a plurality of bits.

[0006] The present invention also includes an analog-to-digital conversion method with a data storage mechanism, which is applied to an analog-to-digital conversion device, including: causing a capacitor array circuit included in a conversion circuit included in at least one analog-to-digital conversion circuit to receive a pair of analog input voltages in a sampling phase of a conversion program, and to perform a capacitor switching operation in a conversion phase of the conversion program to generate a pair of analog output voltages; causing a comparison circuit included in the conversion circuit to sequentially generate a plurality of comparison results according to the pair of analog output voltages in a conversion phase; causing a capacitor control circuit included in the conversion circuit to control the capacitor array circuit to perform a capacitor switching operation in sequence according to the comparison results via a progressive approximation register mechanism in a conversion phase; causing a comparison result storage circuit included in at least one analog-to-digital conversion circuit to store the comparison result; and causing a correction circuit included in at least one analog-to-digital conversion circuit to obtain the comparison result from the comparison result storage circuit, and then perform digital error correction according to a plurality of weights to generate a digital output signal with a plurality of bits.

[0007] The features, practical effects and functions of the present application are described in detail as follows with reference to the accompanying drawings and preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram of an analog-to-digital conversion device with a data storage mechanism according to an embodiment of the present invention is shown;

[0009] Figure 2 shows a waveform diagram of a clock signal related to the operation of an analog-to-digital conversion circuit according to an embodiment of the present invention;

[0010] Figure 3 shows a waveform diagram of a clock signal related to the operation of an analog-to-digital conversion circuit according to another embodiment of the present invention;

[0011] Figure 4 A block diagram of an analog-to-digital conversion device with a data storage mechanism according to another embodiment of the present invention is shown;

[0012] Figure 5 shows a block diagram of an output storage circuit according to an embodiment of the present invention;

[0013] Figure 6 A block diagram showing an output storage circuit according to another embodiment of the present invention; and

[0014] Figure 7 A flow chart of an analog-to-digital conversion method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0015] One of the purposes of the present invention is to provide an analog-to-digital conversion device and method with a data storage mechanism, which can store the comparison results generated by the conversion circuit through a comparison result storage circuit, so that there is sufficient time for digital error correction, thereby allowing the analog-to-digital conversion device to operate at high speed.

[0016] Please refer to Figure 1 . Figure 1 FIG. 1 is a block diagram of an analog-to-digital conversion device 100 with a data storage mechanism according to an embodiment of the present invention. The analog-to-digital conversion device 100 includes: an analog-to-digital conversion circuit 110 .

[0017] The analog-to-digital conversion circuit 110 includes a conversion circuit 120 , a comparison result storage circuit 130 and a correction circuit 140 .

[0018] The conversion circuit 120 includes a capacitor array circuit 150 , a comparison circuit 160 and a capacitor control circuit 170 .

[0019] The capacitor array circuit 150 is configured to receive a pair of analog input voltages Vin and Vip corresponding to a sampling phase of a conversion process, and to perform capacitor switching operations corresponding to a conversion phase of the conversion process to generate a pair of analog output voltages Von and Vop.

[0020] In one embodiment, the capacitor array circuit 150 includes a sampling circuit 180 and two capacitor arrays 190A and 190B. The sampling circuit 180 samples the analog input voltages Vin and Vip. The capacitor arrays 190A and 190B each include a plurality of bit capacitors C P ~C 1 , each bit capacitance C P ~C 1 The capacitance values ​​may be the same or different depending on the design requirements. Wherein, P is a positive integer greater than 1.

[0021] In one embodiment, the bit capacitor C P ~C 1 The capacitor corresponding to the higher bit may have a larger capacitance value, and the capacitor corresponding to the lower bit may have a smaller capacitance value. P ~C 1 Can be configured to make the bit capacitor C P has the largest capacitance value and makes the bit capacitance C 1 Has the smallest capacitance value. In the bit capacitance C P And the bit capacitor C 1 The bit capacitors between the two bits may have decreasing capacitance values, and some bit capacitors may have the same capacitance value. However, the present invention is not limited to the above arrangement.

[0022] Bit Capacitor C P~C 1 The capacitor can be switched under the control of the capacitor control circuit 170 to be electrically coupled to different voltage references, such as Figure 1 The voltage VR and the ground potential GND shown in the figure are used to achieve the purpose of capacitor switching operation and generate different capacitor configurations. It should be noted that in different embodiments, the bit capacitor C P ~C 1 The switching can be performed one by one, or the switching can be performed in groups with multiple bit capacitors as a group. The present invention is not limited to a specific implementation.

[0023] The capacitor arrays 190A and 190B will be based on the bit capacitance C P ~C 1 Changing the capacitor configuration produces analog output voltages Von and Vop of different sizes.

[0024] The comparison circuit 160 is configured to generate a plurality of comparison results B in sequence according to the analog output voltages Von and Vop during the conversion phase. Q ~B 1 Wherein, Q is a positive integer greater than 1. The capacitance control circuit 170 is configured to sequentially calculate the capacitance according to the comparison result B in the conversion phase. Q ~B 1 The capacitor array circuit 150 is controlled by a successive approximation register mechanism to perform the aforementioned capacitor switching operation.

[0025] In one embodiment, the capacitor control circuit 170 enables the capacitor array circuit 150 to perform capacitor switching operations in a bit-by-bit order, so that the comparison circuit 160 generates a comparison result B in a bit-by-bit order. Q ~B 1 .

[0026] The comparison result storage circuit 130 is configured to store the comparison result B Q ~B 1 In one embodiment, the comparison result storage circuit 130 may be as follows: Figure 1 As shown, the comparison result B is received by the capacitor control circuit 170. Q ~B 1 , or selectively receive the comparison result B directly from the comparison circuit 160 Q ~B 1 .

[0027] In one embodiment, the comparison result storage circuit 130 includes a plurality of storage units S Q ~S 1 , and the storage unit S Q ~S 1 The number and comparison results of B Q ~B 1 Corresponding. Storage unit SQ ~S 1 Corresponding to the storage comparison result B Q ~B 1 .

[0028] In one embodiment, the analog-to-digital conversion circuit 110 is a redundant architecture with redundant bits. Therefore, the calibration circuit 140 is configured to obtain the comparison result B from the comparison result storage circuit 130. Q ~B 1 , to perform digital error correction (DEC) according to a plurality of weights to generate a D having a plurality of bits R ~D 1 The digital output signal DOUT is obtained by:

[0029] For example, when Q is 7, the comparison result B 7 ~B 1 The corresponding weights are 30, 14, 8, 4, 4, 2, and 1. In the above weights, 30 can be represented by 16+8+4+2 as the sum of the power values ​​of 2, and 14 can also be represented by 8+4+2 as the sum of the power values ​​of 2. The correction circuit 140 can be configured by, for example, but not limited to, multiple full adders corresponding to weights of different powers, so that the comparison result B 7 ~B 1 According to the above weights, the corresponding full adder is fed to perform addition and carry calculations, and then output as an R-bit digital output signal DOUT. In one embodiment, R is 6, corresponding to 6 bits D 6 ~D 1 The digital output signal DOUT.

[0030] It should be noted that the above comparison results and the number of digital output signals are only examples. In other embodiments, the comparison results and the number of digital output signals may vary depending on the switching method of the capacitor arrays 190A and 190B and the digital error correction method performed by the correction circuit 140. In addition, the structure and operation method of the correction circuit 140 are also only examples. In other embodiments, the correction circuit 140 may include other operation circuits and perform operations in other ways. The present invention is not limited to the above embodiments.

[0031] Since the digital error correction performed by the correction circuit 140 requires time to calculate, if the conversion circuit 120 has started processing the next conversion procedure before the correction circuit 140 completes the calculation, the comparison result B generated by the current conversion procedure Q ~B 1The information may be replaced by the comparison result of the next conversion process, so that the correction circuit 140 cannot output the correct calculation result.

[0032] Therefore, by setting the comparison result storage circuit 130, the comparison result B Q ~B 1 The data can be stored so that the calibration circuit 140 has more time to perform calculations and output a correct digital output signal DOUT.

[0033] It should be noted that, in one embodiment, the storage unit S in the comparison result storage circuit 130 Q ~S 1 The number of flip-flops determines the timing of the correction circuit 140 starting to perform digital error correction.

[0034] Please also refer to Figure 2 . Figure 2 FIG. 4 is a waveform diagram of a clock signal related to the operation of the analog-to-digital conversion circuit 110 according to an embodiment of the present invention.

[0035] In one embodiment, Figure 1 The conversion circuit 150 is based on Figure 2 The illustrated operation is performed over multiple clock cycles of the first clock signal CK1.

[0036] In one embodiment, each clock cycle includes a sampling time and a conversion time after the sampling time. Taking a current clock cycle PC1 included in the first clock signal CK1 as an example, the conversion circuit 150 performs a sampling phase of the conversion process at a sampling time TS1 in the current clock cycle PC1, and performs a conversion phase of the conversion process at a conversion time TC1 after the sampling time TS1 in the current clock cycle PC1.

[0037] The conversion circuit 150 may perform the same operation as the current clock cycle PC1 in any clock cycle of the first clock signal CK1. For example, the conversion circuit 150 may perform the sampling phase of the next conversion process at the sampling time TS2 in the next clock cycle PC2 after the current clock cycle PC1, and perform the conversion phase of the next conversion process at the conversion time TC2 after the sampling time TS2, and so on.

[0038] In this embodiment, the first clock signal CK1 is at a high level during the sampling time (eg, sampling time TS1, TS2) of each clock cycle, and is at a low level during the conversion time (eg, conversion time TC1, TC2) of each clock cycle. However, the present invention is not limited thereto.

[0039] In one embodiment, Figure 1The comparison result storage circuit 130 is based on Figure 2 The second clock signal CK2 has the same frequency as the first clock signal CK1 and a different phase from the first clock signal CK1, so that the comparison result storage circuit 130 stores the comparison result B before the end of the conversion time of each clock cycle according to the second clock signal CK2. Q ~B 1 .

[0040] by Figure 2 For the embodiment of the present invention, the phase of the second clock signal CK2 slightly leads the phase of the first clock signal CK1, and has a phase difference PD. For the current clock cycle PC1, the comparison result storage circuit 130 stores the comparison result of the second clock signal CK2 once before the end of the conversion time TC1. Figure 1 The comparison result B generated by the comparison circuit 160 Q ~B 1 Therefore, the comparison result B generated by the current clock cycle PC1 is Q ~B 1 The storage can be completed before the sampling time TS2 of the next clock cycle PC2 starts, and will not be affected by the next conversion process.

[0041] Corresponding to the conversion process of the current clock cycle PC1, the correction circuit 140 performs digital error correction in the correction time after the current clock cycle PC1. For example, this correction time may correspond to the sampling time TS2 in the next clock cycle PC2. However, the time point at which the correction circuit 140 actually performs digital error correction may be determined according to the timing provided by the comparison result storage circuit 130. The present invention is not limited thereto.

[0042] Please also refer to Figure 3 . Figure 3 FIG. 4 is a waveform diagram of a clock signal related to the operation of the analog-to-digital conversion circuit 110 according to another embodiment of the present invention.

[0043] Figure 3 It also shows Figure 1 The conversion circuit 150 operates according to the first clock signal CK1, and the relationship between the conversion circuit 150 and the first clock signal CK1 is the same as the corresponding Figure 2 The description is the same as that of . No further description is given here.

[0044] In this embodiment, Figure 1 The comparison result storage circuit 130 is based on Figure 3 The plurality of second clock signals CK2 shown 1 ~CK2 K Each second clock signal CK2 1 ~CK2K The second clock signal CK2 has the same frequency as the first clock signal CK1 and a different phase from the first clock signal CK1. 1 ~CK2 K The phases between them are different.

[0045] Comparison results B Q ~B 1 Divided into multiple comparison result groups, the second clock signal CK2 1 ~CK2 K The number K corresponds to the number of comparison result groups. The comparison result storage circuit 130 generates a comparison result according to the second clock signal CK2. 1 ~CK2 K The respective phases sequentially store the comparison result groups before the end of the conversion time of each clock cycle.

[0046] by Figure 3 For example, the second clock signal CK2 1 ~CK2 K The phases of the comparison result storage circuit 130 are ahead of the first clock signal CK1. 1 ~CK2 K , the comparison results in these comparison result groups are stored in sequence before the conversion time TC1 ends. Therefore, the comparison result B generated in the current clock cycle PC1 Q ~B 1 The storage can be completed before the sampling time TS2 of the next clock cycle PC2 starts, and will not be affected by the next conversion process.

[0047] In a numerical example, K is 3. Comparison result B Q ~B 1 will be divided into three comparison result groups so that the comparison result storage circuit 130 can store the comparison result according to the second clock signal CK2. 1 , CK2 2 , CK2 3 The three comparison result groups are stored in sequence before the conversion time TC1 ends. In one embodiment, K can also be equal to Q. The comparison result B Q ~B 1 The comparison result storage circuit 130 is divided into Q comparison result groups so that the comparison result storage circuit 130 can store the comparison result according to the second clock signal CK2. 1 ~CK2 Q The Q comparison result groups are stored sequentially before the conversion time TC1 ends.

[0048] The analog-to-digital conversion device of the present invention can store the comparison result generated by the conversion circuit via the comparison result storage circuit, so that there is sufficient time for digital error correction, thereby allowing the analog-to-digital conversion device to operate at a high speed.

[0049] Please refer to Figure 4 . Figure 4 FIG. 4 is a block diagram of an analog-to-digital conversion device 400 with a data storage mechanism according to another embodiment of the present invention. The analog-to-digital conversion device 400 includes: a plurality of analog-to-digital conversion circuits ADC 1 ~ADC N , output storage circuit 410 and post-processing circuit 420.

[0050] Figure 4 Analog-to-digital conversion circuit ADC 1 ~ADC N Can be respectively Figure 1 The analog-to-digital conversion circuit 110 shown has the same structure and operation mode, which will not be described in detail herein.

[0051] Figure 4 Analog-to-digital conversion circuit ADC 1 ~ADC N The number of is a positive integer N greater than 1, and they are collectively configured as a time-interleaved analog-to-digital conversion circuit. In order to configure the time-interleaved analog-to-digital conversion circuit, these analog-to-digital conversion circuits ADC 1 ~ADC N Required circuit elements (not shown) may be selectively provided as needed. The present invention is not limited to a specific implementation.

[0052] The output storage circuit 410 is configured to store N analog-to-digital conversion circuits ADC 1 ~ADC N The N digital output signals DOUT generated 1 ~DOUT N .

[0053] The post-processing circuit 420 is configured to obtain N digital output signals DOUT from the output storage circuit 410. 1 ~DOUT N In one embodiment, the post-processing circuit 420 can be configured to process the digital output signal DOUT. 1 ~DOUT N Perform further digital error correction or other processing.

[0054] Since the processing performed by the post-processing circuit 420 requires time to calculate, if the analog-to-digital conversion circuit ADC is not1 ~ADC N The subsequent conversion process has begun, and the digital output signal DOUT generated by the current conversion process 1 ~DOUT N The information may be replaced by the digital output signal of the next conversion process, so that the post-processing circuit 420 cannot output the correct calculation result.

[0055] Therefore, by setting the output storage circuit 410, the digital output signal DOUT 1 ~DOUT N The data can be stored so that the post-processing circuit 420 has more time to perform calculations and output the correct final digital output signal FDOUT.

[0056] In one embodiment, Figure 4 N analog-to-digital conversion circuits ADC 1 ~ADC N The output storage circuit 410 may have a structure related to that of the conversion circuit group, including a plurality of storage circuits, and the storage circuits are divided into a plurality of circuit layers that are sequentially connected in series and the number of the circuit layers is at least M.

[0057] When S is not greater than M, the Sth circuit layer receives the digital output signal generated by the Sth conversion circuit group and receives the digital output signal transmitted by the (S-1)th circuit layer for storage. When S is greater than M, the Sth circuit layer receives the digital output signal transmitted by the (S-1)th circuit layer for storage. The post-processing circuit 420 obtains N digital output signals from the last circuit layer for processing.

[0058] An implementation example will be described below using a numerical example where M is 2 and N is 16. In this case, the analog-to-digital conversion circuit ADC 1 ~ADC 16 Divided into two conversion circuit groups. For example, the analog-to-digital conversion circuit ADC 1 ~ADC 6 can be divided into the first conversion circuit group, and the analog-to-digital conversion circuit ADC 7 ~ADC 16 Can be divided into the second conversion circuit group.

[0059] Please refer to Figure 5 . Figure 5 FIG. 4 is a block diagram of an output storage circuit 410 according to an embodiment of the present invention.

[0060] Corresponding to the above numerical example, Figure 5 The output storage circuit 410 includes three circuit layers CL 1 ~CL 3A plurality of storage circuits 500.

[0061] For the first circuit layer CL 1 (S=1, less than M), since there is no 0th circuit layer, the first circuit layer CL 1 Only receives the digital output signal DOUT generated by the first conversion circuit group 1 ~DOUT 6 Therefore, the first circuit layer CL 1 The number of storage circuits 500 that can be configured is 6 to receive the digital output signal DOUT 1 ~DOUT 6 It should be noted that in order to keep the figure simple, Figure 5 Only one storage circuit 500 is shown and the corresponding number is indicated, but not all of them are shown.

[0062] For the second circuit layer CL 2 (S=2, equal to M), the second circuit layer CL 2 The digital output signal DOUT generated by the second conversion circuit group is received 7 ~DOUT 16 , and receiving the first circuit layer CL 1 The digital output signal DOUT is transmitted 1 ~DOUT 6 Therefore, the second circuit layer CL 2 The number of storage circuits 500 that can be configured is 16 to receive DOUT 1 ~DOUT 16 It should be noted that in order to keep the figure simple, Figure 5 Only one storage circuit 500 is shown and the corresponding number is indicated, but not all of them are shown.

[0063] For the third circuit layer CL 3 (S=3, greater than M), the third circuit layer CL 3 Then receive the second circuit layer CL 2 The digital output signal DOUT is transmitted 1 ~DOUT 16 Therefore, the third circuit layer CL 3 The number of storage circuits 500 that can be configured is 16 to receive DOUT 1 ~DOUT 16 It should be noted that in order to keep the figure simple, Figure 5 Only one storage circuit 500 is shown and the corresponding number is indicated, but not all of them are shown.

[0064] The post-processing circuit 420 starts from the last circuit layer CL3 Get 16 digital output signals DOUT 1 ~DOUT 16 to be processed.

[0065] Therefore, in the above example, the circuit layer CL 1 ~CL 2 In fact, the digital output signal DOUT 7 ~DOUT 16 Batch storage, while the circuit layer CL 3 It can be optionally set to add additional timing.

[0066] In one embodiment, Figure 5 The output storage circuit 410 further includes a clock generating circuit 510 configured to provide a circuit layer CL 1 ~CL 3 Multiple trigger clock signals CKT1-CKT3 with different phases are used to make each circuit layer CL 1 ~CL 3 Signals are received and outputted in sequence according to one of the trigger clock signals CKT1 - CKT3 .

[0067] In one embodiment, the clock generating circuit 510 may include a plurality of flip-flops FF1 and FF2. The flip-flops FF1 and FF2 are connected in series to receive the trigger clock signal CKT1 and a reference clock signal CKR having a frequency higher than the trigger clock signal CKT1, so as to adjust the phase of the trigger clock signal CKT1 according to the reference clock signal CKR, and then generate the trigger clock signals CKT2 and CKT3.

[0068] In one embodiment, according to the required timing, the phase of the trigger clock signal CKT2 may be 90 degrees different from the phase of the trigger clock signal CKT1, and the phase of the trigger clock signal CKT3 may be 180 degrees different from the phase of the trigger clock signal CKT1. 1 ~CL 3 The storage circuit 500 in the embodiment can be selectively triggered by the positive edge or the negative edge of the clock signal to receive and output signals. 1 The storage circuit 500 can be triggered according to the negative edge of the trigger clock signal CKT1, and the circuit layer CL 2 The storage circuit 500 can be triggered according to the positive edge of the trigger clock signal CKT2, and the circuit layer CL 3 The storage circuit 500 can be triggered according to the negative edge of the trigger clock signal CKT3. However, the present invention is not limited thereto.

[0069] Another embodiment will be described below using a numerical example where M is 1 and N is 16. In this case, the analog-to-digital conversion circuit ADC 1 ~ADC 16 Divided into 1 conversion circuit group.

[0070] Please refer to Figure 6 . Figure 6 FIG. 4 is a block diagram of an output storage circuit 410 according to an embodiment of the present invention.

[0071] Corresponding to the above numerical example, Figure 6 The output storage circuit 410 includes two circuit layers CL 1 ~CL 2 A plurality of storage circuits 500.

[0072] For the first circuit layer CL 1 (S=1, equal to M), since there is no 0th circuit layer, the first circuit layer CL 1 Receive the digital output signal DOUT generated by the first conversion circuit group 1 ~DOUT 16 Therefore, the first circuit layer CL 1 The number of storage circuits 500 that can be configured is 16 to receive the digital output signal DOUT 1 ~DOUT 16 It should be noted that in order to keep the figure simple, Figure 6 Only one storage circuit 500 is shown and the corresponding number is indicated, but not all of them are shown.

[0073] For the second circuit layer CL 2 (S=2, greater than M), the second circuit layer CL 2 Then receive the first circuit layer CL 1 The digital output signal DOUT is transmitted 1 ~DOUT 16 Therefore, the second circuit layer CL 2 The number of storage circuits 500 that can be configured is 16 to receive DOUT 1 ~DOUT 16 It should be noted that in order to keep the figure simple, Figure 6 Only one storage circuit 500 is shown and the corresponding number is indicated, but not all of them are shown.

[0074] The post-processing circuit 420 starts from the last circuit layer CL 2 Get 16 digital output signals DOUT 1 ~DOUT 16 to be processed.

[0075] Therefore, in the above example, the circuit layer CL 1 In fact, the digital output signal DOUT 7 ~DOUT 16 For storage, the circuit layer CL 2 It can be optionally set to add additional timing.

[0076] In this embodiment, the circuit layer CL 1 And the circuit layer CL 2 The trigger clock signal CKT1 and the trigger clock signal CKT2 with different phases are directly received respectively without additionally setting a clock generating circuit.

[0077] It should be noted that the numbers of the above conversion circuit groups and circuit layers are only examples. In different embodiments, the numbers of the conversion circuit groups and circuit layers may vary depending on the requirements. The present invention is not limited thereto.

[0078] Please refer to Figure 7 . Figure 7 A flow chart of an analog-to-digital conversion method 700 according to an embodiment of the present invention is shown.

[0079] In addition to the aforementioned apparatus, the present invention further discloses an analog-to-digital conversion method 700 with a data storage mechanism, which is applied to, for example, but not limited to Figure 1 In the analog-to-digital conversion device 100. An embodiment of the analog-to-digital conversion method 700 is as follows: Figure 7 As shown, the following steps are included.

[0080] In step S710, the capacitor array circuit 150 included in the conversion circuit 120 included in the analog-to-digital conversion circuit 110 receives a pair of analog input voltages Vin and Vip in a sampling phase of a conversion procedure, and performs a capacitor switching operation in a conversion phase of the conversion procedure to generate a pair of analog output voltages Von and Vop.

[0081] In step S720, the comparison circuit 160 included in the conversion circuit 120 generates a plurality of comparison results B in sequence according to the pair of analog output voltages Von and Vop during the conversion phase. Q ~B 1 .

[0082] In step S730, the capacitor control circuit 170 included in the conversion circuit 120 is enabled to sequentially control the capacitors according to the comparison result B in the conversion phase. Q ~B 1 The capacitor array circuit 150 is controlled to perform capacitor switching operation via a successive approximation register mechanism.

[0083] In step S740, the comparison result storage circuit 130 included in the analog-to-digital conversion circuit 110 stores the comparison result BQ ~B 1 .

[0084] In step S750, the correction circuit 140 included in the analog-to-digital conversion circuit 110 obtains the comparison result B from the comparison result storage circuit 130. Q ~B 1 , and then perform digital error correction according to multiple weights to generate a D R ~D 1 The digital output signal DOUT.

[0085] It should be noted that the above implementation is only an example. In other embodiments, those skilled in the art may make changes without departing from the spirit of the present invention.

[0086] In summary, the analog-to-digital conversion device and method with a data storage mechanism in the present invention can store the comparison results generated by the conversion circuit via the comparison result storage circuit, so that there is sufficient time for digital error correction, thereby allowing the analog-to-digital conversion device to operate at a high speed.

[0087] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Ordinary technicians in the field may change the technical features of the present application based on the explicit or implicit contents of the present application, and these changes may be included in the scope of patent protection sought by the present application. In other words, the scope of patent protection of the present application shall be based on the contents defined in the claims of the present application.

[0088] Description of Reference Numerals

[0089] 100:Analog-to-digital conversion device

[0090] 110:Analog-to-digital conversion circuit

[0091] 120:Conversion circuit

[0092] 130: Comparison result storage circuit

[0093] 140: Correction circuit

[0094] 150:Capacitor array circuit

[0095] 160: Comparison circuit

[0096] 170: Capacitor control circuit

[0097] 180: Sampling circuit

[0098] 190A, 190B: Capacitor array

[0099] 400: Analog-to-digital conversion device

[0100] 410: Output storage circuit

[0101] 420: Post-processing circuit

[0102] 500: storage circuit

[0103] 510: Clock generation circuit

[0104] 700: Analog-to-digital conversion method

[0105] S710~S750: Steps

[0106] ADC 1 ~ADC N :Analog-to-digital conversion circuit

[0107] B Q ~B 1 :Compare results

[0108] CK1: first clock signal

[0109] CK2, CK2 1 ~CK2 K : Second clock signal

[0110] CKR: reference clock signal

[0111] CKT1~CKT3: trigger clock signal

[0112] CL 1 ~CL 3 :Circuit Layer

[0113] C P ~C 1 :Bit Capacitor

[0114] D R ~D 1 :Bit

[0115] DOUT、DOUT 1 ~DOUT N :Digital output signal

[0116] FDOUT: Final digital output signal

[0117] FF1, FF2: Trigger

[0118] GND: Ground potential

[0119] PC1: Current clock cycle

[0120] PC2: next clock cycle

[0121] PD: Phase difference

[0122] S Q ~S1 : Storage Unit

[0123] TC1, TC2: conversion time

[0124] TS1, TS2: Sampling time

[0125] Vin, Vip: analog input voltage

[0126] Von, Vop: analog output voltage

[0127] VR: Voltage

Claims

1. An analog-to-digital conversion device with a data storage mechanism, comprising: At least one analog-to-digital conversion circuit comprising: The conversion circuit comprises: a capacitor array circuit configured to receive a pair of analog input voltages in response to a sampling phase of a conversion process and to perform a capacitor switching operation in response to a conversion phase of the conversion process to generate a pair of analog output voltages; a comparison circuit configured to sequentially generate a plurality of comparison results according to the pair of analog output voltages during the conversion phase; as well as A capacitance control circuit configured to control the capacitance array circuit to perform the capacitance switching operation in the conversion phase according to the plurality of comparison results in sequence via a successive approximation register mechanism; A comparison result storage circuit configured to store the plurality of comparison results; as well as The correction circuit is configured to obtain the plurality of comparison results from the comparison result storage circuit, and then perform digital error correction according to a plurality of weights to generate a digital output signal having a plurality of bits.

2. The analog-to-digital conversion device according to claim 1, wherein the conversion circuit operates according to multiple clock cycles of a first clock signal, each of the multiple clock cycles includes a sampling time and a conversion time after the sampling time, and the conversion circuit performs the sampling phase of the conversion program at the sampling time in a current clock cycle of the multiple clock cycles, and performs the conversion phase of the conversion program at the conversion time in the current clock cycle.

3. The analog-to-digital conversion device according to claim 2, wherein the correction circuit performs the digital error correction in the conversion process corresponding to the current clock cycle at a correction time after the current clock cycle.

4. The analog-to-digital conversion device according to claim 2, wherein the comparison result storage circuit operates according to a second clock signal, the second clock signal having the same frequency as the first clock signal and a different phase from the first clock signal, so that the comparison result storage circuit stores the multiple comparison results before the conversion time of each clock cycle of the multiple clock cycles ends according to the second clock signal.

5. The analog-to-digital conversion device according to claim 2, wherein the comparison result storage circuit operates according to a plurality of second clock signals, each of the plurality of second clock signals having the same frequency as the first clock signal and a different phase from the first clock signal, the phases of the plurality of second clock signals being different from each other; The multiple comparison results are divided into multiple comparison result groups, and the number of the multiple second clock signals corresponds to the number of the multiple comparison result groups, so that the comparison result storage circuit stores the multiple comparison result groups in sequence before the conversion time of each clock cycle of the multiple clock cycles ends according to the respective phases of the multiple second clock signals.

6. The analog-to-digital conversion device according to claim 1, wherein the comparison result storage circuit comprises a plurality of storage units, each of the plurality of storage units comprises a same number of at least one trigger, and the plurality of storage units respectively store the plurality of comparison results.

7. The analog-to-digital conversion device according to claim 1, wherein the number of the analog-to-digital conversion circuits is a positive integer N greater than 1, configured as a time-interleaved analog-to-digital conversion circuit, and the analog-to-digital conversion device further comprises: an output storage circuit configured to store the N digital output signals generated by the N analog-to-digital conversion circuits; and The post-processing circuit is configured to obtain the N digital output signals from the output storage circuit for processing to generate a final digital output signal.

8. The analog-to-digital conversion device according to claim 7, wherein the N analog-to-digital conversion circuits are divided into M conversion circuit groups, the output storage circuit comprises a plurality of storage circuits, and the plurality of storage circuits are divided into a plurality of circuit layers which are sequentially connected in series and the number of which is at least M; Wherein, when S is not greater than M, the Sth circuit layer of the plurality of circuit layers receives the digital output signal generated by the Sth conversion circuit group of the plurality of conversion circuit groups and receives the digital output signal transmitted by the (S-1)th circuit layer of the plurality of circuit layers for storage; When S is greater than M, the Sth circuit layer of the plurality of circuit layers receives the digital output signal transmitted by the (S-1)th circuit layer of the plurality of circuit layers for storage; And the post-processing circuit obtains N digital output signals from the last circuit layer of the multiple circuit layers for processing.

9. The analog-to-digital conversion device according to claim 8, wherein the output storage circuit further comprises a clock generating circuit, configured to provide a plurality of trigger clock signals with different phases to the plurality of circuit layers, so that each of the plurality of circuit layers receives and outputs signals in sequence according to one of the plurality of trigger clock signals.

10. An analog-to-digital conversion method with a data storage mechanism, applied to an analog-to-digital conversion device, comprising: The capacitor array circuit included in the conversion circuit of at least one analog-to-digital conversion circuit receives a pair of analog input voltages in response to a sampling phase of a conversion procedure, and performs a capacitor switching operation in response to a conversion phase of the conversion procedure to generate a pair of analog output voltages; causing a comparison circuit included in the conversion circuit to sequentially generate a plurality of comparison results according to the pair of analog output voltages during the conversion phase; The capacitor control circuit included in the conversion circuit controls the capacitor array circuit to perform the capacitor switching operation in sequence according to the plurality of comparison results via a successive approximation register mechanism during the conversion phase; enabling a comparison result storage circuit included in the at least one analog-to-digital conversion circuit to store the plurality of comparison results; as well as The correction circuit included in the at least one analog-to-digital conversion circuit is enabled to obtain the multiple comparison results from the comparison result storage circuit, and then perform digital error correction according to multiple weights to generate a digital output signal with multiple bits.

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