Signal amplitude detection circuit

Abstract

The invention provides a signal amplitude detection circuit, and belongs to the technical field of electronic circuits. The detection circuit comprises a first branch, a second branch and an OR gate module. The first branch comprises a first voltage comparison module, a first amplification circuit module and a first level conversion module which are connected in sequence; the second branch comprises a second voltage comparison module, a second amplification circuit module and a second level conversion module which are connected in sequence; the output end of the first level conversion module and the output end of the second level conversion module are connected together and are connected with the OR gate module. The first voltage comparison module is used for comparing a first difference value (subtracting a reverse input voltage from a positive input voltage) with a second difference value (subtracting a negative reference voltage from a positive reference voltage), and the second voltage comparison module is used for comparing the first difference value with a third difference value (subtracting the positive reference voltage from the negative reference voltage). Therefore, the gain of the voltage comparison module can be increased, the cascade stage number of the amplification circuit can be reduced, and circuit imbalance and power consumption are reduced.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a signal amplitude detection circuit. Background Art

[0002] In serial communication technology, the higher the data transmission rate, the greater the attenuation of the signal amplitude at the same transmission distance. Therefore, the lower the signal amplitude received by the receiving end, the easier it is to cause bit errors, resulting in a higher bit error rate. In order to ensure that the bit error rate of the signal received by the receiving end can be controlled at an appropriate level, it is often necessary to ensure the amplitude of the received signal. Therefore, it is necessary to set a signal amplitude detection circuit at the receiving end to detect the amplitude of the received signal.

[0003] The existing signal amplitude detection circuit set at the receiving end takes into account that the amplitude of the received signal is very small in some application scenarios, which makes signal detection difficult to implement. Therefore, it is necessary to set up many levels (at least 5 levels or more) of amplifier circuit cascades for signal amplification, but the multi-stage amplifier circuit cascade will cause imbalance and power consumption problems. Summary of the invention

[0004] The main purpose of the embodiment of the present application is to propose a signal amplitude detection circuit, which aims to increase the gain of the voltage comparison module by designing a first voltage comparison module and a second voltage comparison module in parallel, and allowing the first voltage comparison module to compare the first difference (positive input voltage minus reverse input voltage) with the second difference (positive reference voltage minus negative reference voltage), and allowing the second voltage comparison module to compare the first difference (positive input voltage minus reverse input voltage) with the third difference (negative reference voltage minus positive reference voltage), thereby reducing the number of cascaded amplifier circuits to reduce circuit offset and power consumption.

[0005] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application provides a signal amplitude detection circuit, which is applied to a receiving end of high-speed data communication and is used to detect the amplitude of an input signal, comprising a first branch, a second branch and an OR gate module;

[0006] The first branch includes a first voltage comparison module, a first amplifier circuit module and a first level conversion module connected in sequence; the second branch includes a second voltage comparison module, a second amplifier circuit module and a second level conversion module connected in sequence; the output end of the first level conversion module is connected to the output end of the second level conversion module and connected to the OR gate module together; wherein,

[0007] The first voltage comparison module is used to access a positive input voltage, a reverse input voltage, a positive reference voltage and a negative reference voltage, and the first voltage comparison module is used to compare the first difference with the second difference, and output a first positive phase output voltage and a first negative phase output voltage, wherein the first difference is the difference between the positive input voltage and the reverse input voltage, and the second difference is the difference between the positive reference voltage and the negative reference voltage;

[0008] The second voltage comparison module is used to connect a positive input voltage, a reverse input voltage, a positive reference voltage and a negative reference voltage. The second voltage comparison module is used to compare the first difference and the third difference, and output a second positive phase output voltage and a second negative phase output voltage, wherein the third difference is the difference between the negative reference voltage and the positive reference voltage.

[0009] In one embodiment of the present application, the first amplifying circuit module is used to amplify the output first positive phase output voltage and the first negative phase output voltage and output a first target positive phase output voltage and a first target negative phase output voltage;

[0010] The second amplifier circuit module is used to amplify the output second positive phase output voltage and the second negative phase output voltage and output a second target positive phase output voltage and a second target negative phase output voltage.

[0011] In one embodiment of the present application, the first level conversion module is used to convert the first target positive phase output voltage and the first target negative phase output voltage of the current mode logic into a first CMOS voltage;

[0012] The second level conversion module is used for converting the second target positive phase output voltage and the second target negative phase output voltage into a second CMOS voltage.

[0013] In one embodiment of the present application, the OR gate module is used to access the first CMOS voltage and the second CMOS voltage, and output a detection signal after performing OR gate logic processing.

[0014] In one embodiment of the present application, the first amplifier circuit module includes a plurality of first amplifier circuits connected in series, and the second amplifier circuit module includes a plurality of second amplifier circuits connected in series.

[0015] In one embodiment of the present application, the detection circuit also includes an offset calibration module, a first end of the offset calibration module is connected to the output end of the first first amplifier circuit in the first amplifier circuit module, a second end of the offset calibration module is connected to the output end of the first second amplifier circuit in the second amplifier circuit module, a third end of the offset calibration module is connected to the output end of the last first amplifier circuit in the first amplifier circuit module, and a fourth end of the offset calibration module is connected to the output end of the last second amplifier circuit in the second amplifier circuit module.

[0016] In one embodiment of the present application, the offset calibration module includes an offset voltage detection and quantization unit and a compensation calibration unit, a first end of the compensation calibration unit is connected to an output end of a first first amplifier circuit in the first amplifier circuit module and an output end of a first second amplifier circuit in the second amplifier circuit module, a second end of the compensation calibration unit is connected to a first end of the offset voltage detection and quantization unit, and a second end of the offset voltage detection and quantization unit is connected to an output end of a first amplifier circuit at the end of the first amplifier circuit module and an output end of a second amplifier circuit at the end of the second amplifier circuit module;

[0017] The offset voltage detection and quantization unit is used to detect the DC voltage of the output end of the first amplifier circuit at the end of the first amplifier circuit module and the output end of the second amplifier circuit at the end of the second amplifier circuit module to determine the offset voltage and quantify the offset voltage;

[0018] The compensation calibration unit is used for adjusting the current source according to the quantized offset voltage to offset the offset.

[0019] In one embodiment of the present application, the detection circuit also includes a logic output module, which is connected to the output end of the OR gate module. The logic output module is used to provide a detection time window, and output a first signal when it is detected in the detection time window that the detection signal output by the OR gate module is continuously greater than or equal to a set threshold.

[0020] In one embodiment of the present application, the logic output module is further configured to output a second signal when it is detected in the detection time window that there is a detection signal whose value is less than the set threshold value among the detection signals output by the OR gate module.

[0021] In one embodiment of the present application, the logic output module includes a counter unit and a D flip-flop unit, the first input end of the counter unit is connected to the output end of the OR gate module, the second input end of the counter unit is used to access the clock signal, the output end of the counter unit is connected to the first input end of the D flip-flop unit, the second input end of the D flip-flop unit is connected to the output end of the OR gate module, and the output end of the D flip-flop unit is used to output the first signal or the second signal.

[0022] The present application proposes a signal amplitude detection circuit, which is applied to the receiving end of high-speed data communication. The detection circuit includes a first branch, a second branch and an OR gate module. The first branch includes a first voltage comparison module, a first amplification circuit module and a first level conversion module connected in sequence; the second branch includes a second voltage comparison module, a second amplification circuit module and a second level conversion module connected in sequence; the output end of the first level conversion module is connected to the output end of the second level conversion module and connected to the OR gate module together. Among them, the first voltage comparison module is used to compare the size of the first difference (positive input voltage minus reverse input voltage) and the second difference (positive reference voltage minus negative reference voltage), and the second voltage comparison module is used to compare the size of the first difference (positive input voltage minus reverse input voltage) and the third difference (negative reference voltage minus positive reference voltage), so as to increase the gain of the voltage comparison module, and then reduce the number of cascaded amplification circuits to reduce circuit misalignment and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a signal transmission block diagram in high-speed circuit systems;

[0024] Figure 2 is a first block diagram of a signal amplitude detection circuit provided by an embodiment of the present application;

[0025] Figure 3 is a circuit diagram of a first voltage comparison module provided in an embodiment of the present application;

[0026] Figure 4 is a circuit diagram of a first amplifier circuit provided in an embodiment of the present application;

[0027] Figure 5 is a circuit diagram of a first level conversion module provided in an embodiment of the present application;

[0028] Figure 6 is a second block diagram of a signal amplitude detection circuit provided by an embodiment of the present application;

[0029] Figure 7 is a circuit diagram of an offset calibration module provided in an embodiment of the present application;

[0030] Figure 8is a third block diagram of a signal amplitude detection circuit provided by an embodiment of the present application;

[0031] Fig. 9 is a schematic diagram of the structure of an output logic module provided in an embodiment of the present application;

[0032] Fig.10 It is a schematic diagram of the case where the amplitude of the input signal is less than the detection threshold;

[0033] Fig.11 is a schematic diagram showing that the amplitude of the input signal is greater than the detection threshold. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0035] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0037] In the application of high-speed circuit systems, data transmission and reception are indispensable. Generally, the receiving circuit has requirements for the amplitude and electrical characteristics of the common mode point of the input data / clock, in order to meet the normal operation of the receiving circuit. Otherwise, the receiving end will recognize the wrong data / clock and generate corresponding bit errors while affecting the operation of other modules. Among them, most of the common mode points are generated inside the receiving end, which will not become a design bottleneck. However, the signal amplitude is basically determined by the front-end transmitter, and because the channel has a low-pass characteristic from the frequency domain perspective (determined by the hardware routing), this will cause the data / clock amplitude at the receiving end to be smaller than that at the transmitting end (such as Figure 1 In order to ensure that the receiving end can obtain stable data / clock that meets the electrical characteristics, the receiving end needs to set a detection circuit for detecting the amplitude of the high-speed data / clock to detect the amplitude of the received signal.

[0038] The existing signal amplitude detection circuit takes into account that the amplitude of the received signal is very small in some application scenarios, which makes signal detection difficult to implement. Therefore, it is necessary to set up a cascade of amplification circuits of many levels (at least 5 or more) to amplify the signal. The judgment basis for more than 5 levels is: the gain of each designed amplifier (i.e., amplifier circuit) is generally 2 times (6dB, which needs to take into account the deviation of process / power supply voltage / temperature), and the five-level amplification gain is 32 times. For example, the single-ended swing is 10mV and the differential swing is 20mV. After amplification, the single-ended swing is 320mV and the differential swing is 640mV. The specific voltage to be amplified needs to be determined according to the actual specification requirements. However, the cascade of multi-level amplifier circuits will cause offset and power consumption problems.

[0039] Based on this, an embodiment of the present application proposes a signal amplitude detection circuit, which aims to increase the gain of the voltage comparison module by designing a first voltage comparison module and a second voltage comparison module in parallel, and allowing the first voltage comparison module to compare the first difference (positive input voltage minus reverse input voltage) with the second difference (positive reference voltage minus negative reference voltage), and allowing the second voltage comparison module to compare the first difference (positive input voltage minus reverse input voltage) with the third difference (negative reference voltage minus positive reference voltage), thereby reducing the number of cascaded amplifier circuits to reduce circuit offset and power consumption.

[0040] Reference Figure 2 , Figure 2 1 is a first block diagram of a signal amplitude detection circuit provided in an embodiment of the present application. The detection circuit is arranged at a receiving end and is used to detect the amplitude of a signal received by the receiving end. Figure 2As shown, the detection circuit includes a first branch 10, a second branch 20 and an OR gate module 30. The first branch 10 includes a first voltage comparison module 110, a first amplifier circuit module 120 and a first level conversion module 130 connected in sequence. The second branch 20 includes a second voltage comparison module 210, a second amplifier circuit module 220 and a second level conversion module 230 connected in sequence. The output end of the first level conversion module 130 is connected to the output end of the second level conversion module 230 and connected to the OR gate module 30. The first voltage comparison module 110 is used to access the positive input voltage vi np, the reverse input voltage vi nn, the positive reference voltage vrefp and the negative reference voltage vrefn. The first voltage comparison module 110 is used to compare the size between the first difference (vi np-vi nn) and the second difference (vrefp-vrefn), and output the first positive phase output voltage vop_1 and the first negative phase output voltage von_1. The first difference is the difference between the positive input voltage vi np and the reverse input voltage vi nn (i.e., vi np-vi nn), and the second difference is the difference between the positive reference voltage vrefp and the negative reference voltage vrefn (i.e., vrefp-vrefn). The second voltage comparison module 210 is used to access the positive input voltage vi np, the reverse input voltage vi nn, the positive reference voltage vrefp and the negative reference voltage vrefp. The second voltage comparison module 210 is used to compare the first difference (vi np-vi nn) with the third difference (vrefn-vrefp), and output the second positive phase output voltage vop_2 and the second negative phase output voltage von_2, wherein the third difference is the difference between the negative reference voltage vrefn and the positive reference voltage vrefp.

[0041] In the embodiment of the present application, the first voltage comparison module 110 is used to compare the first difference (vi np-vi nn) with the second difference (vrefp-vrefn), and the second voltage comparison module 210 is used to compare the first difference (vi np-vi nn) with the third difference (vrefn-vrefp), that is, through two groups of voltage comparison modules, one group is used to compare whether vi np-vi nn is greater than vrefp-vrefn, and the other group is used to compare whether vi np-vi nn is less than vrefn-vrefp, so as to determine whether |vi np-vi nn| is greater than |vrefp-vrefn|. Among them, the differential mode gain (Ad) of each channel forms an equivalent gain multiplication after the output is superimposed. And the comparison of the reverse channel (Vi nn-Vi np) eliminates the signal swing limitation during unipolar amplification, so that the effective dynamic range of the input signal is expanded to twice the original structure, which can indirectly improve the gain accuracy. By symmetrically processing the same differential signal by two sets of voltage comparison modules (i.e., the first voltage comparison module 110 and the second voltage comparison module 210), common mode noise (such as power supply ripple, temperature drift) can be converted into a common mode signal, which cancels each other out when the output is superimposed, thereby improving the effective signal-to-noise ratio, which is equivalent to gain enhancement. As a result, the gain of the voltage comparison module can be effectively increased, and the number of subsequent amplifier circuit cascades can be reduced to reduce circuit offset and power consumption.

[0042] Reference Figure 3 , Figure 3 is a circuit diagram of a first voltage comparison module and a second voltage comparison module provided in an embodiment of the present application. Figure 3As shown, the first voltage comparison module 110 includes a first differential pair transistor structure, a second differential pair transistor structure, a first resistor R1, a second resistor R2 and a current source I. The first differential pair transistor structure includes a first transistor Q1 and a second transistor Q2, wherein the base of the first transistor Q1 is used to access the positive input voltage vi np, the emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2 and then connected to the current source I, and the current source I is grounded. The collector of the first transistor Q1 is connected to the collector of the second transistor Q2 and then connected to the first end of the first resistor R1, and the second end of the first resistor R1 is used to access the power supply voltage VDD. The base of the second transistor Q2 is used to access the negative reference voltage vrefn. Similarly, the second differential pair transistor structure includes a third transistor Q3 and a fourth transistor Q4, wherein the base of the third transistor Q3 is used to access the positive reference voltage vrefp, and the emitter of the third transistor Q3 is connected to the emitter of the fourth transistor Q4 and then connected to the current source I. The collector of the third transistor Q3 is connected to the collector of the fourth transistor Q4 and then connected to the first end of the second resistor R2. The second end of the second resistor R2 is used to access the power supply voltage VDD. The base of the fourth transistor Q4 is used to access the reverse input voltage vi nn. The second end of the first resistor R1 is also used to output the first negative phase output voltage von_1, and the second end of the second resistor R2 is also used to output the first positive phase output voltage vop_1.

[0043] It should be noted that the circuit structure of the second voltage comparison module 210 is the same as the circuit structure of the first voltage comparison module 110. Figure 3As shown, the second voltage comparison module 210 includes a first differential pair transistor structure, a second differential pair transistor structure, a first resistor R1, a second resistor R2 and a current source I. The first differential pair transistor structure includes a first transistor Q1 and a second transistor Q2, wherein the base of the first transistor Q1 is used to access the positive input voltage vi np, the emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2 and then connected to the current source I, and the current source I is grounded. The collector of the first transistor Q1 is connected to the collector of the second transistor Q2 and then connected to the first end of the first resistor R1, and the second end of the first resistor R1 is used to access the power supply voltage VDD. The base of the second transistor Q2 is used to access the positive reference voltage vrefp. Similarly, the second differential pair transistor structure includes a third transistor Q3 and a fourth transistor Q4, wherein the base of the third transistor Q3 is used to access the negative reference voltage vrefn, and the emitter of the third transistor Q3 is connected to the emitter of the fourth transistor Q4 and then connected to the current source I. The collector of the third transistor Q3 is connected to the collector of the fourth transistor Q4 and then connected to the first end of the second resistor R2. The second end of the second resistor R2 is used to access the power supply voltage VDD. The base of the fourth transistor Q4 is used to access the reverse input voltage vi nn. The second end of the first resistor R1 is also used to output the second negative phase output voltage von_2, and the second end of the second resistor R2 is also used to output the first positive phase output voltage vop_2.

[0044] In the embodiment of the present application, the emitter of the first transistor Q1, the emitter of the second transistor Q2, the emitter of the third transistor Q3 and the emitter of the fourth transistor Q4 are connected and biased by a common current source I. The differential pair structure is composed of two transistors working in opposite directions. The differential pair structure utilizes the common mode suppression capability of the two transistors so that the output signal can still remain stable when there is common mode interference in the input signal. That is, the differential pair structure can effectively resist the influence of noise and interference signals by realizing differential amplification and common mode suppression.

[0045] In the embodiment of the present application, the first amplifier circuit module 120 is used to amplify the output first positive phase output voltage vop_1 and the first negative phase output voltage von_1 and output the first target positive phase output voltage vop_1n and the first target negative phase output voltage von_1n. Similarly, the second amplifier circuit module 220 is used to amplify the output second positive phase output voltage vop_2 and the second negative phase output voltage von_2 and output the second target positive phase output voltage vop_2n and the second target negative phase output voltage von_2n. Among them, the first amplifier circuit module 120 and the second amplifier circuit module 220 can be used to amplify the differential signal and suppress the common mode interference. Specifically, the first amplifier circuit module 120 and the second amplifier circuit module 220 can decompose the two input signals into a differential mode component (effective signal) and a common mode component (noise or interference). The differential mode component can be amplified by the amplifier circuit gain, and the common mode component can be weakened by the circuit symmetry and negative feedback mechanism.

[0046] Reference Figure 2 , the first amplifier circuit module 120 includes a plurality of first amplifier circuits connected in series in sequence, and the second amplifier circuit module 220 includes a plurality of second amplifier circuits connected in series in sequence. In the embodiment of the present application, by designing the first voltage comparison module 120 and the second voltage comparison module 220 to be connected in parallel, and allowing the first voltage comparison module 120 to compare the first difference (positive input voltage minus reverse input voltage) with the second difference (positive reference voltage minus negative reference voltage), and allowing the second voltage comparison module 220 to compare the third difference (reverse input voltage minus positive input voltage) with the second difference (positive reference voltage minus negative reference voltage), the gain of the voltage comparison module can be increased, and the number of cascaded amplifier circuits in the amplifier circuit module can be reduced. Specifically, the amplifier circuits of at least 5 cascades in the amplifier circuit module can be reduced by 1-2 levels. For example, before the improvement, the amplifier circuit module is provided with 5 cascaded amplifier circuits, and after the improvement, the amplifier circuit module only needs to be provided with 3 cascaded amplifier circuits. Thus, the circuit offset and power consumption can be reduced. The amplifier circuit can be a fully differential amplifier.

[0047] Reference Figure 4 , Figure 4 is a circuit diagram of a first amplifier circuit provided in an embodiment of the present application. Figure 4As shown, the first amplifier circuit includes a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2 and a current source I. The base of the first transistor Q1 is used to access the first positive phase output voltage vop_1 output by the first voltage comparison module 110, and the base of the second transistor Q2 is used to access the first negative phase output voltage von_1 output by the first voltage comparison module. The emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2 and then connected to the current source I, and the current source I is grounded. The collector of the first transistor Q1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is used to connect the power supply voltage VDD. The collector of the second transistor Q2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is used to connect the power supply voltage VDD. The second end of the first resistor R1 is also used to output the amplified negative phase output voltage von_12, and the second end of the second resistor R2 is also used to output the amplified positive phase output voltage vop_12.

[0048] It should be noted that the circuit structure of the second amplifier circuit is the same as the circuit structure of the first amplifier circuit.

[0049] In the embodiment of the present application, the first level conversion module 130 is used to convert the first target positive phase output voltage vop_1n and the first target negative phase output voltage von_1n of the current mode logic into a first CMOS voltage. Similarly, the second level conversion module 230 is used to convert the second target positive phase output voltage vop_2n and the second target negative phase output voltage von_2n into a second CMOS voltage. Among them, the first level conversion module 130 may include a transport amplifier and a level shift circuit. An operational amplifier is used to receive the differential signal (including the first target positive phase output voltage vop_1n and the first target negative phase output voltage von_1n) output after amplification by the first amplification circuit module 120. Since the output swing of the current mode logic (CML) is small (usually several hundred mV), it needs to be amplified to the CMOS logic level (such as 0V to 3.3V or 5V) by a high gain operational amplifier. The gain of the operational amplifier needs to be adjusted according to the CMOS input threshold to ensure that the output covers the full swing. The unit gain bandwidth of the operational amplifier needs to be higher than the highest frequency of the signal to avoid distortion. For example, if the CML signal frequency is 100MHz, the op amp bandwidth should be greater than this value, and closed-loop stability should be considered to avoid oscillation caused by insufficient phase margin. CMOS levels are usually referenced to ground, while CML differential signals may contain common-mode voltages. The common-mode voltage needs to be adjusted to the CMOS input range through a level shifting circuit, and the common-mode noise needs to be suppressed. This can be achieved by using a resistor divider or a dedicated level conversion IC.

[0050] In some embodiments, a CMOS buffer (such as an inverter chain) may be added after the operational amplifier to enhance the driving capability and shape the output waveform to ensure that the rise / fall time meets the CMOS interface requirements.

[0051] Reference Figure 5 , Figure 5 is a circuit diagram of a first level conversion module provided in an embodiment of the present application. Figure 5 As shown, the first level conversion module 130 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8 and a current source I. The base of the first transistor Q1 is connected to the base of the second transistor Q2, the base of the first transistor Q1 is also connected to the collector of the first transistor Q1, and the emitter of the first transistor Q1 is grounded. The collector of the first transistor Q1 is connected to the collector of the third transistor Q3, the base of the third transistor Q3 is connected to the base of the fourth transistor Q4, the base of the fourth transistor Q4 is connected to the collector of the fourth transistor Q4 and then connected to the collector of the fifth transistor Q5, the base of the fifth transistor Q5 is used to access the first target positive phase output voltage vop_1n, the emitter of the fifth transistor Q5 is connected to the emitter of the sixth transistor Q6 and then connected to the current source I, and the current source I is grounded. The base of the sixth transistor Q6 is used to access the first target negative phase output voltage von_1n, the collector of the sixth transistor Q6 is connected to the collector of the seventh transistor Q7, the base of the seventh transistor Q7 is connected to the collector of the seventh transistor Q7, the base of the seventh transistor Q7 is also connected to the base of the eighth transistor Q8, the collector of the eighth transistor Q8 is connected to the collector of the second transistor Q2, and the emitter of the second transistor Q2 is grounded. The emitter of the third transistor Q3, the emitter of the fourth transistor Q4, the emitter of the seventh transistor Q7 and the emitter of the eighth transistor Q8 are connected and connected to the power supply voltage VDD together. The collector of the second transistor Q2 and the collector of the eighth transistor Q8 are used to output the first CMOS voltage.

[0052] It should be noted that the circuit structure of the second level conversion module 230 is the same as the circuit structure of the first level conversion module 130 .

[0053] In the embodiment of the present application, the OR gate module 30 is used to access the first CMOS voltage and the second CMOS voltage, and output the detection signal SI G_SET after performing OR gate logic processing. Among them, the processing logic of the OR gate module is: as long as one of the input terminals is at a high level (logic "1"), the output terminal is at a high level (logic "1"); only when all the input terminals are at a low level (logic "0"), the output terminal is at a low level (logic "0"). In other words, as long as one of the first CMOS voltage and the second CMOS voltage is at a high level, the output detection signal is at a high level (logic "1"), and when the first CMOS voltage and the second CMOS voltage are both at a low level, the output detection signal is at a low level (logic "0").

[0054] In some embodiments, reference Figure 6 , Figure 6 is a second block diagram of a signal amplitude detection circuit provided in an embodiment of the present application. The detection circuit is arranged at a receiving end and is used to detect the amplitude of a signal received by the receiving end. Figure 6 As shown, the detection circuit includes a first branch 10, a second branch 20, an OR gate module 30 and an offset calibration module 40. The first branch 10 includes a first voltage comparison module 110, a first amplifier circuit module 120 and a first level conversion module 130 connected in sequence. The second branch 20 includes a second voltage comparison module 210, a second amplifier circuit module 220 and a second level conversion module 230 connected in sequence. The output end of the first level conversion module 130 is connected to the output end of the second level conversion module 230 and connected to the OR gate module 30. The first amplifier circuit module 120 includes a plurality of first amplifier circuits connected in series in sequence, and the second amplifier circuit module includes a plurality of second amplifier circuits connected in series in sequence. A first end of the offset calibration module 40 is connected to an output end of the first first amplifier circuit in the first amplifier circuit module 120, a second end of the offset calibration module 40 is connected to an output end of the first second amplifier circuit in the second amplifier circuit module 220, a third end of the offset calibration module 40 is connected to an output end of the last first amplifier circuit in the first amplifier circuit module 120, and a fourth end of the offset calibration module 40 is connected to an output end of the last second amplifier circuit in the second amplifier circuit module 220.

[0055] The first voltage comparison module 110 is used to access the positive input voltage vi np, the reverse input voltage vi nn, the positive reference voltage vrefp and the negative reference voltage vrefn. The first voltage comparison module 110 is used to compare the first difference (vi np-vi nn) with the second difference (vrefp-vrefn), and output the first positive phase output voltage vop_1 and the first negative phase output voltage von_1. The first difference is the difference between the positive input voltage vi np and the reverse input voltage vi nn, and the second difference is the difference between the positive reference voltage vrefp and the negative reference voltage vrefn. The second voltage comparison module 210 is used to access the positive input voltage vi np, the reverse input voltage vi nn, the positive reference voltage vrefp and the negative reference voltage vrefp. The second voltage comparison module 210 is used to compare the first difference (vi np-vi nn) with the third difference (vrefn-vrefp), and output the second positive phase output voltage vop_2 and the second negative phase output voltage von_2, wherein the third difference is the difference between the negative reference voltage vrefn and the positive reference voltage vrefp.

[0056] The offset calibration module 40 can optimize the signal accuracy by detecting the offset error and dynamically compensating it based on a closed-loop feedback adjustment mechanism. Figure 7 , Figure 7: is a circuit diagram of an offset calibration module provided in an embodiment of the present application. The offset calibration module 40 may include an offset voltage detection and quantization unit 41 and a compensation calibration unit 42. The first end of the compensation calibration unit 42 is connected to the output end of the first first amplifier circuit in the first amplifier circuit module 120 and the output end of the first second amplifier circuit in the second amplifier circuit module 220. The second end of the compensation calibration unit 42 is connected to the first end of the offset voltage detection and quantization unit 41, and the second end of the offset voltage detection and quantization unit 41 is connected to the output end of the first amplifier circuit at the end of the first amplifier circuit module 120 and the output end of the second amplifier circuit at the end of the second amplifier circuit module 220. Among them, the offset voltage detection and quantization unit 41 is used to detect the DC voltage of the output end of the first amplifier circuit at the end of the first amplifier circuit module 120 and the output end of the second amplifier circuit at the end of the second amplifier circuit module 220 to determine the offset voltage and quantify the offset voltage. The compensation calibration unit 42 is used to adjust the current source according to the quantized offset voltage to offset the offset. Specifically, the offset voltage detection and quantization unit 41 can input a fixed common-mode voltage to the differential input terminal in the calibration mode, forcing the output terminal to present a theoretical balance state. The voltage difference of the differential output terminal is monitored in real time by a comparator to quantify the deviation between the actual output and the ideal value. The compensation calibration unit 42 can be used to inject a compensation current into the differential branch through a calibration current generation module when an input offset voltage is detected, and adjust the transistor operating point to offset the initial mismatch. And a digital control code is generated according to the comparison result by a logic unit to drive the DAC to output the corresponding analog adjustment signal to form a closed-loop negative feedback. Then, by adjusting the current ratio of the differential branch mirror current source and changing the transconductance parameter of the input pair tube, the offset voltage can be fine-tuned. Therefore, the influence of the offset change caused by temperature drift can be avoided by continuous calibration of the offset calibration module.

[0057] In the embodiment of the present application, it is considered that the first amplifier circuit module 120 is composed of a plurality of first amplifier circuits in cascade, and the second amplifier circuit module 220 is composed of a plurality of second amplifier circuits in cascade. The offset voltage of each amplifier circuit will produce deviations at the output end. When cascaded, these deviations will be amplified by the subsequent amplifier, resulting in a cumulative effect. That is, the input offset voltage of each amplifier circuit itself will be amplified step by step with the gain and superimposed at the output end. The offset voltage of the pre-stage amplifier circuit will be regarded as a valid input signal by the post-stage amplifier for secondary amplification, resulting in a significant increase in the overall system offset. At the same time, the transistor threshold voltage, transconductance and other parameters of the input stage of each amplifier circuit will drift with temperature changes. The temperature environment of each amplifier circuit in the cascade system may be different, resulting in the superposition of temperature drift errors between multiple stages. In this regard, the embodiment of the present application proposes an offset calibration module, which can continuously calibrate the offset generated in the first amplifier circuit module 120 and the second amplifier circuit module 220, thereby effectively reducing the offset in the circuit.

[0058] In some embodiments, reference Figure 8 , Figure 8 is a third block diagram of a signal amplitude detection circuit provided in an embodiment of the present application. The detection circuit is arranged at a receiving end and is used to detect the amplitude of a signal received by the receiving end. Figure 8 As shown, the detection circuit includes a first branch 10, a second branch 20, an OR gate module 30, an offset calibration module 40 and a logic output module 50. The first branch 10 includes a first voltage comparison module 110, a first amplifier circuit module 120 and a first level conversion module 130 connected in sequence. The second branch 20 includes a second voltage comparison module 210, a second amplifier circuit module 220 and a second level conversion module 230 connected in sequence. The output end of the first level conversion module 130 is connected to the output end of the second level conversion module 230 and connected to the OR gate module 30. The first amplifier circuit module 120 includes a plurality of first amplifier circuits connected in series in sequence, and the second amplifier circuit module includes a plurality of second amplifier circuits connected in series in sequence. The first end of the offset calibration module 40 is connected to the output end of the first first amplifier circuit in the first amplifier circuit module 120, the second end of the offset calibration module 40 is connected to the output end of the first second amplifier circuit in the second amplifier circuit module 220, the third end of the offset calibration module 40 is connected to the output end of the last first amplifier circuit in the first amplifier circuit module 120, and the fourth end of the offset calibration module 40 is connected to the output end of the last second amplifier circuit in the second amplifier circuit module 220. The logic output module 50 is connected to the output end of the OR gate module 40, and the logic output module 50 is used to provide a detection time window, and when it is detected in the detection time window that the detection signal SIG_SET output by the OR gate module 40 is continuously greater than or equal to the set threshold, the logic output module 50 outputs the first signal SIG; when it is detected in the detection time window that there is a detection signal less than the set threshold in the detection signal SIG_SET output by the OR gate module 40, the logic output module 50 outputs the second signal SIG.

[0059] Specifically, refer to Fig. 9 , Fig. 9 is a schematic diagram of the structure of an output logic module provided in an embodiment of the present application. Fig. 9As shown, the output logic module 50 includes a counter unit 51 and a D flip-flop unit 52. Among them, the first input end of the counter unit 51 is connected to the output end of the OR gate module 40, the second input end of the counter unit 51 is used to access the clock signal CKI N, the output end of the counter unit 51 is connected to the first input end of the D flip-flop unit 52, the second input end of the D flip-flop unit 52 is connected to the output end of the OR gate module 40, and the output end of the D flip-flop unit 52 is used to output the first signal or the second signal. In the embodiment of the present application, in the detection time window T, only when the amplitude of the data / clock is continuously greater than the preset detection threshold in the detection time window T, the overall circuit will output a signal that a signal exists to the analog / digital circuit, and perform the next step of operation. In the detection time window T, as long as there is a data / clock amplitude less than the detection threshold, the output signal will become a signal. The output signal indicates that the amplitude of the signal received at the receiving end is unqualified, which may cause the subsequent circuit to be unable to normally identify the lower value of the signal, and it is necessary to guide the subsequent circuit to perform corresponding processing.

[0060] In the embodiment of the present application, by setting the output logic module 50, the signal amplitude is required to continuously exceed the threshold value within the continuous detection time window T, which can filter out pulse noise or short-term interference and avoid false triggering of subsequent circuits; at the same time, continuous detection rather than single sampling can ensure that the signal state transition only occurs under stable conditions, avoiding logical errors caused by metastable states.

[0061] In the embodiment of the present application, the gain of the voltage comparison module can be increased by designing the first voltage comparison module and the second voltage comparison module to be connected in parallel, and the first voltage comparison module is allowed to compare the first difference (positive input voltage minus reverse input voltage) with the second difference (positive reference voltage minus negative reference voltage), and the second voltage comparison module is allowed to compare the first difference (positive input voltage minus reverse input voltage) with the third difference (negative reference voltage minus positive reference voltage). When the amplitude of the input data / clock is less than the detection threshold, the output result is as follows: Fig.10 As shown, the output has no intersection and the |vop-von| difference (differential output signal) is increased by 2-3 times or even more. When the amplitude of the input data / clock is greater than the detection threshold, the output result is as follows Fig.11 As shown, the output has an intersection and the |vop-von| difference is increased by 2-3 times or more. At the same time, as the amplitude of the input data / clock increases, the overlap of the output differential signal will also increase. As the gain of the voltage comparison module is improved, the number of amplifier circuits in the current-mode amplifier circuit module required by the subsequent stage will be reduced by 1-2 levels, and reducing the number of levels will reduce the impact on the offset on the signal chain.

[0062] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A signal amplitude detection circuit, applied to a receiving end of high-speed data communication, for detecting the amplitude of an input signal, characterized in that: It includes a first branch, a second branch and an OR gate module; The first branch includes a first voltage comparison module, a first amplifier circuit module and a first level conversion module connected in sequence; the second branch includes a second voltage comparison module, a second amplifier circuit module and a second level conversion module connected in sequence; the output end of the first level conversion module is connected to the output end of the second level conversion module and connected to the OR gate module together; wherein, The first voltage comparison module is used to access a positive input voltage, a reverse input voltage, a positive reference voltage and a negative reference voltage, and the first voltage comparison module is used to compare the first difference with the second difference, and output a first positive phase output voltage and a first negative phase output voltage, wherein the first difference is the difference between the positive input voltage and the reverse input voltage, and the second difference is the difference between the positive reference voltage and the negative reference voltage; The second voltage comparison module is used to connect a positive input voltage, a reverse input voltage, a positive reference voltage and a negative reference voltage. The second voltage comparison module is used to compare the first difference and the third difference, and output a second positive phase output voltage and a second negative phase output voltage, wherein the third difference is the difference between the negative reference voltage and the positive reference voltage.

2. The detection circuit according to claim 1, characterized in that: The first amplifying circuit module is used to amplify the outputted first positive phase output voltage and the first negative phase output voltage and output a first target positive phase output voltage and a first target negative phase output voltage; The second amplifier circuit module is used to amplify the output second positive phase output voltage and the second negative phase output voltage and output a second target positive phase output voltage and a second target negative phase output voltage.

3. The detection circuit according to claim 2, characterized in that: The first level conversion module is used to convert the first target positive phase output voltage and the first target negative phase output voltage of the current mode logic into a first CMOS voltage; The second level conversion module is used for converting the second target positive phase output voltage and the second target negative phase output voltage into a second CMOS voltage.

4. The detection circuit according to claim 3, characterized in that: The OR gate module is used to access the first CMOS voltage and the second CMOS voltage, and output a detection signal after performing OR gate logic processing.

5. The detection circuit according to claim 1, characterized in that: The first amplifier circuit module includes a plurality of first amplifier circuits connected in series in sequence, and the second amplifier circuit module includes a plurality of second amplifier circuits connected in series in sequence.

6. The detection circuit according to claim 5, characterized in that: The detection circuit also includes an offset calibration module, a first end of the offset calibration module is connected to the output end of the first first amplifier circuit in the first amplifier circuit module, a second end of the offset calibration module is connected to the output end of the first second amplifier circuit in the second amplifier circuit module, a third end of the offset calibration module is connected to the output end of the last first amplifier circuit in the first amplifier circuit module, and a fourth end of the offset calibration module is connected to the output end of the last second amplifier circuit in the second amplifier circuit module.

7. The detection circuit according to claim 6, characterized in that: The offset calibration module comprises an offset voltage detection and quantization unit and a compensation calibration unit, wherein a first end of the compensation calibration unit is connected to an output end of a first first amplifier circuit in the first amplifier circuit module and an output end of a first second amplifier circuit in the second amplifier circuit module, a second end of the compensation calibration unit is connected to a first end of the offset voltage detection and quantization unit, and a second end of the offset voltage detection and quantization unit is connected to an output end of a first amplifier circuit at the end of the first amplifier circuit module and an output end of a second amplifier circuit at the end of the second amplifier circuit module; The offset voltage detection and quantization unit is used to detect the DC voltage of the output end of the first amplifier circuit at the end of the first amplifier circuit module and the output end of the second amplifier circuit at the end of the second amplifier circuit module to determine the offset voltage and quantify the offset voltage; The compensation calibration unit is used for adjusting the current source according to the quantized offset voltage to offset the offset.

8. The detection circuit according to claim 1, characterized in that: The detection circuit also includes a logic output module, which is connected to the output end of the OR gate module. The logic output module is used to provide a detection time window, and output a first signal when it is detected in the detection time window that the detection signal output by the OR gate module is continuously greater than or equal to a set threshold.

9. The detection circuit according to claim 8, characterized in that: The logic output module is further configured to output a second signal when it is detected in the detection time window that there is a detection signal whose value is less than the set threshold value among the detection signals output by the OR gate module.

10. The detection circuit according to claim 8 or 9, characterized in that: The logic output module includes a counter unit and a D flip-flop unit, the first input end of the counter unit is connected to the output end of the OR gate module, the second input end of the counter unit is used to access the clock signal, the output end of the counter unit is connected to the first input end of the D flip-flop unit, the second input end of the D flip-flop unit is connected to the output end of the OR gate module, and the output end of the D flip-flop unit is used to output the first signal or the second signal.

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