GFP frame searching method based on 10G Ethernet system
By splicing data into multiple data branches in the GFP module of the 10G Ethernet system, and independently performing descrambling code and CRC-16 calculations, the problem of high logic levels and difficult to meet timing in the traditional method is solved, and the logic level optimization and timing satisfaction are achieved.
Patent Information
- Application Number
- CN202510288151.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-12
- Publication Date
- 2025-06-06
AI Technical Summary
In the process of searching frames in the 10G Ethernet system, the traditional GFP module has a high logic level and is difficult to meet the timing requirements.
By splicing the data into 4 data branches, descrambling code, CRC-16 calculation and single-bit error correction are performed during independent calculations, a bit error indication signal is generated, and the core frame head position is judged in conjunction with PLI_Cnt.
It effectively reduces the logical level of critical paths, controls them within 5 levels, completes timing optimization, and meets the frame search requirements of 10G Ethernet systems.
Smart Images
Figure CN120110604A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of GFP frame search, and in particular relates to a GFP frame search method based on a 10G Ethernet system. Background Art
[0002] The general purpose framing process (GFP) needs to perform frame search during the frame receiving process, that is, to determine the frame by searching for the position of the core frame header. The core frame header has a bit width of 32 bits, consisting of a 16-bit payload length indication (PLI) and a 16-bit core frame header check code (cHEC), where cHEC is the cyclic redundancy check (CRC) result of the PLI. There are three frame search states in the frame search process, namely, the frame search state (HUNT), the pre-synchronization state (PRESYN), and the synchronization state (SYN). The initial state is the search state. When the correct core frame header is searched, the pre-synchronization state is entered. In the pre-synchronization state, the correct core frame header is continuously searched to enter the synchronization state. In the synchronization state, if the correct core frame header is not detected at the position of the core frame header, the frame search state is immediately returned to the synchronization state.
[0003] In the traditional GFP module, the data width corresponding to one clock cycle (beat) is 8 bits. In the frame search process of the GFP module of the 10G Ethernet system, since the system clock of 344.16MHz is used to collect data, the data width corresponding to one beat is 32 bits. In this environment, since the data length of each frame is not fixed to an integer multiple of 4, there must be a situation where the first byte of the core frame header is not the highest byte in one beat. Therefore, in this case, the data of the two adjacent beats received must be spliced in three ways. Therefore, in one beat, the CRC of four situations needs to be calculated to determine the position of the core frame header. At this time, if the traditional method is used to perform descrambling in the feedback loop, the CRC calculation and single-bit error correction process are placed in the state machine to form a feedback loop to control the state machine jump. The logic level will reach more than 7 levels and it is difficult to optimize, and the timing cannot meet the requirements. Summary of the invention
[0004] The purpose of the present invention is to provide a GFP frame search method based on a 10G Ethernet system to solve the problem that the traditional method proposed in the above background technology performs descrambling, CRC calculation and single-bit error correction in a feedback loop, has a high logic level and is difficult to meet timing requirements.
[0005] To achieve the above object, the present invention provides the following technical solution: a GFP frame search method based on a 10G Ethernet system, comprising the following steps:
[0006] Step 1: Splice and reorganize the data into 4 data branches. The specific splicing method is as follows: Figure 3As shown in the figure, since the first byte of the core frame header appears in any byte of the 4 bytes in a beat, it is necessary to splice the data of the two adjacent beats of the received data GFP_Dat. The method of splicing data is to delay the received data by one beat, and then splice the received data and the data delayed by one beat in the same beat according to Figure 3 The way to splice according to the situation:
[0007] ①: The first byte of the core frame header appears at [31:24].
[0008] ②: The first byte of the core frame header appears at [23:16].
[0009] ③: The first byte of the core frame header appears at [15:8].
[0010] ④: The first byte of the core frame header appears at [7:0].
[0011] Figure 3 The first line of data is the received data, and the second line of data is the data delayed by one beat. The bytes of the received data circled in red and the data circled in black are concatenated into new 32-bit data at the current beat, with the red part located at the high byte and the black part located at the low byte.
[0012] Step 2: Frame header descrambling: The bit width of the spliced and reorganized data in one beat is still 32 bits. The data of each beat is XORed with 32'hB6AB31E0 for descrambling operation; the spliced data is XORed with 32'hB6AB31E0 to obtain 4 groups of CRC_Dat_i for CRC-16 calculation. The polynomial used for calculation is x 16 +x 12 +x 5 +1; 4 sets of core header error check (cHEC) bit error indication signals Err_St are generated based on the 4 sets of CRC-16 calculation results CRC_Dat_o. Err_St has the following three values:
[0013] ① If the calculation result of CRC-16 is 0, Err_St is set to 2'b00, indicating that the cHEC matches the payload length indication (PLI) and there is no bit error;
[0014] ② If the calculation result of CRC-16 is the same as the value in the single-bit error table, Err_St is set to 2'b01, indicating that there is a single-bit error in cHEC or PLI. It is only necessary to correct the single-bit error in PLI in the SYN state;
[0015] ③ If the calculation result of CRC-16 is not 0 and is different from the value in the single-bit error table, Err_St is set to 2'b10, indicating that the cHEC and PLI do not match and there are multi-bit errors;
[0016] The above calculation process is independent of the state machine. The state machine only needs to judge whether there is a bit error in the core frame header according to the Err_St signal and PLI_Cnt to complete the state jump.
[0017] Step 3: The 32-bit data of each beat after descrambling is searched for the position of the core frame header by performing CRC-16 calculation. The calculation result of CRC-16 and the data for which CRC-16 calculation is performed are in the same beat, that is, each beat has a CRC-16 calculation result corresponding to the current beat data;
[0018] Step 4: Lookup table for error correction: The CRC-16 calculation result of the correct core frame header is 0. When a bit in the 32 bits of the correct core frame header is flipped, that is, a single-bit error occurs, the corresponding CRC-16 will get a fixed value;
[0019] Step 5: Synchronize the correct PLI value or the PLI value after table lookup and correction to the PLI counter. If the value of the PLI counter is greater than or equal to 4, the value of the PLI counter is reduced by 4 after the beat.
[0020] Step 6: Determine the core frame header position;
[0021] Step 7: Repeat the above steps.
[0022] As a preferred technical solution in the present invention, in step three, when the CRC-16 calculation result of the data spliced together with the 16-bit data and the CRC-16 calculation result of the data is calculated again, the CRC-16 calculation result should be 0; therefore, when the CRC-16 check result of the 32-bit data is 0, it means that the current beat may be the position of the core frame header, and a check matching mark is generated in the current beat. The specific situation needs to be judged together with the PLI counter; if the CRC-16 check result is not 0, it means that the current beat is not the position of the core frame header.
[0023] As a preferred technical solution in the present invention, in step 4, there are 32 fixed values corresponding to 32 single-bit errors in the CRC-16 calculation result; the single-bit error in the core frame header needs to be corrected in the synchronous state.
[0024] As a preferred technical solution in the present invention, in the frame search process of step four, when the CRC-16 calculation result corresponds to the 32 values, it means that there may be a single-bit error in the core frame header in the current beat, or it may be the check value of data other than the core frame header. A single-bit error mark is generated in the current beat. The specific situation needs to be judged together with the PLI counter. If the current beat is the position of the core frame header and is in a synchronous state, the single-bit error in the current beat needs to be corrected.
[0025] As a preferred technical solution of the present invention, in step six, if the value of the current beat PLI counter is less than 4, it is detected whether there is a check match mark or a single-bit error mark;
[0026] HUNT: Frame search state. Single-bit error correction is disabled in this state. When the state machine detects that cHEC matches PLI, it jumps to the pre-synchronization state.
[0027] PRESYN: Pre-synchronization state. This state does not enable the single-bit error correction function; the value of PLI detected in the HUNT state is synchronized to PLI_Cnt as the initial value, and the position of the core frame header of the next frame is determined by the value of PLI_cnt. At the position of the core frame header, the Err_St signal is used to determine whether the cHEC matches the PLI. If they match, the Delta counter is incremented by 1. If they do not match, the state machine jumps back to the HUNT state to search for a new core frame header again. When Delta correct core frame headers are detected continuously, the state machine jumps to the SYN state. In this state, it is not the position of the core frame header, and even if Err_St indicates that the cHEC matches the PLI, it will be ignored.
[0028] SYN: Synchronous state. This state turns on the single-bit error correction function; the core frame header search process after synchronization is as follows:
[0029] ① The value of PLI detected in the previous frame is used as the initial value of PLI_Cnt.
[0030] ② If the value of PLI is 0, it means that the detected data is idle frame data, and it is necessary to determine whether the cHEC in the next 4 consecutive bytes matches the PLI based on Err_St.
[0031] ③ If the value of PLI is not 0, except for the first beat PLI_Cnt of the current frame, which needs to determine the value to be subtracted based on the position of the first byte of the core frame header, PLI_Cnt needs to subtract 4 bytes after each beat until the value of PLI_Cnt is less than 4.
[0032] ④ When the value of PLI_Cnt is less than 4, it means that all or part of the bytes of the core frame header exist in the current beat. According to the Err_St generated by the 4 CRC-16 calculators, if the values of the 4 Err_St in the current beat all indicate multi-bit errors, the state machine jumps back to the HUNT state; if there is Err_St indicating a single-bit error, it is only necessary to correct the single-bit error in the PLI and synchronize the corrected PLI value to PLI_Cnt, and the state machine remains in the SYN state; if there is Err_St indicating that cHEC matches PLI, the state machine remains in the SYN state.
[0033] ⑤ When PLI_Cnt is greater than 4, even if Err_St indicates a single-bit error or no bit error exists, it will be ignored.
[0034] As a preferred technical solution in the present invention, in step six, if the PLI counter value is less than 4 in the synchronization state, if there is no check match mark or single-bit error mark in the current beat, the frame search state jumps to the search state.
[0035] As a preferred technical solution in the present invention, in step six, if the PLI counter value is less than 4 in the pre-synchronization state, the frame search state immediately jumps to the search state as long as there is no check match mark in the current beat.
[0036] Compared with the prior art, the present invention has the following beneficial effects:
[0037] In the present invention, the descrambling code, CRC calculation and single-bit error correction process are moved out of the feedback loop and calculated separately to generate a bit error indication signal, which is coordinated with PLI_Cnt to determine whether the core frame header matches to perform frame search, effectively reducing the logic level of the critical path, controlling the logic level within 5 levels, and completing timing optimization. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 This is a functional block diagram of the traditional GFP core frame header search;
[0039] Figure 2 This is a functional block diagram of the GFP frame search function of the present invention;
[0040] Figure 3 This is the method for splicing two adjacent beat data of the present invention. DETAILED DESCRIPTION
[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0042] See also Figures 1 to 3 The present invention provides a technical solution: a GFP frame search method based on a 10G Ethernet system, comprising the following steps:
[0043] Step 1: Splice and reorganize the data into 4 data branches. The specific splicing method is as follows: Figure 3 As shown in the figure, since the first byte of the core frame header appears in any byte of the 4 bytes in a beat, it is necessary to splice the data of the two adjacent beats of the received data GFP_Dat. The method of splicing data is to delay the received data by one beat, and then splice the received data and the data delayed by one beat in the same beat according to Figure 3 The way to splice according to the situation:
[0044] ①: The first byte of the core frame header appears at [31:24].
[0045] ②: The first byte of the core frame header appears at [23:16].
[0046] ③: The first byte of the core frame header appears at [15:8].
[0047] ④: The first byte of the core frame header appears at [7:0].
[0048] Figure 3 The first line of data is the received data, and the second line of data is the data delayed by one beat. The bytes of the received data circled in red and the data circled in black are concatenated into new 32-bit data at the current beat, with the red part located at the high byte and the black part located at the low byte.
[0049] Step 2: Frame header descrambling: The bit width of the spliced and reorganized data in one beat is still 32 bits. The data of each beat is XORed with 32'hB6AB31E0 for descrambling operation; the spliced data is XORed with 32'hB6AB31E0 to obtain 4 groups of CRC_Dat_i for CRC-16 calculation. The polynomial used for calculation is x 16 +x 12 +x 5+1; 4 sets of core header error check (cHEC) bit error indication signals Err_St are generated based on the 4 sets of CRC-16 calculation results CRC_Dat_o. Err_St has the following three values:
[0050] ① If the calculation result of CRC-16 is 0, Err_St is set to 2'b00, indicating that the cHEC matches the payload length indication (PLI) and there is no bit error;
[0051] ② If the calculation result of CRC-16 is the same as the value in the single-bit error table, Err_St is set to 2'b01, indicating that there is a single-bit error in cHEC or PLI. It is only necessary to correct the single-bit error in PLI in the SYN state;
[0052] ③ If the calculation result of CRC-16 is not 0 and is different from the value in the single-bit error table, Err_St is set to 2'b10, indicating that the cHEC and PLI do not match and there are multi-bit errors;
[0053] The above calculation process is independent of the state machine. The state machine only needs to judge whether there is a bit error in the core frame header according to the Err_St signal and PLI_Cnt to complete the state jump.
[0054] Step 3: The 32-bit data of each beat after descrambling is searched for the position of the core frame header by performing CRC-16 calculation. The calculation result of CRC-16 and the data for which CRC-16 calculation is performed are in the same beat, that is, each beat has a CRC-16 calculation result corresponding to the current beat data;
[0055] Step 4: Lookup table for error correction: The CRC-16 calculation result of the correct core frame header is 0. When a bit in the 32 bits of the correct core frame header is flipped, that is, a single-bit error occurs, the corresponding CRC-16 will get a fixed value;
[0056] Step 5: Synchronize the correct PLI value or the PLI value after table lookup and correction to the PLI counter. If the value of the PLI counter is greater than or equal to 4, the value of the PLI counter is reduced by 4 after the beat.
[0057] Step 6: Determine the core frame header position;
[0058] Step 7: Repeat the above steps.
[0059] In this embodiment, in step three, when the CRC-16 calculation result of the data spliced together with the 16-bit data and the CRC-16 calculation result of the data is calculated again, the CRC-16 calculation result should be 0; therefore, if the CRC-16 check result of the 32-bit data is 0, it means that the current beat may be the position of the core frame header, and a check match mark is generated in the current beat. The specific situation needs to be judged together with the PLI counter; if the CRC-16 check result is not 0, it means that the current beat is not the position of the core frame header.
[0060] In this embodiment, in step 4, there are 32 fixed values in the CRC-16 calculation result corresponding to 32 single-bit errors; in the synchronous state, the single-bit error in the core frame header needs to be corrected.
[0061] In this embodiment, during the frame search process in step four, when the CRC-16 calculation result corresponds to the 32 values, it means that there may be a single-bit error in the core frame header in the current beat, or it may be the check value of data other than the core frame header. A single-bit error mark is generated in the current beat. The specific situation needs to be judged together with the PLI counter. If the current beat is at the position of the core frame header and is in a synchronous state, the single-bit error in the current beat needs to be corrected.
[0062] In this embodiment, in step six, if the value of the current beat PLI counter is less than 4, it is detected whether there is a check match mark or a single-bit error mark;
[0063] HUNT: Frame search state. Single-bit error correction is disabled in this state. When the state machine detects that cHEC matches PLI, it jumps to the pre-synchronization state.
[0064] PRESYN: Pre-synchronization state. This state does not enable the single-bit error correction function; the value of PLI detected in the HUNT state is synchronized to PLI_Cnt as the initial value, and the position of the core frame header of the next frame is determined by the value of PLI_cnt. At the position of the core frame header, the Err_St signal is used to determine whether the cHEC matches the PLI. If they match, the Delta counter is incremented by 1. If they do not match, the state machine jumps back to the HUNT state to search for a new core frame header again. When Delta correct core frame headers are detected continuously, the state machine jumps to the SYN state. In this state, it is not the position of the core frame header, and even if Err_St indicates that the cHEC matches the PLI, it will be ignored.
[0065] SYN: Synchronous state. This state turns on the single-bit error correction function; the core frame header search process after synchronization is as follows:
[0066] ① The value of PLI detected in the previous frame is used as the initial value of PLI_Cnt.
[0067] ② If the value of PLI is 0, it means that the detected data is idle frame data, and it is necessary to determine whether the cHEC in the next 4 consecutive bytes matches the PLI based on Err_St.
[0068] ③ If the value of PLI is not 0, except for the first beat PLI_Cnt of the current frame, which needs to determine the value to be subtracted based on the position of the first byte of the core frame header, PLI_Cnt needs to subtract 4 bytes after each beat until the value of PLI_Cnt is less than 4.
[0069] ④ When the value of PLI_Cnt is less than 4, it means that all or part of the bytes of the core frame header exist in the current beat. According to the Err_St generated by the 4 CRC-16 calculators, if the values of the 4 Err_St in the current beat all indicate multi-bit errors, the state machine jumps back to the HUNT state; if there is Err_St indicating a single-bit error, it is only necessary to correct the single-bit error in the PLI and synchronize the corrected PLI value to PLI_Cnt, and the state machine remains in the SYN state; if there is Err_St indicating that cHEC matches PLI, the state machine remains in the SYN state.
[0070] ⑤ When PLI_Cnt is greater than 4, even if Err_St indicates a single-bit error or no bit error exists, it will be ignored.
[0071] In this embodiment, in step six, in the synchronization state, if the PLI counter value is less than 4, and if there is no check match mark or single-bit error mark in the current beat, the frame search state jumps to the search state.
[0072] In this embodiment, in step six, if the PLI counter value is less than 4 in the pre-synchronization state, the frame search state immediately jumps to the search state as long as there is no check match mark in the current beat.
[0073] exist Figure 1 In the data bit width corresponding to one beat, 8 bits are used. Due to the low clock frequency, descrambling, CRC-16 calculation, single-bit error correction and the state machine form a feedback loop to search frames and still meet the timing requirements. The error indication signal after the table lookup error correction controls whether the state machine is in the synchronous state.
[0074] Although embodiments of the present invention have been shown and described (see the above detailed description for details), it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.
Claims
1. A GFP frame search method based on a 10G Ethernet system, characterized in that: The following steps are involved: Step 1: Splice and reorganize the data into 4 data branches; Step 2: Frame header descrambling: The bit width of the spliced and reorganized data in one beat is still 32 bits. The data of each beat is XORed with 32'hB6AB31E0 to perform descrambling operation; Step 3: The 32-bit data of each beat after descrambling is searched for the position of the core frame header by performing CRC-16 calculation. The calculation result of CRC-16 and the data for which CRC-16 calculation is performed are in the same beat, that is, each beat has a CRC-16 calculation result corresponding to the current beat data; Step 4: Lookup table for error correction: The CRC-16 calculation result of the correct core frame header is 0. When a bit in the 32 bits of the correct core frame header is flipped, that is, a single-bit error occurs, the corresponding CRC-16 will get a fixed value; Step 5: Synchronize the correct PLI value or the PLI value after table lookup and correction to the PLI counter. If the value of the PLI counter is greater than or equal to 4, the value of the PLI counter is reduced by 4 after the beat. Step 6: Determine the core frame header position; Step 7: Repeat the above steps.
2. A GFP frame search method based on a 10G Ethernet system according to claim 1, characterized in that: In step 3, when the CRC-16 calculation result of the data spliced together with the 16-bit data and the CRC-16 calculation result of the data is calculated again, the result should be 0; therefore, when the CRC-16 check result of the 32-bit data is 0, it means that the current beat may be the position of the core frame header, and a check match mark is generated in the current beat; If the CRC-16 check result is not 0, it means that the current beat is not the position of the core frame header.
3. A GFP frame search method based on a 10G Ethernet system according to claim 1, characterized in that: In step 4, there are 32 fixed values corresponding to 32 single-bit errors in the CRC-16 calculation result; in the synchronous state, the single-bit error in the core frame header needs to be corrected.
4. A GFP frame search method based on a 10G Ethernet system according to claim 3, characterized in that: During the frame search process of step four, when the CRC-16 calculation result corresponds to the 32 values, it means that there may be a single-bit error in the core frame header in the current beat, or it may be the check value of data other than the core frame header. A single-bit error mark is generated in the current beat. If the current beat is at the position of the core frame header and is in a synchronous state, the single-bit error in the current beat needs to be corrected.
5. A GFP frame search method based on a 10G Ethernet system according to claim 1, characterized in that: In step six, if the value of the current beat PLI counter is less than 4, it is detected whether there is a check match mark or a single-bit error mark.
6. A GFP frame search method based on a 10G Ethernet system according to claim 5, characterized in that: In step six, in the synchronization state, if the PLI counter value is less than 4, and if there is no check match mark or single-bit error mark in the current beat, the frame search state jumps to the search state.
7. A GFP frame search method based on a 10G Ethernet system according to claim 5, characterized in that: In step six, in the pre-synchronization state, if the PLI counter value is less than 4, the frame search state immediately jumps to the search state as long as there is no check match mark in the current beat.