Algorithm function management method and device, storage medium and program product

Abstract

The embodiment of the invention provides an algorithm function management method and device, a storage medium and a program product, relates to the technical field of communication, and can manage algorithm functions to reduce power consumption. The method is applied to a first node, and comprises the following steps: sending request information to the first node, the request information being used for indicating responses to a plurality of algorithm functions; and receiving indication information sent by the first node, wherein the indication information is used for indicating the second node to respond to at least two algorithm functions in the plurality of algorithm functions in parallel. And responding to the plurality of algorithm functions based on the indication information.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a method, device, storage medium and program product for managing algorithm functions. Background Art

[0002] In recent years, with the development of communication technology, the combination of mobile communication systems and artificial intelligence (AI) / machine learning (ML) is an inevitable trend in the future to improve the operating efficiency of mobile communication systems. For example, the reference signal overhead can be reduced through the inference and prediction of AI / ML algorithm functions, the channel state information feedback overhead can be reduced, or the terminal positioning accuracy can be improved.

[0003] However, the algorithm functions of AI / ML will improve the performance and efficiency of mobile communication systems, but they also have to pay the price of the algorithm functions’ own power consumption, which in turn increases power consumption. Therefore, how to manage the algorithm functions to reduce power consumption has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments of the present disclosure provide a method, device, storage medium, and program product for managing algorithm functions, which can manage algorithm functions to reduce power consumption.

[0005] In one aspect, a method for managing algorithm functions is provided, the method being applied to a first node, comprising: receiving request information sent by a second node, the request information being used to indicate a response to a plurality of algorithm functions; and sending indication information to the second node, the indication information being used to indicate that the second node responds to at least two of the plurality of algorithm functions in parallel.

[0006] In another aspect, a method for managing algorithm functions is provided, the method being applied to a second node, comprising: sending request information to a first node, the request information being used to indicate a response to a plurality of algorithm functions; receiving indication information sent by the first node, the indication information being used to indicate that the second node should respond to at least two of the plurality of algorithm functions in parallel; and responding to the plurality of algorithm functions based on the indication information.

[0007] On the other hand, a management device for algorithm functions is provided, which is applied to a first node. The device includes: a receiving module and a sending module.

[0008] The receiving module is used to receive request information sent by the second node, the request information is used to indicate the response to the multiple algorithm functions. The sending module is used to send indication information to the second node, the indication information is used to indicate that the second node responds to at least two of the multiple algorithm functions in parallel.

[0009] On the other hand, a device for managing algorithm functions is provided, which is applied to a second node. The device includes: a sending module, a receiving module and a processing module.

[0010] The sending module is used to send request information to the first node, where the request information is used to indicate a response to the multiple algorithm functions. The receiving module is used to receive indication information sent by the first node, where the indication information is used to indicate that the second node responds to at least two of the multiple algorithm functions in parallel. The processing module is used to respond to the multiple algorithm functions based on the indication information.

[0011] In another aspect, a device for managing algorithm functions is provided, comprising: a memory and a processor. The memory and the processor are coupled. The memory is used to store a computer program. When the processor executes the computer program, the method for managing the algorithm functions of any of the above embodiments is implemented.

[0012] On the other hand, a computer-readable storage medium is provided, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, a management method for the algorithm function of any of the above embodiments is implemented.

[0013] On the other hand, a computer program product is provided, which includes computer program instructions, and when the computer program instructions are executed, the management method of the algorithm function of any of the above embodiments is implemented.

[0014] The disclosed embodiment discloses that by managing the response timing of multiple algorithm functions, some algorithm functions are integrated together for centralized response, thereby reducing the power consumption of the dispersed responses to multiple algorithm functions. In this way, the management efficiency of the algorithm functions can be improved and the energy consumption can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and a person skilled in the art can also obtain other drawings based on these drawings.

[0016] Figure 1 A schematic diagram of a model framework provided for some embodiments of the present disclosure;

[0017] Figure 2 A schematic diagram of a communication system provided for some embodiments of the present disclosure;

[0018] Figure 3 A flowchart of a method for managing algorithm functions provided in some embodiments of the present disclosure;

[0019] Figure 4An example schematic diagram of response power consumption and response time of an algorithm function provided in some embodiments of the present disclosure;

[0020] Figure 5 A flowchart of another algorithm function management method provided in some embodiments of the present disclosure;

[0021] Figure 6 A flowchart of another algorithm function management method provided in some embodiments of the present disclosure;

[0022] Figure 7 An example schematic diagram of a data structure provided for some embodiments of the present disclosure;

[0023] Figure 8 An example schematic diagram of another data structure provided for some embodiments of the present disclosure;

[0024] Fig. 9 A schematic diagram of a flow chart of algorithm function management based on computing power space provided in some embodiments of the present disclosure;

[0025] Fig.10 A schematic diagram of a flow chart of algorithm function management based on power space provided in some embodiments of the present disclosure;

[0026] Fig.11 A schematic diagram of a flow chart of algorithm function management through algorithm transfer provided in some embodiments of the present disclosure;

[0027] Fig.12 A schematic diagram of a process for managing algorithm functions based on hyperparameter configuration provided in some embodiments of the present disclosure;

[0028] Fig.13 Another flowchart of algorithm function management through algorithm transfer provided for some embodiments of the present disclosure;

[0029] Fig.14 A schematic diagram of an example of model prediction provided in some embodiments of the present disclosure;

[0030] Fig.15 A schematic diagram of an example of model training provided in some embodiments of the present disclosure;

[0031] Fig.16 A schematic diagram of a power space prediction process provided for some embodiments of the present disclosure;

[0032] Fig.17 A schematic diagram of a process of computing power space prediction provided for some embodiments of the present disclosure;

[0033] Fig.18An example schematic diagram of a response sequence of a computing power management function provided by some embodiments of the present disclosure;

[0034] Fig.19 A schematic diagram of a management device for an algorithm function provided in some embodiments of the present disclosure Figure 1 ;

[0035] Fig. 20 A schematic diagram of a management device for an algorithm function provided in some embodiments of the present disclosure Figure 2 ;

[0036] Fig.21 A schematic diagram of a management device for an algorithm function provided in some embodiments of the present disclosure Figure 3 . DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the present disclosure to clearly and completely describe the technical solutions in the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0038] It should be noted that, in the present disclosure, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present disclosure should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0039] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0040] In the description of the present disclosure, unless otherwise specified, " / " means "or", for example, A / B can mean A or B. "And / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, "at least one" means one or more, and "a plurality" means two or more.

[0041] Artificial intelligence (AI) includes machine learning (ML), deep learning, reinforcement learning, transfer learning, deep reinforcement learning, meta-learning and other devices, components, software and modules with self-learning capabilities.

[0042] In some cases, artificial intelligence can be implemented through an artificial intelligence network (or neural network), which includes multiple layers, each layer includes at least one node, typically, the neural network includes an input layer, an output layer, and at least one hidden layer, wherein each layer of the neural network includes but is not limited to the use of at least one of a fully connected layer, a dense layer, a convolutional layer, a transposed convolutional layer, a direct connection layer, an activation function, a normalization layer, a pooling layer, etc.

[0043] In other cases, each layer of the neural network may include a sub-neural network, such as a residual network block / resnet block, a dense network (densenet block), a recurrent neural network (RNN), etc. The artificial intelligence network includes a neural network model and / or neural network parameters corresponding to the neural network model, wherein the neural network model can be referred to as a network model, and the neural network parameters can be referred to as network parameters. A network model defines the network architecture such as the number of layers of the neural network, the size of each layer, the activation function, the connection status, the convolution kernel and the size convolution step, the convolution type (such as 1D convolution, 2D convolution, 3D convolution, hollow convolution, transposed convolution, separable convolution, grouped convolution, extended convolution, etc.), and the network parameters are the weights and / or biases of each layer of the network in the network model and their values. A network model can correspond to multiple sets of different neural network parameter values ​​to adapt to different scenarios. The values ​​of the network parameters can be obtained by offline training and / or online training, such as by inputting at least one sample and label, and training the neural network model to obtain the neural network parameters. A neural network model can correspond to multiple different neural network parameter values.

[0044] AI / ML is a promising enhancement direction for mobile communication systems. Introducing AI / ML technology into mobile communication systems, such as the fifth generation mobile communication technology (5G), the future fifth generation mobile communication technology (5G-A), and the sixth generation mobile communication technology (6G), can improve the operating efficiency of the system, such as reducing the reference signal overhead, reducing the channel state information feedback overhead, or improving the accuracy of terminal positioning through AI / ML reasoning and prediction. Its benefits have been preliminarily verified or are being verified.

[0045] For communication systems using AI / ML technology, in all parts of this disclosure, the narrow definition of AI / ML model is: a mathematical algorithm that applies machine learning techniques to generate a set of outputs based on a set of inputs. It can include metadata, which includes relevant information about the training model and the applicable operating environment. AI / ML models can be managed, stored, and transmitted as artifacts, which may be containers, images, or proprietary file formats.

[0046] Broadly defined AI / ML "model" is a general term used to describe a device's ability to perform a processing method, function, feature, or feature group. A "model" can be a function, functional module, processing method, information processing method, implementation method, functional group, configuration, configuration set, data set (e.g., for model training), or data-driven algorithm, etc.

[0047] In all parts of this disclosure, algorithms, functions, algorithm functions, or functional algorithms may be used to describe models, algorithms, functions, algorithm functions, or functional algorithms. Unless otherwise specified, their connotations and meanings are the same.

[0048] In all parts of this disclosure, when AI and ML are described separately, AI and ML can be used interchangeably. AI / ML is equivalent to AI and ML used separately.

[0049] It should be noted that the basic AI / ML framework used in communication systems can be as follows Figure 1 As shown, including:

[0050] 1. Data collection (functional module): Provides input data for model training, management, and reasoning functions. The input data required for AI / ML model training functions is training data. The input data required for managing AI / ML models or AI / ML functions is monitoring data. The input data required for AI / ML reasoning functions is reasoning data. The collected monitoring data may be label data that provides a calibration-like function and is sent to the model management functional module for comparison with the reasoning output to output the corresponding decision or management command.

[0051] 2. Model training (functional module): performs AI / ML model training, verification, and testing. Model training trains the ML model by learning the input / output relationship in a data-driven manner and obtains the trained ML model for reasoning.

[0052] 3. Model management (functional module) can perform the following functions:

[0053] (1) Indicates operations related to AI / ML models, such as model selection / activation / deactivation / switching / rollback, etc.

[0054] (2) Monitor model performance.

[0055] (3) Make decisions or instructions to ensure correct reasoning operations based on data received from the data collection function and the reasoning function.

[0056] (4) This functional module is also responsible for requesting the model from the model storage function for model transmission / delivery requests.

[0057] (5) Input performance feedback / retraining request to the model training function module for model (re)training or updating.

[0058] 4. Model inference (functional module): The process of taking the data provided by the data collection function as input and running the input through the trained machine learning model to produce a set of outputs. The inference output is the final output of the entire AI / ML model or function, which can include decisions or predictions or statistics or recommendations. It is used for other units in the mobile system. The output data can also be input to the management function module for internal monitoring of the performance of the AI / ML model or AI / ML function.

[0059] 5. Model storage (functional module) is a function responsible for storing trained / updated models that can be used to perform inference functions.

[0060] All functions involved in the model mentioned in the above AI / ML framework belong to the processing process. Unless otherwise specified, the processing processes mentioned in the subsequent instructions can be implemented in the form of models.

[0061] In the field of mobile communications, the introduction of AI / ML models and the training, reasoning and model-related functions of the models will inevitably bring new energy costs. The hardware based on AI, such as the central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), etc., requires an astonishing amount of energy to process a large number of calculations. For example, the thermal design power (TDP) of the NVIDIA H100 GPU (an accelerator for AI and deep learning) is about 700 watts. When processing large models, the number of GPUs required is extremely large, which will bring huge energy costs. Therefore, considering energy saving in communication systems is a very challenging problem. When the AI ​​model is in a mobile communication terminal, due to the limited battery capacity of the mobile communication terminal, energy-saving control is required for the operation of the AI ​​model in the terminal to maintain the terminal battery life for as long as possible.

[0062] In summary, AI models will improve the performance and efficiency of mobile communication systems, but this will also come at the cost of the AI ​​model's own power consumption. It is necessary to strike a balance between the power consumption cost and the improvement of mobile communication performance. In other words, how to manage algorithm functions to reduce power consumption has become a technical problem that needs to be solved urgently.

[0063] It should be noted that the factors affecting the energy consumption of conventional AI models mainly depend on the following aspects:

[0064] 1. Model size and complexity.

[0065] Number of parameters: The more parameters a model has, the more complex it is, and usually requires more computing resources to process. Large models such as Transformer (a model architecture for processing sequence data) and BERT (a pre-trained model based on Transformer) consume a lot of power due to their huge number of parameters and deep network structure.

[0066] Depth: The depth of a neural network directly affects the learning ability and computational requirements of the model. The more layers there are, the more forward and backward propagation calculations are required, and the correspondingly higher energy consumption.

[0067] Structure: The more complex the structure of a neural network, the higher the corresponding energy consumption.

[0068] 2. Training algorithm.

[0069] Optimization algorithm: The optimization algorithm used (such as adaptive moment estimation (Adam), stochastic gradient descent (SGD)) affects the convergence speed and stability, and indirectly affects the energy consumption of the training process. Some algorithms may require more iterations to converge, increasing the overall energy consumption.

[0070] 3. Configuration of model hyper parameters.

[0071] The model's hyperparameter configuration will also greatly affect the power consumption of the AI ​​model. Possible hyperparameters involved are:

[0072] Batch size: The batch size during training affects the utilization and memory requirements of processing units such as GPUs. Larger batches can improve the efficiency of parallel processing, but may also increase memory pressure and energy consumption.

[0073] Number of shards: Model inference and training tasks are divided into a large number of hardware processing units. Since communication between hardware processing units also consumes power, the more shards there are, the higher the additional power consumption.

[0074] Complexity of generated results: The more complex the generated results are, the more power will be consumed. Taking the natural language model as an example, the longer the generated token (the smallest unit in a text sequence) is, the more power will be consumed.

[0075] 4. Number of training times and iterations.

[0076] Number of epochs: The more epochs a model is trained in, the more total computation required to complete the training, and the higher the energy consumption.

[0077] 5. Hardware efficiency.

[0078] Processor type: The type of hardware used (such as CPU, GPU, NPU, tensor processing unit (TPU) etc.) greatly affects energy efficiency. GPUs are generally more energy efficient than CPUs when processing large-scale matrix calculations in parallel.

[0079] Hardware utilization: Insufficient utilization of hardware resources will lead to energy waste. Optimizing hardware utilization can reduce energy consumption when idle. Taking the GPU as an example, hardware utilization mainly refers to the number of compute unified device architecture (CUDA) cores inside the GPU and the utilization of video memory. Since the baseline static power of the GPU always exists, when the utilization cannot be fully loaded, the baseline static power overhead will increase. Therefore, the more fully utilized the GPU is, the higher the power efficiency will be in theory.

[0080] 6. Power limitation.

[0081] Theory and experiments have proven that for AI / ML training and reasoning, appropriately limiting the power ceiling of the hardware for model training and reasoning and extending the training and reasoning time can achieve a balance point in power consumption.

[0082] 7. Model deployment and inference.

[0083] Quantization: By quantizing the model, floating-point parameters are converted to low-precision formats (such as int8), which can reduce the model size and energy consumption at runtime.

[0084] Pruning: Removing redundant connections in the network (weight pruning) can reduce model complexity and energy consumption during the inference phase.

[0085] Distillation: By training a smaller model (the student model) to mimic the behavior of a larger model (the teacher model), energy consumption during inference can be reduced without significantly reducing accuracy.

[0086] 8. Software and tool optimization.

[0087] Software framework: The software framework used to implement the model (such as TensorFlow (an open source software library), PyTorch (an open source machine learning library)) also affects the operating efficiency and energy consumption. Different frameworks may differ in memory management and computational optimization.

[0088] Compiler optimization: Advanced compiler optimization techniques, such as graph optimization and operation fusion, can improve runtime efficiency and reduce energy consumption.

[0089] Based on this, in order to solve the above technical problems, the embodiments of the present disclosure provide a method for managing algorithm functions, which is applied to energy-saving management scenarios in AI / ML model training, reasoning and other processes. By managing the response timing of multiple algorithm functions, some algorithm functions are integrated together for centralized response, reducing the power consumption of decentralized responses to multiple algorithm functions. In this way, the management efficiency of algorithm functions can be improved and energy consumption can be reduced.

[0090] The network architecture of the mobile communication network (including but not limited to 2G, 3G, 4G, 5G and future mobile communication networks (such as the future evolution of the fifth generation mobile communication technology (5th generation mobile communication technology advanced, 5G-A), the sixth generation mobile communication technology (6th generation mobile communication technology, 6G)) in the disclosed embodiment may include at least a first communication node and a second communication node. It should be understood that in this example, the first communication node may be a network (network, NW) side device (for example, including but not limited to a base station), and the second communication node may be a terminal side device (for example, including but not limited to a terminal). In the device-to-device communication between the two communication nodes, the first communication node and the second communication node may both be a base station or a terminal. The first communication node and the second communication node may be referred to as the first node and the second node, respectively.

[0091] For example, Figure 2 FIG. 2 is a schematic diagram of a communication system provided by an embodiment of the present disclosure, and the communication system may include: a first node 201 and a second node 202. The second node 202 may be one or more, and the number is not limited.

[0092] The second node 202 may send request information for instructing to respond to the multiple algorithm functions based on the usage scenarios of the multiple algorithm functions to the first node 201. Then, the first node 201 may instruct the first node 201 to respond to at least two of the multiple algorithm functions in parallel based on the request information from the second node 202 to save energy consumption.

[0093] It should be noted that, in the embodiment of the present disclosure, the first node 201 may be a network-side device (such as a base station), and the second node 202 may be a user-side device (such as a terminal).

[0094] A base station (BS) can be a base station or evolutionary node B (eNB or eNodeB) in LTE, long term evolution advanced (LTEA), a base station device (gNB) in a 5G network, or a base station in a future communication system. The base station can include various macro base stations, micro base stations, home base stations, wireless remote stations, reconfigurable intelligent surfaces (RISs), routers, relay stations, transmission and reception points (TRP), receivers, access points, wireless fidelity (WIFI) devices and other network-side devices. A base station can sometimes also be called a reader / writer used to communicate with a terminal.

[0095] The terminal can be a device with wireless transceiver function. The terminal can be a mobile phone, a tablet computer, a computer with wireless transceiver function, a virtual reality (VR) terminal, an augmented reality (AR) terminal, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc. The embodiments of the present disclosure do not limit the application scenarios. The terminal can sometimes also be called a user, user equipment (UE), A-IoT device, access terminal, UE unit, UE station, mobile station, mobile station, remote station, transmitter, remote terminal, mobile device, UE terminal, wireless communication equipment, UE agent or UE device, etc., and the embodiments of the present disclosure do not limit this.

[0096] It should be noted that Figure 2 This is just an exemplary framework diagram. Figure 2 The number of devices included in the Figure 2 In addition to the devices shown, the communication system may also include other devices, such as core network devices.

[0097] The application scenarios of the embodiments of the present disclosure are not limited. The system architecture and business scenarios described in the embodiments of the present disclosure are intended to more clearly illustrate the technical solutions of the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions provided by the embodiments of the present disclosure. It is known to those skilled in the art that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided by the embodiments of the present disclosure are also applicable to similar technical problems.

[0098] Figure 3 A flowchart of a method for managing algorithm functions is shown, such as Figure 3 As shown, the management method of the algorithm function is applied to the first node, including:

[0099] S301: Receive request information sent by a second node.

[0100] The request information is used to indicate responses to multiple algorithm functions.

[0101] That is, the second node can request the first node to manage multiple algorithm functions in the second node by reporting request information to the first node, so as to meet the response requirements of the second node for multiple algorithm functions.

[0102] It should be noted that the multiple algorithm functions may be algorithm functions being responded to in the second node, or the multiple algorithm functions may be algorithm functions to be responded to in the second node.

[0103] That is to say, the response phases of the multiple algorithm functions being managed are described, that is, the multiple algorithm functions may be managed at the first response, or may be managed during the response process.

[0104] As a possible implementation manner, the request information may include available resource information of the second node.

[0105] That is to say, the second node can provide a reference for the first node's management of multiple algorithm functions in the second node by reporting the availability (or idleness) of its own resources to the first node, so as to ensure the accuracy of the second node's response to multiple algorithm functions.

[0106] In an embodiment of the present disclosure, the available resource information in the request information may include: available computing power information and / or available power information.

[0107] The available computing power information may include: an available computing power value and / or an available duration of the available computing power value.

[0108] That is to say, the second node can report its own idle computing power value and the effective duration of the idle computing power value to the first node (that is, the second node has a corresponding idle computing power value within the effective duration, and the idle computing power value of the second node will change outside the effective duration) to provide a reference for the first node to manage multiple algorithm functions in the second node, so as to ensure that the responses of multiple algorithm functions can match the availability of the second node's own computing power.

[0109] Similarly, the available power information may include: an available power value and / or an available duration of the available power value.

[0110] It should be noted that the available resource information may be real-time information of the second node at the current moment, or the available resource information may be predicted information of the second node at a future moment.

[0111] That is, when managing the responses to multiple algorithm functions, not only real-time management can be performed based on currently available resources in the node, but also pre-management can be performed based on future available resources in the node.

[0112] Optionally, when the available resource information is the predicted information of the second node at a future time, the available resource information may be predicted by the second node and reported to the first node. Alternatively, the available resource information may be predicted by the first node based on the resource information reported by the second node in the past.

[0113] In which, when the available resource information is predicted by the second node, the first node can send prediction auxiliary control information (including predicted future time period, predicted resource type (such as available computing power and / or available power), etc.) to the second node, so that the second node predicts the available resource information in response to the prediction auxiliary control information from the first node.

[0114] S302: Send indication information to the second node.

[0115] The indication information is used to instruct the second node to respond in parallel to at least two algorithm functions among the multiple algorithm functions.

[0116] In other words, by managing the response timing of multiple algorithm functions, some algorithm functions are integrated together for centralized response, reducing the power consumption of decentralized responses to multiple algorithm functions. In this way, the management efficiency of algorithm functions can be improved and energy consumption can be reduced.

[0117] In the embodiment of the present disclosure, the indication information may include time information for responding to each algorithm function, and the time information may include at least one of the following: time period, start time, duration, and time threshold.

[0118] Exemplarily, the typical configurations of the execution cycle (i.e., time cycle) of the algorithm function, the execution time starting point (i.e., start time), and the execution duration (i.e., duration) are specifically described as follows.

[0119] The time period is generally expressed by a period number, such as milliseconds (ms), and the commonly used unit is a time slot or a subframe or an integer multiple of a frame. The configuration time period is used to describe the repetition time interval.

[0120] The start time is usually one or more time offsets relative to the system frame number (SFN) or to an alternative reference point. It is used to specify the first triggering moment of a periodic event. When a more granular start time is required, the symbol start position parameter is also added.

[0121] Duration describes the duration of an operation or execution.

[0122] To improve power efficiency, it is required to compress the execution of one or more algorithm functions into a shorter time segment (i.e., algorithm-time domain resource allocation) and make full use of hardware resources. To maintain sufficient configuration flexibility, the network-side device (i.e., the first node) configures one or more sets of periodic parameters (such as integer form). The parameter set (sequence) needs to contain the identifier (id) of one or more algorithm functions, period (period), start time (slot offset, starting symbol, etc.), duration (duration), as shown in the following parameter structure:

[0123]

[0124] The parameters in the parameter structure can also be expressed jointly. For example, the period and slot offset can be jointly expressed as periodicity and offset, and the starting symbol and duration can be jointly expressed as starting time and length.

[0125] All parameters can be expressed as integers or enumerated values.

[0126] To replace the parameter configuration of the period, time starting point, and duration mentioned above, a threshold parameter can also be configured for the UE (i.e., the second node). The threshold parameter can be a specific time length, such as 1ms, or a ratio, such as 5%. This ratio can be relative to the global time (including activation or silence) or the entire activation time. The UE can decide on its own the starting time for actually executing (processing) model training or reasoning after the model is available (applicable) or activated. However, no matter where the starting point is, the execution time length should not exceed the configured threshold, for example, not more than 5% of the activation time.

[0127] As a possible implementation, in the process of the first node sending indication information to the second node, the first node may obtain response requirement information of multiple algorithm functions, and determine the indication information based on the available resource information and the response requirement information of the multiple algorithm functions, and then send the indication information to the second node. The response requirement information of the algorithm function may include: resource requirement information of the algorithm function, and the indication information indicates that the resources required for the response of each algorithm function can match the available resources in the second node.

[0128] In other words, by referring to the available resources in the node and the resource requirements of each algorithm function, managing the response timing of multiple algorithm functions can ensure that the node can provide corresponding resources for the response requirements of each algorithm function at different response times to support the response of the algorithm function. In other words, the utilization of hardware resources seriously affects the power efficiency of the AI ​​model. The core of improving power efficiency or energy saving is to concentrate dynamic tasks as much as possible in the same time period to complete them and maximize hardware utilization.

[0129] It should be noted that, in combination with the above introduction to available resource information, the resource requirement information of the algorithm function may include: the computing power requirement information of the algorithm function and / or the power requirement information of the algorithm function, the computing power requirement information may include: the computing power requirement value and / or the duration of the computing power requirement value, and the power requirement information may include: the power requirement value and / or the duration of the power requirement value.

[0130] In the embodiment of the present disclosure, the response requirement information of the algorithm function may further include: the response delay of the algorithm function.

[0131] In other words, by referring to the response delay requirements of each algorithm function, it is ensured that some of the algorithm functions that require concentrated responses can be responded to in a timely manner.

[0132] For example, Figure 4As shown in the figure, if the task (training or reasoning) of an AI model is completed in one time period or divided into N discontinuous time periods, the hardware that undertakes the AI ​​model task, such as CPU, GPU, NPU, TPU, etc., has a static baseline power, that is, regardless of whether the model task is started or not, the minimum power will always exist as long as the model is activated. When the task is completed in N discontinuous time periods, (N-1) more static baseline power will be consumed, resulting in energy waste and low power efficiency. In other words, the AI ​​model task is completed in one time and in four times, and the total dynamic power is equivalent, but the scenario of completing the task in four times has 3 more static baseline power overheads, resulting in reduced power efficiency under a single task.

[0133] It should be noted that appropriate hyperparameter configuration of the algorithm function can effectively reduce the energy or power consumption of the algorithm function and maintain the performance of the algorithm function. Hyperparameters that are relatively easy to adjust in the algorithm function and are extremely sensitive to power consumption include batch size, quantization bit number, etc.

[0134] In the embodiment of the present disclosure, the indication information may further include: parameter configuration of each algorithm function, and the parameter configuration may include at least one of the following: batch size, number of quantization bits, number of iterations, maximum power, and minimum power.

[0135] Among them, reasonable setting of batch size can make full use of hardware and improve hardware utilization, thereby achieving the purpose of saving power.

[0136] The lower the number of quantization bits, the shorter the algorithm function runs, the less hardware resources are needed, and power can be saved. However, the consideration of the number of quantization bits also needs to take into account the performance degradation caused by reducing the number of quantization bits. The lower the number of quantization bits, the better.

[0137] It should be noted that the multiple algorithm functions may be preconfigured by the first node to the second node, or the multiple algorithm functions may be preconfigured locally for the second node.

[0138] That is to say, the sources of the multiple algorithm functions are limited and described, that is, the multiple algorithm functions can be algorithm functions pre-configured by the upstream node to the downstream node, or the multiple algorithm functions can be algorithm functions pre-configured locally at the node.

[0139] As a possible implementation method, when multiple algorithm functions are pre-configured from the first node to the second node, the first node may pre-store response requirement information of each algorithm function, and the first node may directly obtain the response requirement information of the multiple algorithm functions from the storage space.

[0140] That is to say, in the case where multiple algorithm functions are pre-configured by the upstream node to the downstream node, since the upstream node can know the multiple algorithm functions in advance, it can directly determine the response requirements of each algorithm function.

[0141] As another possible implementation method, when multiple algorithm functions are pre-configured locally for the second node, the first node can receive the configuration information of the multiple algorithm functions reported by the second node, and determine the response requirement information of the multiple algorithm functions based on the configuration information of the multiple algorithm functions (such as the first node locally deploys multiple algorithm functions based on the configuration information of each algorithm function, and then detects the response requirement information of the multiple algorithm functions) to obtain the response requirement information of the multiple algorithm functions.

[0142] That is to say, when multiple algorithm functions are pre-configured locally for the downstream node, since the upstream node is unaware of the multiple algorithm functions, the downstream node needs to report the relevant configurations of the multiple algorithm functions to the upstream node, so that the upstream node can determine the response requirements of each algorithm function based on the relevant configurations of the multiple algorithm functions, and then provide a reference for the subsequent determination of the response order of the multiple algorithm functions.

[0143] In some embodiments, the indication information may further include: the response order of the second node to the multiple algorithm functions.

[0144] That is, the first node chronologically orders the response timings of the multiple algorithm functions in the second node based on the information reported by the second node, and indicates the response order of the second node to the multiple algorithm functions through the indication information.

[0145] As a possible implementation manner, the response requirement information of the algorithm function may also include: the response priority of the algorithm function (ie, the urgency of the node's response to the algorithm function).

[0146] That is to say, when arranging the response order of different algorithm functions, it is also necessary to refer to the response priority of each algorithm function to ensure that high-priority algorithm functions can receive timely responses.

[0147] The present disclosure also provides a method for managing algorithm functions, which is applied to a second node, such as Figure 5 As shown, the management method of the algorithm function may include:

[0148] S501. Send request information to a first node.

[0149] It should be noted that, for the introduction of the request information, reference may be made to the description of the request information in the embodiment in the above S301, which will not be described in detail here.

[0150] It should be noted that the embodiment of the present disclosure does not limit the triggering condition (ie, stimulus) for the second node to send the request information to the first node.

[0151] For example, the second node may send the request information to the first node based on a preset timer (such as a periodic timer or a prohibition timer).

[0152] For another example, the second node may send a request message to the first node when the change range of the available computing power value and / or the available power value in the second node is greater than a preset threshold.

[0153] For another example, the second node may send request information to the first node in response to the request from the first node.

[0154] S502: Receive indication information sent by the first node.

[0155] It should be noted that, for the introduction of the indication information, reference may be made to the description of the indication information in the embodiment in the above S302, which will not be described in detail here.

[0156] S503: Respond to multiple algorithm functions based on the indication information.

[0157] The following takes the interaction between the first node and the second node as an example to introduce the management method of the algorithm function provided in the above embodiment. Figure 6 As shown, including:

[0158] S601: The second node sends request information to the first node.

[0159] S602: The first node receives request information sent by the second node.

[0160] S603: The first node sends indication information to the second node.

[0161] S604: The second node receives the indication information sent by the first node.

[0162] S605: The second node responds to multiple algorithm functions based on the indication information.

[0163] That is to say, the embodiments of the present disclosure analyze the key factors affecting the power consumption of the AI ​​model based on the above-mentioned hardware utilization, power limitation, quantization bit and hyperparameter configuration, and provide corresponding energy-saving solutions for mobile communication systems.

[0164] The following describes the management method of the algorithm function provided by the present disclosure in conjunction with specific embodiments.

[0165] Embodiment 1: Improve the hardware utilization of AI models.

[0166] Among them, hardware utilization mainly refers to the number of core computing units in various processors, the amount of video memory, etc. Taking GPU as an example, the ability of the core hardware unit is evaluated by the number of internal CUDA cores, the size of video memory, and other parameters.

[0167] Insufficient hardware utilization leads to energy waste. Optimizing hardware utilization can reduce energy consumption when idle. For example, when the GPU is not fully utilized, the baseline static power overhead will increase.

[0168] When AI models are mainly trained or inferred on network-side devices, such as base stations, core networks or gateway servers, due to the natural multi-task aggregation mechanism of network-side devices and the processing of multiple users under network coverage within the same device, it is a very feasible solution to compress a large number of AI model tasks or algorithms into a shorter time interval or continuously process the AI ​​model tasks or algorithms for AI model training or inference.

[0169] When the AI ​​model is mainly trained or inferred on the user equipment, such as the UE side, a single training or inference task is scattered among various users. However, independent terminals are likely to use multiple AI models or algorithm functions, such as beam management, channel state information estimation, positioning functions, demodulation, encoding and decoding, data compression and other algorithm functions. It is possible to consider unifying different types of AI models or algorithm functions and coordinating the algorithm functions for training or inference in the same time period. Since the management of AI models or algorithm functions is located in the network side device, the network side device needs to perform relevant configurations on the UE side. Configuration parameters include periodic configuration parameters, such as the execution cycle, execution starting point, execution duration, etc. of the algorithm function, which are generally configured through the high-level radio resource control (RRC) or medium access control (MAC) layer. Configuration parameters can also be dynamically indicated, and the relevant configuration parameters are carried by the physical downlink shared channel (PDSCH) scheduled by downlink control information (DCI) signaling or DCI signaling. Dynamic indication is more flexible and belongs to non-periodic configuration. The combination of periodic configuration and non-periodic configuration takes into account the characteristics of semi-static stability and dynamic flexibility.

[0170] It is important to note that the algorithmic function of the AI ​​model exists in four stages or four states:

[0171] (1) Function support means that the UE can indicate through UE capability information (via RRC / location procedure protocol (LPP) signaling) that the function is supported;

[0172] (2) Functional suitability means that the UE is ready for training or inference;

[0173] (3) Function activation refers to enabling training or inference;

[0174] (4) Functional execution refers to the actual execution of training or reasoning;

[0175] These four stages or states distinguish the AI ​​model or algorithm functions from weak to strong in terms of time urgency. Function activation only indicates that the model or function is allowed to run processing, but training or reasoning operations are not necessarily performed when there is no actual task demand. Function execution actually performs training or reasoning operations.

[0176] The granularity of the algorithm function may refer to the application scenarios mentioned above, such as beam management, channel state information estimation, positioning function, demodulation, encoding and decoding, data compression and other algorithm functions, or it may be a newer sub-application scenario, such as a certain sub-scenario of beam management, or it may be an application scenario configured with different wireless parameter sets.

[0177] The parameters that network equipment configures or indicates the AI ​​model or algorithm functions on the UE side need to rely on the capability information and operating status reported by the UE.

[0178] The UE capability information includes the algorithm functions supported by the UE, the computing power required by the algorithm functions, the delay requirements of the algorithm functions, etc.

[0179] Because the configuration of relevant parameters on the network side needs to consider aligning the processing time of multiple algorithm functions or models on the UE side and making full use of the hardware resources of the UE, it is necessary to understand the required computing power of each algorithm function, so as to evaluate the total computing power requirements of multiple algorithm functions and further efficiently schedule the algorithm functions of each operation time segment. For example, the floating-point computing power in a typical terminal chip processor is 4.6 T floating-point operations per second (FLOPS), and an algorithm function such as channel state information (CSI) predicts the channel state information of a single antenna. It requires about 40 M FLOPS computing power, so that the inference time required to complete a single-antenna CSI prediction inference function does not exceed 0.01 ms, that is, 0.01 subframe length. It is entirely possible to compress the inference operations of multiple models or algorithm functions into a short interval within a subframe. Further, multiple inference operations of multiple models or algorithm functions can be compressed into a subframe or even a shorter time.

[0180] Network equipment also needs to understand the latency requirements of algorithm functions, especially the minimum latency requirements, to avoid forcibly aligning the processing time of algorithm functions, which will cause a one-sided increase in latency and affect performance. For example, if the minimum latency requirement of algorithm function A is 5ms and the minimum latency requirement of algorithm function B is 20ms, then these two sets of functions can be configured with different processing time cycles to match their minimum latency requirements. Of course, the processing time cycles of functions A and B can also be aligned to the most stringent 5ms to meet the minimum latency requirements of both A and B.

[0181] The computing power situation on the terminal side belongs to an operating state of the terminal side. The total computing power of the terminal UE is close to being stable for a period of time, but the computing power reserved for the AI ​​model or algorithm function is floating and changing. For example, the computing power of the terminal UE is mainly used to run games, or to execute applications (applications, APPs) that require computing power. Then the network side equipment needs to promptly understand the status of the remaining computing power of the terminal in order to adjust and update the computing power allocation of each algorithm function in a timely manner. The terminal UE can periodically report the computing power space (compute headroom report, CHR). The computing power space is the remaining computing power (that is, the available computing power information) after the total computing power is deducted from the used computing power. The computing power space reporting method is configured by the network side through RRC parameters. The network side device can also instruct the UE to report CHR on demand, and the on-demand signaling can be carried by RRC, MAC layer or physical layer signaling.

[0182] This specific computing power space is dedicated to the algorithm function of the communication system. Due to the diversity of the algorithm functions of the communication system, for example, some algorithm functions require floating-point computing power, and some algorithm functions require fixed-point computing power, the terminal UE can report computing power spaces of multiple algorithm functions or multiple computing power types separately. The computing power space CHR can be multiplexed on the medium access control-control element (MAC-CE) and transmitted on the physical uplink shared channel (PUSCH).

[0183] If the CHR only carries a single computing space, the MAC-CE reported by the computing space to the CHR is identified by a specific MAC subheader. The data structure of the MAC-CE is as follows Figure 7 and Figure 8 shown.

[0184] in, Figure 7 It is a report of the available computing space of a single entry. Figure 8 It is the reporting of available computing space with multiple entries (such as available computing space 0, available computing space 1, ..., available computing space 7), where C0 to C7 are flags indicating whether computing space reporting of computing function or computing type exists. The flag is not limited to only 8 bits, and can also be expanded according to actual conditions. Some reserved bits can also be provided in the structure for subsequent function expansion.

[0185] In addition, the reported value of CHR in the data structure should be a quantized value. The quantized table can be similar to Table 1 below. The maximum number of valid rows is 64, which can also be expanded according to actual conditions. When the table is expanded, Figure 7 or Figure 8 One byte in the CHR may not be enough, and more bytes or bits are needed.

[0186] Table 1 Quantification table of computing power space

[0187] Computing Space Index Computing Space Level Value 0 Computing space level value 0 1 Computing space level value 1 2 Computing Space Level Value 2 … … 61 Computing power space level value 61 62 Computing power space level value 62 63 Computing power level value 63

[0188] It should be noted that the network side device controls the reporting of CHR through RRC parameters, and these RRC parameters may include one or more of the following:

[0189] (1)CHR periodic timer (chr-periodic timer);

[0190] (2)CHR-prohibit timer;

[0191] (3)CHR computing power change factor (chr-tx-power factor change);

[0192] (4) CHR reporting mode (chr-mode);

[0193] (5) CHR reporting resource pool (chr-resource pool), etc.

[0194] In addition, the hashrate reporting may be triggered by the following single event or multiple single events:

[0195] (1) The CHR cycle timer expires;

[0196] (2) CHR prohibit timer expires;

[0197] (3) The CHR computing power change exceeds the CHR computing power change factor, where the computing power change factor is a threshold value configured by RRC;

[0198] (4) Receive instructions from the network side to report CHR.

[0199] If the MAC entity has new transmission resources, the CHR cycle timer is started from the first new uplink transmission resource after the last MAC reset.

[0200] Based on the key technical points of power saving mentioned above, the network device requests the terminal UE to report its terminal capability or computing power status. After receiving the capability report or computing power status, it configures the execution time of the terminal-side AI model or algorithm function and compresses it into a set time period. The whole process is as follows: Fig. 9 As shown:

[0201] Step 1: The network (i.e., the first node) sends a request capability reporting message to the terminal (i.e., the second node) reporting its AI / ML support functions.

[0202] Step 2: The terminal sends a capability message (i.e., capability reporting) to the network, which includes at least one or more of the algorithm functions supported by the terminal side, the computing power required by the algorithm functions, and the delay requirements of the algorithm functions.

[0203] Step 3: The network provides the terminal with an RRC reconfiguration message (i.e., initial configuration of the algorithm function), which may include one or more of the following but is not limited to:

[0204] 1) Additional conditions on the network side, which can be assumed to be association IDs.

[0205] 2) The configuration of the algorithm functions supported by the terminal (such as training or reasoning configuration), etc., must at least include the execution (process) parameters involved in the above, such as the execution cycle of the algorithm function, the execution starting point, the execution time or the threshold parameters, etc. The number of algorithm functions involved in the execution parameters supports being greater than or equal to one (optionally).

[0206] 3) The network side configures the terminal to report at least one of its applicable functions, computing power status (computing power space), or responses to additional conditions on the network side.

[0207] Note: Between "Step 3" and "Step 4", the terminal determines the applicable function based on the additional conditions on the network side (if provided in Step 3), execution parameters (if any), the additional conditions on the terminal side itself, or the availability of algorithm functions in the device.

[0208] Step 4: The terminal reports the applicable function it determines (i.e., reporting the applicable algorithm function), where the applicable function is one of the algorithm function set supported by the UE capability. Optionally, the reporting computing power space can be increased, or a response to additional conditions on the network side can be provided.

[0209] Step 5: (Optional) Second RRC reconfiguration (ie, algorithm function reconfiguration).

[0210] 1) If no training or reasoning configuration based on supported functions is provided in step 3, the network configures the training or reasoning configuration to the terminal after the applicable function report.

[0211] 2) If an inference configuration based on supported functions is provided in step 3, whether to provide an updated configuration depends on the network implementation.

[0212] Step 6: (Optional) The terminal activates the applicable algorithm function.

[0213] Step 7: The terminal executes the algorithm function according to the configured operating parameters.

[0214] Step 8: (Optional) After the algorithm function is executed, report the computing power space after the computing power is recovered.

[0215] Step 9: (Optional) Deactivate the algorithm function.

[0216] In the above process, all the configurations related to the algorithm functions are semi-statically indicated by RRC signaling. Alternatively, the configuration parameters of the algorithm functions can also be semi-dynamically or dynamically indicated, and the relevant configuration parameters are carried by the MAC layer, DCI signaling, or the downlink PDSCH scheduled by DCI signaling. For example, in step 3, the relevant parameters are not configured or partially configured, and the RRC reconfiguration in step 5 is replaced by the MAC layer, DCI signaling, or the downlink PDSCH scheduled by DCI signaling to indicate the algorithm function parameters.

[0217] The reporting of the computing power space in step 4 is not necessary to respond to step 3 here. The computing power space reporting can be reported separately according to the configuration signaling or reporting indication of the computing power space reporting.

[0218] Instead of reporting computing power space, the current computing power level of the terminal UE can be reported using the current computing power of the terminal UE, which can achieve a similar effect as reporting computing power space. The UE sends a UE capability message to the network, which can include its total computing power or total computing power level. The UE can also report the total computing power or total computing power level in other ways. The network device combines the reported total computing power or total computing power level, deducts the current computing power report or computing power level, and obtains the computing power space. In other words, computing power reporting or current computing power level reporting is also a type of computing power status reporting.

[0219] The data structure, RRC parameter configuration, trigger conditions, etc. of computing power reporting or computing power level reporting can use similar technical solutions as those for computing power space reporting.

[0220] When the network initially configures the terminal UE to use a traditional technical solution rather than an algorithm function solution, the terminal UE can also be required to report its computing power status such as computing power space, so as to learn whether the terminal UE has excess computing power to support the algorithm function, and then enable the algorithm function and execute the switch from the traditional function to the algorithm function.

[0221] In this way, the power overhead of the AI ​​model or algorithm function in the UE can be saved.

[0222] Embodiment 2: Limiting the power of the AI ​​model.

[0223] The execution of algorithm functions relies on hardware implementation, and the comprehensive energy consumption required depends on the execution time multiplied by the average power under this operating state. That is, total energy consumption (total energy) = time (time) * average power (average power).

[0224] Due to the characteristics of power consumption when hardware implements algorithms, it is often nonlinear, especially when the running rate reaches the peak, the required power often increases nonlinearly. For example, the recommended operating frequency of a CPU is 4 GHz, and the average power required is X watts. When the CPU is overclocked, such as overclocking to 4.2GHz, the task completion time will be saved to 95% of the original, but the average power required is far more than 5%, and it may require 110%*X watt at the standard operating frequency. In this way, although time is saved after overclocking, the actual comprehensive energy consumption increases by 95%*110%-100%=4.5%. It is not advisable to unilaterally emphasize speeding up the execution time of tasks, and it is necessary to consider the balance between running time and energy consumption.

[0225] If the algorithm function is trained and inferred by the terminal UE itself, the UE can determine the upper and lower power limits of the appropriate algorithm function by itself. If the algorithm function is trained by a network device or a third-party device and transferred to the UE by the network device, because the network device knows the algorithm function trained by itself better than the terminal, the network device can recommend or configure the maximum operating power or minimum operating power to the UE. This operating power limit is not for the conventional power limit of the UE, but for the power limit for the algorithm function inside the UE. Obviously, the power required by the algorithm function cannot exceed the maximum power of the UE, or more accurately, it cannot exceed the upper limit of the UE for all algorithm functions. The UE needs to report the available power space (algorithm power headroom report, APHR) (i.e., available power information) of the algorithm function to the network device in real time or quasi-real time, so as to assist the network device in configuring the maximum or minimum operating power of the UE's algorithm function. The available power space of the algorithm function can also be alternatively expressed as a computer power headroom report (compute power headroom report, CPHR). The specific process is as follows Fig.10 As shown:

[0226] Step 1: (optionally) the network sends a computing power status reporting request message to the terminal (i.e., a computing power status reporting request).

[0227] Step 2: (Optionally) the terminal sends a computing power status message (i.e., computing power status report) to the network, which at least includes the total computing power and computing power space supported by the UE side.

[0228] Step 3: (Optional) The network transfers the algorithm function to the terminal.

[0229] Step 4: The network requests the terminal to report the algorithm function available power space APHR (i.e., requesting available power space reporting).

[0230] Step 5: The terminal reports its APHR (available power headroom reporting).

[0231] Step 6: The network configures power limits for algorithm functions, such as maximum execution power.

[0232] The request report message, report message, etc. in the above steps may be based on RRC signaling, or may be based on MAC layer signaling or physical layer signaling.

[0233] Even if the algorithm function is trained by the terminal UE, the UE can transfer the algorithm function to the network, and the network equipment determines the power limit of the algorithm function. Fig.11 As shown:

[0234] Step 1: The network sends a message requesting algorithm function transfer (i.e. requesting transfer of algorithm function) to the terminal.

[0235] Step 2: The terminal transfers the algorithm function to the network.

[0236] Step 3: The network requests the terminal to report the algorithm function available power space APHR (i.e., requesting available power space reporting).

[0237] Step 4: The terminal reports its APHR (available power headroom reporting).

[0238] Step 5: The network configures power limits for algorithm functions, such as maximum execution power.

[0239] The request report message, report, configuration message, etc. in the above steps may be based on RRC signaling, or may be based on MAC layer signaling or physical layer signaling.

[0240] It should be noted that the current algorithm power report or current algorithm power level of the terminal UE can be used instead of APHR reporting to achieve a similar effect to APHR reporting. Because the UE can report its total algorithm power or total algorithm power level to the network. The network device combines the reported total algorithm power or total algorithm power level, deducts the current algorithm power report or algorithm power level, and obtains the algorithm power space.

[0241] Embodiment 3: Hyperparameter configuration of algorithm functions.

[0242] If the algorithm function is trained by the network device or a third-party device and transferred to the UE by the network device, the network device can recommend or configure hyperparameters (quantization bit or batch size) to the UE. The configuration parameters are for the algorithm function of the UE. The UE needs to give the network device to assist the network device in configuring the hyperparameters of the UE's algorithm function. The specific process is as follows Fig.12 As shown:

[0243] Step 1: The network sends a message requesting computing power status reporting to the terminal (i.e. requesting computing power status reporting).

[0244] Step 2: The terminal sends a computing power status message (i.e., computing power status report) to the network, which at least includes the computing power space of the UE.

[0245] Step 3: (Optional) The network transfers the algorithm function to the terminal.

[0246] Step 4: The network determines the hyperparameters of the algorithm function and configures the hyperparameters to the terminal (i.e., configures the algorithm function hyperparameters), such as the number of quantization bits or batch size.

[0247] The request report message, report, configuration message, etc. in the above steps may be based on RRC signaling, or may be based on MAC layer signaling or physical layer signaling.

[0248] Similarly, even if the algorithm function is trained by the terminal UE, the UE can transfer the algorithm function to the network, and the network equipment determines and configures the hyper parameters of the algorithm function, such as Fig.13 As shown:

[0249] Step 1: The network sends a message requesting algorithm function transfer (i.e. requesting transfer of algorithm function) to the terminal.

[0250] Step 2: The terminal transfers the algorithm function to the network.

[0251] Step 3: The network determines the hyperparameters based on the algorithm function and configures the hyperparameters of the algorithm function to the terminal (i.e., configures the hyperparameters of the algorithm function), such as the number of quantization bits or the batch size.

[0252] The request, report, configuration message, etc. in the above steps may be based on RRC signaling, or may be based on MAC layer signaling or physical layer signaling.

[0253] Except for the number of quantization bits or batch size, other hyperparameters that can affect energy consumption can be configured according to the above two processes.

[0254] Embodiment 4: Energy consumption and available power headroom (PHR / APHR) prediction.

[0255] In the above-mentioned embodiment 2, it is mentioned that the UE needs to report the available power space of the algorithm function to the network device in real time or quasi-real time, so as to assist the network device in configuring the power limit of the algorithm function of the UE. In fact, after the introduction of AI / ML, the available power space can be predicted based on the historical business behavior pattern of the UE, the power consumption of the algorithm function, etc. When PHR or APHR is predictable, the reporting frequency of the available power space can be reduced, and the reporting overhead can be reduced; there can be more time to prepare for the next step of configuration or scheduling to reduce latency.

[0256] PHR / APHR prediction is divided into two dimensions, one is to predict the PHR / APHR at a certain point in the future, and the other is to predict the effective duration of the PHR / APHR reported value. For example, the UE can predict the PHR / APHR at a certain point in the future, such as 5ms later, based on the historical PHR and APHR data and the currently measured PHR / APHR; the UE can also predict the effective duration of the current PHR / APHR reported value, such as the reported value can last for 1ms, which can assist the network equipment to compress the algorithm function as much as possible within 1ms, and will not affect the power allocation after 1ms; of course, combined with the first two, the UE can predict the PHR / APHR value at a certain point in the future and the effective duration of this value.

[0257] like Fig.14 As shown, the historical available power space and the currently measured available power space (i.e., the current available power space) are input into the prediction model, and the prediction model outputs three possible results: (1) the available power space at a certain point in the future (i.e., the future available power space); (2) the effective duration of the value reported by the current available power space (i.e., the effective duration of the current available power space); (3) the available power space value at a certain point in the future and the effective duration of this value (i.e., the future available power space and its effective duration).

[0258] The prediction model can be based on AI / ML. If the prediction model is based on AI / ML, then the prediction model can be trained with historical data.

[0259] like Fig.15 As shown in the figure, the prediction model has two sets of inputs, one of which is the historical available power space and the currently measured available power space, and the other is the label, which includes the future available power space, or the effective duration of the current available power space, or the future available power space and effective duration. Labels are used as input, which means that the training of the AI / ML model is based on a supervised learning mechanism. Labels can also be omitted. When there are no labels, it means that the training of the AI / ML model is based on an unsupervised learning mechanism.

[0260] Similar predictions of PHR / APHR can also be done on the network side, because both historical and current PHR / APHR will be reported by the UE to the network side device. The difference is that when the prediction is done on the UE side, the UE needs to report the corresponding prediction results, including but not limited to the future PHR / APHR, the current PHR / APHR effective duration or the future PHR / APHR and effective duration. The future PHR / APHR report needs to carry a time stamp.

[0261] The network also needs to provide some auxiliary control information for the prediction on the UE side, such as the PHR / APHR information at which point in the future the network wants the UE to predict, or which prediction information, etc. However, this auxiliary control information is not necessary in some scenarios. The process of exchanging prediction information between the network side and the UE side is as follows: Fig.16 As shown:

[0262] Step 1: (optionally) the network provides prediction auxiliary control information to the terminal;

[0263] Step 2: The network requests the terminal to report the available power space prediction;

[0264] Step 3: The terminal reports the available power space prediction (result) to the network.

[0265] Among them, the first two steps can be adjusted in sequence or combined into one, and the PHR / APHR (available power space) report needs to carry a time tag (ie, effective duration).

[0266] Embodiment 5: Available computing power space (CHR) prediction.

[0267] In the first embodiment, it is mentioned that the UE needs to report the CHR of the algorithm function to the network device in real time or quasi-real time, so as to assist the network device in configuring the algorithm function and its related parameters. Similar to the prediction of the available power space in the fourth embodiment, the CHR can also be predicted based on the historical UE business behavior pattern, the consumption of the algorithm function computing power, etc. When the CHR is predictable, the reporting frequency of the CHR can be reduced, and the reporting overhead can be reduced; there can be more time for the next step of the algorithm function configuration or scheduling preparation to reduce the delay.

[0268] CHR prediction is divided into two dimensions, one is to predict the CHR at a certain point in the future, and the other is to predict the effective duration of the CHR reported value. For example, the UE can predict the CHR at a certain point in the future, such as 5ms later, based on the historical CHR data and the currently measured CHR; the UE can also predict the effective duration of the current CHR reported value, such as the reported value can last for 1ms, which can assist the network equipment to compress the algorithm function as much as possible within 1ms, and will not affect the computing power allocation after 1ms; of course, combining the first two, the UE can predict the CHR value at a certain point in the future and the effective duration of this value.

[0269] Similar to the fourth embodiment, the historical CHR and the currently measured CHR are input into the prediction model, and the prediction model outputs three possible results: (1) CHR at a certain point in the future; (2) the effective duration of the value reported by the current CHR; (3) the CHR value at a certain point in the future and the effective duration of this value.

[0270] The network also needs to provide some auxiliary control information for the prediction on the UE side, such as the CHR information at which point in the future the network wants the UE to predict, or what kind of prediction information, etc. In some scenarios, this auxiliary control information is not necessary. The process of exchanging prediction information between the network side and the UE side is as follows Fig.17 As shown:

[0271] Step 1: (optionally) the network provides prediction auxiliary control information to the terminal;

[0272] Step 2: The network requests the terminal to report the available computing power space forecast;

[0273] Step 3: The terminal reports the available computing power space prediction (result) to the network.

[0274] Among them, the first two steps can be adjusted sequentially or combined into one, and the CHR (available computing space) report needs to carry a time stamp (i.e., effective duration).

[0275] Embodiment 6: computing power priority.

[0276] As mentioned in Example 1, when the AI ​​model is mainly trained or inferred on the user equipment, such as the UE side, a single training or inference task is scattered among various users. However, independent terminals are likely to use multiple AI models or algorithm functions, such as beam management, channel state information estimation, positioning functions, demodulation, encoding and decoding, data compression and other algorithm functions. It is possible to consider unifying different types of AI models or algorithm functions and coordinating the algorithm functions for training or inference in the same time period.

[0277] The premise for the operation of multiple algorithm functions compressed into the same time period is that the computing power resources are sufficient, that is, there is a balance in the computing power space. When the computing power space is not enough to support the operation of multiple algorithm functions in the same time period, it may be necessary to abandon the operation of some algorithm functions. Similarly, when the algorithm power space (APHR) is insufficient, it is also necessary to abandon the operation of some algorithm functions.

[0278] The trigger mechanism for abandoning some algorithm functions comes from insufficient computing power space or insufficient algorithm power space.

[0279] There are many specific operations for abandoning the operation of the algorithm function. The most direct abandonment is to cancel or halt. A more moderate cancellation behavior can be to defer or skip. Deferring or skipping means that the algorithm function may be able to be restored in time if there is a margin in the computing power space or algorithm power space. For the algorithm function that has been canceled or halted, it is necessary to perform a similar operation as in Example 1. Fig. 9The process (not necessarily fully executed, some steps may be selected to optimize latency) is reactivated for execution. However, for operations that are postponed or skipped, the system will continuously query whether the computing power space or algorithm power space is sufficient. Once sufficient, the corresponding algorithm function can be restored.

[0280] Taking algorithm function A and algorithm function B as an example, when the computing power space or algorithm power space cannot satisfy both A and B at the same time, the network decides to abandon B and takes corresponding operations such as cancellation, suspension, postponement, and skipping. Fig.18 The trigger judgment mechanism of the abandonment algorithm function and the corresponding abandonment operation process are demonstrated.

[0281] Fig.18 The trigger for abandoning the algorithm function in the algorithm power space is whether the computing power space can support both A and B, or only support A or B, or neither A nor B. The algorithm power space is similar. When only one of the algorithm functions A or B is supported, one of the algorithm functions needs to be abandoned.

[0282] The judgment of computing power space and power space can coexist in the system process, or one or the other can exist.

[0283] The trade-off between A and B depends on priority and space margin. If A has a higher priority than B, A will be executed first, unless the computing power space or power space only allows B to be executed. When A can be executed, B will be abandoned. The same applies to the opposite priority. When A and B have the same priority, the decision on which algorithm function to abandon is based on whether the computing power space or power space margin allows A or B.

[0284] 1. Scenarios of UE self-scheduling algorithm function:

[0285] The priorities of various algorithm functions can be configured by the network to the terminal UE through RRC high-level signaling or MAC layer signaling. The terminal UE decides which algorithm function to execute and which algorithm function to abandon based on the configured algorithm function priorities.

[0286] To assist the UE in making decisions, the network can configure a computing power threshold. When the terminal computing power exceeds or falls below the threshold, the computing power is controlled according to the priority of each configured algorithm function. Alternatively, the network can configure the maximum power value of the algorithm function to the UE. When the terminal power exceeds the maximum power threshold, power control is performed according to the priority.

[0287] When the algorithm function abandonment operation may include possible operations such as cancel, halt, defer or skip, the network device may also instruct the terminal UE to select a specific abandonment instruction through RRC high-level signaling or MAC layer signaling.

[0288] 2. Network equipment controls UE algorithm function scheduling:

[0289] If the scheduling of the algorithm function is controlled by the network device, the network device may instruct the terminal UE to abandon the algorithm function through RRC high-level signaling or MAC layer signaling, or instruct the terminal UE to abandon the algorithm function through more dynamic physical layer signaling such as DCI signaling. The signaling indicating the abandonment of the algorithm function may include the identifier of the algorithm function, or take one of the operations of cancel, halt, defer or skip.

[0290] When an algorithm function is abandoned, it does not mean the end of similar algorithm functions. If the abandonment operation is postponed or skipped, the corresponding algorithm function will be started at any time when the computing power space and power space are met. Even if the abandonment operation is canceled or terminated, there is a chance to start running through the reactivation process. While waiting for the restart, the terminal UE can fall back to the non-algorithm function mode, such as the AI-assisted beam management falls back to the conventional beam management, and will not cause the collapse of the system function.

[0291] It is understandable that the management device of the algorithm function includes hardware structures and / or software modules corresponding to the execution of each function in order to realize the above functions. Those skilled in the art should easily realize that, in combination with the algorithm steps of each example described in the embodiments of the present disclosure, the present disclosure can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present disclosure.

[0292] The disclosed embodiment can divide the management device of the algorithm function into functional modules according to the above method embodiment. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one functional module. The above integrated module can be implemented in the form of hardware or software. It should be noted that the division of modules in the disclosed embodiment is schematic and is only a logical function division. There may be other division methods in actual implementation. The following is an example of dividing each functional module corresponding to each function.

[0293] Fig.19 This is a schematic diagram of the structure of a management device for an algorithm function provided by an embodiment of the present disclosure. Figure 1 , the management device of the algorithm function can be applied to the first node and execute the above Figure 3management methods for the algorithmic functions shown, and Figure 6 The embodiment corresponding to the first node in the management method of the algorithm function shown in FIG. Fig.19 As shown, the algorithm function management device 1900 includes: a receiving module 1901 and a sending module 1902.

[0294] The receiving module 1901 is used to receive request information sent by the second node, the request information is used to indicate the response to multiple algorithm functions. The sending module 1902 is used to send indication information to the second node, the indication information is used to indicate that the second node responds to at least two of the multiple algorithm functions in parallel.

[0295] In some embodiments, the request information includes: available resource information of the second node. The algorithm function management device 1900 also includes: a processing module 1903. The processing module 1903 is used to obtain response requirement information of multiple algorithm functions, and the response requirement information of the algorithm functions includes: resource requirement information of the algorithm functions. The processing module 1903 is also used to determine the indication information based on the available resource information and the response requirement information of the multiple algorithm functions.

[0296] In some embodiments, the resource requirement information of the algorithm function includes: computing power requirement information and / or power requirement information of the algorithm function, and the available resource information includes: available computing power information and / or available power information.

[0297] In some embodiments, the available computing power information includes: an available computing power value and / or an available duration of the available computing power value, and the available power information includes: an available power value and / or an available duration of the available power value.

[0298] In some embodiments, the response requirement information of the algorithm function also includes: the response delay of the algorithm function.

[0299] In some embodiments, the response requirement information of the algorithm function also includes: the response priority of the algorithm function.

[0300] In some embodiments, the available resource information is real-time information of the second node at the current moment, or the available resource information is predicted information of the second node at a future moment.

[0301] In some embodiments, the indication information includes time information for responding to each algorithm function, and the time information includes at least one of the following: time period, start time, duration, and time threshold.

[0302] In some embodiments, the indication information includes a parameter configuration in response to each algorithm function, and the parameter configuration includes at least one of the following:

[0303] Batch size.

[0304] The number of quantization bits.

[0305] Number of iterations.

[0306] Maximum power.

[0307] Minimum power.

[0308] In some embodiments, the indication information includes a response order of the second node to the plurality of algorithm functions.

[0309] In some embodiments, the plurality of algorithm functions are algorithm functions being responded to in the second node. Alternatively, the plurality of algorithm functions are algorithm functions to be responded to in the second node.

[0310] In some embodiments, the plurality of algorithm functions are preconfigured by the first node to the second node. Alternatively, the plurality of algorithm functions are preconfigured locally by the second node.

[0311] In some embodiments, the receiving module 1901 is further used to receive configuration information of multiple algorithm functions reported by the second node when multiple algorithm functions are pre-configured locally for the second node. The processing module 1903 is specifically used to determine response requirement information of multiple algorithm functions according to the configuration information of multiple algorithm functions.

[0312] Fig. 20 This is a schematic diagram of the structure of a management device for an algorithm function provided by an embodiment of the present disclosure. Figure 2 , the management device of the algorithm function can be applied to the second node and execute the above Figure 5 management methods for the algorithmic functions shown, and Figure 6 The embodiment corresponding to the second node in the management method of the algorithm function shown in FIG. Fig. 20 As shown, the algorithm function management device 2000 includes: a sending module 2001, a receiving module 2002 and a processing module 2003.

[0313] The sending module 2001 is used to send request information to the first node, where the request information is used to indicate a response to multiple algorithm functions. The receiving module 2002 is used to receive indication information sent by the first node, where the indication information is used to indicate that the second node responds to at least two of the multiple algorithm functions in parallel. The processing module 2003 is used to respond to the multiple algorithm functions based on the indication information.

[0314] In some embodiments, the request information includes: available resource information of the second node, the indication information is determined by the first node based on the available resource information and response requirement information of multiple algorithm functions, and the response requirement information of the algorithm functions includes: resource requirement information of the algorithm functions.

[0315] In some embodiments, the resource requirement information of the algorithm function includes: computing power requirement information and / or power requirement information of the algorithm function, and the available resource information includes: available computing power information and / or available power information.

[0316] In some embodiments, the available computing power information includes: an available computing power value and / or an available duration of the available computing power value, and the available power information includes: an available power value and / or an available duration of the available power value.

[0317] In some embodiments, the response requirement information of the algorithm function also includes: the response delay of the algorithm function.

[0318] In some embodiments, the response requirement information of the algorithm function also includes: the response priority of the algorithm function.

[0319] In some embodiments, the available resource information is real-time information of the second node at the current moment, or the available resource information is predicted information of the second node at a future moment.

[0320] In some embodiments, the indication information includes time information for responding to each algorithm function, and the time information includes at least one of the following: time period, start time, duration, and time threshold.

[0321] In some embodiments, the indication information includes a parameter configuration in response to each algorithm function, and the parameter configuration includes at least one of the following:

[0322] Batch size.

[0323] The number of quantization bits.

[0324] Number of iterations.

[0325] Maximum power.

[0326] Minimum power.

[0327] In some embodiments, the indication information includes a response order of the second node to the plurality of algorithm functions.

[0328] In some embodiments, the plurality of algorithm functions are algorithm functions being responded to in the second node. Alternatively, the plurality of algorithm functions are algorithm functions to be responded to in the second node.

[0329] In some embodiments, the plurality of algorithm functions are preconfigured by the first node to the second node. Alternatively, the plurality of algorithm functions are preconfigured locally by the second node.

[0330] In some embodiments, the sending module 2001 is further used to report configuration information of multiple algorithm functions to the first node when the multiple algorithm functions are pre-configured locally for the second node.

[0331] In some embodiments, the sending module 2001 is specifically used to send a request message to the first node based on a preset timer. Alternatively, the sending module 2001 is specifically used to send a request message to the first node when the change range of the available computing power value and / or the available power value in the second node is greater than a preset threshold. Alternatively, the sending module 2001 is specifically used to send a request message to the first node in response to the request of the first node.

[0332] In the case of implementing the functions of the above-mentioned integrated modules in the form of hardware, the present disclosure provides another possible structural schematic diagram of the management device of the algorithm functions involved in the above-mentioned embodiments. Figure 3 .like Fig.21 As shown, the algorithm function management device 2100 includes: a processor 2102 and a bus 2104. Optionally, the algorithm function management device may further include a memory 2101; optionally, the algorithm function management device may further include a communication interface 2103.

[0333] The processor 2102 may be a processor that implements or executes various exemplary logic blocks, modules, and circuits described in conjunction with the embodiments of the present disclosure. The processor 2102 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the embodiments of the present disclosure. The processor 2102 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0334] The communication interface 2103 is used to connect with other devices via a communication network, such as Ethernet, wireless access network, wireless local area network (WLAN), etc.

[0335] The memory 2101 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.

[0336] As a possible implementation, the memory 2101 may exist independently of the processor 2102, and the memory 2101 may be connected to the processor 2102 via a bus 2104 to store instructions or program codes. When the processor 2102 calls and executes the instructions or program codes stored in the memory 2101, the management method of the algorithm function provided in the embodiment of the present disclosure can be implemented.

[0337] In another possible implementation, the memory 2101 may also be integrated with the processor 2102 .

[0338] The bus 2104 may be an extended industry standard architecture (EISA) bus, etc. The bus 2104 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.21 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0339] Some embodiments of the present disclosure provide a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium) having computer program instructions stored therein. When the computer program instructions are executed on a computer, the computer executes a management method for the algorithm functions described in any of the above embodiments.

[0340] Exemplarily, the above-mentioned computer-readable storage media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks or magnetic tapes, etc.), optical disks (e.g., compact disks (CDs), digital versatile disks (DVDs), etc.), smart cards and flash memory devices (e.g., erasable programmable read-only memory (EPROM), cards, sticks or key drives, etc.). The various computer-readable storage media described in the present disclosure may represent one or more devices and / or other machine-readable storage media for storing information. The term "machine-readable storage medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing and / or carrying instructions and / or data.

[0341] The embodiments of the present disclosure provide a computer program product including instructions. When the computer program product is run on a computer, the computer is enabled to execute the management method of the algorithm function described in any one of the above embodiments.

[0342] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for managing algorithmic functions, characterized in that: Applied to the first node, including: receiving request information sent by the second node, where the request information is used to indicate responses to multiple algorithm functions; Indication information is sent to the second node, where the indication information is used to instruct the second node to respond to at least two of the multiple algorithm functions in parallel.

2. The method according to claim 1, characterized in that The request information includes: available resource information of the second node; and the sending of the indication information to the second node includes: Acquire response requirement information of the plurality of algorithm functions, wherein the response requirement information of the algorithm functions includes: resource requirement information of the algorithm functions; The indication information is determined based on the available resource information and the response requirement information of the multiple algorithm functions.

3. The method according to claim 2, characterized in that The resource requirement information of the algorithm function includes: computing power requirement information and / or power requirement information of the algorithm function, and the available resource information includes: available computing power information and / or available power information.

4. The method according to claim 3, characterized in that The available computing power information includes: an available computing power value and / or an available duration of the available computing power value, and the available power information includes: an available power value and / or an available duration of the available power value.

5. The method according to claim 2, characterized in that: The response requirement information of the algorithm function also includes: the response delay of the algorithm function.

6. The method according to claim 2, characterized in that The response requirement information of the algorithm function also includes: the response priority of the algorithm function.

7. The method according to claim 2, characterized in that The available resource information is the real-time information of the second node at the current moment; or, The available resource information is prediction information of the second node at a future moment.

8. The method according to claim 1, characterized in that The indication information includes time information for responding to each of the algorithm functions, and the time information includes at least one of the following: time period, start time, duration, and time threshold.

9. The method according to claim 1, characterized in that: The indication information includes a parameter configuration in response to each of the algorithm functions, and the parameter configuration includes at least one of the following: Batch size; The number of quantization bits; Number of iterations; Maximum power; Minimum power.

10. The method according to claim 1, characterized in that The indication information includes a response order of the second node to the multiple algorithm functions.

11. The method according to claim 1, characterized in that: The multiple algorithm functions are algorithm functions being responded to in the second node; or, The multiple algorithm functions are algorithm functions to be responded to in the second node.

12. The method according to claim 2, characterized in that: The multiple algorithm functions are preconfigured by the first node to the second node; or, The multiple algorithm functions are pre-configured locally by the second node.

13. The method according to claim 12, characterized in that The obtaining of the response requirement information of the multiple algorithm functions includes: In a case where the multiple algorithm functions are locally pre-configured for the second node, receiving configuration information of the multiple algorithm functions reported by the second node; According to the configuration information of the multiple algorithm functions, response requirement information of the multiple algorithm functions is determined.

14. A method for managing algorithmic functions, characterized in that: Applied to the second node, including: Sending request information to the first node, wherein the request information is used to indicate a response to a plurality of algorithm functions; receiving indication information sent by the first node, where the indication information is used to instruct the second node to respond to at least two of the multiple algorithm functions in parallel; Based on the indication information, respond to the plurality of algorithm functions.

15. The method according to claim 14, characterized in that The request information includes: available resource information of the second node, and the indication information is determined by the first node based on the available resource information and response requirement information of the multiple algorithm functions, and the response requirement information of the algorithm functions includes: resource requirement information of the algorithm functions.

16. The method according to claim 15, characterized in that The resource requirement information of the algorithm function includes: computing power requirement information and / or power requirement information, and the available resource information includes: available computing power information and / or available power information.

17. The method according to claim 16, characterized in that The available computing power information includes: an available computing power value and / or an available duration of the available computing power value, and the available power information includes: an available power value and / or an available duration of the available power value.

18. The method according to claim 15, characterized in that The response requirement information of the algorithm function also includes: the response delay of the algorithm function.

19. The method according to claim 15, characterized in that The response requirement information of the algorithm function also includes: the response priority of the algorithm function.

20. The method according to claim 15, characterized in that The available resource information is the real-time information of the second node at the current moment; or, The available resource information is prediction information of the second node at a future moment.

21. The method according to claim 14, characterized in that The indication information includes time information for responding to each of the algorithm functions, and the time information includes at least one of the following: time period, start time, duration, and time threshold.

22. The method according to claim 14, characterized in that The indication information includes a parameter configuration in response to each of the algorithm functions, and the parameter configuration includes at least one of the following: Batch size; The number of quantization bits; Number of iterations; Maximum power; Minimum power.

23. The method according to claim 14, characterized in that The indication information includes a response order of the second node to the multiple algorithm functions.

24. The method according to claim 14, characterized in that The multiple algorithm functions are algorithm functions being responded to in the second node; or, The multiple algorithm functions are algorithm functions to be responded to in the second node.

25. The method according to claim 14, characterized in that The multiple algorithm functions are preconfigured by the first node to the second node; or, The multiple algorithm functions are pre-configured locally by the second node.

26. The method according to claim 25, characterized in that In a case where the plurality of algorithm functions are locally preconfigured for the second node, the method further comprises: Configuration information of the multiple algorithm functions reported to the first node.

27. The method according to claim 14, characterized in that The sending the request information to the first node includes: Based on a preset timer, sending the request information to the first node; or, When the change range of the available computing power value and / or the available power value in the second node is greater than a preset threshold, sending the request information to the first node; or, The request message is sent to the first node in response to the request of the first node.

28. A management device for algorithmic functions, characterized in that: include: Memory and processor; Memory and processor coupling; The memory is used to store instructions executable by the processor; When the processor executes the instructions, the method according to any one of claims 1 to 27 is performed.

29. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and when the computer instructions are executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 27.

30. A computer program product, characterized in that The computer program product comprises computer program instructions which, when executed, implement the method according to any one of claims 1 to 27.

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