A memory chip, logic chip, chip stack structure and memory

Abstract

The present disclosure provides a memory chip, a logic chip, a chip stack structure and a memory, a global signal region of the logic chip, wherein a plurality of conductive via groups are arranged, 4 normal conductive vias in an i-th conductive via group are electrically connected to 4 internal ports in an i-th internal port group one by one, and the correspondence between the 4 normal conductive vias and the 4 internal ports is determined based on the selection signal.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory chip, a logic chip, a chip stacking structure, and a memory. Background Technology

[0002] With the development of integrated circuit technology, the manufacturing process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, limitations of existing development techniques, and limits of stored electron density. Against this backdrop, to address the difficulties encountered in two-dimensional semiconductor devices and to pursue lower production costs per unit memory cell, bonding processes (e.g., hybrid bonding, bumping, wire bonding) can be used to stack multiple chips to form three-dimensional semiconductor devices. However, for three-dimensional semiconductor devices, the connection structure between different chips still suffers from problems such as large parasitic capacitance and resistance, affecting signal transmission quality. Summary of the Invention

[0003] This disclosure provides a memory chip, a logic chip, a chip stack structure, and a memory.

[0004] In a first aspect, embodiments of this disclosure provide a global signal region defined as the center point of the active surface of the memory chip and its adjacent area, wherein the center point of the global signal region coincides with the center point of the active surface; the global signal region has a first axis and a second axis, the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to a first side of the memory chip, and the second axis is parallel to a second side of the memory chip;

[0005] The global signal region is penetrated by n conductive via groups along a third direction, the third direction being perpendicular to the active surface, where n is a positive integer;

[0006] Each of the aforementioned conductive via groups includes four normal conductive vias, wherein the first and second normal conductive vias are symmetrical about the first axis, the third and fourth normal conductive vias are symmetrical about the first axis, and the first and fourth normal conductive vias are symmetrical about the second axis.

[0007] The internal circuitry of the memory chip includes n internal port groups, and each internal port group includes 4 internal ports.

[0008] The memory chip further includes n selection circuits; the i-th selection circuit is configured to receive and, based on a selection signal, electrically connect the four normal conductive vias in the i-th conductive via group to the four internal ports in the i-th internal port group in a one-to-one correspondence; wherein, the correspondence between the four normal conductive vias and the four internal ports is determined based on the selection signal, and i is a positive integer less than or equal to n.

[0009] In some embodiments, the internal port group includes a first internal port, a second internal port, a third internal port, and a fourth internal port;

[0010] The selection circuit is specifically configured such that if the selection signal is a first preset value, the first normal conductive via, the second normal conductive via, the third normal conductive via, and the fourth normal conductive via are electrically connected to the first internal port, the second internal port, the third internal port, and the i-th fourth internal port, respectively.

[0011] If the selection signal is the second preset value, then the first normal conductive via, the second normal conductive via, the third normal conductive via, and the fourth normal conductive via are electrically connected to the second internal port, the first internal port, the fourth internal port, and the third internal port, respectively, one by one.

[0012] If the selection signal is a third preset value, then the first normal conductive via, the second normal conductive via, the third normal conductive via, and the fourth normal conductive via are electrically connected to the third internal port, the fourth internal port, the first internal port, and the second internal port, respectively, one by one.

[0013] If the selection signal meets the fourth preset value, then the first normal conductive via, the second normal conductive via, the third normal conductive via, and the fourth normal conductive via are electrically connected to the fourth internal port, the third internal port, the second internal port, and the first internal port, respectively, in a one-to-one correspondence.

[0014] In some embodiments, every four of the memory chips are stacked in a third direction to form a stacking unit, and the chip position identifier of each memory chip indicates the position of the memory chip in its respective stacking unit;

[0015] The memory chip also includes:

[0016] The decoding circuit is configured to receive the chip position identification code; if the chip position identification code indicates that the memory chip is in a first type of position, then output the selection signal of a first preset value; if the chip position identification signal group indicates that the memory chip is in a second type of position, then output the selection signal of a second preset value; if the chip position identification signal group indicates that the memory chip is in a third type of position, then output the selection signal of a third preset value; if the chip position identification signal group indicates that the memory chip is in a fourth type of position, then output the selection signal that conforms to a fourth preset value.

[0017] The top surfaces of the memory chips located in the first and third types of positions face upwards along a third direction, while the top surfaces of the memory chips located in the second and fourth types of positions face downwards along a third direction. The active surface of each memory chip is divided into a low-level transmission region and a high-level transmission region. The low-level transmission regions in the memory chips located in the first type of position, the high-level transmission regions in the memory chips located in the second type of position, the high-level transmission regions in the memory chips located in the third type of position, and the low-level transmission regions in the memory chips located in the fourth type of position are aligned along a third direction.

[0018] In some embodiments, each of the conductive via groups further includes a first redundant conductive via, a second redundant conductive via, a third redundant conductive via, and a fourth redundant conductive via; the a first redundant conductive via and the a second redundant conductive via are symmetrical about a first axis, the a third redundant conductive via and the a fourth redundant conductive via are symmetrical about the first axis, and the a first redundant conductive via and the a fourth redundant conductive via are symmetrical about a second axis; a is a positive integer;

[0019] For each of the aforementioned conductive via groups, a of the first redundant conductive vias, a of the second redundant conductive vias, the first normal conductive vias, and the second normal conductive vias constitute a repair unit, and a of the third redundant conductive vias, a of the fourth redundant conductive vias, the third normal conductive vias, and the fourth normal conductive vias constitute another repair unit.

[0020] The selection circuit is further configured to, when any of the normal conductive vias fails, use other conductive vias of the same repair unit to replace the failed normal conductive via and electrically connect them to the corresponding internal port.

[0021] In some embodiments, when a = 1,

[0022] The selection circuit is specifically configured such that if the first normal conductive via fails, the first redundant conductive via or the fourth normal conductive via is used to replace the first normal conductive via and electrically connect to the corresponding internal port.

[0023] If the fourth normal conductive via fails, the fourth redundant conductive via or the first normal conductive via is used to replace the fourth normal conductive via and electrically connect to the corresponding internal port.

[0024] If the second normal conductive via fails, the second redundant conductive via or the third normal conductive via is used to replace the second normal conductive via and electrically connect to the corresponding internal port.

[0025] If the third normal conductive via fails, the third redundant conductive via or the second normal conductive via is used to replace the third normal conductive via and electrically connect to the corresponding internal port.

[0026] In some embodiments, the selection signal includes a first selection signal and a second selection signal; the i-th selection circuit includes an i-th first selection circuit, an i-th second selection circuit, an i-th first signal output circuit, and an i-th second signal output circuit;

[0027] For the i-th first selection circuit, one side is coupled to the first normal conductive via, the fourth normal conductive via, the first redundant conductive via, and the fourth redundant conductive via in the i-th conductive via group, and the other side is coupled to the i-th first primary node and the i-th fourth secondary node; the first selection circuit is configured to receive and, based on the i-th first via state parameter group and the first selection signal, electrically connect one of the coupled conductive vias to the i-th first primary node, and electrically connect the other coupled conductive via to the i-th fourth secondary node;

[0028] For the i-th second selection circuit, one side is coupled to the second normal conductive via, the third normal conductive via, the second redundant conductive via, and the third redundant conductive via in the i-th conductive via group, and the other side is coupled to the i-th second-level node and the i-th third-level node; the second selection circuit is configured to receive and, based on the i-th second via state parameter group and the first selection signal, electrically connect one of the coupled conductive vias to the i-th second-level node, and electrically connect the other coupled conductive via to the i-th third-level node;

[0029] The i-th first signal output circuit is configured to receive and, based on the second selection signal, electrically connect the i-th first primary node to the i-th first internal port and electrically connect the i-th fourth secondary node to the i-th fourth internal port; or, electrically connect the i-th second secondary node to the i-th first internal port and electrically connect the i-th third secondary node to the i-th fourth internal port.

[0030] The i-th second signal output circuit is configured to receive and, based on the second selection signal, electrically connect the i-th second-level node to the i-th second internal port and electrically connect the i-th third-level node to the i-th third internal port; or, electrically connect the i-th first-level node to the i-th second internal port and electrically connect the i-th fourth-level node to the i-th third internal port.

[0031] In some embodiments, the i-th first selection circuit includes an i-th first repair circuit, an i-th second repair circuit, and an i-th first selection output circuit;

[0032] For the i-th first repair circuit, one side is coupled to the first redundant conductive via, the first normal conductive via, and the fourth normal conductive via in the i-th conductive via group, and the other side is coupled to the i-th first primary node; the first repair circuit is configured to receive and electrically connect one of the coupled conductive vias to the i-th first primary node based on the i-th first via state parameter group.

[0033] For the i-th second repair circuit, one side is coupled to the first normal conductive via, the fourth normal conductive via, and the fourth redundant conductive via in the i-th conductive via group, and the other side is coupled to the i-th fourth primary node; the second repair circuit is configured to receive and electrically connect one of the coupled conductive vias to the i-th fourth primary node based on the i-th first via state parameter group;

[0034] The i-th first selection output circuit is configured to receive and, based on the first selection signal, electrically connect the i-th first primary node to the i-th first secondary node and electrically connect the i-th fourth primary node to the i-th fourth secondary node; or, electrically connect the i-th first primary node to the i-th fourth secondary node and electrically connect the i-th fourth primary node to the i-th first secondary node.

[0035] In some embodiments, the i-th first via state parameter group includes a first state parameter, a second state parameter, a third state parameter and a fourth state parameter, and each indicates whether the first redundant conductive via, the first normal conductive via, the fourth normal conductive via and the fourth redundant conductive via in the i-th conductive via group are ineffective.

[0036] The i-th first repair circuit includes a first switching unit, a second switching unit, a third switching unit, a first logic unit, a second logic unit, and a third logic unit;

[0037] The first logic unit is configured to output a first control signal of an enable state only when the i-th first via state parameter group meets a first preset condition; wherein, the first preset condition means that the first state parameter is in an enable state and the second state parameter is in a disabled state, or that both the first state parameter and the second state parameter are in an enable state and both the third state parameter and the fourth state parameter are in a disabled state.

[0038] The first switching unit is configured to control the i-th first redundant conductive via to be electrically connected to the i-th first primary node only when the first control signal is enabled.

[0039] The second logic unit is configured to output a second control signal for an enabled state only when the i-th first via state parameter group meets the second preset condition; wherein, the second preset condition means that the second state parameter is in an enabled state, and at least one of the third state parameter and the fourth state parameter is in an enabled state;

[0040] The second switching unit is configured to control the first normal conductive via to be electrically connected to the first primary node only when the second control signal is enabled;

[0041] The third logic unit is configured to output a third control signal of an enabled state only when the i-th first via state parameter group meets a third preset condition; wherein, the third preset condition means that both the first state parameter and the second state parameter are in a disabled state, and the third state parameter is in an enabled state;

[0042] The third switching unit is configured to control the i-th fourth normal conductive via to be electrically connected to the i-th first primary node only when the third control signal is enabled.

[0043] When any state parameter is in the enabled state, it indicates that the corresponding conductive via is not in failure; when any state parameter is in the disabled state, it indicates that the corresponding conductive via is in failure.

[0044] In some embodiments, the i-th second repair circuit includes a fourth switching unit, a fifth switching unit, a sixth switching unit, a fourth logic unit, a fifth logic unit, and a sixth logic unit;

[0045] The fourth logic unit is configured to output a fourth control signal of the enable state only when the i-th first via state parameter group meets the fourth preset condition; wherein, the fourth preset condition means that the fourth state parameter is in the enable state and the third state parameter is in the disable state, or, when both the fourth state parameter and the third state parameter are in the enable state and both the second state parameter and the first state parameter are in the disable state.

[0046] The fourth switching unit is configured to control the i-th fourth redundant conductive via to be electrically connected to the i-th fourth primary node only when the fourth control signal is enabled.

[0047] The fifth logic unit is configured to output a fifth control signal for an enabled state only when the i-th first via state parameter group meets a fifth preset condition; wherein, the fifth preset condition means that the third state parameter is in an enabled state, and at least one of the second state parameter and the first state parameter is in an enabled state;

[0048] The fifth switching unit is configured to control the i-th fourth normal conductive via to be electrically connected to the i-th fourth primary node only when the fifth control signal is enabled.

[0049] The sixth logic unit is configured to output a sixth control signal in an enabled state only when the i-th first via state parameter group meets the sixth preset condition; wherein, the sixth preset condition means that the fourth state parameter and the third state parameter are both in a disabled state, and the second state parameter is in an enabled state;

[0050] The sixth switching unit is configured to control the first normal conductive via to be electrically connected to the first fourth primary node only when the sixth control signal is enabled.

[0051] In some embodiments, when the enable state is high and the disable state is low, the first logic unit includes a first NOT gate, a first AND gate, and a first OR gate; the second logic unit includes a second AND gate and a second OR gate; the third logic unit includes a third NOT gate and a third AND gate; the fourth logic unit includes a fourth NOT gate, a fourth AND gate, and a fourth OR gate; the fifth logic unit includes a fifth AND gate and a fifth OR gate; and the sixth logic unit includes a sixth NOT gate and a sixth AND gate.

[0052] The input terminal of the first NOT gate receives the second state parameter, the output terminal of the first NOT gate is connected to one input terminal of the first AND gate, the other input terminal of the first AND gate receives the first state parameter, the output terminal of the first AND gate and the output terminal of the sixth AND gate are respectively connected to the two input terminals of the first OR gate, and the first OR gate outputs the first control signal.

[0053] The two inputs of the second OR gate receive the third state parameter and the fourth state parameter respectively. The output of the second OR gate is connected to one input of the second AND gate. The other input of the second AND gate receives the second state parameter. The second AND gate outputs the second control signal.

[0054] The input terminal of the third NOT gate is connected to the output terminal of the fifth OR gate, the output terminal of the third NOT gate is connected to one input terminal of the third AND gate, the other input terminal of the third AND gate receives the third state parameter, and the third AND gate outputs the third control signal;

[0055] The input terminal of the fourth NOT gate receives the third state parameter, the output terminal of the fourth NOT gate is connected to one input terminal of the fourth AND gate, the other input terminal of the fourth AND gate receives the fourth state parameter, the output terminal of the fourth AND gate and the output terminal of the third AND gate are respectively connected to the two input terminals of the fourth OR gate, and the fourth OR gate outputs the fourth control signal;

[0056] The two inputs of the fifth OR gate receive the first state parameter and the second state parameter respectively. The output of the fifth OR gate is connected to one input of the fifth AND gate. The other input of the fifth AND gate receives the third state parameter. The fifth AND gate outputs the fifth control signal.

[0057] The input of the sixth NOT gate is connected to the output of the second OR gate, the output of the sixth NOT gate is connected to one input of the sixth AND gate, the other input of the sixth AND gate receives the second state parameter, and the sixth AND gate outputs the sixth control signal.

[0058] In some embodiments, the i-th second selection circuit includes the i-th third repair unit, the i-th fourth repair unit, and the i-th second selection output circuit;

[0059] For the i-th third repair unit, one side is coupled to the second redundant conductive via, the first normal conductive via, and the second normal conductive via in the i-th conductive via group, and the other side is coupled to the i-th second primary node; the third repair unit is configured to receive and, based on the i-th second via state parameter group, electrically connect one of the coupled conductive vias to the i-th second primary node.

[0060] For the i-th fourth repair unit, one side is coupled to the second normal conductive via, the normal conductive via, and the third redundant conductive via in the i-th conductive via group, and the other side is coupled to the i-th third primary node; the fourth repair unit is configured to receive and, based on the i-th second via state parameter group, electrically connect one of the coupled conductive vias to the i-th third primary node;

[0061] The i-th second selection output circuit is configured to receive and, based on the first selection signal, electrically connect the i-th second primary node to the i-th second secondary node and electrically connect the i-th third primary node to the i-th third secondary node; or, electrically connect the i-th third primary node to the i-th second secondary node and electrically connect the i-th second primary node to the i-th third secondary node.

[0062] In some embodiments, the i-th second via state parameter group includes a fifth state parameter, a sixth state parameter, a seventh state parameter, and an eighth state parameter, and each indicates whether the second redundant conductive via, the second normal conductive via, the third normal conductive via, and the third redundant conductive via in the i-th corresponding conductive via group are ineffective.

[0063] The i-th third repair unit includes a seventh switching unit, an eighth switching unit, a ninth switching unit, a seventh logic unit, an eighth logic unit, and a ninth logic unit;

[0064] The seventh logic unit is configured to output a seventh control signal of the enable state only when the i-th second via state parameter group meets the seventh preset condition; wherein, the seventh preset condition means that the fifth state parameter is in the enable state and the sixth state parameter is in the disable state, or that both the fifth state parameter and the sixth state parameter are in the enable state and both the seventh state parameter and the eighth state parameter are in the disable state.

[0065] The seventh switching unit is configured to control the i-th second redundant conductive via to be electrically connected to the i-th second primary node only when the seventh control signal is enabled.

[0066] The eighth logic unit is configured to output an eighth control signal of the enable state only when the i-th second via state parameter group meets the eighth preset condition; wherein, the eighth preset condition means that the sixth state parameter is in the enable state, and at least one of the seventh state parameter and the eighth state parameter is in the enable state;

[0067] The eighth switching unit is configured to control the i-th second normal conductive via to be electrically connected to the i-th second primary node only when the eighth control signal is enabled;

[0068] The ninth switching unit is configured to output a ninth control signal in an enabled state only when the i-th second via state parameter group meets the ninth preset condition; wherein, the ninth preset condition means that the fifth state parameter and the sixth state parameter are both in a disabled state, and the seventh state parameter is in an enabled state;

[0069] The ninth switching unit is configured to control the i-th third normal conductive via to be electrically connected to the i-th second primary node only when the ninth control signal is enabled.

[0070] When any state parameter is in the enabled state, it indicates that the corresponding conductive via is not in failure; when any state parameter is in the disabled state, it indicates that the corresponding conductive via is in failure.

[0071] In some embodiments, the i-th fourth repair unit includes a tenth switching unit, an eleventh switching unit, a twelfth switching unit, a tenth logic unit, an eleventh logic unit, and a twelfth logic unit;

[0072] The tenth logic unit is configured to output a tenth control signal of the enable state only when the i-th second via state parameter group meets the tenth preset condition; wherein, the tenth preset condition means that the eighth state parameter is in the enable state and the seventh state parameter is in the disable state, or that both the seventh state parameter and the eighth state parameter are in the enable state and both the fifth state parameter and the sixth state parameter are in the disable state.

[0073] The tenth switching unit is configured to control the i-th third redundant conductive via to be electrically connected to the i-th third primary node only when the tenth control signal is enabled.

[0074] The eleventh logic unit is configured to output an eleventh control signal for an enable state only when the i-th second via state parameter group meets the eleventh preset condition; wherein, the eleventh preset condition means that the seventh state parameter is in an enable state, and at least one of the sixth state parameter and the fifth state parameter is in an enable state;

[0075] The eleventh switching unit is configured to control the i-th third normal conductive via to be electrically connected to the i-th third primary node only when the eleventh control signal is enabled.

[0076] The twelfth logic unit is configured to output an enable state twelfth control signal only when the i-th second via state parameter group meets the twelfth preset condition; wherein, the twelfth preset condition means that the eighth state parameter and the seventh state parameter are both disabled, and the sixth state parameter is enabled;

[0077] The twelfth switching unit is configured to control the i-th second normal conductive via to be electrically connected to the i-th third primary node only when the twelfth control signal is enabled.

[0078] In some embodiments, when the enable state is high and the disable state is low, the seventh logic unit includes a seventh NOT gate, a seventh AND gate, and a seventh OR gate; the eighth logic unit includes an eighth AND gate and an eighth OR gate; the ninth logic unit includes a ninth NOT gate and a ninth AND gate; the tenth logic unit includes a tenth NOT gate, a tenth AND gate, and a tenth OR gate; the eleventh logic unit includes an eleventh AND gate and an eleventh OR gate; and the twelfth logic unit includes a twelfth NOT gate and a twelfth AND gate.

[0079] The input terminal of the seventh NOT gate receives the sixth state parameter, the output terminal of the seventh NOT gate is connected to one input terminal of the seventh AND gate, the other input terminal of the seventh AND gate receives the fifth state parameter, the output terminal of the seventh AND gate and the output terminal of the twelfth AND gate are respectively connected to the two input terminals of the seventh OR gate, and the seventh OR gate outputs the seventh control signal;

[0080] The two inputs of the eighth OR gate receive the seventh state parameter and the eighth state parameter respectively. The output of the eighth OR gate is connected to one input of the eighth AND gate. The other input of the eighth AND gate receives the sixth state parameter. The eighth AND gate outputs the eighth control signal.

[0081] The input terminal of the ninth NOT gate is connected to the output terminal of the eleventh OR gate, the output terminal of the ninth NOT gate is connected to one input terminal of the ninth AND gate, the other input terminal of the ninth AND gate receives the seventh state parameter, and the ninth AND gate outputs the ninth control signal.

[0082] The input terminal of the tenth NOT gate receives the seventh state parameter, the output terminal of the tenth NOT gate is connected to one input terminal of the tenth AND gate, the other input terminal of the tenth AND gate receives the sixth state parameter, the output terminal of the tenth AND gate and the output terminal of the ninth AND gate are respectively connected to the two input terminals of the tenth OR gate, and the tenth OR gate outputs the tenth control signal;

[0083] The two inputs of the eleventh OR gate receive the fifth state parameter and the sixth state parameter respectively. The output of the eleventh OR gate is connected to one input of the eleventh AND gate. The other input of the eleventh AND gate receives the seventh state parameter. The eleventh AND gate outputs the eleventh control signal.

[0084] The input of the twelfth NOT gate is connected to the output of the eighth OR gate, the output of the twelfth NOT gate is connected to one input of the twelfth AND gate, the other input of the twelfth AND gate receives the sixth state parameter, and the twelfth AND gate outputs the twelfth control signal.

[0085] In some embodiments, the conductive vias are fabricated using any one or more of the following processes: via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same memory chip are electrically isolated from each other.

[0086] Secondly, this disclosure provides a logic chip, wherein the center point of the active surface of the logic chip and its adjacent area are defined as a global signal region, and the center point of the global signal region coincides with the center point of the active surface; the global signal region has a first axis and a second axis, the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to a first side of the logic chip, and the second axis is parallel to a second side of the logic chip;

[0087] The global signal region is penetrated by n conductive via groups along a third direction, the third direction being perpendicular to the active surface, where n is a positive integer;

[0088] Each of the aforementioned conductive via groups includes four normal conductive vias, wherein the first and second normal conductive vias are symmetrical about the first axis, the third and fourth normal conductive vias are symmetrical about the first axis, and the first and fourth normal conductive vias are symmetrical about the second axis.

[0089] The logic chip also includes n control circuits, and the internal circuits of the logic chip include n first signal ports, n second signal ports, n third signal ports and n fourth signal ports;

[0090] The i-th control circuit is configured to electrically connect the first normal conductive via, the second normal conductive via, the third normal conductive via, and the fourth normal conductive via in the i-th conductive via group to the i-th first signal port, the i-th second signal port, the i-th third signal port, and the i-th fourth signal port, respectively.

[0091] In some embodiments, each of the conductive via groups further includes 4a redundant conductive vias, wherein a first redundant conductive via and a second redundant conductive via are symmetrical about a first axis, a third redundant conductive via and a fourth redundant conductive via are symmetrical about the first axis, and a first redundant conductive via and a fourth redundant conductive via are symmetrical about a second axis.

[0092] A first redundant conductive via, a second redundant conductive via, a first normal conductive via, and a second normal conductive via constitute a repair unit; a third redundant conductive via, a fourth redundant conductive via, a third normal conductive via, and a fourth normal conductive via constitute another repair unit.

[0093] The i-th control circuit is further configured to, when any of the normal conductive vias fails, use other conductive vias of the same repair unit to replace the failed normal conductive via and electrically connect it to the corresponding signal port.

[0094] In some embodiments, when a = 1,

[0095] The control circuit is specifically configured such that if the first normal conductive via fails, the first redundant conductive via or the fourth normal conductive via is used to replace the first normal conductive via and electrically connect to the corresponding signal port.

[0096] If the fourth normal conductive via fails, the fourth redundant conductive via or the first normal conductive via is used to replace the fourth normal conductive via and electrically connect to the corresponding signal port.

[0097] If the second normal conductive via fails, the second redundant conductive via or the third normal conductive via is used to replace the second normal conductive via and electrically connect to the corresponding signal port.

[0098] If the third normal conductive via fails, the third redundant conductive via or the second normal conductive via is used to replace the third normal conductive via and electrically connect to the corresponding signal port.

[0099] In some embodiments, the i-th control circuit includes an i-th first control circuit and an i-th second control circuit;

[0100] For the i-th first control circuit, one side is coupled to the first normal conductive via, the fourth normal conductive via, the first redundant conductive via, and the fourth redundant conductive via in the i-th conductive via group, and the other side is coupled to the i-th first signal port and the i-th fourth signal port; the i-th first control circuit is configured to receive and, based on the i-th first via state parameter group, electrically connect one of the coupled conductive vias to the i-th first signal port, and electrically connect the other coupled conductive via to the i-th fourth signal port;

[0101] For the i-th second control circuit, one side is coupled to the second normal conductive via, the third normal conductive via, the second redundant conductive via, and the third redundant conductive via in the i-th conductive via group, and the other side is coupled to the i-th second signal port and the i-th third signal port; the i-th second control circuit is configured to receive and, based on the i-th second via state parameter group, electrically connect one of the coupled conductive vias to the i-th second signal port, and electrically connect the other coupled conductive via to the i-th third signal port.

[0102] In some embodiments, the i-th first control circuit includes an i-th first repair circuit and an i-th second repair circuit;

[0103] For the i-th first repair circuit, one side is coupled to the first redundant conductive via, the first normal conductive via, and the fourth normal conductive via in the i-th conductive via group, and the other side is coupled to the i-th first signal port; the first repair circuit is configured to receive and electrically connect one of the coupled conductive vias to the i-th first signal port based on the i-th first via state parameter group.

[0104] For the i-th second repair circuit, one side is coupled to the first normal conductive via, the fourth normal conductive via, and the fourth redundant conductive via in the i-th conductive via group, and the other side is coupled to the i-th four signal port; the second repair circuit is configured to receive and, based on the i-th first via state parameter group, electrically connect one of the coupled conductive vias to the i-th fourth signal port.

[0105] In some embodiments, the i-th first via state parameter group includes a first state parameter, a second state parameter, a third state parameter, and a fourth state parameter, which correspond one-to-one to indicate whether the first redundant conductive via, the first normal conductive via, the fourth normal conductive via, and the fourth redundant conductive via in the i-th conductive via group are ineffective.

[0106] The i-th first repair circuit includes a first switching unit, a second switching unit, a third switching unit, a first logic unit, a second logic unit, and a third logic unit;

[0107] The first logic unit is configured to output a first control signal of an enable state only when the i-th first via state parameter group meets a first preset condition; wherein, the first preset condition means that the first state parameter is in an enable state and the second state parameter is in a disabled state, or, the first state parameter and the second state parameter are both in an enable state and the third state parameter and the fourth state parameter are both in a disabled state.

[0108] The first switching unit is configured to control the i-th first redundant conductive via to be electrically connected to the i-th first signal port only when the first control signal is enabled.

[0109] The second logic unit is configured to output a second control signal for an enabled state only when the i-th first via state parameter group meets the second preset condition; wherein, the second preset condition means that the second state parameter is in an enabled state, and at least one of the third state parameter and the fourth state parameter is in an enabled state;

[0110] The second switching unit is configured to control the first normal conductive via to be electrically connected to the first signal port only when the second control signal is enabled;

[0111] The third logic unit is configured to output a third control signal of an enabled state only when the i-th first via state parameter group meets a third preset condition; wherein, the third preset condition means that both the first state parameter and the second state parameter are in a disabled state, and the third state parameter is in an enabled state;

[0112] The third switching unit is configured to control the i-th fourth normal conductive via to be electrically connected to the i-th first signal port only when the third control signal is enabled.

[0113] When any state parameter is in the enabled state, it indicates that the corresponding conductive via is not in failure; when any state parameter is in the disabled state, it indicates that the corresponding conductive via is in failure.

[0114] In some embodiments, the i-th second repair circuit includes a fourth switching unit, a fifth switching unit, a sixth switching unit, a fourth logic unit, a fifth logic unit, and a sixth logic unit;

[0115] The fourth logic unit is configured to output a fourth control signal of the enable state only when the i-th first via state parameter group meets the fourth preset condition; wherein, the fourth preset condition means that the fourth state parameter is in the enable state and the third state parameter is in the disable state, or, when both the fourth state parameter and the third state parameter are in the enable state and both the second state parameter and the first state parameter are in the disable state.

[0116] The fourth switching unit is configured to control the i-th fourth redundant conductive via to be electrically connected to the i-th fourth signal port only when the fourth control signal is enabled.

[0117] The fifth logic unit is configured to output a fifth control signal for an enabled state only when the i-th first via state parameter group meets a fifth preset condition; wherein, the fifth preset condition means that the third state parameter is in an enabled state, and at least one of the second state parameter and the first state parameter is in an enabled state;

[0118] The fifth switching unit is configured to control the i-th fourth normal conductive via to be electrically connected to the i-th fourth signal port only when the fifth control signal is enabled;

[0119] The sixth switching unit is configured to output a sixth control signal in an enabled state only when the i-th first through-hole state parameter group meets the sixth preset condition; wherein, the sixth preset condition means that the fourth state parameter and the third state parameter are both in a disabled state, and the second state parameter is in an enabled state;

[0120] The sixth switching unit is configured to control the first normal conductive via to be electrically connected to the first fourth signal port only when the sixth control signal is enabled.

[0121] In some embodiments, when the enable state is high and the disable state is low, the first logic unit includes a first NOT gate, a first AND gate, and a first OR gate; the second logic unit includes a second AND gate and a second OR gate; the third logic unit includes a third NOT gate and a third AND gate; the fourth logic unit includes a fourth NOT gate, a fourth AND gate, and a fourth OR gate; the fifth logic unit includes a fifth AND gate and a fifth OR gate; and the third logic unit includes a sixth NOT gate and a sixth AND gate.

[0122] The input terminal of the first NOT gate receives the second state parameter, the output terminal of the first NOT gate is connected to one input terminal of the first AND gate, the other input terminal of the first AND gate receives the first state parameter, the output terminal of the first AND gate and the output terminal of the sixth AND gate are respectively connected to the two input terminals of the first OR gate, and the first OR gate outputs the first control signal.

[0123] The two inputs of the second OR gate receive the third state parameter and the fourth state parameter respectively. The output of the second OR gate is connected to one input of the second AND gate. The other input of the second AND gate receives the second state parameter. The second AND gate outputs the second control signal.

[0124] The input terminal of the third NOT gate is connected to the output terminal of the fifth OR gate, the output terminal of the third NOT gate is connected to one input terminal of the third AND gate, the other input terminal of the third AND gate receives the third state parameter, and the third AND gate outputs the third control signal;

[0125] The input terminal of the fourth NOT gate receives the third state parameter, the output terminal of the fourth NOT gate is connected to one input terminal of the fourth AND gate, the other input terminal of the fourth AND gate receives the fourth state parameter, the output terminal of the fourth AND gate and the output terminal of the third AND gate are respectively connected to the two input terminals of the fourth OR gate, and the fourth OR gate outputs the fourth control signal;

[0126] The two inputs of the fifth OR gate receive the first state parameter and the second state parameter respectively. The output of the fifth OR gate is connected to one input of the fifth AND gate. The other input of the fifth AND gate receives the third state parameter. The fifth AND gate outputs the fifth control signal.

[0127] The input of the sixth NOT gate is connected to the output of the second OR gate, the output of the sixth NOT gate is connected to one input of the sixth AND gate, the other input of the sixth AND gate receives the second state parameter, and the sixth AND gate outputs the sixth control signal.

[0128] In some embodiments, the i-th second control circuit includes an i-th third repair unit and an i-th fourth repair unit;

[0129] For the i-th third repair unit, one side is coupled to the second redundant conductive via, the first normal conductive via, and the second normal first state parameter via in the i-th conductive via group, and the other side is coupled to the i-th second signal port; the third repair unit is configured to receive and, based on the second via state parameter group, electrically connect one of the coupled conductive vias to the i-th second signal port.

[0130] For the i-th fourth repair unit, one side is coupled to the second normal conductive via, the normal conductive via, and the third redundant conductive via in the i-th conductive via group, and the other side is coupled to the i-th third signal port; the fourth repair unit is configured to receive and, based on the second via state parameter group, electrically connect one of the coupled conductive vias to the i-th third signal port.

[0131] In some embodiments, the i-th second via state parameter group includes a fifth state parameter, a sixth state parameter, a seventh state parameter, and an eighth state parameter, which correspond one-to-one to indicate whether the second redundant conductive via, the second normal conductive via, the third normal conductive via, and the third redundant conductive via in the i-th conductive via group are ineffective.

[0132] The i-th third repair unit includes a seventh switching unit, an eighth switching unit, a ninth switching unit, a seventh logic unit, an eighth logic unit, and a ninth logic unit;

[0133] The seventh logic unit is configured to output a seventh control signal of the enable state only when the i-th second via state parameter group meets the seventh preset condition; wherein, the seventh preset condition means that the fifth state parameter is in the enable state and the sixth state parameter is in the disable state, or that both the fifth state parameter and the sixth state parameter are in the enable state and both the seventh state parameter and the eighth state parameter are in the disable state.

[0134] The seventh switching unit is configured to control the i-th second redundant conductive via to be electrically connected to the i-th second signal port only when the seventh control signal is enabled.

[0135] The eighth logic unit is configured to output an eighth control signal of the enable state only when the i-th second via state parameter group meets the eighth preset condition; wherein, the eighth preset condition means that the sixth state parameter is in the enable state, and at least one of the seventh state parameter and the eighth state parameter is in the enable state;

[0136] The eighth switching unit is configured to control the i-th second normal conductive via to be electrically connected to the i-th second signal port only when the eighth control signal is enabled;

[0137] The ninth logic unit is configured to output a ninth control signal in an enabled state only when the i-th second via state parameter group meets the ninth preset condition; wherein, the ninth preset condition means that the fifth state parameter and the sixth state parameter are both in a disabled state, and the seventh state parameter is in an enabled state;

[0138] The ninth switching unit is configured to control the third normal conductive via to be electrically connected to the i-th second signal port only when the ninth control signal is enabled;

[0139] When any state parameter is in the enabled state, it indicates that the corresponding conductive via is not in failure; when any state parameter is in the disabled state, it indicates that the corresponding conductive via is in failure.

[0140] In some embodiments, the fourth repair unit includes a tenth switching unit, an eleventh switching unit, a twelfth switching unit, a tenth logic unit, an eleventh logic unit, and a twelfth logic unit;

[0141] The tenth logic unit is configured to output a tenth control signal for an enabled state only when the i-th second via state parameter group meets the tenth preset condition; wherein, the tenth preset condition refers to when the eighth state parameter is enabled and the seventh state parameter is disabled, or when both the eighth state parameter and the seventh state parameter are enabled and both the sixth state parameter and the fifth state parameter are disabled.

[0142] The tenth switching unit is configured to control the i-th third redundant conductive via to be electrically connected to the i-th third signal port only when the tenth control signal is enabled.

[0143] The eleventh logic unit is configured to output an eleventh control signal for an enable state only when the i-th second via state parameter group meets the eleventh preset condition; wherein, the eleventh preset condition means that the seventh state parameter is in an enable state, and at least one of the sixth state parameter and the fifth state parameter is in an enable state;

[0144] The eleventh switching unit is configured to control the i-th third normal conductive via to be electrically connected to the i-th third signal port only when the eleventh control signal is enabled.

[0145] The twelfth logic unit is configured to output an enable state twelfth control signal only when the i-th second via state parameter group meets the twelfth preset condition; wherein, the twelfth preset condition means that the eighth state parameter and the seventh state parameter are both disabled, and the sixth state parameter is enabled;

[0146] The twelfth switching unit is configured to control the i-th second normal conductive via to be electrically connected to the i-th third signal port only when the twelfth control signal is enabled.

[0147] In some embodiments, when the enable state is high and the disable state is low, the seventh logic unit includes a seventh NOT gate, a seventh AND gate, and a seventh OR gate; the eighth logic unit includes an eighth AND gate and an eighth OR gate; the ninth logic unit includes a ninth NOT gate and a ninth AND gate; the tenth logic unit includes a tenth NOT gate, a tenth AND gate, and a tenth OR gate; the eleventh logic unit includes an eleventh AND gate and an eleventh OR gate; and the twelfth logic unit includes a twelfth NOT gate and a twelfth AND gate.

[0148] The input of the seventh NOT gate receives the sixth state parameter; the output of the seventh NOT gate is connected to one input of the seventh AND gate; the other input of the seventh AND gate receives the fifth state parameter; the outputs of the seventh AND gate and the twelfth AND gate are respectively connected to the two inputs of the seventh OR gate; the seventh OR gate outputs the seventh control signal. The two inputs of the eighth OR gate receive the seventh state parameter and the eighth state parameter respectively; the output of the eighth OR gate is connected to one input of the eighth AND gate; the other input of the eighth AND gate receives the sixth state parameter; the eighth AND gate outputs the eighth control signal. The input of the ninth NOT gate is connected to the output of the eleventh OR gate; the output of the ninth NOT gate is connected to one input of the ninth AND gate; the other input of the ninth AND gate receives the seventh state parameter; the ninth AND gate outputs the ninth control signal.

[0149] The input of the tenth NOT gate receives the seventh state parameter, the output of the tenth NOT gate is connected to one input of the tenth AND gate, the other input of the tenth AND gate receives the sixth state parameter, the output of the tenth AND gate and the output of the ninth AND gate are respectively connected to the two inputs of the tenth OR gate, and the tenth OR gate outputs the tenth control signal; the two inputs of the eleventh OR gate receive the fifth state parameter and the sixth state parameter respectively, the output of the eleventh OR gate is connected to one input of the eleventh AND gate, the other input of the eleventh AND gate receives the seventh state parameter, and the eleventh AND gate outputs the eleventh control signal; the input of the twelfth NOT gate is connected to the output of the eighth OR gate, the output of the twelfth NOT gate is connected to one input of the twelfth AND gate, the other input of the twelfth AND gate receives the sixth state parameter, and the twelfth AND gate outputs the twelfth control signal.

[0150] Thirdly, embodiments of this disclosure provide a chip stacking structure, the chip stacking structure including a logic chip as described in the second aspect and at least one stacking unit, wherein the logic chip and at least one stacking unit are stacked sequentially along a third direction; each stacking unit includes a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip stacked sequentially along the third direction, the third direction being perpendicular to the top surface of each memory chip; the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are all memory chips as described in the first aspect;

[0151] The first memory chip and the second memory chip are stacked face-to-face, the second memory chip and the third memory chip are stacked back-to-back, and the third memory chip and the fourth memory chip are stacked face-to-face.

[0152] The first memory chip and the logic chip in the first stacking unit are stacked back to back, or the first memory chip and the logic chip in the first stacking unit are stacked back to back.

[0153] In some embodiments, the chip location identifier of the first memory chip indicates a first type of location, the chip location identifier of the second memory chip indicates a second type of location, the chip location identifier of the third memory chip indicates a third type of location, and the chip location identifier of the fourth memory chip indicates a fourth type of location; or, the chip location identifier of the first memory chip indicates a first type of location, the chip location identifier of the second memory chip indicates a fourth type of location, the chip location identifier of the third memory chip indicates a third type of location, and the chip location identifier of the fourth memory chip indicates a second type of location.

[0154] In some embodiments, where the logic chip and the first memory chip are stacked back-to-back,

[0155] The fourth normal conductive via in the i-th conductive via group of the logic chip, the first normal conductive via in the i-th conductive via group of each first memory chip, the second normal conductive via in the i-th conductive via group of each second memory chip, the third normal conductive via in the i-th conductive via group of each third memory chip, and the fourth normal conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a normal signal transmission channel;

[0156] The third normal conductive via in the i-th conductive via group of the logic chip, the second normal conductive via in the i-th conductive via group of each first memory chip, the first normal conductive via in the i-th conductive via group of each second memory chip, the fourth normal conductive via in the i-th conductive via group of each third memory chip, and the third normal conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a normal signal transmission channel;

[0157] The second normal conductive via in the i-th conductive via group of the logic chip, the third normal conductive via in the i-th conductive via group of each first memory chip, the fourth normal conductive via in the i-th conductive via group of each second memory chip, the first normal conductive via in the i-th conductive via group of each third memory chip, and the second normal conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a normal signal transmission channel;

[0158] The first normal conductive via in the i-th conductive via group of the logic chip, the fourth normal conductive via in the i-th conductive via group of each first memory chip, the third normal conductive via in the i-th conductive via group of each second memory chip, the second normal conductive via in the i-th conductive via group of each third memory chip, and the first normal conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a normal signal transmission channel;

[0159] Where i is a positive integer less than or equal to n.

[0160] In some embodiments, the fourth redundant conductive via in the i-th conductive via group of the logic chip, the first redundant conductive via in the i-th conductive via group of each first memory chip, the second redundant conductive via in the i-th conductive via group of each second memory chip, the third redundant conductive via in the i-th conductive via group of each third memory chip, and the fourth redundant conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a redundant signal transmission channel;

[0161] The third redundant conductive via in the i-th conductive via group of the logic chip, the second redundant conductive via in the i-th conductive via group of each first memory chip, the first redundant conductive via in the i-th conductive via group of each second memory chip, the fourth redundant conductive via in the i-th conductive via group of each third memory chip, and the third redundant conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a redundant signal transmission channel.

[0162] The second redundant conductive via in the i-th conductive via group of the logic chip, the third redundant conductive via in the i-th conductive via group of each first memory chip, the fourth redundant conductive via in the i-th conductive via group of each second memory chip, the first redundant conductive via in the i-th conductive via group of each third memory chip, and the second redundant conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a redundant signal transmission channel;

[0163] The first redundant conductive via in the i-th conductive via group of the logic chip, the fourth redundant conductive via in the i-th conductive via group of each first memory chip, the third redundant conductive via in the i-th conductive via group of each second memory chip, the second redundant conductive via in the i-th conductive via group of each third memory chip, and the first redundant conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a redundant signal transmission channel.

[0164] In some embodiments, where the logic chip and the first memory chip are stacked back-to-back,

[0165] The second normal conductive via in the i-th conductive via group of the logic chip, the first normal conductive via in the i-th conductive via group of each first memory chip, the second normal conductive via in the i-th conductive via group of each second memory chip, the third normal conductive via in the i-th conductive via group of each third memory chip, and the fourth normal conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a normal signal transmission channel;

[0166] The first normal conductive via in the i-th conductive via group of the logic chip, the second normal conductive via in the i-th conductive via group of each first memory chip, the first normal conductive via in the i-th conductive via group of each second memory chip, the fourth normal conductive via in the i-th conductive via group of each third memory chip, and the third normal conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a normal signal transmission channel;

[0167] The fourth normal conductive via in the i-th conductive via group of the logic chip, the third normal conductive via in the i-th conductive via group of each first memory chip, the fourth normal conductive via in the i-th conductive via group of each second memory chip, the first normal conductive via in the i-th conductive via group of each third memory chip, and the second normal conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a normal signal transmission channel;

[0168] The third normal conductive via in the i-th conductive via group of the logic chip, the fourth normal conductive via in the i-th conductive via group of each first memory chip, the third normal conductive via in the i-th conductive via group of each second memory chip, the second normal conductive via in the i-th conductive via group of each third memory chip, and the first normal conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a normal signal transmission channel.

[0169] In some embodiments, the second redundant conductive via in the i-th conductive via group of the logic chip, the first redundant conductive via in the i-th conductive via group of each first memory chip, the second redundant conductive via in the i-th conductive via group of each second memory chip, the third redundant conductive via in the i-th conductive via group of each third memory chip, and the fourth redundant conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a redundant signal transmission channel;

[0170] The first redundant conductive via in the i-th conductive via group of the logic chip, the second redundant conductive via in the i-th conductive via group of each first memory chip, the first redundant conductive via in the i-th conductive via group of each second memory chip, the fourth redundant conductive via in the i-th conductive via group of each third memory chip, and the third redundant conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a redundant signal transmission channel.

[0171] The fourth redundant conductive via in the i-th conductive via group of the logic chip, the third redundant conductive via in the i-th conductive via group of each first memory chip, the fourth redundant conductive via in the i-th conductive via group of each second memory chip, the first redundant conductive via in the i-th conductive via group of each third memory chip, and the second redundant conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a redundant signal transmission channel;

[0172] The third redundant conductive via in the i-th conductive via group of the logic chip, the fourth redundant conductive via in the i-th conductive via group of each first memory chip, the third redundant conductive via in the i-th conductive via group of each second memory chip, the second redundant conductive via in the i-th conductive via group of each third memory chip, and the first redundant conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a redundant signal transmission channel.

[0173] In some embodiments, for two chips connected face-to-face, the conductive vias aligned along the third direction are electrically connected using a hybrid bonding process; for two chips connected back-to-back or back-to-face, the conductive vias aligned along the third direction are electrically connected using a conductive bump bonding process; or...

[0174] For two chips connected face-to-face, or two chips connected back-to-back, or two chips connected back-to-face, the conductive vias aligned along the third direction are electrically connected using the hybrid bonding process; or,

[0175] For two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected back-to-face, the conductive vias aligned along the third direction are electrically connected through the conductive bump bonding process.

[0176] Fourthly, embodiments of this disclosure provide a memory comprising a chip stacking structure as described in any one of the third aspects.

[0177] This disclosure provides a memory chip, a logic chip, a chip stack structure, and a memory. Each conductive via in the global signal region transmits signals into the chip, improving signal transmission efficiency. Simultaneously, the symmetrically arranged conductive vias enable the chip stack structure formed by the memory chip to achieve signal rotation transmission through the direct connection configuration of the conductive vias, resulting in relatively low parasitic resistance and capacitance. Furthermore, the symmetrically arranged repair units enable redundancy repair functions for the above structure, improving the stability of the memory chip. Attached Figure Description

[0178] Figure 1 This is a schematic diagram of the structure of a chip;

[0179] Figure 2A A schematic diagram of a chip stacking structure Figure 1 ;

[0180] Figure 2B A schematic diagram of a chip stacking structure Figure 1 ;

[0181] Figure 3 A schematic diagram of a memory chip provided in an embodiment of this disclosure;

[0182] Figure 4 A schematic diagram of a global signal region in a memory chip provided in this disclosure embodiment. Figure 1 ;

[0183] Figure 5A A schematic diagram of a chip stack for a memory chip provided in an embodiment of this disclosure;

[0184] Figure 5B A schematic diagram of a chip stack for another memory chip provided in an embodiment of this disclosure;

[0185] Figure 6 Schematic diagram 2 of a global signal region in a memory chip provided in this embodiment of the present disclosure;

[0186] Figure 7 A schematic diagram of a selection circuit in a memory chip provided in an embodiment of this disclosure;

[0187] Figure 8 A partial structural schematic diagram of the first selection circuit provided in an embodiment of this disclosure;

[0188] Figures 9A to 9F A schematic diagram illustrating a repair process in a memory chip according to an embodiment of this disclosure;

[0189] Figure 10 A partial structural schematic diagram of the second selection circuit provided in an embodiment of this disclosure;

[0190] Figure 11 A schematic diagram of a logic chip provided in an embodiment of this disclosure;

[0191] Figure 12 A schematic diagram of a global signal region in a logic chip provided in this embodiment of the present disclosure. Figure 1 ;

[0192] Figure 13 A schematic diagram of a selection circuit in a logic chip provided in an embodiment of this disclosure;

[0193] Figure 14 A partial structural schematic diagram of the first control circuit provided in an embodiment of this disclosure;

[0194] Figure 15 A partial structural schematic diagram of the second control circuit provided in an embodiment of this disclosure;

[0195] Figure 16This is a schematic diagram of the composition of a chip stacking structure provided in an embodiment of the present disclosure;

[0196] Figure 17A / Figure 17B This is a detailed schematic diagram of the first chip stacking structure provided in the embodiments of this disclosure;

[0197] Figure 18A / Figure 18B This is a detailed schematic diagram of the second chip stacking structure provided in the embodiments of this disclosure;

[0198] Figure 19 This is a schematic diagram of signal transmission in a chip stacking structure provided in an embodiment of the present disclosure;

[0199] Figure 20A / Figure 20B This is a schematic diagram illustrating the repair of a chip stacking structure according to an embodiment of the present disclosure;

[0200] Figure 21A / Figure 21B This is a detailed schematic diagram of the third chip stacking structure provided in the embodiments of this disclosure;

[0201] Figure 22A / Figure 22B This is a detailed schematic diagram of the fourth chip stacking structure provided in the embodiments of this disclosure;

[0202] Figure 23 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Detailed Implementation

[0203] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and are not intended to limit the scope of this disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0204] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0205] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0206] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0207] Before introducing the embodiments of this disclosure, we first define three directions that may be used in the plane to describe the three-dimensional structure in the following embodiments. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0208] Please see Figure 1 A semiconductor chip (specifically, a memory chip or a logic chip) may include a top surface on the front side and a bottom surface on the back side opposite to the front side. Ignoring the flatness of the top and bottom surfaces, the direction intersecting (e.g., perpendicular) with the top and bottom surfaces of the semiconductor chip is defined as a third direction. On the top surface of the semiconductor chip, two mutually perpendicular directions are defined, namely a first direction and a second direction, where the first direction is perpendicular to one edge of the semiconductor chip, and the second direction is perpendicular to the other edge of the semiconductor chip.

[0209] Please see Figure 1 A semiconductor chip includes a substrate, one side of which is used to fabricate devices (such as transistors, capacitors, etc.) forms an active surface. Multiple metal layers, such as M1, M2, M3, etc., are distributed between the substrate and its top surface. Figure 1 The diagram also shows two types of conductive vias (e.g., silicon conductive vias), both used to enable signal connections between different stacked chips.

[0210] like Figure 1 As shown, for a type 1 conductive via, it penetrates the bottom surface and the top surface in a third direction, and the conductive via is connected to the internal circuitry of the chip through a metal layer.

[0211] like Figure 1 As shown, for type 2 conductive vias that penetrate the substrate only along a third direction, signal transmission is achieved in conjunction with a contact structure that penetrates the top surface along the third direction. The contact structure and the conductive via are not directly electrically connected, but rather indirectly connected through a metal layer. For example: Figure 1 The contact structure is connected to M4, and M4 is connected to M1 via M3 and M2 in sequence. M1 is then connected to the conductive via. Of course, in other embodiments, the contact structure and the conductive via can also be designed to be directly electrically connected.

[0212] Furthermore, the types of conductive vias are not limited to the two types mentioned above; the examples are merely illustrative. In particular, the illustrations presented in this disclosure are not intended to be actual views of any particular microelectronic device or its components, but are merely idealized representations used to describe illustrative embodiments. Therefore, the drawings are not necessarily to scale.

[0213] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0214] In one embodiment, a memory chip and a logic chip are provided. Both the memory chip and the logic chip include multiple conductive vias extending through the chip in a third direction. These conductive vias are used to enable signal transmission between different chips, and all conductive vias can be located at any position. Specifically, every four conductive vias can be functionally considered as a group of conductive vias, but the individual positions of these four conductive vias are not limited.

[0215] In one specific embodiment, eight of the aforementioned memory chips and one logic chip are stacked to form a 3D memory device. Simultaneously, the conductive vias of the eight memory chips are aligned along a third direction, and the nine aligned conductive vias along the third direction are connected to form an electrical path. See also... Figure 2A This illustrates a signal transmission diagram of a chip stacking structure. (Example) Figure 2A As shown, the chip stacking structure includes memory chips 0-7 and logic chips. Figure 2A For each memory chip, only 4 conductive vias D0 to D3 are shown, and these 4 conductive vias D0 to D3 belong to the same conductive via group. At this time, the conductive vias D0 in 8 memory chips and 1 logic chip are aligned to form a single electrical path, and the conductive vias D1 in 8 memory chips and 1 logic chip are aligned to form a single electrical path... The remaining conductive vias are similar.

[0216] At the same time, each memory chip and logic chip is also equipped with multiple driver circuits. Figure 2A Only one driving circuit is shown in the image (the rest are not shown), and each conductive via is connected to one driving circuit; each memory chip also has multiple data selectors (e.g., Figure 2A In the configuration (mux0~7), each via group corresponds to one data selector. That is, all the vias in a via group are connected to the data port of the data selector through their respective drive circuits. In other words, the data selector can choose which via transmits the signal to the memory chip or which via outputs the signal from the memory chip.

[0217] For the overall storage device, different regions in different memory chips are managed by different channels (e.g., CH0, CH1, CH4, CH5). The signal Signal_CH0 of channel CH0 is transmitted through an electrical path consisting of "conductive via D0 in the logic chip, conductive via D0 in memory chip 0, conductive via D0 in memory chip 1, conductive via D0 in memory chip 2, conductive via D0 in memory chip 3, conductive via D0 in memory chip 4, conductive via D0 in memory chip 5, conductive via D0 in memory chip 6, and conductive via D0 in memory chip 7". The selection signals of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 are both SEL_C0, that is, the signal Signal_CH0 can enter memory chip 0 and memory chip 4 through the aforementioned electrical path; the signal output process can be understood similarly.

[0218] As can be seen from the above, memory chip 0 only needs to obtain signals from conductive via D0, memory chip 1 only needs to obtain signals from conductive via D1, and so on. That is, each memory chip only needs to obtain signals from one of the conductive vias in a group of conductive vias. It is worth noting that different memory chips may need to obtain signals from different conductive vias. However, since all memory chips need to be designed with the exact same structure during manufacturing (to maximize cost and labor savings), all conductive vias in the memory chip need to be designed with corresponding drive structures and data selectors to achieve structural consistency. Furthermore, when using… Figure 2A In the chip stacking structure shown, each conductive via corresponds to a driving circuit. During the operation of this chip stacking structure, it is necessary to drive all the driving circuits of all memory chips in the same channel. This results in a large load and large parasitic capacitance, which seriously affects the performance of the chips, restricts the transmission efficiency, increases power consumption, and also limits the number of chips stacked in the three-dimensional device.

[0219] In another embodiment, please refer to Figure 2B This illustrates signal transmission in another chip stacking structure. Specifically, Figure 2B Only some conductive vias (D0~D3) are marked; others are omitted. However, for... Figure 4 For example, the markings for conductive vias aligned along a third direction are the same. Figure 2BAs shown, the chip stack structure also includes eight memory chips and one logic chip aligned along a third direction. However, the conductive vias in each memory chip are rotatably connected to another conductive via at a different position in another memory chip, achieving a spiral upward connection as a whole. That is, the signal Signal_CH0 of channel CH0 is transmitted through “conductive via D0 in logic chip 0 – conductive via D1 in memory chip 0 – conductive via D2 in memory chip 1 – conductive via D3 in memory chip 2 – conductive via D0 in memory chip 3 – conductive via D1 in memory chip 4 – conductive via D2 in memory chip 5 – conductive via D3 in memory chip 6 – conductive via D0 in memory chip 7”, and the other signals are similar.

[0220] In this way, memory chip 0 can obtain the signal Signal_CH0 through the output terminal of the conductive via D0 in the logic chip, memory chip 1 can obtain the signal Signal_CH1 through the input terminal of the conductive via D0 in memory chip 0, memory chip 2 can obtain the signal Signal_CH4 through the input terminal of the conductive via D0 in memory chip 1, memory chip 3 can obtain the signal Signal_CH5 through the input terminal of the conductive via D0 in memory chip 2, and so on. For each memory chip, only one conductive via is needed to connect to the driving circuit in each group of conductive vias, and no data selector is required, which reduces the number of devices and thus reduces parasitic capacitance. However, compared to Figure 2A The conductive via direct connection configuration. Figure 2B The process of rotary connection of through-holes in medium-voltage systems is more complex, specifically... Figure 2B A horizontal interconnect structure needs to be set between adjacent conductive vias in each memory chip. Figure 2B (Only one is marked with a pentagram in the image). The signal interconnect structure can be a metal interconnect, a conductive via, etc. To achieve the rotating connection of the conductive via, the input signal signal_CH0 must first be transmitted upwards from the conductive via D0 of the logic chip to the interconnect structure below the conductive via D0 of the memory chip 0 (not directly connected to the conductive via D0 of the memory chip 0), and then horizontally transmitted from the interconnect structure below the conductive via D0 of the memory chip 0 to the conductive via D1 of the memory chip 0. That is: Figure 2B The structure shown requires the signal to pass through the interconnect structure in each memory chip during the signal transmission process, and the output signal is similar. This inevitably leads to an increase in parasitic resistance and also increases the complexity of the manufacturing process.

[0221] In particular, Figure 2A and Figure 2BIn the chip stacking structure, all chips are active-facing, meaning that different memory chips are stacked back-to-back, and memory chips and logic chips are also stacked back-to-back, that is, the bottom surface of the upper chip is in contact with the top surface of the lower chip.

[0222] In summary, on the one hand, Figure 2A The chip stacking structure requires numerous conductive vias to transmit the corresponding signals. Combined with the associated driver circuitry and data selectors, this results in a large load and parasitic capacitance. Figure 2B The chip stacking structure has a large parasitic resistance due to its rotational configuration; on the other hand... Figure 2A and Figure 2B All existing stacking structures have certain problems and cannot be directly applied to face-to-face stacking structures. Specifically, if we want to further realize face-to-face chip stacking structures, one approach is to use two sets of masks to create two different chips, one as the active-facing chip and the other as the active-facing chip. This approach has high process complexity and uncontrollable costs. Another approach is to create an additional set of conductive vias and connect both sets of conductive vias to the same driving circuit within the memory chip. However, this leads to complex internal wiring of the memory chip, increasing both process complexity and power consumption.

[0223] In another embodiment of this disclosure, see Figure 11 This illustration shows a structural schematic diagram of a memory chip 10 provided in an embodiment of this disclosure, which can be specifically understood as a cross-sectional schematic diagram of the active surface. For example... Figure 11 As shown, the memory chip 10 includes m channels ( Figure 11 (Taking m=4 as an example for illustration), m channels are arranged sequentially along the first direction. Each channel includes a first storage array area, a channel signal area, and a second storage array area distributed sequentially along the second direction. The center of each channel signal area coincides with the center of its respective channel.

[0224] The center of the active surface of the memory chip 10 and its adjacent area are defined as the global signal region 20, and the center point of the global signal region 20 coincides with the center point of the active surface; the m channels are symmetrical about the global signal region 20. Both the global signal region 20 and the channel signal regions are penetrated by a number of conductive vias along a third direction, and the third direction is perpendicular to the active surface.

[0225] Here, the conductive via can be a through-silicon via (TSV), specifically a vertical interconnect structure that penetrates a silicon wafer / chip. Alternatively, in other embodiments, it can be other conductive vias with conductive functions, without specific limitations. Furthermore, the conductive via can take the form of type 1 described above, or the form of type 2 described above.

[0226] For global signal region 20, each conductive via is used to transmit global signals, which are shared by all areas of the memory chip. Specifically, global signals include, but are not limited to: reset signals, power-on signals, stack identifier signals SID / CID, power-related signals Voltage Monitor, and timing-related signals Timing Aligner. In some cases, global signal region 20 may also refer to the pad area. Global signals can be test signals for Design for Test (DFT), through which the operating status of the internal circuitry and the transmission status of related signals can be determined. Furthermore, because the DFT pin pads in a logic chip are generally located in the middle of the chip, the conductive vias for global signals such as DFT are preferably located in a narrower area in the middle of the chip, i.e., ... Figure 3 The location of the global signal region 20 is shown. Conversely, for the channel signal region, each conductive via is used to transmit a channel signal, and each channel signal is only used by the corresponding channel.

[0227] Please see Figure 3 The active surface includes a first axis AA' and a second axis BB'. The first axis AA' is parallel to the first side of the logic chip 70, and the first axis AA' and the second axis BB' intersect each other perpendicularly at the center point of the active surface. Figure 3 In this embodiment, the first axis AA' extends along a first direction, and the second axis BB' extends along a second direction; in other embodiments, the first axis AA' may extend along a second direction, and the second axis BB' may extend along a first direction.

[0228] For the global signal region 20, the multiple conductive vias are divided into multiple conductive via groups. That is, the global signal region 20 is penetrated by n conductive via groups along a third direction, where n is a positive integer. Please refer to [link to relevant documentation]. Figure 4 Each conductive via group includes four normal conductive vias (D0, D1, D2, D3), and the first normal conductive via D0 and the second normal conductive via D1 are symmetrical about the first axis AA', the third normal conductive via D2 and the fourth normal conductive via D3 are symmetrical about the first axis AA', and the first normal conductive via D0 and the fourth normal conductive via D3 are symmetrical about the second axis BB'.

[0229] Please see Figure 4 The memory chip 10 also includes n selection circuits 30, and the internal circuitry of the memory chip 10 includes n internal port groups (In0 to In2). Due to space limitations, Figure 4 Only one group of conductive vias and one group of internal ports are shown.

[0230] The i-th selection circuit 30 is configured to receive and, based on the selection signal, electrically connect the four normal conductive vias in the i-th conductive via group to the four internal ports in the i-th internal port group, with the correspondence between the four normal conductive vias and the four internal ports determined based on the selection signal.

[0231] For ease of explanation, each i-th internal port group includes the i-th first internal port In0, the i-th second internal port In1In0, the i-th third internal port In3In1, and the i-th fourth internal port In3In2.

[0232] Please refer to Table 1. The i-th selection circuit is configured as follows: (1) If the selection signal is the first preset value, the first normal conductive via D0, the second normal conductive via D1, the third normal conductive via D2, and the fourth normal conductive via D3 in the i-th conductive via group are electrically connected to the i-th fourth internal port In3, the i-th third internal port In3, the i-th second internal port In1, and the i-th first internal port In0, respectively, i.e., case 1 in Table 1; (2) If the selection signal is the second preset value, the first normal conductive via D0, the second normal conductive via D1, the third normal conductive via D2, and the fourth normal conductive via D3 in the i-th conductive via group are electrically connected to the i-th second internal port In1, the i-th first internal port In0, the i-th fourth internal port In3, and the i-th third internal port In3, respectively, i.e., case 1 in Table 1; (3) If the selection signal is the second preset value, the first normal conductive via D0, the second normal conductive via D1, the third normal conductive via D2, and the fourth normal conductive via D3 in the i-th conductive via group are electrically connected to the i-th second internal port In1, the i-th first internal port In0, the i-th fourth internal port In3, and the i-th third internal port In3, respectively, i.e., case 1 in Table 1; Case 2 in 1; (3) If the selected signal is the third preset value, then the first normal conductive via D0, the second normal conductive via D1, the third normal conductive via D2, and the fourth normal conductive via D3 in the i-th conductive via group are electrically connected to the i-th third internal port In3, the i-th fourth internal port In3, the i-th first internal port In0, and the i-th second internal port In1, which is Case 3 in Table 1; (4) If the selected signal is the fourth preset value, then the first normal conductive via D0, the second normal conductive via D1, the third normal conductive via D2, and the fourth normal conductive via D3 in the i-th conductive via group are electrically connected to the i-th fourth internal port In3, the i-th third internal port In3, the i-th second internal port In1, and the i-th first internal port In0, which is Case 4 in Table 1.

[0233] Table 1

[0234] Case 1 Case 2 Case 3 Case 4 Select signal Se[1:0] 00 10 11 01 First internal port In0 D0 D1 D2 D3 Second internal port In1 D1 D0 D3 D2 Third internal port In3 D2 D3 D0 D1 Fourth internal port In3 D3 D2 D1 D0

[0235] Please refer to the above. Figure 2A or Figure 2BLogic chips and multiple memory chips 10 are stacked along a third direction to form a chip stack structure; in the chip stack structure, every four memory chips 10 form one stack unit. Each memory chip 10 has a chip location identifier (CID) and a chip location identifier (SID). The CID indicates the position of the memory chip 10 in its respective stack unit; the SID indicates the position of the stack unit to which the memory chip 10 belongs within its respective chip stack structure.

[0236] Taking a chip stacking unit consisting of one logic chip and eight memory chips 10 stacked together (each stacking unit consists of four memory chips 10, for a total of two stacking units) as an example, the CID has two sub-signals CID[1:0], the SID has two sub-signals SID[1:0], and the chip location identification code CID[1:0] is decoded from the chip location identification signal group CID0[3:0]. Specifically, during the normal operation phase of the memory chips 10, they are numbered from the logic chip side (i.e., from bottom to top), and the CID[1:0] and SID[1:0] of each chip are shown in Table 2. During the initialization phase of the memory chips 10, they are numbered from the side away from the logic chip (i.e., from top to bottom). This case is not shown for now, but it can be understood accordingly.

[0237] Table 2

[0238]

[0239] Specifically, in this embodiment, the different memory chips 10 are positioned differently in the chip stack structure. For ease of explanation, the active surface of each memory chip 10 (the plane containing the first and second directions) is divided into a low-order transmission region and a high-order transmission region. Please refer to [link to relevant documentation]. Figure 5A The arrow on each chip points to the high-order transmission area.

[0240] In this embodiment of the disclosure, the positions of the memory chips 10 are divided into four categories: the top surfaces of the memory chips in the first and third categories face upward along a third direction, and the top surfaces of the memory chips in the second and fourth categories face downward along a third direction; the active surface of each memory chip is divided into a low-level transmission region and a high-level transmission region, and the low-level transmission regions in the memory chips in the first category, the high-level transmission regions in the memory chips in the second category, the high-level transmission regions in the memory chips in the third category, and the low-level transmission regions in the memory chips in the fourth category are aligned along a third direction.

[0241] In one stacking method, please refer to Figure 5A(1) The first memory chip 11 is in the first type position, the second memory chip 12 is in the second type position, the third memory chip 13 is in the third type position, and the fourth memory chip 14 is in the fourth type position;

[0242] For another stacking method, please refer to Figure 5B (1) The first memory chip 11 is in the first type position, the second memory chip 12 is in the fourth type position, the third memory chip 13 is in the third type position, and the fourth memory chip 14 is in the second type position.

[0243] The storage chip 10 further includes a decoding circuit 21 configured to receive a chip location identification code CID[1:0]. If the chip location identification code CID[1:0] indicates a first type of location, the circuit outputs a selection signal with a first preset value; if the chip location identification code CID[1:0] indicates a second type of location, the circuit outputs a selection signal with a second preset value; if the chip location identification code CID[1:0] indicates a third type of location, the circuit outputs a selection signal with a third preset value; and if the chip location identification code CID[1:0] indicates a fourth type of location, the circuit outputs a selection signal that conforms to a fourth preset value.

[0244] In other embodiments, the decoding circuit 21 may also generate a selection signal based on CID0[3:0].

[0245] In some embodiments, see Figure 6 Each group of conductive vias also includes a first redundant conductive via R0, a second redundant conductive via R1, a third redundant conductive via R2 and a fourth redundant conductive via R3. Figure 6 We'll use a = 1 as an example for now, but a can take other positive integer values. For example... Figure 6 As shown, a first redundant conductive via R0 and a second redundant conductive via R1 are symmetrical about the first axis AA', a third redundant conductive via R2 and a fourth redundant conductive via R3 are symmetrical about the first axis AA', and a first redundant conductive via R0 and a fourth redundant conductive via R3 are symmetrical about the second axis BB'.

[0246] For each group of conductive vias, a first redundant conductive vias R0, a second redundant conductive vias R1, a first normal conductive vias D0 and a second normal conductive vias D1 constitute a repair unit, and a third redundant conductive vias R2, a fourth redundant conductive vias R3, a third normal conductive vias D2 and a fourth normal conductive vias D3 constitute another repair unit.

[0247] The selection circuit 30 is further configured to, when any normal conductive via fails, use other conductive vias of the same repair unit to replace the failed normal conductive via and electrically connect it to the corresponding internal port. For example, assuming the selection signal is a first preset value, if the first normal conductive via D0 is not failed, the selection circuit 30 electrically connects the first normal conductive via D0 to the first internal port In0; if the first normal conductive via D0 fails, it electrically connects other conductive vias of the same repair unit to the first internal port In0.

[0248] It should be noted that via failure refers to the failure of the signal transmission channel formed by the via and other vias aligned along a third direction (belonging to other memory chips). In other words, for multiple vias aligned along a third direction, damage to any one via will cause the signal transmission channel to fail, and the other vias will also fail even if they are not damaged.

[0249] Here, a normal conductive via refers to a conductive via designed from the outset to transmit valid signals, while a redundant conductive via refers to a conductive via designed from the outset not to transmit any signals. However, when any normal conductive via fails, a redundant conductive via can be converted into a normal conductive via to transmit valid signals, so that the memory can still function normally. That is, for the same repair unit, when any normal conductive via fails, the valid signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset switching direction. Specifically: (1) If the next conductive via being switched to is a redundant conductive via, the repair ends, and the redundant conductive via becomes a new normal conductive via; (2) If the next conductive via being switched to is another normal conductive via, the signal originally transmitted by the switched normal conductive via continues to be switched to its next conductive via along the preset switching direction.

[0250] Thus, via the selection circuit 30, any conductive via in any repair unit is electrically connected to the internal circuitry of the logic chip 10 when transmitting a valid signal, and is electrically isolated from the internal circuitry of the logic chip 10 when not transmitting a valid signal.

[0251] The following example, using a=1, provides a redundant repair logic example to better understand the foregoing explanation. However, this example is not the only solution. In this specific embodiment, each normal conductive via can be repaired via two other conductive vias; but this is merely an example. In other embodiments, more redundant conductive vias can be provided, or each normal conductive via can be repaired via an additional number of other conductive vias.

[0252] In some embodiments, see Figure 6The selection circuit 30 is specifically configured such that if the first normal conductive via D0 fails, a first redundant conductive via R0 or a fourth normal conductive via D3 is used to replace the first normal conductive via D0 and electrically connect it to the corresponding internal port; if the fourth normal conductive via D3 fails, a fourth redundant conductive via R3 or a first normal conductive via D0 is used to replace the fourth normal conductive via D3 and electrically connect it to the corresponding internal port; and if the second normal conductive via D1 fails, a second redundant conductive via R1 or a third normal conductive via D2 is used to replace the second normal conductive via D1 and electrically connect it to the corresponding internal port; and if the third normal conductive via D2 fails, a third redundant conductive via R2 or a second normal conductive via D1 is used to replace the third normal conductive via D2 and electrically connect it to the corresponding internal port.

[0253] It should be noted that if a normal conductive via is used to replace another failed normal conductive via, then another redundant conductive via is also needed to replace the fourth normal conductive via D3 in electrical connection to the corresponding internal port, until a redundant conductive via is enabled. For example, if the fourth normal conductive via D3 replaces the first normal conductive via D0 in electrical connection to the corresponding internal port, then it may also be necessary to enable the fourth redundant conductive via R3 in electrical connection to the fourth normal conductive via D3 in electrical connection to the corresponding internal port.

[0254] In this way, the repair unit in the logic chip 10 has a four-quadrant symmetry relationship, and the normal conductive vias therein also have a four-quadrant symmetry relationship. Thus, the chip stack structure formed by the logic chip and the memory chip 10 (which also has this characteristic) can achieve the signal rotation transmission effect through the direct connection configuration of the conductive vias. The parasitic resistance and parasitic capacitance are relatively small, as can be seen in the following description. At the same time, the redundancy repair function of the above structure can also be realized through the four-quadrant symmetrical repair unit, thereby improving the stability of the chip.

[0255] In one specific embodiment, please refer to Figure 7 The selection signals include a first selection signal Ch0 and a second selection signal Ch1. The i-th selection circuit 30 includes an i-th first selection circuit 31, an i-th second selection circuit 32, an i-th first signal output circuit 33, and an i-th second signal output circuit 34.

[0256] For the i-th first selection circuit 31, one side is coupled to the first normal conductive via D0, the fourth normal conductive via D3, the first redundant conductive via R0 and the fourth redundant conductive via R3 in the i-th conductive via group, and the other side is coupled to the i-th first secondary node Sec0 and the i-th fourth secondary node Sec3.

[0257] The i-th first selection circuit 31 is configured to receive and, based on the first via state parameter group and the first selection signal Ch0, electrically connect one of the coupled conductive vias to the i-th first secondary node Sec0, and electrically connect the other coupled conductive via to the i-th fourth secondary node Sec3.

[0258] For the i-th second selection circuit 32, one side is coupled to the second normal conductive via D1, the third normal conductive via D2, the second redundant conductive via R1 and the third redundant conductive via R2 in the i-th conductive via group, and the other side is coupled to the i-th second-level node Sec1 and the i-th third-level node Sec2.

[0259] The i-th second selection circuit 32 is configured to receive and, based on the second via state parameter group and the first selection signal Ch0, electrically connect one of the coupled conductive vias to the i-th second-level node Sec1, and electrically connect the other coupled conductive via to the i-th third-level node Sec2.

[0260] The i-th first signal output circuit 33 is configured to receive and, based on the second selection signal Ch1, electrically connect the i-th first primary node Sec0 to the i-th first internal port In0, and electrically connect the i-th fourth secondary node Sec3 to the i-th fourth internal port In3; or, electrically connect the i-th second primary node Sec1 to the i-th first internal port In0, and electrically connect the i-th third secondary node Sec2 to the i-th fourth internal port In3.

[0261] The i-th second signal output circuit 34 is configured to receive and, based on the second selection signal Ch1, electrically connect the i-th second secondary node Sec1 to the i-th second internal port In1, and electrically connect the i-th third secondary node Sec2 to the i-th third internal port In2; or, electrically connect the i-th first primary node Sec0 to the i-th second internal port In1, and electrically connect the i-th fourth secondary node Sec3 to the i-th third internal port In3.

[0262] Assuming that when a normal conductive via fails, it is preferentially repaired using another redundant conductive via; only if both the normal conductive via and the corresponding redundant conductive via fail will another normal conductive via be used for repair. The following provides a specific selection circuit.

[0263] Please see Figure 7 The i-th first selection circuit 31 includes the i-th first repair circuit 311, the i-th second repair circuit 312, and the i-th first selection output circuit 313;

[0264] For the i-th first repair circuit 311, one side is coupled to the first redundant conductive via R0, the first normal conductive via D0 and the fourth normal conductive via D3 in the i-th conductive via group, and the other side is coupled to the i-th first primary node Middle0; the first repair circuit 311 is configured to receive and, based on the i-th first via state parameter group, electrically connect one of the three coupled first normal conductive via D0, first redundant conductive via R0 and fourth normal conductive via D3 to the i-th first primary node Middle0;

[0265] For the i-th second repair circuit 312, one side is coupled to the first normal conductive via D0, the fourth normal conductive via D3, and the fourth redundant conductive via R3 in the i-th conductive via group, and the other side is coupled to the i-th fourth primary node Middle3; the second repair circuit 312 is configured to receive and, based on the i-th first via state parameter group, connect one of the three coupled to the i-th fourth primary node Middle3.

[0266] The i-th first selection output circuit 313 is configured to receive and select the first signal Ch0, and then electrically connect the i-th first primary node Middle0 to the i-th first secondary node Sec0, and electrically connect the i-th fourth primary node Middle3 to the i-th fourth secondary node Sec3; or, electrically connect the i-th fourth primary node Middle3 to the i-th first secondary node Sec0, and electrically connect the i-th first primary node Middle0 to the i-th fourth secondary node Sec3.

[0267] In one specific embodiment, the following premise is given: the first preset value refers to the selection signal Ch[1:0] = 00, the second preset value refers to the selection signal Ch[1:0] = 10, the third preset value refers to the selection signal Ch[1:0] = 11, and the fourth preset value refers to the selection signal Ch[1:0] = 01. For a feasible structure of the first selection output circuit 313, please refer to [link to relevant documentation]. Figure 8 .

[0268] like Figure 8As shown, each selection output circuit 313 may include four enable transmission gates. The first enable transmission gate is coupled between the first primary node Middle0 and the first secondary node Sec0; the second enable transmission gate is coupled between the first primary node Middle0 and the fourth secondary node Sec3; and the enable terminal of the first enable transmission gate receives the inverted signal of the first selection signal Ch0, while the enable terminal of the second enable transmission gate receives the first selection signal Ch0. The third enable transmission gate is coupled between the fourth primary node Middle3 and the first secondary node Sec0; the fourth enable transmission gate is coupled between the fourth primary node Middle3 and the fourth secondary node Sec3; and the enable terminal of the third enable transmission gate receives the first selection signal Ch0, while the enable terminal of the fourth enable transmission gate receives the inverted signal of the first selection signal Ch0. The structures of the first signal output unit 33 and the second signal output unit 34 are similar.

[0269] In one specific embodiment, the i-th first via state parameter group includes a first state parameter R0E, a second state parameter D0E, a third state parameter D3E, and a fourth state parameter R3E, which correspond one-to-one to indicate whether the first redundant conductive via R0, the first normal conductive via D0, the fourth normal conductive via D3, and the fourth redundant conductive via R3 in the i-th conductive via group are ineffective; when any state parameter is in an enabled state, it indicates that the corresponding conductive via is not ineffective; when any state parameter is in a disabled state, it indicates that the corresponding conductive via is ineffective.

[0270] Please see Figure 8 The i-th first repair circuit 311 includes a first switching unit 412, a second switching unit 422, a third switching unit 432, a first logic unit 411, a second logic unit 421, and a third logic unit 431;

[0271] The first logic unit 411 is configured to output a first control signal Ctr1 in an enabled state only when the state parameter group of the i-th first via meets the first preset condition; wherein, the first preset condition means that the first state parameter R0E is in an enabled state and the second state parameter D0E is in a disabled state, or that both the first state parameter R0E and the second state parameter D0E are in an enabled state and both the third state parameter D3E and the fourth state parameter R3E are in a disabled state; the first switching unit 412 is configured to control the i-th first redundant conductive via R0 to be electrically connected to the i-th first primary node Middle0 only when the first control signal Ctr1 is in an enabled state.

[0272] Thus, R0 replacing D0 (R0 is electrically connected to the first primary node Middle0) occurs in the following two cases: (1) R0 is not faulty and D0 is faulty, please refer to Figure 9A as well as Figure 9E(2) If R0 and D0 are not faulty but D3 and R3 are both faulty, then the faulty D0 needs to replace the faulty D3 and be electrically connected to the corresponding internal port. Therefore, R0 also needs to replace D0. Please refer to [link to relevant documentation]. Figure 9B .

[0273] The second logic unit 421 is configured to output a second control signal Ctr2 enabling state only when the state parameter group of the i-th first via meets the second preset condition; wherein, the second preset condition means that the second state parameter D0E is enabled, and at least one of the third state parameter D3E and the fourth state parameter R3E is enabled; the second switching unit 422 is configured to control the i-th first normal conductive via D0 to be electrically connected to the i-th first primary node Middle0 only when the second control signal Ctr2 is enabled.

[0274] Please see below. Figure 9C or Figure 9F D0 is working normally (D0 is electrically connected to the first primary node Middle0) when: (1) D0 is not faulty and at least one of D3 and R3 is not faulty.

[0275] The third logic unit 431 is configured to output a third control signal Ctr3 in an enabled state only when the state parameter group of the i-th first via meets the third preset condition; wherein, the third preset condition means that the first state parameter R0E and the second state parameter D0E are both disabled, and the third state parameter D3E is enabled; the third switching unit 432 is configured to control the i-th fourth normal conductive via D3 to be electrically connected to the i-th first primary node Middle0 only when the third control signal Ctr3 is enabled.

[0276] Please see below. Figure 9D When D3 replaces D0 (D3 is electrically connected to the first primary node Middle0), the following situations exist: (1) D0 and R0 both fail, but D3 does not fail.

[0277] Similarly, the i-th second repair circuit 312 includes a fourth switching unit 442, a fifth switching unit 452, a sixth switching unit 462, a fourth logic unit 441, a fifth logic unit 451, and a sixth logic unit 461;

[0278] The fourth logic unit 441 is configured to output an enable fourth control signal Ctr4 only when the state parameter group of the i-th first via meets the fourth preset condition; wherein, the fourth preset condition refers to when the fourth state parameter R3E is enabled and the third state parameter D3E is disabled, or when both the fourth state parameter R3E and the third state parameter D3E are enabled and both the second state parameter D0E and the first state parameter R0E are disabled; the fourth switching unit 442 is configured to control the i-th fourth redundant conductive via R3 to be electrically connected to the i-th fourth primary node Middle3 only when the fourth control signal Ctr4 is enabled.

[0279] Thus, R3 replacing D3 (R3 is electrically connected to the fourth primary node Middle3) occurs in the following two cases: (1) R3 is not faulty and D3 is faulty, see [link to relevant documentation] Figure 9F (2) R3 and D3 are not invalid and D0 and R0 are both invalid. At this time, the invalid D3 needs to replace the invalid D0 and be electrically connected to the corresponding internal port. Therefore, R3 also needs to replace D3 to work.

[0280] The fifth logic unit 451 is configured to output a fifth control signal Ctr5 in an enabled state only when the state parameter group of the i-th first via meets the fifth preset condition; wherein, the fifth preset condition means that the third state parameter D3E is in an enabled state, and at least one of the second state parameter D0E and the first state parameter R0E is in an enabled state; the fifth switching unit 452 is configured to control the i-th fourth normal conductive via D3 to be electrically connected to the i-th fourth primary node Middle3 only when the fifth control signal Ctr5 is in an enabled state.

[0281] Thus, D3 operates normally (D3 is electrically connected to the fourth primary node Middle3) under the following conditions: (1) D3 is not faulty, and at least one of D0 and R0 is not faulty. Please refer to [link to relevant documentation]. Figure 9C as well as Figure 9E .

[0282] The sixth switching unit 462 is configured to output a sixth control signal Ctr6 in an enabled state only when the state parameter group of the i-th first via meets the sixth preset condition; wherein, the sixth preset condition means that the fourth state parameter R3E and the third state parameter D3E are both disabled, and the second state parameter D0E is enabled; the sixth switching unit 462 is configured to control the i-th first normal conductive via D0 to be electrically connected to the i-th fourth primary node Middle3 only when the sixth control signal Ctr6 is enabled.

[0283] Thus, D0 replacing D3 and electrically connecting to the corresponding internal port occurs in the following situation (D0 is electrically connected to the fourth primary node Middle3): The following situation exists where both D3 and R3 fail, but D0 does not fail. Please refer to [link to relevant documentation]. Figure 9B .

[0284] For the following circuit settings: enable state is high level, disable state is low level, providing feasible structures for each of the above circuit units, but not the only structure.

[0285] like Figure 8 As shown, the first logic unit 411 includes a first NOT gate 501, a first AND gate 502, and a first OR gate 503; the second logic unit 421 includes a second AND gate 511 and a second OR gate 512; the third logic unit 431 includes a third NOT gate 521 and a third AND gate 522; the fourth logic unit 441 includes a fourth NOT gate 531, a fourth AND gate 532, and a fourth OR gate 533; the fifth logic unit 451 includes a fifth AND gate 541 and a fifth OR gate 542; and the sixth logic unit 461 includes a sixth NOT gate 551 and a sixth AND gate 552.

[0286] The input of the first NOT gate 501 receives the second state parameter D0E. The output of the first NOT gate 501 is connected to one input of the first AND gate 502. The other input of the first AND gate 502 receives the first state parameter R0E. The outputs of the first AND gate 502 and the sixth AND gate 552 are respectively connected to the two inputs of the first OR gate 503. The first OR gate 503 outputs the first control signal Ctr1. The two inputs of the second OR gate 512 receive the third state parameter D3E and the fourth state parameter R3E respectively. The output of the second OR gate 512 is connected to one input of the second AND gate 511. The other input of the second AND gate 511 receives the second state parameter D0E. The second AND gate 511 outputs the second control signal Ctr2. The input of the third NOT gate 521 is connected to the output of the fifth OR gate 542. The output of the third NOT gate 521 is connected to one input of the third AND gate 522. The other input of the third AND gate 522 receives the third state parameter D3E. The third AND gate 522 outputs the third control signal Ctr3.

[0287] The input of the fourth NOT gate 531 receives the third state parameter D3E. The output of the fourth NOT gate 531 is connected to one input of the fourth AND gate 532. The other input of the fourth AND gate 532 receives the fourth state parameter R3E. The outputs of the fourth AND gate 532 and the third AND gate 522 are respectively connected to the two inputs of the fourth OR gate 533. The fourth OR gate 533 outputs the fourth control signal Ctr4. The two inputs of the fifth OR gate 542 receive the first state parameter R0E and the second state parameter D0E respectively. The output of the fifth OR gate 542 is connected to one input of the fifth AND gate 541. The other input of the fifth AND gate 541 receives the third state parameter D3E. The fifth AND gate 541 outputs the fifth control signal Ctr5. The input of the sixth NOT gate 551 is connected to the output of the second OR gate 512. The output of the sixth NOT gate 551 is connected to one input of the sixth AND gate 552. The other input of the sixth AND gate 552 receives the second state parameter D0E. The sixth AND gate 552 outputs the sixth control signal Ctr6.

[0288] The second selection circuit 32 has a similar structure to the first selection circuit 31, and their working principles can be understood accordingly.

[0289] In some specific embodiments, such as Figure 10 As shown, the i-th second selection circuit 32 includes the i-th third repair unit 321, the i-th fourth repair unit 322, and the i-th second selection output circuit 323;

[0290] For the i-th third repair unit 321, one side is coupled to the second redundant conductive via R1, the first normal conductive via D0, and the second normal conductive via D1 in the i-th conductive via group, and the other side is coupled to the i-th second primary node Middle1; the third repair unit 321 is configured to receive and, based on the i-th second via state parameter group, electrically connect one of the three coupled second normal conductive via D1, second redundant conductive via R1, and third normal conductive via D2 to the i-th second primary node Middle1;

[0291] For the i-th fourth repair unit 322, one side is coupled to the second normal conductive via D1, the normal conductive via, and the third redundant conductive via R2 in the i-th conductive via group, and the other side is coupled to the i-th third primary node Middle3; the fourth repair unit 322 is configured to receive and, based on the i-th second via state parameter group, electrically connect one of the three coupled second normal conductive via D1, the third normal conductive via D2, and the third redundant conductive via R2 to the i-th third primary node Middle3;

[0292] The i-th second selection output circuit 323 is configured to receive and 20 the first selection signal Ch0, electrically connect the i-th second primary node Middle1 to the i-th second secondary node Sec1, and electrically connect the i-th third primary node Middle2 to the i-th third secondary node Sec2; or, electrically connect the i-th third primary node Middle2 to the i-th second secondary node Sec1, and electrically connect the i-th second primary node Middle1 to the i-th third secondary node Sec2.

[0293] Similarly, the second selection output circuit 323 also consists of four enable transmission gates, and its principle can be found in the description of the first selection output circuit 313 above.

[0294] In some embodiments, the i-th second via state parameter group includes a fifth state parameter R1E, ​​a sixth state parameter D1E, a seventh state parameter D2E, and an eighth state parameter R2E, which correspond one-to-one to indicate whether the second redundant conductive via R1, the second normal conductive via D1, the third normal conductive via D2, and the third redundant conductive via R2 in the i-th corresponding conductive via group are ineffective; when any state parameter is in an enabled state, it indicates that the corresponding conductive via is not ineffective; when any state parameter is in a disabled state, it indicates that the corresponding conductive via is ineffective.

[0295] Please see Figure 10 The i-th third repair unit 321 includes a seventh switching unit 612, an eighth switching unit 622, a ninth switching unit 632, a seventh logic unit 611, an eighth logic unit 621, and a ninth logic unit 631;

[0296] Please see Figure 10 The seventh logic unit 611 is configured to output a seventh control signal Ctr7 in an enabled state only when the state parameter group of the i-th second via meets the seventh preset condition; wherein, the seventh preset condition means that the fifth state parameter R1E is in an enabled state and the sixth state parameter D1E is in a disabled state, or, both the fifth state parameter R1E and the sixth state parameter D1E are in an enabled state and both the seventh state parameter D2E and the eighth state parameter R2E are in a disabled state; the i-th seventh switching unit 612 is configured to control the i-th second redundant conductive via R1 to be electrically connected to the i-th third primary node Middle2 only when the seventh control signal Ctr7 is in an enabled state.

[0297] Thus, R1 replacing D1 (R1 is electrically connected to the second primary node Middle1) occurs in the following two situations: (1) R1 is not faulty and D1 is faulty; (2) R1 and D1 are not faulty and D2 and R2 are both faulty. In this case, the faulty D1 needs to replace the faulty D2 and be electrically connected to the corresponding internal port, so R1 also needs to replace D1.

[0298] Please see Figure 10 The eighth logic unit 621 is configured to output an eighth control signal Ctr8 in an enabled state only when the state parameter group of the i-th second via meets the eighth preset condition; wherein, the eighth preset condition means that the sixth state parameter D1E is in an enabled state, and at least one of the seventh state parameter D2E and the eighth state parameter R2E is in an enabled state; the eighth switching unit 622 is configured to control the i-th second normal conductive via D1 to be electrically connected to the i-th third primary node Middle2 only when the eighth control signal Ctr8 is in an enabled state.

[0299] Thus, D1 works normally (D1 is electrically connected to the second primary node Middle1) under the following conditions: (1) D1 is not faulty and at least one of D2 and R2 is not faulty.

[0300] Please see Figure 10 The ninth logic unit 631 is configured to output the ninth control signal Ctr9, which is in an enabled state, only when the state parameter group of the i-th second via meets the ninth preset condition; wherein, the ninth preset condition means that the fifth state parameter R1E and the sixth state parameter D1E are both in a disabled state, and the seventh state parameter D2E is in an enabled state; the ninth switching unit 632 is configured to control the i-th third normal conductive via D2 to be electrically connected to the i-th third primary node Middle2 only when the ninth control signal Ctr9 is in an enabled state.

[0301] Thus, D2 replaces D1 and is electrically connected to the corresponding internal port in the following situations (D2 is electrically connected to the second primary node Middle1): (1) D1 and R1 are both unsuccessful, and D2 is not unsuccessful.

[0302] In one specific embodiment, please refer to Figure 10 The fourth repair unit 322 includes a tenth switching unit 642, an eleventh switching unit 652, a twelfth switching unit 662, a tenth logic unit 641, an eleventh logic unit 651, and a twelfth logic unit 661.

[0303] Please see Figure 10The tenth logic unit 641 is configured to output the seventh control signal Ctr7, which is in an enabled state, only when the state parameter group of the i-th second via meets the tenth preset condition; wherein, the fourth preset condition refers to the eighth state parameter R2E being in an enabled state and the seventh state parameter D2E being in a disabled state, or the eighth state parameter R2E and the seventh state parameter D2E being in an enabled state and the sixth state parameter D1E and the fifth state parameter R1E being in a disabled state; the tenth switching unit 642 is configured to control the i-th third redundant conductive via R2 to be electrically connected to the i-th fourth primary node only when the tenth control signal Ctr10 is in an enabled state.

[0304] Thus, R2 replacing D2 (R2 is electrically connected to the third primary node Middle2) occurs in the following two situations: (1) R2 is not faulty and D2 is faulty; (2) R2 and D2 are not faulty and D1 and R1 are both faulty. In this case, the faulty D2 needs to replace the faulty D1 and be electrically connected to the corresponding internal port, so R2 also needs to replace D2.

[0305] Please see Figure 10 The eleventh logic unit 651 is configured to output the eleventh control signal Ctr11, which is enabled, only under the eleventh preset condition of the eleventh state parameter group of the i-th second via. The eleventh preset condition means that the seventh state parameter D2E is enabled, and at least one of the sixth state parameter D1E and the fourth state parameter R3E is enabled. The eleventh switching unit 652 is configured to control the i-th third normal conductive via D2 to be electrically connected to the i-th fourth primary node only when the eleventh control signal Ctr11 is enabled.

[0306] Thus, D2 can function normally (D2 is electrically connected to the third primary node Middle2) under the following conditions: (1) D2 is not faulty and at least one of D1 and R1 is not faulty.

[0307] Please see Figure 10 The twelfth logic unit 661 is configured to output the twelfth control signal Ctr12, which is enabled, only under the twelfth preset condition of the twelfth state parameter group of the i-th second via. The twelfth preset condition means that the eighth state parameter R2E and the seventh state parameter D2E are both disabled, and the sixth state parameter D1E is enabled. The twelfth switching unit 662 is configured to control the i-th second normal conductive via D1 to be electrically connected to the i-th fourth primary node only when the twelfth control signal Ctr12 is enabled.

[0308] Thus, D1 replaces D2 and is electrically connected to the corresponding internal port in the following situation (D1 is electrically connected to the third primary node Middle2): D1 and R1 both fail and D2 does not fail.

[0309] In a specific embodiment, referring to FIG9, when the enable state is high and the disable state is low, the seventh logic unit 611 includes a seventh NOT gate 701, a seventh AND gate 702 and a seventh OR gate 703; the eighth logic unit 621 includes an eighth AND gate 711 and an eighth OR gate 712; the ninth logic unit 631 includes a ninth NOT gate 721 and a ninth AND gate 722; the tenth logic unit 641 includes a tenth NOT gate 731, a tenth AND gate 732 and a tenth OR gate 733; the eleventh logic unit 651 includes an eleventh AND gate 741 and an eleventh OR gate 742; and the twelfth logic unit 631 includes a twelfth NOT gate 751 and a twelfth AND gate 752.

[0310] The input of the seventh NOT gate 701 receives the sixth state parameter D1E. The output of the seventh NOT gate 701 is connected to one input of the seventh AND gate 702. The other input of the seventh AND gate 702 receives the fifth state parameter R1E. The outputs of the seventh AND gate 702 and the twelfth AND gate 752 are respectively connected to the two inputs of the seventh OR gate 703. The two inputs of the eighth OR gate 712 receive the seventh state parameter D2E and the eighth state parameter R2E respectively. The output of the eighth OR gate 712 is connected to the eighth AND gate 711. One input terminal of the eighth AND gate 711 is connected to the other input terminal of the eleventh OR gate 742; the output terminal of the ninth NOT gate 721 is connected to one input terminal of the ninth AND gate 722; the other input terminal of the ninth AND gate 722 receives the seventh state parameter D2E; the seventh OR gate 703 outputs the seventh control signal Ctr7; the eighth AND gate 711 outputs the eighth control signal Ctr8; and the ninth AND gate 722 outputs the ninth control signal Ctr9.

[0311] The input of the tenth NOT gate 731 receives the seventh state parameter D2E. The output of the tenth NOT gate 731 is connected to one input of the tenth AND gate 732. The other input of the tenth AND gate 732 receives the eighth state parameter R2E. The outputs of the tenth AND gate 732 and the ninth AND gate 722 are respectively connected to the two inputs of the tenth OR gate 733, which outputs the tenth control signal Ctr10. The two inputs of the eleventh OR gate 742 receive the fifth state parameter R1E and the sixth state parameter D1E respectively. The output of gate 742 is connected to one input of the eleventh AND gate 741. The other input of the eleventh AND gate 741 receives the seventh state parameter D2E, and the eleventh AND gate 741 outputs the eleventh control signal Ctr11. The input of the twelfth NOT gate 751 is connected to the output of the eighth OR gate 712. The output of the twelfth NOT gate 751 is connected to one input of the twelfth AND gate 752. The other input of the twelfth AND gate 752 receives the sixth state parameter D1E, and the twelfth AND gate 752 outputs the twelfth control signal Ctr12.

[0312] It should also be noted that the conductive vias mentioned above can at least be embodied as through-silicon vias (TSVs), specifically a vertical interconnect structure that penetrates the silicon wafer / memory chip 10, for example... Figure 1 Type 1 in the above; of course, conductive vias can also be used. Figure 1 Type 2 in the diagram, together with the contact structure, enables signal transmission. In other embodiments, other electrical connection structures can also be selected as conductive vias.

[0313] Conductive vias can be fabricated using one or more of the following processes: pre-via, mid-via, post-via, and back-via. Pre-via refers to a via fabrication process where the via structure is created before the device, such as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), is manufactured. Mid-via fabrication involves creating the via structure during the manufacturing process, often after device formation but before the stack-up. Post-via fabrication involves forming the via from the front side of the wafer after the back-end of line (BEOL) process. Back-via fabrication involves creating the via structure from the back side of the wafer after the BEOL process. In other words, pre-via fabrication can mean creating the via first, then the circuitry; mid-via fabrication can mean creating the circuitry and part of the metal layer first, then the via, and finally the remaining via; post-via and back-via fabrication can mean creating the circuitry and metal layer first, then the via.

[0314] In summary, the present disclosure provides a memory chip that transmits four different global signals through four different normal conductive vias, resulting in high signal transmission efficiency. Furthermore, each of the four different normal conductive vias corresponds to four redundant conductive vias, enabling redundancy repair. The chip stack structure formed by this memory chip and a logic chip (which also possesses this characteristic) achieves signal rotation transmission through the direct connection configuration of the conductive vias, resulting in relatively low parasitic resistance and capacitance.

[0315] In another embodiment of this disclosure, see Figure 11 This illustration shows a structural schematic diagram of a logic chip 70 provided in an embodiment of this disclosure, which can be specifically understood as a cross-sectional schematic diagram of the active surface. For example... Figure 11 As shown, the logic chip 70 includes m channel signal regions arranged sequentially along a first direction. Figure 10 (Taking m=4 as an example) and the center of each channel signal area coincides with the center of its respective channel.

[0316] The center of the active surface of the logic chip 70 and its adjacent area are defined as the global signal region 20, and the center point of the global signal region 20 coincides with the center point of the active surface; the m channel signal regions are symmetrical about the global signal region 20. Both the global signal region 20 and the channel signal regions are penetrated by a number of conductive vias along a third direction, and the third direction is perpendicular to the active surface. For the global signal region 20, each conductive via is used to transmit a global signal, and the global signal is shared by all areas of the memory chip 10; for the channel signal regions, each conductive via is used to transmit a channel signal, and each channel signal is only used by the corresponding channel.

[0317] Specifically, the global signal region 20 of the logic chip 70 and the memory chip 10 have the same area, but the active surface area of ​​the logic chip 70 may be greater than or equal to the active surface area of ​​the memory chip 10.

[0318] Please see Figure 11 The global signal region 20 has a first axis AA' and a second axis BB'. The first axis AA' is parallel to the first side of the logic chip 70, and the first axis AA' and the second axis BB' intersect each other perpendicularly at the center point of the active surface. Figure 11 In this example, the first axis AA' extends along the first direction, and the second axis BB' extends along the second direction, but this is only an example and does not constitute a specific limitation.

[0319] The logic chip 70 also has a group of conductive vias similar to those in the aforementioned logic chip 70, as detailed below.

[0320] Please see Figure 12 The global signal region 20 is penetrated by n conductive via groups along a third direction. Each conductive via group includes 4 normal conductive vias (D0, D1, D2, D3), and the first normal conductive via D0 and the second normal conductive via D1 are symmetrical about the first axis AA', the third normal conductive via D2 and the fourth normal conductive via D3 are symmetrical about the first axis AA', and the first normal conductive via D0 and the fourth normal conductive via D3 are symmetrical about the second axis BB'.

[0321] Please see Figure 12 The logic chip 70 also includes n control circuits 80. The internal circuits of the logic chip 70 include n first signal ports TA0, n second signal ports TA1, n third signal ports TA2 and n fourth signal ports TA3.

[0322] The i-th control circuit 80 is configured to electrically connect the first normal conductive via D0, the second normal conductive via D1, the third normal conductive via D2, and the fourth normal conductive via D3 in the i-th conductive via group to the i-th first signal port TA1, the i-th second signal port TA2, the i-th third signal port TA4, and the i-th fourth signal port TA4, respectively.

[0323] In some embodiments, see Figure 12 Each group of conductive vias also includes 4a redundant conductive vias ( Figure 12 Taking a=1 as an example, the 4a first redundant conductive via R0 and 4a second redundant conductive via R1 are symmetrical about the first axis AA', the 4a third redundant conductive via R2 and 4a fourth redundant conductive via R3 are symmetrical about the first axis AA', and the 4a first redundant conductive via R0 and 4a fourth redundant conductive via R3 are symmetrical about the second axis BB'. a first redundant conductive via R0, a second redundant conductive via R1, a first normal conductive via D0 and a second normal conductive via D1 constitute one repair unit, and a third redundant conductive via R2, a fourth redundant conductive via R3, a third normal conductive via D2 and a fourth normal conductive via D3 constitute another repair unit.

[0324] The control circuit 80 is also configured to, when any normal conductive via fails, use other conductive vias in the same repair unit to replace the failed normal conductive via and electrically connect them to the corresponding signal port.

[0325] In one specific embodiment, the control circuit 80 is specifically configured such that if the first normal conductive via D0 fails, a first redundant conductive via R0 or a fourth normal conductive via D3 is used to replace the first normal conductive via D0 and electrically connect it to the corresponding signal port (i.e., connect it to the first signal port TA1); and if the fourth normal conductive via D3 fails, a fourth redundant conductive via R3 or a first normal conductive via D0 is used to replace the fourth normal conductive via D3 and electrically connect it to the corresponding signal port (i.e., connect it to the fourth signal port TA3); and if the second normal conductive via D1 fails, a second redundant conductive via R1 or a third normal conductive via D2 is used to replace the second normal conductive via D1 and electrically connect it to the corresponding signal port (i.e., connect it to the second signal port TA2); and if the third normal conductive via D2 fails, a third redundant conductive via R2 or a second normal conductive via D1 is used to replace the third normal conductive via D2 and electrically connect it to the corresponding signal port (i.e., connect it to the third signal port TA3).

[0326] In one specific embodiment, please refer to Figure 12 The i-th control circuit 80 includes the i-th first control circuit 81 and the i-th second control circuit 82;

[0327] For the i-th first control circuit 81, one side is coupled to the first normal conductive via D0, the fourth normal conductive via D3, the first redundant conductive via R0, and the fourth redundant conductive via R3 in the i-th conductive via group, and the other side is coupled to the i-th first signal port TA1 and the i-th fourth signal port TA4; the i-th first control circuit 81 is configured to receive the i-th first via state parameter group, and based on the first via state parameter group and the selection signal, electrically connect one of the coupled conductive vias to the i-th first signal port TA1, and electrically connect the other coupled conductive via to the i-th fourth signal port TA4;

[0328] For the i-th second control circuit 82, one side is coupled to the second normal conductive via D1, the third normal conductive via D2, the second redundant conductive via R1, and the third redundant conductive via R2 in the i-th conductive via group, and the other side is coupled to the i-th second signal port TA2 and the i-th third signal port TA3; the i-th second control circuit 82 is configured to receive the i-th second via status parameter group, and based on the second via status parameter group and the selection signal, electrically connect one of the coupled conductive vias to the second signal port TA2, and electrically connect the other coupled conductive via to the third signal port TA3.

[0329] In one specific embodiment, please refer to Figure 13 The i-th first control circuit 81 includes the i-th first repair circuit 311 and the i-th second repair circuit 312;

[0330] For the i-th first repair circuit 311, one side is coupled to the first redundant conductive via R0, the first normal conductive via D0 and the second normal conductive via D1 in the i-th conductive via group, and the other side is coupled to the first signal port TA1; the first repair circuit 311 is configured to receive and, based on the first via state parameter group, electrically connect one of the three coupled to the first normal conductive via D0, the first redundant conductive via R0 and the fourth normal conductive via D3 to the i-th first signal port TA0;

[0331] For the i-th second repair circuit 312, one side is coupled to the first normal conductive via D0, the normal conductive via, and the fourth redundant conductive via R3 in the i-th conductive via group, and the other side is coupled to the third signal port TA2; the second repair circuit 312 is configured to receive the i-th first via status parameter group, and is electrically connected to the i-th third signal port TA2 based on one of the three: the first normal conductive via D0, the fourth normal conductive via D3, and the fourth redundant conductive via R3.

[0332] In some embodiments, the i-th first via state parameter group includes a first state parameter R0E, a second state parameter D0E, a third state parameter D3E, and a fourth state parameter R3E, which correspond one-to-one to indicate whether the first redundant conductive via R0, the first normal conductive via D0, the fourth normal conductive via D3, and the fourth redundant conductive via R3 in the i-th conductive via group are ineffective; when any state parameter is in an enabled state, it indicates that the corresponding conductive via is not ineffective; when any state parameter is in a disabled state, it indicates that the corresponding conductive via is ineffective.

[0333] Please see Figure 14 The i-th first repair circuit 311 includes a first switching unit 412, a second switching unit 422, a third switching unit 432, a first logic unit 411, a second logic unit 421, and a third logic unit 431;

[0334] The first logic unit 411 is configured to output a first control signal Ctr1 in an enabled state only when the state parameter group of the i-th first via meets the first preset condition; wherein, the first preset condition means that the first state parameter R0E is in an enabled state and the second state parameter D0E is in a disabled state, or that both the first state parameter R0E and the second state parameter D0E are in an enabled state and both the third state parameter D3E and the fourth state parameter R3E are in a disabled state; the first switching unit 412 is configured to control the i-th first redundant conductive via R0 to be electrically connected to the i-th first signal port TA0 only when the first control signal Ctr1 is in an enabled state.

[0335] The second logic unit 421 is configured to output a second control signal Ctr2 enabling state only when the state parameter group of the i-th first via meets the second preset condition; wherein, the second preset condition means that the second state parameter D0E is enabled, and at least one of the third state parameter D3E and the fourth state parameter R3E is enabled; the second switching unit 422 is configured to control the i-th first normal conductive via D0 to be electrically connected to the i-th first signal port TA0 only when the second control signal Ctr2 is enabled.

[0336] The third switching unit 432 is configured to output a third control signal Ctr3 in an enabled state only when the state parameter group of the i-th first through hole meets the third preset condition; wherein, the third preset condition means that the first state parameter R0E and the second state parameter D0E are both disabled, and the third state parameter D3E is enabled; the third switching unit 432 is configured to control the i-th fourth normal conductive through hole D3 to be electrically connected to the i-th first signal port TA0 only when the third control signal Ctr3 is enabled.

[0337] In some embodiments, see Figure 14The i-th second repair circuit 312 includes a fourth switching unit 442, a fifth switching unit 452, a sixth switching unit 462, a fourth logic unit 441, a fifth logic unit 451, and a sixth logic unit 461;

[0338] The fourth logic unit 441 is configured to output an enabled fourth control signal Ctr4 only when the i-th first via state parameter group meets the fourth preset condition; wherein, the fourth preset condition means that the fourth state parameter R3E is enabled and the third state parameter D3E is disabled, or, when both the fourth state parameter R3E and the third state parameter D3E are enabled and both the second state parameter D0E and the first state parameter R0E are disabled; the fourth switching unit 442 is configured to control the i-th fourth redundant conductive via R3 to be electrically connected to the i-th fourth signal port TA3 only when the fourth control signal Ctr4 is enabled.

[0339] The fifth logic unit 451 is configured to output a fifth control signal Ctr5 in an enabled state only when the state parameter group of the i-th first via meets the fifth preset condition; wherein, the fifth preset condition means that the third state parameter D3E is in an enabled state, and at least one of the second state parameter D0E and the first state parameter R0E is in an enabled state; the fifth switching unit 452 is configured to control the i-th fourth normal conductive via D3 to be electrically connected to the i-th fourth signal port TA3 only when the fifth control signal Ctr5 is in an enabled state.

[0340] The sixth switching unit 462 is configured to output a sixth control signal Ctr6 in an enabled state only when the state parameter group of the i-th first via meets the sixth preset condition; wherein, the sixth preset condition means that the fourth state parameter R3E and the third state parameter D3E are both disabled, and the second state parameter D0E is enabled; the sixth switching unit 462 is configured to control the i-th first normal conductive via D0 to be electrically connected to the i-th fourth signal port TA3 only when the sixth control signal Ctr6 is enabled.

[0341] In some embodiments, see Figure 14 When the enabled state is high and the disabled state is low, the first logic unit 411 includes a first NOT gate 501, a first AND gate 502, and a first OR gate 503; the second logic unit 421 includes a second AND gate 511 and a second OR gate 512; the third logic unit 431 includes a third NOT gate 521 and a third AND gate 522; the fourth logic unit 441 includes a fourth NOT gate 531, a fourth AND gate 532, and a fourth OR gate 533; the fifth logic unit 451 includes a fifth AND gate 541 and a fifth OR gate 542; and the sixth logic unit 431 includes a sixth NOT gate 551 and a sixth AND gate 552.

[0342] The input of the first NOT gate 501 receives the second state parameter D0E. The output of the first NOT gate 501 is connected to one input of the first AND gate 502. The other input of the first AND gate 502 receives the first state parameter R0E. The outputs of the first AND gate 502 and the sixth AND gate 552 are respectively connected to the two inputs of the first OR gate 503. The two inputs of the second OR gate 512 receive the third state parameter D3E and the fourth state parameter R3E respectively. The output of the second OR gate 512 is connected to one input of the second AND gate 511. The other input of the second AND gate 511 receives the second state parameter D0E. The input of the third NOT gate 521 is connected to the output of the fifth OR gate 542. The output of the third NOT gate 521 is connected to one input of the third AND gate 522. The other input of the third AND gate 522 receives the third state parameter D3E. The first OR gate 503 outputs the first control signal Crt1. The second AND gate 511 outputs the second control signal Crt2. The third AND gate 522 outputs the third control signal Crt3.

[0343] The input of the fourth NOT gate 531 receives the third state parameter D3E. The output of the fourth NOT gate 531 is connected to one input of the fourth AND gate 532. The other input of the fourth AND gate 532 receives the fourth state parameter R3E. The outputs of the fourth AND gate 532 and the third AND gate 522 are respectively connected to the two inputs of the fourth OR gate 533. The two inputs of the fifth OR gate 542 receive the first state parameter R0E and the second state parameter D0E respectively. The output of the fifth OR gate 542 is connected to one input of the fifth AND gate 541. The other input of the fifth AND gate 541 receives the third state parameter D3E. The input of the sixth NOT gate 551 is connected to the output of the second OR gate 512. The output of the sixth NOT gate 551 is connected to one input of the sixth AND gate 552. The other input of the sixth AND gate 552 receives the second state parameter D0E. The fourth OR gate 533 outputs the fourth control signal Crt4, the fifth AND gate 541 outputs the fifth control signal Crt5, and the sixth AND gate 552 outputs the sixth control signal Crt6.

[0344] In some embodiments, see Figure 15 The i-th second selection circuit 32 includes a third repair unit 321 and a fourth repair unit 322;

[0345] For the third repair unit 321, one side is coupled to the second redundant conductive via R1, the first normal conductive via D0, and the second normal first state parameter R0E via in the i-th conductive via group, and the other side is coupled to the second signal port TA1; the third repair unit 321 is configured to receive and, based on the second via state parameter group, electrically connect one of the three coupled to the i-th second signal port TA1: the second normal conductive via D1, the second redundant conductive via R1, and the third normal conductive via D2;

[0346] For the fourth repair unit 322, one side is coupled to the second normal conductive via D1, the normal conductive via, and the third redundant conductive via R2 in the i-th conductive via group, and the other side is coupled to the fourth signal port TA2; the fourth repair unit 322 is configured to receive and, based on the second via state parameter group, electrically connect one of the three—the second normal conductive via D1, the third normal conductive via D2, and the third redundant conductive via R2—to the i-th third signal port TA2.

[0347] In some embodiments, the i-th second via state parameter group includes four state parameters, and the fifth state parameter R1E, ​​the sixth state parameter D1E, the seventh state parameter D2E, and the eighth state parameter R2E correspond one-to-one to indicate whether the second redundant conductive via R1, the second normal conductive via D1, the third normal conductive via D2, and the third redundant conductive via R2 in the i-th conductive via group are ineffective; when any state parameter is in an enabled state, it indicates that the corresponding conductive via is not ineffective; when any state parameter is in a disabled state, it indicates that the corresponding conductive via is ineffective.

[0348] Please see Figure 15 The i-th third repair unit 321 includes a seventh switching unit 612, an eighth switching unit 622, a ninth switching unit 632, a seventh logic unit 611, an eighth logic unit 621, and a ninth logic unit 631;

[0349] The seventh logic unit 611 is configured to output a seventh control signal Ctr7 in an enabled state only when the state parameter group of the i-th second via meets the seventh preset condition; wherein, the seventh preset condition means that the fifth state parameter R1E is in an enabled state and the sixth state parameter D1E is in a disabled state, or that both the fifth state parameter R1E and the sixth state parameter D1E are in an enabled state and both the seventh state parameter D2E and the eighth state parameter R2E are in a disabled state; the seventh switching unit 612 is configured to control the i-th second redundant conductive via R1 to be electrically connected to the i-th second signal port TA1 only when the seventh control signal Ctr7 is in an enabled state;

[0350] The eighth logic unit 621 is configured to output an eighth control signal Ctr8 in an enabled state only when the state parameter group of the i-th second via meets the eighth preset condition; wherein, the eighth preset condition means that the sixth state parameter D1E is in an enabled state, and at least one of the seventh state parameter D2E and the eighth state parameter R2E is in an enabled state; the eighth switching unit 622 is configured to control the i-th second normal conductive via D1 to be electrically connected to the i-th second signal port TA1 only when the eighth control signal Ctr8 is in an enabled state.

[0351] The ninth switching unit 632 is configured to output a ninth control signal Ctr9 in an enabled state only when the i-th second via state parameter group meets the ninth preset condition; wherein, the ninth preset condition means that the fifth state parameter R1E and the sixth state parameter D1E are both disabled, and the seventh state parameter D2E is enabled; the ninth switching unit 632 is configured to control the third normal conductive via D2 to be electrically connected to the second signal port TA1 only when the ninth control signal Ctr9 is enabled.

[0352] In some embodiments, see Figure 15 The fourth repair unit 322 includes a tenth switching unit 642, an eleventh switching unit 652, a twelfth switching unit 662, a tenth logic unit 641, an eleventh logic unit 651, and a twelfth logic unit 661.

[0353] The tenth logic unit 641 is configured to output the tenth control signal Ctr10, which is in an enabled state, only when the state parameter group of the i-th second via meets the tenth preset condition; wherein, the tenth preset condition means that the eighth state parameter R2E is in an enabled state and the seventh state parameter D2E is in a disabled state, or that both the eighth state parameter R2E and the seventh state parameter D2E are in an enabled state and both the sixth state parameter D1E and the fifth state parameter R1E are in a disabled state; the tenth switching unit 642 is configured to control the i-th third redundant conductive via R2 to be electrically connected to the i-th third signal port TA2 only when the tenth control signal Ctr10 is in an enabled state.

[0354] The eleventh logic unit 651 is configured to output the eleventh control signal Ctr11 in an enabled state only when the state parameter group of the i-th second via meets the eleventh preset condition; wherein, the eleventh preset condition means that the seventh state parameter D2E is in an enabled state, and at least one of the fifth state parameter R1E and the sixth state parameter D1E is in an enabled state; the eleventh switching unit 652 is configured to control the i-th third normal conductive via D2 to be electrically connected to the i-th third signal port TA2 only when the eleventh control signal Ctr11 is in an enabled state.

[0355] The twelfth switching unit 662 is configured to output the twelfth control signal Ctr12 in an enabled state only when the state parameter group of the i-th second via meets the twelfth preset condition; wherein, the twelfth preset condition means that the eighth state parameter R2E and the seventh state parameter D2E are both disabled, and the sixth state parameter D1E is enabled; the twelfth switching unit 662 is configured to control the i-th second normal conductive via D1 to be electrically connected to the i-th third signal port TA2 only when the twelfth control signal Ctr12 is enabled.

[0356] In one specific embodiment, when the enable state is high and the disable state is low, the seventh logic unit 611 includes a seventh NOT gate 701, a seventh AND gate 702, and a seventh OR gate 703; the eighth logic unit 621 includes an eighth AND gate 711 and an eighth OR gate 712; the ninth logic unit 631 includes a ninth NOT gate 721 and a ninth AND gate 722; the tenth logic unit 641 includes a tenth NOT gate 731, a tenth AND gate 732, and a tenth OR gate 733; the eleventh logic unit 651 includes an eleventh AND gate 741 and an eleventh OR gate 742; and the twelfth logic unit 631 includes a twelfth NOT gate 751 and a twelfth AND gate 752.

[0357] The input of the seventh NOT gate 701 receives the sixth state parameter D1E. The output of the seventh NOT gate 701 is connected to one input of the seventh AND gate 702. The other input of the seventh AND gate 702 receives the fifth state parameter R1E. The outputs of the seventh AND gate 702 and the twelfth AND gate 752 are respectively connected to the two inputs of the seventh OR gate 703. The two inputs of the eighth OR gate 712 receive the seventh state parameter D2E and the eighth state parameter R2E respectively. The output of the eighth OR gate 712 is connected to the eighth AND gate 711. One input terminal of the eighth AND gate 711 is connected to the other input terminal of the eleventh OR gate 742; the output terminal of the ninth NOT gate 721 is connected to one input terminal of the ninth AND gate 722; the other input terminal of the ninth AND gate 722 receives the seventh state parameter D2E; the seventh OR gate 703 outputs the seventh control signal Ctr7; the eighth AND gate 711 outputs the eighth control signal Ctr8; and the ninth AND gate 722 outputs the ninth control signal Ctr9.

[0358] The input of the tenth NOT gate 731 receives the seventh state parameter D2E. The output of the tenth NOT gate 731 is connected to one input of the tenth AND gate 732. The other input of the tenth AND gate 732 receives the eighth state parameter R2E. The outputs of the tenth AND gate 732 and the ninth AND gate 722 are respectively connected to the two inputs of the tenth OR gate 733, which outputs the tenth control signal Ctr10. The two inputs of the eleventh OR gate 742 receive the fifth state parameter R1E and the sixth state parameter D1E respectively. The output of gate 742 is connected to one input of the eleventh AND gate 741. The other input of the eleventh AND gate 741 receives the seventh state parameter D2E, and the eleventh AND gate 741 outputs the eleventh control signal Ctr11. The input of the twelfth NOT gate 751 is connected to the output of the eighth OR gate 712. The output of the twelfth NOT gate 751 is connected to one input of the twelfth AND gate 752. The other input of the twelfth AND gate 752 receives the sixth state parameter D1E, and the twelfth AND gate 752 outputs the twelfth control signal Ctr12.

[0359] This disclosure provides a logic chip 70 that transmits four different global signals through four different normal conductive vias, resulting in high signal transmission efficiency. Simultaneously, each of the four different normal conductive vias corresponds to four redundant conductive vias, enabling redundancy repair. The chip stack structure formed by this memory chip and the logic chip (which also has this characteristic) achieves signal rotation transmission through the direct connection configuration of the conductive vias, resulting in relatively small parasitic resistance and capacitance.

[0360] In another embodiment of this disclosure, see [reference needed]. Figure 16 This illustrates a schematic diagram of the composition of a chip stacking structure 90 provided in an embodiment of this disclosure. For example... Figure 16 As shown, the chip stacking structure 90 includes the aforementioned logic chip 70 and at least one stacking unit, and the logic chip 70 and at least one stacking unit are stacked sequentially along a third direction; each stacking unit includes a first memory chip 11, a second memory chip 12, a third memory chip 13 and a fourth memory chip 14 stacked along a third direction; the logic chip 70, and the first memory chip 11, the second memory chip 12, the third memory chip 13 and the fourth memory chip 14 are all based on the aforementioned memory chip 10.

[0361] For each stacking unit, the first memory chip 11 and the second memory chip 12 are stacked face-to-face, the second memory chip 12 and the third memory chip 13 are stacked back-to-back, and the third memory chip 13 and the fourth memory chip 14 are stacked face-to-face; the first memory chip 11 and the logic chip 70 in the first stacking unit are stacked back-to-face, or the first memory chip 11 and the logic chip 70 in the first stacking unit are stacked back-to-back.

[0362] In this embodiment of the disclosure, face-to-face stacking means that the top surfaces of two chips are approximately aligned along a third direction; back-to-back stacking means that the top surfaces of two chips are approximately aligned along a third direction; face-to-back stacking means that the top surface of one chip is approximately aligned with the bottom surface of another chip along a third direction. Unless otherwise specified, "chip" can refer to either a logic chip or a memory chip. In the chip stacking structure 90, the center points of all chips, the first axis AA' and the second axis BB' of the top surface are aligned along a third direction.

[0363] It should be noted that, in one possibility, for two chips connected face-to-face, the bonding surfaces (the positions where the conductive vias are aligned along the third direction) are electrically connected through a hybrid bonding structure (also known as bonding pillars); for two chips connected back-to-back or back-to-face, the bonding surfaces (the positions where the conductive vias are aligned along the third direction) are electrically connected through conductive bumps (UBumps, also known as microbumps).

[0364] In another possibility, for two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected back-to-face, the bonding surfaces (positions where the conductive vias are aligned along a third direction) of both are connected by a hybrid bonding structure.

[0365] In another possibility, for two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected back-to-face, the mating surfaces (positions where the conductive vias are aligned along a third direction) of both are connected by conductive bumps.

[0366] Here, the above chip can refer to either logic chip 70 or memory chip 10.

[0367] It should be noted that, compared to conductive bump technology, face-to-face bonding using hybrid bonding technology allows for a tighter fit between adjacent memory chips, virtually eliminating gaps. This significantly reduces the height of the chip stack structure, which is one of the advantages of face-to-face stacking. Of course, two memory chips connected back-to-back can also be linked using a hybrid bonding structure, but its connection performance is weaker than that achieved through conductive bump technology. Therefore, in this embodiment, the chip stack structure 90 supports face-to-face stacking, resulting in better performance.

[0368] As mentioned above, the logic chip 70 or each memory chip can be divided into a high-order transmission region and a low-order transmission region. In the following figures, the arrows for each chip are uniformly located in the high-order transmission region of the chip. In particular, the high-order transmission region and low-order transmission region in this embodiment of the disclosure are merely two regions that distinguish the memory chip, and do not have any other additional limitations. They are not related to the high-order data and low-order data commonly referred to in the data transmission process.

[0369] When the logic chip 30 and the first memory chip 11 are stacked back-to-back and the logic chip 30 and the fourth memory chip 14 are arranged in the same way, a first specific implementation method and a second specific implementation method are provided; when the logic chip 30 and the first memory chip 11 are stacked back-to-back and the logic chip 30 and the second memory chip 12 are arranged in the same way, a third specific implementation method and a fourth specific implementation method are provided, as detailed below.

[0370] In the first specific embodiment, such as Figure 17A As shown, assuming that the logic chip 70 and each memory chip's respective first axis AA' divides the chip into a high-order transmission region and a low-order transmission region (i.e., the first axis AA' extends along the first direction), the high-order transmission region of the logic chip 70, the high-order transmission region of the first memory chip 11, the low-order transmission region of the second memory chip 12, the low-order transmission region of the third memory chip 13, and the high-order transmission region of the fourth memory chip 14 are aligned along the third direction; the low-order transmission region of the logic chip 70, the low-order transmission region of the first memory chip 11, the high-order transmission region of the second memory chip 12, the high-order transmission region of the third memory chip 13, and the low-order transmission region of the fourth memory chip 14 are aligned along the third direction.

[0371] At this point, according to the aforementioned classification rules: the top surface of the memory chips in the first and third categories faces upward along the third direction, and the top surface of the memory chips in the second and fourth categories faces downward along the third direction; the active surface of each memory chip is divided into a low-level transmission region and a high-level transmission region, and the low-level transmission region in the memory chip in the first category, the high-level transmission region in the memory chip in the second category, the high-level transmission region in the memory chip in the third category, and the low-level transmission region in the memory chip in the fourth category are aligned along the third direction.

[0372] At this time, the first memory chip 11 is in the first type position, the second memory chip 12 is in the second type position, the third memory chip 13 is in the third type position, and the fourth memory chip 14 is in the fourth type position.

[0373] In the second specific embodiment, such as Figure 18A As shown, assuming that the second axis BB' of each logic chip 70 and each memory chip divides the chip into a high-order transmission region and a low-order transmission region (i.e., the second axis BB' extends along the first direction), the high-order transmission region of logic chip 70, the low-order transmission region of the first memory chip 11, the low-order transmission region of the second memory chip 12, the high-order transmission region of the third memory chip 13, and the high-order transmission region of the fourth memory chip 14 are aligned along the third direction; the low-order transmission region of logic chip 70, the high-order transmission region of the first memory chip 11, the high-order transmission region of the second memory chip 12, the low-order transmission region of the third memory chip 13, and the low-order transmission region of the fourth memory chip 14 are aligned along the third direction.

[0374] Similarly, the first memory chip 11 is a first-class position, the second memory chip 12 is a second-class position, the third memory chip 13 is a third-class position, and the fourth memory chip 14 is a fourth-class position.

[0375] Please see Figure 17B or Figure 18B For the first and second specific embodiments, each through hole has the following alignment relationship:

[0376] The fourth normal conductive via D3 in the i-th conductive via group of logic chip 70, the first normal conductive via D0 in the i-th conductive via group of each first memory chip 11, the second normal conductive via D1 in the i-th conductive via group of each second memory chip 12, the third normal conductive via D2 in the i-th conductive via group of each third memory chip 13, and the fourth normal conductive via D3 in the i-th conductive via group of each fourth memory chip 14 are aligned along a third direction and form a normal signal transmission channel, assuming it is used to transmit SignalA;

[0377] The third normal conductive via D2 in the i-th conductive via group of logic chip 70, the second normal conductive via D1 in the i-th conductive via group of each first memory chip 11, the first normal conductive via D0 in the i-th conductive via group of each second memory chip 12, the fourth normal conductive via D3 in the i-th conductive via group of each third memory chip 13, and the third normal conductive via D2 in the i-th conductive via group of each fourth memory chip 14 are aligned along a third direction and form a normal signal transmission channel, assuming it is used to transmit SignalB;

[0378] The second normal conductive via D1 in the i-th conductive via group of logic chip 70, the third normal conductive via D2 in the i-th conductive via group of each first memory chip 11, the fourth normal conductive via D3 in the i-th conductive via group of each second memory chip 12, the first normal conductive via D0 in the i-th conductive via group of each third memory chip 13, and the second normal conductive via D1 in the i-th conductive via group of each fourth memory chip 14 are aligned along a third direction and form a normal signal transmission channel; assuming it is used to transmit SignalC;

[0379] The first normal conductive via D0 in the i-th conductive via group of logic chip 70, the fourth normal conductive via D3 in the i-th conductive via group of each first memory chip 11, the third normal conductive via D2 in the i-th conductive via group of each second memory chip 12, the second normal conductive via D1 in the i-th conductive via group of each third memory chip 13, and the first normal conductive via D0 in the i-th conductive via group of each fourth memory chip 14 are aligned along a third direction and form a normal signal transmission channel, assuming it is used to transmit SignalD.

[0380] against Figure 17AFor a schematic diagram of the signal transmission of the / B chip stacking structure, please refer to [link / reference]. Figure 19 , Figure 18A In the chip stacking structure of / B, only the connection relationship between the internal ports and conductive vias in the logic chip 70 is different. That is to say, regardless of... Figure 17A / B or Figure 18A / B, the correspondence between the four internal ports and conductive vias, and the specific signals in each chip is shown in Table 3 below. Although the first memory chip 11 to the fourth memory chip 14 adopt different placement methods, the first internal port In0 of each chip receives the same signal SignalA, the second internal port In1 of each chip receives the same signal SignalB, the third internal port In2 of each chip receives the same signal SignalC, and the fourth internal port In3 of each chip receives the same signal SignalD. In particular, in Figure 19 In this context, the internal ports / signal ports are coupled to the corresponding conductive vias rather than being directly electrically connected. For example, the first internal port In0 in the first memory chip 11 is coupled to the first conductive via D0, and so on.

[0381] Table 3

[0382]

[0383] Please see Figure 17B or Figure 18B The fourth redundant conductive via R3 in the i-th conductive via group of logic chip 70, the first redundant conductive via R0 in the i-th conductive via group of each first memory chip 11, the second redundant conductive via R1 in the i-th conductive via group of each second memory chip 12, the third redundant conductive via R2 in the i-th conductive via group of each third memory chip 13, and the fourth redundant conductive via R3 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a redundant signal transmission channel.

[0384] The third redundant conductive via R2 in the i-th conductive via group of logic chip 70, the second redundant conductive via R1 in the i-th conductive via group of each first memory chip 11, the first redundant conductive via R0 in the i-th conductive via group of each second memory chip 12, the fourth redundant conductive via R3 in the i-th conductive via group of each third memory chip 13, and the third redundant conductive via R2 in the i-th conductive via group of each fourth memory chip 14 are aligned along a third direction and form a redundant signal transmission channel.

[0385] The second redundant conductive via R1 in the i-th conductive via group of logic chip 70, the third redundant conductive via R2 in the i-th conductive via group of each first memory chip 11, the fourth redundant conductive via R3 in the i-th conductive via group of each second memory chip 12, the first redundant conductive via R0 in the i-th conductive via group of each third memory chip 13, and the second redundant conductive via R1 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a redundant signal transmission channel.

[0386] The first redundant conductive via R0 in the i-th conductive via group of logic chip 70, the fourth redundant conductive via R3 in the i-th conductive via group of each first memory chip 11, the third redundant conductive via R2 in the i-th conductive via group of each second memory chip 12, the second redundant conductive via R1 in the i-th conductive via group of each third memory chip 13, and the first redundant conductive via R0 in the i-th conductive via group of each fourth memory chip 14 are aligned along a third direction and form a redundant signal transmission channel.

[0387] It should be noted that when the normal signal transmission channel of each chip fails, a redundant signal transmission channel will be activated to replace the normal signal transmission channel. This is only for... Figure 17A For example, regarding the chip stacking structure provided by / B, please refer to [link / reference]. Figure 20A and Figure 20B Assuming the normal signal transmission channel (originally used for transmitting SignalA) formed by D3 in logic chip 70 – D0 in first memory chip 12 – D1 in second memory chip 11 – D2 in third memory chip 13 – D3 in fourth memory chip 14 fails (e.g., any conductive via is damaged or the connection is damaged), then R3 in logic chip 70 replaces D3, R0 in first memory chip 12 replaces D0, R1 in second memory chip 11 replaces D1, R2 in third memory chip 13 replaces D2, and R3 in fourth memory chip 14 replaces D3. At this time, the redundant signal transmission channel formed by R3 in logic chip 70 – R0 in first memory chip 12 – R1 in second memory chip 11 – R2 in third memory chip 13 – R3 in fourth memory chip 14 will be used to transmit SignalA. For other similar cases, please refer to the working principle of the selection circuit 30 in the memory chip and the control circuit 80 in the logic chip for further understanding.

[0388] In the third specific embodiment, such as Figure 21AAs shown, assuming that the logic chip 70 and each memory chip's respective first axis AA' divides the chip into a high-order transmission region and a low-order transmission region (i.e., the first axis AA' extends along a first direction), the low-order transmission region of the logic chip 70, the high-order transmission region of the first memory chip 11, the low-order transmission region of the second memory chip 12, the low-order transmission region of the third memory chip 13, and the high-order transmission region of the fourth memory chip 14 are aligned along a third direction; the high-order transmission region of the logic chip 70, the low-order transmission region of the first memory chip 11, the high-order transmission region of the second memory chip 12, the high-order transmission region of the third memory chip 13, and the low-order transmission region of the fourth memory chip 14 are aligned along a third direction. At this time, the first memory chip 11 is in a first-type position, the second memory chip 12 is in a fourth-type position, the third memory chip 13 is in a third-type position, and the fourth memory chip 14 is in a second-type position.

[0389] In the fourth specific embodiment, such as Figure 22A As shown, assuming that the second axis BB' of each logic chip 70 and each memory chip divides the chip into a high-order transmission region and a low-order transmission region (i.e., the second axis BB' extends along the first direction), the low-order transmission regions of logic chip 70, the low-order transmission regions of the first memory chip 11, the low-order transmission regions of the second memory chip 12, the high-order transmission regions of the third memory chip 13, and the high-order transmission regions of the fourth memory chip 14 are aligned along the third direction; the high-order transmission regions of logic chip 70, the high-order transmission regions of the first memory chip 11, the high-order transmission regions of the second memory chip 12, the low-order transmission regions of the third memory chip 13, and the low-order transmission regions of the fourth memory chip 14 are aligned along the third direction. At this time, the first memory chip 11 is in the first type of position, the second memory chip 12 is in the fourth type of position, the third memory chip 13 is in the third type of position, and the fourth memory chip 14 is in the second type of position.

[0390] Please see Figure 21B or Figure 22B For the third and fourth specific embodiments, each signal region has the following alignment relationship:

[0391] The second normal conductive via D1 in the i-th conductive via group of logic chip 70, the first normal conductive via D0 in the i-th conductive via group of each first memory chip 11, the second normal conductive via D1 in the i-th conductive via group of each second memory chip 12, the third normal conductive via D2 in the i-th conductive via group of each third memory chip 13, and the fourth normal conductive via D3 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a normal signal transmission channel.

[0392] The first normal conductive via D0 in the i-th conductive via group of logic chip 70, the second normal conductive via D1 in the i-th conductive via group of each first memory chip 11, the first normal conductive via D0 in the i-th conductive via group of each second memory chip 12, the fourth normal conductive via D3 in the i-th conductive via group of each third memory chip 13, and the third normal conductive via D2 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a normal signal transmission channel.

[0393] The fourth normal conductive via D3 in the i-th conductive via group of logic chip 70, the third normal conductive via D2 in the i-th conductive via group of each first memory chip 11, the fourth normal conductive via D3 in the i-th conductive via group of each second memory chip 12, the first normal conductive via D0 in the i-th conductive via group of each third memory chip 13, and the second normal conductive via D1 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a normal signal transmission channel.

[0394] The third normal conductive via D2 in the i-th conductive via group of logic chip 70, the fourth normal conductive via D3 in the i-th conductive via group of each first memory chip 11, the third normal conductive via D2 in the i-th conductive via group of each second memory chip 12, the second normal conductive via D1 in the i-th conductive via group of each third memory chip 13, and the first normal conductive via D0 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a normal signal transmission channel.

[0395] Similarly, the first memory chip 11 is a first-class position, the second memory chip 12 is a second-class position, the memory chip 13 is a third-class position, and the memory chip 14 is a fourth-class position. Therefore, the same internal ports all receive the same signals.

[0396] Please also see Figure 21B and Figure 22B The alignment of redundant conductive vias is as follows:

[0397] The second redundant conductive via R1 in the i-th conductive via group of logic chip 70, the first redundant conductive via R0 in the i-th conductive via group of each first memory chip 11, the second redundant conductive via R1 in the i-th conductive via group of each second memory chip 12, the third redundant conductive via R2 in the i-th conductive via group of each third memory chip 13, and the fourth redundant conductive via R3 in the i-th conductive via group of each fourth memory chip 14 are aligned along a third direction and form a redundant signal transmission channel.

[0398] The first redundant conductive via R0 in the i-th conductive via group of logic chip 70, the second redundant conductive via R1 in the i-th conductive via group of each first memory chip 11, the first redundant conductive via R0 in the i-th conductive via group of each second memory chip 12, the fourth redundant conductive via R3 in the i-th conductive via group of each third memory chip 13, and the third redundant conductive via R2 in the i-th conductive via group of each fourth memory chip 14 are aligned along a third direction and form a redundant signal transmission channel.

[0399] The fourth redundant conductive via R3 in the i-th conductive via group of logic chip 70, the third redundant conductive via R2 in the i-th conductive via group of each first memory chip 11, the fourth redundant conductive via R3 in the i-th conductive via group of each second memory chip 12, the first redundant conductive via R0 in the i-th conductive via group of each third memory chip 13, and the second redundant conductive via R1 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a redundant signal transmission channel.

[0400] The third redundant conductive via R2 in the i-th conductive via group of logic chip 70, the fourth redundant conductive via R3 in the i-th conductive via group of each first memory chip 11, the third redundant conductive via R2 in the i-th conductive via group of each second memory chip 12, the second redundant conductive via R1 in the i-th conductive via group of each third memory chip 13, and the first redundant conductive via R0 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a redundant signal transmission channel.

[0401] Meanwhile, for repairs when a normal signal transmission channel fails, please refer to the aforementioned content.

[0402] Whether Figure 21A / B or Figure 22A For the correspondence between the four internal ports and conductive vias and specific signals in each chip, please refer to Table 4 below.

[0403] Table 4

[0404]

[0405]

[0406] At the same time, from Figures 17A-22BIt can be seen that for the chip stack structure 90, the signal transmission path from bottom to top will be similar to the following form: the fourth conductive via D3 in the logic chip 70 — the first conductive via D0 in the first memory chip 11 — the second conductive via D1 in the second memory chip 12 — the third conductive via D2 in the third memory chip 13 — the fourth conductive via D3 in the fourth memory chip 14… . In other words, for the chip stack structure 90, from a physical point of view, the conductive vias are still in a direct connection configuration. However, from the absolute position of the conductive vias on the active surface, the conductive vias can also be regarded as a functional rotation configuration. That is, a signal transmission effect similar to that in Figure 2 (i.e., a rotational transmission effect such as conductive via D0-conductive via D1-conductive via D2-conductive via D3…) is achieved through a physically direct connection configuration. In short, Figure 2B The chip stacking structure 90 in the present invention requires a physical spiral structure, which necessarily includes lateral interconnection structures. However, the chip stacking structure 90 in this embodiment is physically a direct connection structure, which does not require lateral interconnection structures. This significantly reduces parasitic resistance and greatly improves transmission speed and transmission performance.

[0407] In another embodiment of this disclosure, see Figure 23 This illustrates a schematic diagram of the composition structure of a memory 100 provided in an embodiment of this disclosure. For example... Figure 23 As shown, the memory 100 includes the chip stack structure 90 of the aforementioned embodiment.

[0408] In some embodiments, memory 100 may be such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), etc., and there is no specific limitation on it here.

[0409] In this embodiment of the disclosure, the chip area of ​​the memory 100 can be reduced, thereby reducing the chip manufacturing cost.

[0410] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0411] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0412] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0413] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0414] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0415] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0416] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0417] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory chip, characterized by, A center point of an active surface of the memory chip and a region adjacent to the center point are defined as a global signal region, and a center point of the global signal region coincides with the center point of the active surface; the global signal region has a first axis and a second axis, the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to a first side edge of the memory chip, and the second axis is parallel to a second side edge of the memory chip; The global signal region is penetrated by n groups of conductive vias along a third direction, the third direction is perpendicular to the active surface, and n is a positive integer; Each of the groups of conductive vias includes four normal conductive vias, a first normal conductive via and a second normal conductive via are symmetrical about the first axis, a third normal conductive via and a fourth normal conductive via are symmetrical about the first axis, and the first normal conductive via and the fourth normal conductive via are symmetrical about the second axis; The internal circuit of the memory chip includes n groups of internal ports, and each group of internal ports includes four internal ports; The memory chip further includes n selection circuits; an i-th selection circuit is configured to receive a selection signal and electrically connect, based on the selection signal, the four normal conductive vias in an i-th group of conductive vias to the four internal ports in an i-th group of internal ports in a one-to-one correspondence; wherein the correspondence between the four normal conductive vias and the four internal ports is determined based on the selection signal, and i is a positive integer less than or equal to n.

2. The memory chip of claim 1, wherein, The group of internal ports includes a first internal port, a second internal port, a third internal port, and a fourth internal port; The selection circuit is specifically configured to, if the selection signal is a first preset value, electrically connect the first normal conductive via, the second normal conductive via, the third normal conductive via, and the fourth normal conductive via to the first internal port, the second internal port, the third internal port, and an i-th fourth internal port in a one-to-one correspondence; If the selection signal is a second preset value, electrically connect the first normal conductive via, the second normal conductive via, the third normal conductive via, and the fourth normal conductive via to the second internal port, the first internal port, the fourth internal port, and the third internal port in a one-to-one correspondence; If the selection signal is a third preset value, electrically connect the first normal conductive via, the second normal conductive via, the third normal conductive via, and the fourth normal conductive via to the third internal port, the fourth internal port, the first internal port, and the second internal port in a one-to-one correspondence; If the selection signal is a fourth preset value, electrically connect the first normal conductive via, the second normal conductive via, the third normal conductive via, and the fourth normal conductive via to the fourth internal port, the third internal port, the second internal port, and the first internal port in a one-to-one correspondence.

3. The memory chip of claim 2, wherein, Each of the memory chips is stacked into one stacked unit along a third direction with four memory chips, and a chip position identification code of each of the memory chips indicates a position of the memory chip in the stacked unit; The memory chip further comprises: a decoding circuit configured to receive the chip position identification code, output a first preset value of the selection signal if the chip position identification code indicates that the memory chip is in a first type of position, output a second preset value of the selection signal if the chip position identification code indicates that the memory chip is in a second type of position, output a third preset value of the selection signal if the chip position identification code indicates that the memory chip is in a third type of position, and output a fourth preset value of the selection signal if the chip position identification code indicates that the memory chip is in a fourth type of position; wherein a top surface of the memory chip in the first type of position and the third type of position faces upward along the third direction, and a top surface of the memory chip in the second type of position and the fourth type of position faces downward along the third direction; an active surface of each of the memory chips is divided into a low-transmission region and a high-transmission region, and the low-transmission region of the memory chip in the first type of position, the high-transmission region of the memory chip in the second type of position, the high-transmission region of the memory chip in the third type of position, and the low-transmission region of the memory chip in the fourth type of position are aligned along the third direction.

4. The memory chip according to claim 2 or 3, characterized in that, each of the groups of conductive vias further comprises a first redundant conductive via, a second redundant conductive via, a third redundant conductive via, and a fourth redundant conductive via; the first redundant conductive via and the second redundant conductive via are symmetrical about a first axis, the third redundant conductive via and the fourth redundant conductive via are symmetrical about the first axis, and the first redundant conductive via and the fourth redundant conductive via are symmetrical about a second axis; a is a positive integer; for each of the groups of conductive vias, the first redundant conductive via, the second redundant conductive via, the first normal conductive via, and the second normal conductive via constitute a repair unit, and the third redundant conductive via, the fourth redundant conductive via, the third normal conductive via, and the fourth normal conductive via constitute another repair unit; the selection circuit is further configured to, when any of the normal conductive vias fails, use other conductive vias of the same repair unit to replace the failed normal conductive via and electrically connect with the corresponding internal port.

5. The memory chip of claim 4, wherein, in the case of a = 1, the selection circuit is specifically configured to, when the first normal conductive via fails, use the first redundant conductive via or the fourth normal conductive via to replace the first normal conductive via and electrically connect with the corresponding internal port; and when the fourth normal conductive via fails, use the fourth redundant conductive via or the first normal conductive via to replace the fourth normal conductive via and electrically connect with the corresponding internal port. If the second normal conductive via fails, the second redundant conductive via or the third normal conductive via is used to replace the second normal conductive via to be electrically connected with the corresponding internal port; If the third normal conductive via fails, the third redundant conductive via or the second normal conductive via is used to replace the third normal conductive via to be electrically connected with the corresponding internal port.

6. The memory chip of claim 5, wherein, The selection signals include first selection signals and second selection signals; the i-th selection circuit includes an i-th first selection circuit, an i-th second selection circuit, an i-th first signal output circuit and an i-th second signal output circuit; For the i-th first selection circuit, one side is coupled to the first normal conductive via, the fourth normal conductive via, the first redundant conductive via and the fourth redundant conductive via in the i-th conductive via group, and the other side is coupled to an i-th first secondary node and an i-th fourth secondary node; the first selection circuit is configured to receive and, based on an i-th first via state parameter group and the first selection signal, electrically connect one of the coupled conductive vias with the i-th first secondary node and electrically connect the other of the coupled conductive vias with the i-th fourth secondary node; For the i-th second selection circuit, one side is coupled to the second normal conductive via, the third normal conductive via, the second redundant conductive via and the third redundant conductive via in the i-th conductive via group, and the other side is coupled to an i-th second secondary node and an i-th third secondary node; the second selection circuit is configured to receive and, based on an i-th second via state parameter group and the first selection signal, electrically connect one of the coupled conductive vias with the i-th second secondary node and electrically connect the other of the coupled conductive vias with the i-th third secondary node; The i-th first signal output circuit is configured to receive and, based on the second selection signal, electrically connect the i-th first secondary node with an i-th first internal port and electrically connect the i-th fourth secondary node with an i-th fourth internal port; or electrically connect the i-th second secondary node with the i-th first internal port and electrically connect the i-th third secondary node with the i-th fourth internal port; The i-th second signal output circuit is configured to receive and, based on the second selection signal, electrically connect the i-th second secondary node with an i-th second internal port and electrically connect the i-th third secondary node with an i-th third internal port; or electrically connect the i-th first secondary node with the i-th second internal port and electrically connect the i-th fourth secondary node with the i-th third internal port.

7. The memory chip of claim 6, wherein, The i-th first selection circuit includes an i-th first repair circuit, an i-th second repair circuit and an i-th first selection output circuit; For the i-th first repair circuit, one side is coupled to the first redundant conductive via, the first normal conductive via and the fourth normal conductive via in the i-th conductive via group respectively, and the other side is coupled to the i-th first primary node; The first repair circuit is configured to receive and electrically connect one of the coupled conductive vias to the i-th first primary node based on the i-th first via state parameter group; For the i-th second repair circuit, one side is coupled to the first normal conductive via, the fourth normal conductive via and the fourth redundant conductive via in the i-th conductive via group respectively, and the other side is coupled to the i-th fourth primary node; the second repair circuit is configured to receive and electrically connect one of the coupled conductive vias to the i-th fourth primary node based on the i-th first via state parameter group; The i-th first selection output circuit is configured to electrically connect the i-th first primary node to the i-th first secondary node and electrically connect the i-th fourth primary node to the i-th fourth secondary node based on the first selection signal; Or, electrically connect the i-th first primary node to the i-th fourth secondary node and electrically connect the i-th fourth primary node to the i-th first secondary node.

8. The memory chip of claim 7, wherein, The i-th first via state parameter group includes a first state parameter, a second state parameter, a third state parameter and a fourth state parameter, and one-to-one corresponds to indicating whether the first redundant conductive via, the first normal conductive via, the fourth normal conductive via and the fourth redundant conductive via in the i-th conductive via group are failed; The i-th first repair circuit includes a first switching unit, a second switching unit, a third switching unit, a first logic unit, a second logic unit and a third logic unit; The first logic unit is configured to output a first control signal of an enabled state only when the i-th first via state parameter group meets a first preset condition; wherein the first preset condition means that the first state parameter is in an enabled state and the second state parameter is in a disabled state, or the first state parameter and the second state parameter are both in an enabled state and the third state parameter and the fourth state parameter are both in a disabled state; The first switching unit is configured to electrically connect the i-th first redundant conductive via to the i-th first primary node only when the first control signal is in an enabled state; The second logic unit is configured to output a second control signal of an enabled state only when the i-th first via state parameter group meets a second preset condition; wherein the second preset condition means that the second state parameter is in an enabled state and at least one of the third state parameter and the fourth state parameter is in an enabled state; The second switching unit is configured to electrically connect the i-th first normal conductive via to the i-th first primary node only when the second control signal is in an enabled state; The third logic unit is configured to output a third control signal in an enabled state only when the i-th first via state parameter group meets a third preset condition; the third preset condition refers to that the first state parameter and the second state parameter are both in a disabled state, and the third state parameter is in an enabled state; The third switching unit is configured to control the i-th fourth normal conductive via to be electrically connected with the i-th first primary node only when the third control signal is in the enabled state; Any state parameter in the enabled state indicates that the corresponding conductive via is not failed, and any state parameter in the disabled state indicates that the corresponding conductive via is failed.

9. The memory chip of claim 8, wherein, The i-th second repair circuit comprises a fourth switching unit, a fifth switching unit, a sixth switching unit, a fourth logic unit, a fifth logic unit and a sixth logic unit; The fourth logic unit is configured to output a fourth control signal in an enabled state only when the i-th first via state parameter group meets a fourth preset condition; the fourth preset condition refers to that the fourth state parameter is in the enabled state and the third state parameter is in the disabled state, or the fourth state parameter and the third state parameter are both in the enabled state and the second state parameter and the first state parameter are both in the disabled state; The fourth switching unit is configured to control the i-th fourth redundant conductive via to be electrically connected with the i-th fourth primary node only when the fourth control signal is in the enabled state; The fifth logic unit is configured to output a fifth control signal in an enabled state only when the i-th first via state parameter group meets a fifth preset condition; the fifth preset condition refers to that the third state parameter is in the enabled state, and at least one of the second state parameter and the first state parameter is in the enabled state; The fifth switching unit is configured to control the i-th fourth normal conductive via to be electrically connected with the i-th fourth primary node only when the fifth control signal is in the enabled state; The sixth logic unit is configured to output a sixth control signal in an enabled state only when the i-th first via state parameter group meets a sixth preset condition; the sixth preset condition refers to that the fourth state parameter and the third state parameter are both in the disabled state, and the second state parameter is in the enabled state; The sixth switching unit is configured to control the i-th first normal conductive via to be electrically connected with the i-th fourth primary node only when the sixth control signal is in the enabled state.

10. The memory chip of claim 9, wherein, In the case that the enabled state is a high level and the disabled state is a low level, the first logic unit comprises a first NAND gate, a first AND gate and a first OR gate; the second logic unit comprises a second AND gate and a second OR gate; the third logic unit comprises a third NAND gate and a third AND gate; the fourth logic unit comprises a fourth NAND gate, a fourth AND gate and a fourth OR gate; the fifth logic unit comprises a fifth AND gate and a fifth OR gate; and the sixth logic unit comprises a sixth NAND gate and a sixth AND gate. An input end of the first NOT gate receives the second state parameter, an output end of the first NOT gate is connected with an input end of the first AND gate, another input end of the first AND gate receives the first state parameter, the output end of the first AND gate and the output end of the sixth AND gate are connected with two input ends of the first OR gate respectively, and the first OR gate outputs the first control signal; Two input ends of the second OR gate receive the third state parameter and the fourth state parameter respectively, an output end of the second OR gate is connected with an input end of the second AND gate, another input end of the second AND gate receives the second state parameter, and the second AND gate outputs the second control signal; An input end of the third NOT gate is connected with an output end of the fifth OR gate, an output end of the third NOT gate is connected with an input end of the third AND gate, another input end of the third AND gate receives the third state parameter, and the third AND gate outputs the third control signal; An input end of the fourth NOT gate receives the third state parameter, an output end of the fourth NOT gate is connected with an input end of the fourth AND gate, another input end of the fourth AND gate receives the fourth state parameter, the output end of the fourth AND gate and the output end of the third AND gate are connected with two input ends of the fourth OR gate respectively, and the fourth OR gate outputs the fourth control signal; Two input ends of the fifth OR gate receive the first state parameter and the second state parameter respectively, an output end of the fifth OR gate is connected with an input end of the fifth AND gate, another input end of the fifth AND gate receives the third state parameter, and the fifth AND gate outputs the fifth control signal; An input end of the sixth NOT gate is connected with an output end of the second OR gate, an output end of the sixth NOT gate is connected with an input end of the sixth AND gate, another input end of the sixth AND gate receives the second state parameter, and the sixth AND gate outputs the sixth control signal.

11. The memory chip of claim 6, wherein, The i-th second selection circuit comprises an i-th third repair unit, an i-th fourth repair unit and an i-th second selection output circuit. For the i-th third repair unit, one side thereof is respectively coupled to a second redundant conductive via, a first normal conductive via and a second normal conductive via in the i-th group of conductive vias, and the other side thereof is coupled to an i-th second primary node. The third repair unit is configured to receive and electrically connect one of the coupled conductive vias to the i-th second primary node based on the i-th second via state parameter group. For the i-th fourth repair unit, one side thereof is respectively coupled to a second normal conductive via, a normal conductive via and the third redundant conductive via in the i-th group of conductive vias, and the other side thereof is coupled to an i-th third primary node. The fourth repair unit is configured to receive and electrically connect one of the coupled conductive vias to the i-th third primary node based on the i-th second via state parameter group. The i-th second selection output circuit is configured to receive and electrically connect the i-th second primary node and the i-th second secondary node and electrically connect the i-th third primary node and the i-th third secondary node based on the first selection signal; Or, electrically connect the i-th third primary node and the i-th second secondary node and electrically connect the i-th second primary node and the i-th third secondary node.

12. The memory chip of claim 11, wherein, The i-th second via state parameter group includes a fifth state parameter, a sixth state parameter, a seventh state parameter and an eighth state parameter, and one-to-one corresponds to indicating whether a second redundant conductive via, a second normal conductive via, a third normal conductive via and a third redundant conductive via in the i-th corresponding conductive via group are failed; The i-th third repair unit includes a seventh switching unit, an eighth switching unit, a ninth switching unit, a seventh logic unit, an eighth logic unit and a ninth logic unit; The seventh logic unit is configured to output a seventh control signal in an enabled state only when the i-th second via state parameter group meets a seventh preset condition; wherein the seventh preset condition refers to that the fifth state parameter is in an enabled state and the sixth state parameter is in a disabled state, or the fifth state parameter and the sixth state parameter are both in an enabled state and the seventh state parameter and the eighth state parameter are both in a disabled state; The seventh switching unit is configured to control the i-th second redundant conductive via to be electrically connected with the i-th second primary node only when the seventh control signal is in an enabled state; The eighth logic unit is configured to output an eighth control signal in an enabled state only when the i-th second via state parameter group meets an eighth preset condition; wherein the eighth preset condition refers to that the sixth state parameter is in an enabled state and at least one of the seventh state parameter and the eighth state parameter is in an enabled state; The eighth switching unit is configured to control the i-th second normal conductive via to be electrically connected with the i-th second primary node only when the eighth control signal is in an enabled state; The ninth switching unit is configured to output a ninth control signal in an enabled state only when the i-th second via state parameter group meets a ninth preset condition; wherein the ninth preset condition refers to that the fifth state parameter and the sixth state parameter are both in a disabled state and the seventh state parameter is in an enabled state; The ninth switching unit is configured to control the i-th third normal conductive via to be electrically connected with the i-th second primary node only when the ninth control signal is in an enabled state; Wherein, any state parameter in an enabled state indicates that the corresponding conductive via is not failed; any state parameter in a disabled state indicates that the corresponding conductive via is failed.

13. The memory chip of claim 12, wherein, The i-th fourth repair unit includes a tenth switching unit, an eleventh switching unit, a twelfth switching unit, a tenth logic unit, an eleventh logic unit and a twelfth logic unit; The tenth logic unit is configured to output a tenth control signal in an enabled state only when the i-th second via state parameter group meets a tenth preset condition; the tenth preset condition refers to that the eighth state parameter is in the enabled state and the seventh state parameter is in the disabled state, or the seventh state parameter and the eighth state parameter are both in the enabled state and the fifth state parameter and the sixth state parameter are both in the disabled state; The tenth switching unit is configured to control the i-th third redundant conductive via to be electrically connected with the i-th third primary node only when the tenth control signal is in the enabled state; The eleventh logic unit is configured to output an eleventh control signal in the enabled state only when the i-th second via state parameter group meets an eleventh preset condition; the eleventh preset condition refers to that the seventh state parameter is in the enabled state and at least one of the sixth state parameter and the fifth state parameter is in the enabled state; The eleventh switching unit is configured to control the i-th third normal conductive via to be electrically connected with the i-th third primary node only when the eleventh control signal is in the enabled state; The twelfth logic unit is configured to output a twelfth control signal in the enabled state only when the i-th second via state parameter group meets a twelfth preset condition; the twelfth preset condition refers to that the eighth state parameter and the seventh state parameter are both in the disabled state and the sixth state parameter is in the enabled state; The twelfth switching unit is configured to control the i-th second normal conductive via to be electrically connected with the i-th third primary node only when the twelfth control signal is in the enabled state.

14. The memory chip of claim 13, wherein, When the enabled state is a high level and the disabled state is a low level, the seventh logic unit includes a seventh NOT gate, a seventh AND gate and a seventh OR gate; the eighth logic unit includes an eighth AND gate and an eighth OR gate; the ninth logic unit includes a ninth NOT gate and a ninth AND gate; the tenth logic unit includes a tenth NOT gate, a tenth AND gate and a tenth OR gate; the eleventh logic unit includes an eleventh AND gate and an eleventh OR gate; and the twelfth logic unit includes a twelfth NOT gate and a twelfth AND gate; An input end of the seventh NOT gate receives the sixth state parameter, an output end of the seventh NOT gate is connected with an input end of the seventh AND gate, another input end of the seventh AND gate receives the fifth state parameter, an output end of the seventh AND gate and an output end of the twelfth AND gate are connected with two input ends of the seventh OR gate respectively, and the seventh OR gate outputs the seventh control signal; Two input ends of the eighth OR gate receive the seventh state parameter and the eighth state parameter respectively, an output end of the eighth OR gate is connected with an input end of the eighth AND gate, another input end of the eighth AND gate receives the sixth state parameter, and the eighth AND gate outputs the eighth control signal; An input end of the ninth NOT gate is connected with an output end of the eleventh OR gate, an output end of the ninth NOT gate is connected with an input end of the ninth AND gate, another input end of the ninth AND gate receives the seventh state parameter, and the ninth AND gate outputs the ninth control signal; An input end of the tenth NOT gate receives the seventh state parameter, an output end of the tenth NOT gate is connected with an input end of the tenth AND gate, another input end of the tenth AND gate receives the sixth state parameter, and an output end of the tenth AND gate and an output end of the ninth AND gate are respectively connected with two input ends of the tenth OR gate, and the tenth OR gate outputs the tenth control signal; Two input ends of the eleventh OR gate respectively receive the fifth state parameter and the sixth state parameter, and an output end of the eleventh OR gate is connected with an input end of the eleventh AND gate, another input end of the eleventh AND gate receives the seventh state parameter, and the eleventh AND gate outputs the eleventh control signal; An input end of the twelfth NOT gate is connected with an output end of the eighth OR gate, an output end of the twelfth NOT gate is connected with an input end of the twelfth AND gate, another input end of the twelfth AND gate receives the sixth state parameter, and the twelfth AND gate outputs the twelfth control signal.

15. The memory chip according to any one of claims 1-3, 5-14, wherein: The conductive vias are prepared by any one of a via-first process, a via-middle process, a via-last process, a back side via-last process, or a plurality of processes, and different conductive vias in the same memory chip are electrically isolated from each other.

16. A logic chip, characterized by A center point of the active surface of the logic chip and a region adjacent to the center point are defined as a global signal region, and a center point of the global signal region coincides with the center point of the active surface; the global signal region has a first axis and a second axis, the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to a first side edge of the logic chip, and the second axis is parallel to a second side edge of the logic chip; The global signal region is penetrated by n conductive via groups along a third direction, the third direction is perpendicular to the active surface, and n is a positive integer; Each of the conductive via groups includes four normal conductive vias, a first normal conductive via and a second normal conductive via are symmetrical about the first axis, a third normal conductive via and a fourth normal conductive via are symmetrical about the first axis, and the first normal conductive via and the fourth normal conductive via are symmetrical about the second axis; The logic chip further includes n control circuits, and internal circuits of the logic chip include n first signal ports, n second signal ports, n third signal ports, and n fourth signal ports. The i-th control circuit is configured to electrically connect the first normal conductive via, the second normal conductive via, the third normal conductive via and the fourth normal conductive via in the i-th conductive via group to the i-th first signal port, the i-th second signal port, the i-th third signal port and the i-th fourth signal port respectively.

17. The logic chip of claim 16, wherein, Each of the conductive via groups further comprises 4a redundant conductive vias, and a first redundant conductive via and a second redundant conductive via are symmetric about a first axis, a third redundant conductive via and a fourth redundant conductive via are symmetric about the first axis, and the first redundant conductive via and the fourth redundant conductive via are symmetric about a second axis; The first redundant conductive via, the second redundant conductive via, the first normal conductive via and the second normal conductive via constitute a repair unit, and the third redundant conductive via, the fourth redundant conductive via, the third normal conductive via and the fourth normal conductive via constitute another repair unit; The i-th control circuit is further configured to, when any of the normal conductive vias fails, use other conductive vias in the same repair unit to replace the failed normal conductive via and electrically connect to the corresponding signal port.

18. The logic chip of claim 17, wherein, In the case of a = 1, The control circuit is specifically configured to, if the first normal conductive via fails, use the first redundant conductive via or the fourth normal conductive via to replace the first normal conductive via and electrically connect to the corresponding signal port; If the fourth normal conductive via fails, use the fourth redundant conductive via or the first normal conductive via to replace the fourth normal conductive via and electrically connect to the corresponding signal port; If the second normal conductive via fails, use the second redundant conductive via or the third normal conductive via to replace the second normal conductive via and electrically connect to the corresponding signal port; If the third normal conductive via fails, use the third redundant conductive via or the second normal conductive via to replace the third normal conductive via and electrically connect to the corresponding signal port.

19. The logic chip of claim 18, wherein, The i-th control circuit comprises an i-th first control circuit and an i-th second control circuit; For the i-th first control circuit, one side is coupled to the first normal conductive via, the fourth normal conductive via, the first redundant conductive via and the fourth redundant conductive via in the i-th conductive via group, and the other side is coupled to the i-th first signal port and the i-th fourth signal port; the i-th first control circuit is configured to receive and, based on an i-th first via state parameter group, electrically connect one of the coupled conductive vias to the i-th first signal port and electrically connect the other of the coupled conductive vias to the i-th fourth signal port; For the i-th second control circuit, one side is coupled to the second normal conductive via, the third normal conductive via, the second redundant conductive via and the third redundant conductive via in the i-th conductive via group, and the other side is coupled to the i-th second signal port and the i-th third signal port; the i-th second control circuit is configured to receive and, based on the i-th second via state parameter group, electrically connect one of the coupled conductive vias to the i-th second signal port and electrically connect the other of the coupled conductive vias to the i-th third signal port.

20. The logic chip of claim 19, wherein, The i-th first control circuit includes an i-th first repair circuit and an i-th second repair circuit; For the i-th first repair circuit, one side is respectively coupled to the first redundant conductive via, the first normal conductive via and the fourth normal conductive via in the i-th conductive via group, and the other side is coupled to the i-th first signal port; The first repair circuit is configured to receive and, based on the i-th first via state parameter group, electrically connect one of the coupled conductive vias to the i-th first signal port; For the i-th second repair circuit, one side is respectively coupled to the first normal conductive via, the fourth normal conductive via and the fourth redundant conductive via in the i-th conductive via group, and the other side is coupled to the i-th fourth signal port; the second repair circuit is configured to receive and, based on the i-th first via state parameter group, electrically connect one of the coupled conductive vias to the i-th fourth signal port.

21. The logic chip of claim 20, wherein, The i-th first via state parameter group includes a first state parameter, a second state parameter, a third state parameter and a fourth state parameter, which one-to-one correspond to indicate whether the first redundant conductive via, the first normal conductive via, the fourth normal conductive via and the fourth redundant conductive via in the i-th conductive via group are failed; The i-th first repair circuit includes a first switching unit, a second switching unit, a third switching unit, a first logic unit, a second logic unit and a third logic unit; The first logic unit is configured to output a first control signal of an enable state only when the i-th first via state parameter group meets a first preset condition; wherein the first preset condition refers to that the first state parameter is in an enable state and the second state parameter is in a disable state, or the first state parameter and the second state parameter are both in an enable state and the third state parameter and the fourth state parameter are both in a disable state; The first switching unit is configured to control the i-th first redundant conductive via to be electrically connected to the i-th first signal port only when the first control signal is in an enable state; The second logic unit is configured to output a second control signal in an enabled state only when the i-th first via state parameter group meets a second preset condition; the second preset condition refers to that the second state parameter is in the enabled state, and at least one of the third state parameter and the fourth state parameter is in the enabled state; The second switching unit is configured to control the i-th first normal conductive via and the i-th first signal port to be electrically connected only when the second control signal is in the enabled state; The third logic unit is configured to output a third control signal in an enabled state only when the i-th first via state parameter group meets a third preset condition; the third preset condition refers to that the first state parameter and the second state parameter are both in the disabled state, and the third state parameter is in the enabled state; The third switching unit is configured to control the i-th fourth normal conductive via and the i-th first signal port to be electrically connected only when the third control signal is in the enabled state; When any state parameter is in the enabled state, it indicates that the corresponding conductive via is not failed; when any state parameter is in the disabled state, it indicates that the corresponding conductive via is failed.

22. The logic chip of claim 21, wherein, The i-th second repair circuit includes a fourth switching unit, a fifth switching unit, a sixth switching unit, a fourth logic unit, a fifth logic unit, and a sixth logic unit; The fourth logic unit is configured to output a fourth control signal in an enabled state only when the i-th first via state parameter group meets a fourth preset condition; the fourth preset condition refers to that the fourth state parameter is in the enabled state and the third state parameter is in the disabled state, or the fourth state parameter and the third state parameter are both in the enabled state and the second state parameter and the first state parameter are both in the disabled state; The fourth switching unit is configured to control the i-th fourth redundant conductive via and the i-th fourth signal port to be electrically connected only when the fourth control signal is in the enabled state; The fifth logic unit is configured to output a fifth control signal in an enabled state only when the i-th first via state parameter group meets a fifth preset condition; the fifth preset condition refers to that the third state parameter is in the enabled state, and at least one of the second state parameter and the first state parameter is in the enabled state; The fifth switching unit is configured to control the i-th fourth normal conductive via and the i-th fourth signal port to be electrically connected only when the fifth control signal is in the enabled state; The sixth switching unit is configured to output a sixth control signal in an enabled state only when the i-th first via state parameter group meets a sixth preset condition; the sixth preset condition refers to that the fourth state parameter and the third state parameter are both in the disabled state, and the second state parameter is in the enabled state; The sixth switching unit is configured to control the i-th first normal conductive via and the i-th fourth signal port to be electrically connected only when the sixth control signal is in the enabled state.

23. The logic chip of claim 22, wherein, In the case that the enable state is high and the disable state is low, the first logic unit comprises a first NOT gate, a first AND gate and a first OR gate; the second logic unit comprises a second AND gate and a second OR gate; the third logic unit comprises a third NOT gate and a third AND gate; the fourth logic unit comprises a fourth NOT gate, a fourth AND gate and a fourth OR gate; the fifth logic unit comprises a fifth AND gate and a fifth OR gate; and the sixth logic unit comprises a sixth NOT gate and a sixth AND gate. The input end of the first NOT gate receives the second state parameter, the output end of the first NOT gate is connected with one input end of the first AND gate, the other input end of the first AND gate receives the first state parameter, the output end of the first AND gate and the output end of the sixth AND gate are connected with two input ends of the first OR gate respectively, and the first OR gate outputs the first control signal. The two input ends of the second OR gate receive the third state parameter and the fourth state parameter respectively, the output end of the second OR gate is connected with one input end of the second AND gate, the other input end of the second AND gate receives the second state parameter, and the second AND gate outputs the second control signal. The input end of the third NOT gate is connected with the output end of the fifth OR gate, the output end of the third NOT gate is connected with one input end of the third AND gate, the other input end of the third AND gate receives the third state parameter, and the third AND gate outputs the third control signal. The input end of the fourth NOT gate receives the third state parameter, the output end of the fourth NOT gate is connected with one input end of the fourth AND gate, the other input end of the fourth AND gate receives the fourth state parameter, the output end of the fourth AND gate and the output end of the third AND gate are connected with two input ends of the fourth OR gate respectively, and the fourth OR gate outputs the fourth control signal. The two input ends of the fifth OR gate receive the first state parameter and the second state parameter respectively, the output end of the fifth OR gate is connected with one input end of the fifth AND gate, the other input end of the fifth AND gate receives the third state parameter, and the fifth AND gate outputs the fifth control signal. The input end of the sixth NOT gate is connected with the output end of the second OR gate, the output end of the sixth NOT gate is connected with one input end of the sixth AND gate, the other input end of the sixth AND gate receives the second state parameter, and the sixth AND gate outputs the sixth control signal.

24. The logic chip of claim 19, wherein, The i-th second control circuit comprises an i-th third repair unit and an i-th fourth repair unit. For the i-th third repair unit, one side thereof is respectively coupled to a second redundant conductive via, a first normal conductive via and a second normal first state parameter via in the i-th group of conductive vias, and the other side thereof is coupled to the i-th second signal port. The third repair unit is configured to receive and electrically connect one of the coupled conductive vias and the i-th second signal port based on the second group of via state parameters. For the i-th fourth repair unit, one side is coupled to the second normal conductive via, the normal conductive via and the third redundant conductive via in the i-th conductive via group respectively, and the other side is coupled to the i-th third signal port; the fourth repair unit is configured to receive and electrically connect one of the coupled conductive vias and the i-th third signal port based on the second via state parameter group.

25. The logic chip of claim 24, wherein, The i-th second via state parameter group includes a fifth state parameter, a sixth state parameter, a seventh state parameter and an eighth state parameter, and is used to indicate whether the second redundant conductive via, the second normal conductive via, the third normal conductive via and the third redundant conductive via in the i-th conductive via group are failed. The i-th third repair unit includes a seventh switching unit, an eighth switching unit, a ninth switching unit, a seventh logic unit, an eighth logic unit and a ninth logic unit. The seventh logic unit is configured to output a seventh control signal in an enabled state only when the i-th second via state parameter group meets a seventh preset condition; wherein the seventh preset condition refers to that the fifth state parameter is in an enabled state and the sixth state parameter is in a disabled state, or the fifth state parameter and the sixth state parameter are both in an enabled state and the seventh state parameter and the eighth state parameter are both in a disabled state. The seventh switching unit is configured to control the i-th second redundant conductive via to be electrically connected to the i-th second signal port only when the seventh control signal is in an enabled state. The eighth logic unit is configured to output an eighth control signal in an enabled state only when the i-th second via state parameter group meets an eighth preset condition; wherein the eighth preset condition refers to that the sixth state parameter is in an enabled state and at least one of the seventh state parameter and the eighth state parameter is in an enabled state. The eighth switching unit is configured to control the i-th second normal conductive via to be electrically connected to the i-th second signal port only when the eighth control signal is in an enabled state. The ninth logic unit is configured to output a ninth control signal in an enabled state only when the i-th second via state parameter group meets a ninth preset condition; wherein the ninth preset condition refers to that the fifth state parameter and the sixth state parameter are both in a disabled state and the seventh state parameter is in an enabled state. The ninth switching unit is configured to control the third normal conductive via to be electrically connected to the i-th second signal port only when the ninth control signal is in an enabled state. Wherein, any state parameter in an enabled state indicates that the corresponding conductive via is not failed; any state parameter in a disabled state indicates that the corresponding conductive via is failed.

26. The logic chip of claim 25, wherein, The fourth repair unit includes a tenth switching unit, an eleventh switching unit, a twelfth switching unit, a tenth logic unit, an eleventh logic unit and a twelfth logic unit. The tenth logic unit is configured to output a tenth control signal in an enabled state only when the ith second via state parameter group meets a tenth preset condition; the tenth preset condition refers to that the eighth state parameter is in the enabled state and the seventh state parameter is in the disabled state, or the eighth state parameter and the seventh state parameter are both in the enabled state and the sixth state parameter and the fifth state parameter are both in the disabled state; The tenth switching unit is configured to control the ith third redundant conductive via to be electrically connected with the ith third signal port only when the tenth control signal is in the enabled state; The eleventh logic unit is configured to output an eleventh control signal in an enabled state only when the ith second via state parameter group meets an eleventh preset condition; the eleventh preset condition refers to that the seventh state parameter is in the enabled state and at least one of the sixth state parameter and the fifth state parameter is in the enabled state; The eleventh switching unit is configured to control the ith third normal conductive via to be electrically connected with the ith third signal port only when the eleventh control signal is in the enabled state; The twelfth logic unit is configured to output a twelfth control signal in an enabled state only when the ith second via state parameter group meets a twelfth preset condition; the twelfth preset condition refers to that the eighth state parameter and the seventh state parameter are both in the disabled state and the sixth state parameter is in the enabled state; The twelfth switching unit is configured to control the ith second normal conductive via to be electrically connected with the ith third signal port only when the twelfth control signal is in the enabled state.

27. The logic chip of claim 26, wherein, When the enabled state is a high level and the disabled state is a low level, the seventh logic unit comprises a seventh NOT gate, a seventh AND gate and a seventh OR gate; the eighth logic unit comprises an eighth AND gate and an eighth OR gate; the ninth logic unit comprises a ninth NOT gate and a ninth AND gate; the tenth logic unit comprises a tenth NOT gate, a tenth AND gate and a tenth OR gate; the eleventh logic unit comprises an eleventh AND gate and an eleventh OR gate; and the twelfth logic unit comprises a twelfth NOT gate and a twelfth AND gate. An input end of the seventh NOT gate receives the sixth state parameter, an output end of the seventh NOT gate is connected with an input end of the seventh AND gate, another input end of the seventh AND gate receives the fifth state parameter, an output end of the seventh AND gate and an output end of the twelfth AND gate are connected with two input ends of the seventh OR gate respectively, and the seventh OR gate outputs a seventh control signal; two input ends of the eighth OR gate receive the seventh state parameter and the eighth state parameter respectively, an output end of the eighth OR gate is connected with an input end of the eighth AND gate, another input end of the eighth AND gate receives the sixth state parameter, and the eighth AND gate outputs the eighth control signal; an input end of the ninth NOT gate is connected with an output end of the eleventh OR gate, an output end of the ninth NOT gate is connected with an input end of the ninth AND gate, another input end of the ninth AND gate receives the seventh state parameter, and the ninth AND gate outputs the ninth control signal; An input end of the tenth NOT gate receives the seventh state parameter, an output end of the tenth NOT gate is connected with an input end of the tenth AND gate, another input end of the tenth AND gate receives the sixth state parameter, an output end of the tenth AND gate and an output end of the ninth AND gate are connected with two input ends of the tenth OR gate respectively, and the tenth OR gate outputs the tenth control signal; two input ends of the eleventh OR gate receive the fifth state parameter and the sixth state parameter respectively, an output end of the eleventh OR gate is connected with an input end of the eleventh AND gate, another input end of the eleventh AND gate receives the seventh state parameter, and the eleventh AND gate outputs the eleventh control signal; an input end of the twelfth NOT gate is connected with an output end of the eighth OR gate, an output end of the twelfth NOT gate is connected with an input end of the twelfth AND gate, another input end of the twelfth AND gate receives the sixth state parameter, and the twelfth AND gate outputs the twelfth control signal.

28. A chip stack structure, comprising: The chip stacking structure comprises the logic chip and at least one stacking unit as claimed in any one of claims 16-27, and the logic chip and the at least one stacking unit are stacked in sequence along a third direction; each stacking unit comprises a first memory chip, a second memory chip, a third memory chip and a fourth memory chip stacked in sequence along the third direction, and the third direction is perpendicular to a top surface of each memory chip; The first memory chip, the second memory chip, the third memory chip and the fourth memory chip are all the memory chip as claimed in any one of claims 1-15; The first memory chip and the second memory chip are stacked in a face-to-face manner, the second memory chip and the third memory chip are stacked in a back-to-back manner, and the third memory chip and the fourth memory chip are stacked in a face-to-face manner; The first memory chip in the first stacking unit and the logic chip are stacked in a face-to-face manner, or the first memory chip in the first stacking unit and the logic chip are stacked in a back-to-back manner.

29. The chip stack structure of claim 28, wherein, the chip position identification code of the first memory chip indicates a first type of position, the chip position identification code of the second memory chip indicates a second type of position, the chip position identification code of the third memory chip indicates a third type of position, and the chip position identification code of the fourth memory chip indicates a fourth type of position; or, the chip position identification code of the first memory chip indicates a first type of position, the chip position identification code of the second memory chip indicates a fourth type of position, the chip position identification code of the third memory chip indicates a third type of position, and the chip position identification code of the fourth memory chip indicates a second type of position. in the case where the logic chip and the first memory chip are stacked in a back-to-back manner, 30. The chip stack structure of claim 29, wherein, the fourth normal conductive via in the i-th conductive via group in the logic chip, the first normal conductive via in the i-th conductive via group in each of the first memory chips, the second normal conductive via in the i-th conductive via group in each of the second memory chips, the third normal conductive via in the i-th conductive via group in each of the third memory chips, and the fourth normal conductive via in the i-th conductive via group in each of the fourth memory chips are aligned along the third direction and constitute a normal signal transmission channel; the third normal conductive via in the i-th conductive via group in the logic chip, the second normal conductive via in the i-th conductive via group in each of the first memory chips, the first normal conductive via in the i-th conductive via group in each of the second memory chips, the fourth normal conductive via in the i-th conductive via group in each of the third memory chips, and the third normal conductive via in the i-th conductive via group in each of the fourth memory chips are aligned along the third direction and constitute a normal signal transmission channel; the second normal conductive via in the i-th conductive via group in the logic chip, the third normal conductive via in the i-th conductive via group in each of the first memory chips, the fourth normal conductive via in the i-th conductive via group in each of the second memory chips, the first normal conductive via in the i-th conductive via group in each of the third memory chips, and the second normal conductive via in the i-th conductive via group in each of the fourth memory chips are aligned along the third direction and constitute a normal signal transmission channel; the first normal conductive via in the i-th conductive via group in the logic chip, the fourth normal conductive via in the i-th conductive via group in each of the first memory chips, the third normal conductive via in the i-th conductive via group in each of the second memory chips, the second normal conductive via in the i-th conductive via group in each of the third memory chips, and the first normal conductive via in the i-th conductive via group in each of the fourth memory chips are aligned along the third direction and constitute a normal signal transmission channel; wherein i is a positive integer less than or equal to n.

31. The chip stack structure of claim 30, wherein, ​ The fourth redundant conductive via in the i-th conductive via group in the logic chip, the first redundant conductive via in the i-th conductive via group in each of the first memory chips, the second redundant conductive via in the i-th conductive via group in each of the second memory chips, the third redundant conductive via in the i-th conductive via group in each of the third memory chips, and the fourth redundant conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and constitute a redundant signal transmission channel. The third redundant conductive via in the i-th conductive via group in the logic chip, the second redundant conductive via in the i-th conductive via group in each of the first memory chips, the first redundant conductive via in the i-th conductive via group in each of the second memory chips, the fourth redundant conductive via in the i-th conductive via group in each of the third memory chips, and the third redundant conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and constitute a redundant signal transmission channel. The second redundant conductive via in the i-th conductive via group in the logic chip, the third redundant conductive via in the i-th conductive via group in each of the first memory chips, the fourth redundant conductive via in the i-th conductive via group in each of the second memory chips, the first redundant conductive via in the i-th conductive via group in each of the third memory chips, and the second redundant conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and constitute a redundant signal transmission channel. The first redundant conductive via in the i-th conductive via group in the logic chip, the fourth redundant conductive via in the i-th conductive via group in each of the first memory chips, the third redundant conductive via in the i-th conductive via group in each of the second memory chips, the second redundant conductive via in the i-th conductive via group in each of the third memory chips, and the first redundant conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and constitute a redundant signal transmission channel.

32. The chip stack structure of claim 29, wherein, In the case where the logic chip and the first memory chip are stacked in a back-to-back manner, The second normal conductive via in the i-th conductive via group in the logic chip, the first normal conductive via in the i-th conductive via group in each of the first memory chips, the second normal conductive via in the i-th conductive via group in each of the second memory chips, the third normal conductive via in the i-th conductive via group in each of the third memory chips, and the fourth normal conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and constitute a normal signal transmission channel. The first normal conductive via in the i-th conductive via group in the logic chip, the second normal conductive via in the i-th conductive via group in each of the first memory chips, the first normal conductive via in the i-th conductive via group in each of the second memory chips, the fourth normal conductive via in the i-th conductive via group in each of the third memory chips, and the third normal conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and form a normal signal transmission channel. The fourth normal conductive via in the i-th conductive via group in the logic chip, the third normal conductive via in the i-th conductive via group in each of the first memory chips, the fourth normal conductive via in the i-th conductive via group in each of the second memory chips, the first normal conductive via in the i-th conductive via group in each of the third memory chips, and the second normal conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and form a normal signal transmission channel. The third normal conductive via in the i-th conductive via group in the logic chip, the fourth normal conductive via in the i-th conductive via group in each of the first memory chips, the third normal conductive via in the i-th conductive via group in each of the second memory chips, the second normal conductive via in the i-th conductive via group in each of the third memory chips, and the first normal conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and form a normal signal transmission channel.

33. The chip stack structure of claim 32, wherein The second redundant conductive via in the i-th conductive via group in the logic chip, the first redundant conductive via in the i-th conductive via group in each of the first memory chips, the second redundant conductive via in the i-th conductive via group in each of the second memory chips, the third redundant conductive via in the i-th conductive via group in each of the third memory chips, and the fourth redundant conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and form a redundant signal transmission channel. The first redundant conductive via in the i-th conductive via group in the logic chip, the second redundant conductive via in the i-th conductive via group in each of the first memory chips, the first redundant conductive via in the i-th conductive via group in each of the second memory chips, the fourth redundant conductive via in the i-th conductive via group in each of the third memory chips, and the third redundant conductive via in the i-th conductive via group in each of the fourth memory chips are aligned in the third direction and form a redundant signal transmission channel. the fourth redundant conductive via in the i-th conductive via group in the logic chip, the third redundant conductive via in the i-th conductive via group in each of the first memory chips, the fourth redundant conductive via in the i-th conductive via group in each of the second memory chips, the first redundant conductive via in the i-th conductive via group in each of the third memory chips, and the second redundant conductive via in the i-th conductive via group in each of the fourth memory chips are aligned along the third direction and form a redundant signal transmission channel; the third redundant conductive via in the i-th conductive via group in the logic chip, the fourth redundant conductive via in the i-th conductive via group in each of the first memory chips, the third redundant conductive via in the i-th conductive via group in each of the second memory chips, the second redundant conductive via in the i-th conductive via group in each of the third memory chips, and the first redundant conductive via in the i-th conductive via group in each of the fourth memory chips are aligned along the third direction and form a redundant signal transmission channel.

34. The chip stack structure of any one of claims 28-33, wherein, for two chips connected face-to-face, the positions where the conductive vias in the two chips are aligned along the third direction are electrically connected by a hybrid bonding process; for two chips connected back-to-back or for two chips connected back-to-face, the positions where the conductive vias in the two chips are aligned along the third direction are electrically connected by a conductive bump bonding process; or, for two chips connected face-to-face or for two chips connected back-to-back or for two chips connected back-to-face, the positions where the conductive vias in the two chips are aligned along the third direction are electrically connected by the hybrid bonding process; or, for two chips connected face-to-face or for two chips connected back-to-back or for two chips connected back-to-face, the positions where the conductive vias in the two chips are aligned along the third direction are electrically connected by the conductive bump bonding process.

35. A memory, comprising: The memory comprises the chip stack structure of any one of claims 28-34.

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