Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a preparation method thereof. The preparation method comprises: providing a substrate, forming a first dielectric layer in an array region, and forming a first conductive layer in a peripheral region; forming a plurality of contact holes in the array region, the contact holes penetrating through the first dielectric layer and exposing corresponding active regions; filling a second conductive layer in the contact holes; laminating a third conductive layer and a second dielectric layer on a side of the first dielectric layer, the first conductive layer and the second conductive layer away from the substrate; and patterning the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer to form a plurality of bit line structures, wherein the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer are respectively patterned in a preset order, and the first dielectric layer and the second conductive layer are respectively patterned using different etching gases. The present disclosure is conducive to reducing the parasitic capacitance of the bit line structure, thereby effectively improving the performance and reliability of the memory.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in computers and other electronic devices, consisting of multiple memory cells. Each memory cell includes a storage capacitor and a transistor electrically connected to the storage capacitor. The transistor includes a gate, a source region, and a drain region. The transistor's gate is used to electrically connect to the word line structure, the transistor's source region forms the bit line contact region and is electrically connected to the bit line structure, and the transistor's drain region forms the memory node contact region and is electrically connected to the storage capacitor.

[0003] Currently, in the fabrication process of matching memory cells, transistors are buried in the substrate, and bit line structures are connected to the bit line contact area through contact holes and extend above the substrate along a predetermined direction. However, due to the footing effect in the dry etching process, the bottom of the extension of the bit line structure above the substrate tends to be significantly larger than the upper middle part of the extension. This can easily lead to a smaller distance between the bottom of the extension and the adjacent bit line structure, resulting in a large parasitic capacitance of the bit line structure, which in turn can easily affect the performance and reliability of the memory. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, which helps to reduce the parasitic capacitance of the bit line structure, thereby effectively improving the performance and reliability of the memory.

[0005] On one hand, embodiments of this disclosure provide a method for fabricating a semiconductor structure, comprising the following steps.

[0006] A substrate is provided; the substrate has an array region and a peripheral region, and also includes: multiple active regions located within the array region.

[0007] A first dielectric layer is formed in the array region, and a first conductive layer is formed in the peripheral region. The first conductive layer is patterned to form a gate.

[0008] Multiple contact holes are formed in the array region; the contact holes penetrate the first dielectric layer and expose the corresponding active regions.

[0009] A second conductive layer is filled into the contact hole.

[0010] A third conductive layer and a second dielectric layer are formed by stacking the first dielectric layer, the first conductive layer and the second conductive layer on the side away from the substrate.

[0011] The second dielectric layer, the third conductive layer, the first dielectric layer, and the second conductive layer are patterned to form multiple bit line structures. The second dielectric layer, the third conductive layer, the first dielectric layer, and the second conductive layer are patterned in a preset order, and the first dielectric layer and the second conductive layer are patterned using different etching gases.

[0012] In some embodiments of this disclosure, the top surface of the first dielectric layer away from the substrate is substantially flush with the top surface of the second conductive layer away from the substrate.

[0013] In some embodiments of this disclosure, forming a first dielectric layer in the array region and a first conductive layer in the peripheral region includes the following steps.

[0014] A first mask layer is formed, which covers the substrate of the array region and exposes the substrate of the surrounding region.

[0015] A first conductive layer is formed on the substrate in the peripheral region.

[0016] A first protective layer is formed on the first conductive layer.

[0017] Remove the first mask layer.

[0018] A first dielectric layer is formed on the substrate of the array region.

[0019] In some embodiments of this disclosure, the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer. The formation of the first dielectric layer on the substrate of the array region further includes the following steps.

[0020] A first sub-dielectric layer is formed on the substrate of the array region.

[0021] Remove the first protective layer.

[0022] A second mask layer is formed, which covers the first conductive layer and exposes the first sub-dielectric layer.

[0023] A second sub-dielectric layer is formed on the first sub-dielectric layer.

[0024] A second protective layer is formed on the second sub-dielectric layer.

[0025] Remove the second mask layer;

[0026] Remove the second protective layer.

[0027] In some embodiments of this disclosure, the first sub-dielectric layer and the second sub-dielectric layer are made of the same material.

[0028] In other embodiments of this disclosure, forming a first dielectric layer in the array region and a first conductive layer in the peripheral region includes the following steps.

[0029] A first conductive material layer is formed on the substrate.

[0030] A third protective layer is formed on the first conductive material layer in the surrounding area.

[0031] Remove the first conductive material layer in the array region so that the first conductive material layer in the surrounding region constitutes the first conductive layer.

[0032] A third mask layer is formed, which covers the first conductive layer and exposes the substrate of the array region.

[0033] A first dielectric layer is formed on the substrate of the array region.

[0034] A fourth protective layer is formed on the first dielectric layer.

[0035] Remove the third mask layer.

[0036] Remove the fourth protective layer.

[0037] In some embodiments of this disclosure, the etching gas for the first and second dielectric layers includes fluorine-containing gas or nitrogen. The etching gas for the second conductive layer includes one or more of chlorine, hydrogen chloride, or hydrogen bromide.

[0038] On the other hand, this disclosure also provides a semiconductor structure that can be prepared using the semiconductor structure preparation methods described in some of the above embodiments.

[0039] The semiconductor structure includes a substrate, a first conductive layer, and multiple bit line structures. The substrate has an array region and a peripheral region, and includes multiple active regions and multiple contact holes located within the array region; the contact holes expose corresponding active regions. The first conductive layer is located in the peripheral region. Multiple bit line structures are disposed parallel to each other on the substrate.

[0040] The bitline structure includes a first part and a second part. The first part is located within a contact hole and is electrically connected to the active region. The first part includes a second conductive layer, a third conductive layer, and a second dielectric layer sequentially stacked in a direction away from the active region. The second part is located on a substrate and is electrically connected to the first part. The second part includes a first dielectric layer, a third conductive layer, and a second dielectric layer sequentially stacked in a direction away from the substrate, wherein the sidewalls of the first dielectric layer are flush with the sidewalls of the third conductive layer, and the sidewalls of the first dielectric layer are substantially perpendicular to the substrate.

[0041] In some embodiments of this disclosure, the top surface of the first dielectric layer away from the substrate is substantially flush with the top surface of the second conductive layer away from the substrate.

[0042] In some embodiments of this disclosure, the first dielectric layer includes: a first sub-dielectric layer and a second sub-dielectric layer stacked along a direction away from the substrate; the first sub-dielectric layer and the second sub-dielectric layer are made of the same material. The second dielectric layer includes: a third sub-dielectric layer and a fourth sub-dielectric layer stacked along a direction away from the substrate; the third sub-dielectric layer and the fourth sub-dielectric layer are made of the same material.

[0043] The embodiments disclosed herein may have, or at least have, the following advantages:

[0044] In this embodiment, the first dielectric layer and the second conductive layer used to form the bit line structure are formed independently in a direction parallel to the substrate. The second dielectric layer, the third conductive layer, the first dielectric layer, and the second conductive layer are patterned in a predetermined order, and different etching gases are used to pattern the first dielectric layer and the second conductive layer. This ensures that the sidewalls of the bottom first dielectric layer in the bit line structure remain as vertical as possible without damaging the substrate surface isolation layer. This effectively improves the problem of large parasitic capacitance between adjacent bit line structures due to the large bottom dimension of the first dielectric layer caused by the etching footing effect. This embodiment can reduce the parasitic capacitance of the bit line structure, thereby effectively improving the performance and reliability of the memory.

[0045] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features, objects, and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in some embodiments;

[0048] Figure 2 for Figure 1 A flowchart illustrating step S200 in the method shown.

[0049] Figure 3 for Figure 2 A flowchart illustrating step S250 in the method shown.

[0050] Figure 4 for Figure 1 A flowchart illustrating another step S200 in the method shown.

[0051] Figure 5 A structural comparison diagram of two semiconductor structures provided in some embodiments;

[0052] Figure 6 This is a top view schematic diagram of a semiconductor structure provided in some embodiments;

[0053] Figure 7 This is a schematic diagram of a structure obtained after forming a first subdielectric layer, as provided in some embodiments;

[0054] Figure 8 This is a schematic diagram of a structure obtained after forming a first photoresist pattern layer, as provided in some embodiments;

[0055] Figure 9 This is a schematic diagram of a structure obtained after exposing the peripheral substrate region, as provided in some embodiments;

[0056] Figure 10 This is a schematic diagram of a structure obtained after forming a first conductive layer, as provided in some embodiments;

[0057] Figure 11 This is a schematic diagram of a structure obtained after forming a first protective layer and removing a first mask layer, as provided in some embodiments;

[0058] Figure 12 This is a schematic diagram of the structure obtained after removing the first protective layer, provided in some embodiments;

[0059] Figure 13 This is a schematic diagram of a structure obtained after forming a second photoresist pattern layer, provided in some embodiments;

[0060] Figure 14 This is a schematic diagram of a structure obtained after exposing the first subdielectric layer, as provided in some embodiments;

[0061] Figure 15 This is a schematic diagram of a structure obtained after forming a second sub-dielectric layer and a second protective layer, provided in some embodiments;

[0062] Figure 16 This is a schematic diagram of a structure obtained after removing the second mask layer in the peripheral region, as provided in some embodiments;

[0063] Figure 17 This is a schematic diagram of a structure obtained after forming a first dielectric layer in the array region and a first conductive layer in the peripheral region, as provided in some embodiments;

[0064] Figure 18 This is a schematic diagram of a structure obtained after forming a first conductive material layer, as provided in some embodiments;

[0065] Figure 19 This is a schematic diagram of a structure obtained after forming a third protective layer in the peripheral area, as provided in some embodiments;

[0066] Figure 20 This is a schematic diagram of a structure obtained after forming a first conductive layer in the peripheral region, as provided in some embodiments;

[0067] Figure 21 This is a schematic diagram of a structure obtained after forming a third photoresist pattern layer, provided in some embodiments;

[0068] Figure 22 This is a schematic diagram of a structure obtained after exposing the first sub-dielectric layer of the array region, as provided in some embodiments;

[0069] Figure 23 This is a schematic diagram of a structure obtained after forming a second sub-dielectric layer in the array region, as provided in some embodiments;

[0070] Figure 24 This is a schematic diagram of a structure obtained after forming a fourth protective layer in the array region, as provided in some embodiments;

[0071] Figure 25 This is a schematic diagram of a structure obtained after exposing the first conductive layer in the peripheral region, as provided in some embodiments;

[0072] Figure 26 This is a schematic diagram of a structure obtained after forming a fourth mask layer, provided in some embodiments;

[0073] Figure 27 This is a schematic diagram of a structure obtained after forming contact holes in the array region, as provided in some embodiments;

[0074] Figure 28 This is a schematic diagram of a structure obtained after forming a second conductive material layer, as provided in some embodiments;

[0075] Figure 29 This is a schematic diagram of a structure obtained after forming a second conductive layer, provided in some embodiments;

[0076] Figure 30 This is a schematic diagram of a structure obtained after forming a second dielectric layer and a gate structure in the peripheral region, as provided in some embodiments;

[0077] Figure 31 This is a schematic diagram of a structure obtained after forming a second interlayer dielectric layer, as provided in some embodiments;

[0078] Figure 32This is a schematic diagram of a structure obtained after forming a second antireflective layer, provided in some embodiments;

[0079] Figure 33 This is a schematic diagram of a structure obtained after a patterned hard mask layer, as provided in some embodiments;

[0080] Figure 34 This is a schematic diagram of a structure obtained after forming a bitline structure, provided in some embodiments;

[0081] Figure 35 This is a schematic flowchart illustrating the etching process of each thin film in a bitline structure provided in some embodiments.

[0082] Explanation of reference numerals in the attached figures:

[0083] 1-Substrate, 01-Bottom silicon nitride layer, 02-Polysilicon layer, 03-Titanium nitride layer, 04-Tungsten metal layer, 05-Top silicon nitride layer, 06-Sidewall, 061-First silicon nitride layer, 062-Silicon oxide layer, 063-Second silicon nitride layer; AA-Active region, BL-Bit line structure, BLA-First part, BLB-Second part, WL-Word line structure, 11-Isolation layer, 21-First dielectric layer, 211-First sub-dielectric layer, 212-Second sub-dielectric layer, 22-Second dielectric layer, 221-Third sub-dielectric layer, 222-Fourth sub-dielectric layer, 31-First conductive layer, 310-First conductive material layer, 32-Second conductive layer, 33-Third Conductive layer, 34-Barrier layer, R1-Array region, R2-Peripheral region, H-Contact hole, YM1-First mask layer, PR1-First photoresist pattern layer, YM2-Second mask layer, PR2-Second photoresist pattern layer, YM3-Third mask layer, PR3-Third photoresist pattern layer, 41-First protective layer, 42-Second protective layer, 43-Third protective layer, 44-Fourth protective layer, YM4-Fourth mask layer, SOH-Spin-coating mask layer, 51-Pattern transfer layer, 61-Gate dielectric layer, 62-Sidewall, 63-First interlayer dielectric layer, 64-Second interlayer dielectric layer, 71-Hard mask layer, 72-First anti-reflection layer, 73-Second anti-reflection layer. Detailed Implementation

[0084] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0085] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0086] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "electrically connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0087] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0088] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.

[0089] Currently, in the fabrication process of matching memory cells, transistors are buried in the substrate, and bit line structures are connected to the bit line contact area through contact holes and extend above the substrate along a predetermined direction. However, due to the footing effect in the dry etching process, the bottom of the extension of the bit line structure above the substrate tends to be significantly larger than the upper middle part of the extension. This can easily lead to a smaller distance between the bottom of the extension and the adjacent bit line structure, resulting in a large parasitic capacitance of the bit line structure, which in turn can easily affect the performance and reliability of the memory.

[0090] Based on this, the present disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure, which helps to reduce the parasitic capacitance of the bit line structure, thereby effectively improving the performance and reliability of the memory.

[0091] Please see Figure 1 This disclosure provides a method for fabricating a semiconductor structure, comprising the following steps.

[0092] S100 provides a substrate; the substrate has an array region and a peripheral region, and also includes multiple active regions located within the array region.

[0093] S200, a first dielectric layer is formed in the array region and a first conductive layer is formed in the peripheral region. The first conductive layer is patterned to form a gate.

[0094] S300, multiple contact holes are formed in the array region; the contact holes penetrate the first dielectric layer and expose the corresponding active regions.

[0095] S400, a second conductive layer is filled into the contact hole.

[0096] S500, a third conductive layer and a second dielectric layer are formed by stacking the first dielectric layer, the first conductive layer and the second conductive layer on the side away from the substrate.

[0097] S600, patterning the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer to form multiple bit line structures; wherein, the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer are patterned in a preset order, and the first dielectric layer and the second conductive layer are patterned using different etching gases.

[0098] In this embodiment, the first dielectric layer and the second conductive layer used to form the bit line structure are formed independently in a direction parallel to the substrate. The second dielectric layer, the third conductive layer, the first dielectric layer, and the second conductive layer are patterned in a predetermined order, and different etching gases are used to pattern the first dielectric layer and the second conductive layer. This ensures that the sidewalls of the bottom first dielectric layer in the bit line structure remain as vertical as possible without damaging the substrate surface isolation layer. This effectively improves the problem of large parasitic capacitance between adjacent bit line structures due to the large bottom dimension of the first dielectric layer caused by the etching footing effect. This embodiment can reduce the parasitic capacitance of the bit line structure, thereby effectively improving the performance and reliability of the memory.

[0099] In some embodiments of this disclosure, the top surface of the first dielectric layer away from the substrate is substantially flush with the top surface of the second conductive layer away from the substrate.

[0100] In some embodiments of this disclosure, please refer to Figure 2 In step S200, a first dielectric layer is formed in the array region and a first conductive layer is formed in the peripheral region, including the following steps S210 to S250.

[0101] S210, forming a first mask layer, the first mask layer covers the substrate of the array region and exposes the substrate of the surrounding region.

[0102] S220, a first conductive layer is formed on the substrate in the peripheral region.

[0103] S230, a first protective layer is formed on the first conductive layer.

[0104] S240, Remove the first mask layer.

[0105] S250, a first dielectric layer is formed on the substrate of the array region.

[0106] In some embodiments of this disclosure, the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer. See also... Figure 3 In step S250, the formation of a first dielectric layer on the substrate of the array region further includes the following steps S251 to S257.

[0107] S251, a first sub-dielectric layer is formed on the substrate of the array region.

[0108] S252, Remove the first protective layer.

[0109] S253, forming a second mask layer, the second mask layer covering the first conductive layer and exposing the first sub-dielectric layer.

[0110] S254, a second sub-dielectric layer is formed on the first sub-dielectric layer.

[0111] S255, a second protective layer is formed on the second sub-dielectric layer.

[0112] S256, Remove the second mask layer;

[0113] S257, Remove the second protective layer.

[0114] In some embodiments of this disclosure, the first sub-dielectric layer and the second sub-dielectric layer are made of the same material.

[0115] In other embodiments of this disclosure, please refer to Figure 4 In step S200, a first dielectric layer is formed in the array region and a first conductive layer is formed in the peripheral region, including the following steps S210' to S280'.

[0116] S210', a first conductive material layer is formed on the substrate.

[0117] S220' forms a third protective layer on the first conductive material layer in the surrounding area.

[0118] S230', Remove the first conductive material layer of the array region, so that the first conductive material layer of the peripheral region constitutes the first conductive layer.

[0119] S240', forming a third mask layer, which covers the first conductive layer and exposes the substrate of the array region.

[0120] S250' forms a first dielectric layer on the substrate of the array region.

[0121] S260', a fourth protective layer is formed on the first dielectric layer.

[0122] S270', Remove the third mask layer.

[0123] S280', Remove the fourth protective layer.

[0124] In some embodiments of this disclosure, the etching gas for the first and second dielectric layers includes fluorine-containing gas or nitrogen. The etching gas for the second conductive layer includes one or more of chlorine, hydrogen chloride, or hydrogen bromide.

[0125] It is understood that in some of the above embodiments, although Figures 1-4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-4At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0126] To more clearly illustrate the method for fabricating the semiconductor structure provided in the embodiments of this disclosure, the following is combined with... Figures 5 to 35 Some possible implementations of the method for fabricating this semiconductor structure are described in detail. Furthermore, before detailing the method for fabricating the semiconductor structure provided in the embodiments of this disclosure, for ease of understanding, a brief introduction to the semiconductor structure provided in the embodiments of this disclosure is given, and a structural comparison is made between the bit line structure in related technologies and this application. Figure 5 Figure (a) is a schematic diagram of a semiconductor structure in the related art. Figure 5 Figure (b) is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0127] Please see Figure 5 In Figure (a), in the semiconductor structure provided by the related technology, the extension of the bit line structure BL above the substrate 1 may include, for example, a bottom silicon nitride layer 01 and a polysilicon layer 02, a titanium nitride layer 03, a tungsten metal layer 04, and a top silicon nitride layer 05 stacked on the bottom silicon nitride layer 01. Since the polysilicon layer 02 serves as a hard mask for patterning the bottom silicon nitride layer 01 during etching, the patterned bottom silicon nitride layer 01 tends to have base plates, resulting in a relatively small distance D2 between the bottom silicon nitride layer 01 and the adjacent bit line structure BL. For example... Figure 5 As shown in Figure (a), the distance dimension D2 is smaller than the distance dimension D1 between the tops of adjacent bit line structures BL. Accordingly, after the sidewalls 06 of the subsequent bit line structures BL are formed (e.g., non-ON sidewalls composed of a first silicon nitride layer 061, a silicon oxide layer 062, and a second silicon nitride layer 063), the sidewalls 06 will conformally cover the bottom silicon nitride layer 01, resulting in a large parasitic capacitance between adjacent bit line structures BL.

[0128] Please see Figure 5 In Figure (b), this embodiment of the present disclosure changes the type of thin film to be deposited during the fabrication of the extension of the bit line structure BL located above the substrate 1, and accordingly adjusts the etching sequence and process of each thin film (see the fabrication method provided below for details). This allows the extension to include a first dielectric layer 21, a third conductive layer 33, and a second dielectric layer 22 sequentially stacked along a direction away from the substrate 1, ensuring that the sidewalls of the first dielectric layer 21 are flush with the sidewalls of the third conductive layer 33, and that the sidewalls of the first dielectric layer 21 are approximately perpendicular to the substrate 1. Thus, for example... Figure 5 As shown in Figure (b), the distance D3 between the bottom of the first dielectric layer 21 and the adjacent bit line structure BL can be consistent with, or approximately equal to, the distance D1 between the tops of the adjacent bit line structures BL. This effectively reduces the parasitic capacitance of the bit line structure BL, thereby improving the performance and reliability of the semiconductor structure and memory.

[0129] Figure 6 A top view schematic diagram of a semiconductor structure is shown. Furthermore, in Figures 7 to 34 Among the various aa, bb, cc, dd, and ee views shown, the aa view corresponds to... Figure 6 A schematic cross-sectional view along the inner aa direction; the corresponding bb view is... Figure 6 A schematic cross-sectional view along the inner bb direction; the corresponding cc view is... Figure 6 A schematic cross-sectional view along the inner cc direction; the corresponding dd view is... Figure 6 A schematic cross-sectional view along the inner edge dd direction; the corresponding ee view is... Figure 6 A schematic cross-sectional view along the inner ee direction.

[0130] In step S100, please refer to Figure 6 and Figure 7 A substrate 1 is provided, which has an array region R1 and a peripheral region R2. Furthermore, the substrate 1 also includes a plurality of active regions AA located within the array region R1.

[0131] For example, substrate 1 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 can be a single-layer structure or a multilayer structure. For example, substrate 1 can be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 can be a layered substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0132] For example, a shallow trench isolation structure (STI) is provided in the substrate 1. The shallow trench isolation structure (STI) can isolate multiple active regions (AA) arranged in an array within the array region R1 of the substrate 1.

[0133] In some examples, shallow trench isolation structures (STIs) include, but are not limited to, silicon oxide (SiO2) isolation structures. For example, shallow trench isolation structures (STIs) can also be composed of multiple layers of isolation layers stacked together.

[0134] It is understandable that the peripheral region R1 of substrate 1 can also be isolated by shallow trench isolation structure STI to create multiple active regions for housing planar transistors required in external circuits.

[0135] For example, please refer to Figure 6 The array region R1 of substrate 1 is typically matched with the distribution of the active region AA, and includes multiple word line structures WL and multiple bit line structures BL arranged in parallel and spaced order. The word line structures WL extend, for example, along the X direction, and can be embedded within substrate 1. Figure 7 As shown in the illustration. The internal composition of the word line structure WL is not described in detail in this embodiment. The bit line structure BL extends, for example, along the Y direction; the fabrication of the bit line structure BL can be found in the subsequent related steps of this embodiment. The aforementioned X and Y directions intersect, for example, orthogonally.

[0136] Please continue reading. Figure 7 After forming the word line structure WL in the substrate 1, an isolation layer 11 can be formed on the surface of the substrate 1 in the array region R1 to cover the top surface of the word line structure WL and the surface of the substrate 1. The isolation layer 11 is, for example, a silicon oxide layer.

[0137] In some of the following embodiments, taking the first dielectric layer 21 including a first sub-dielectric layer 211 and a second sub-dielectric layer 212 as an example, two different implementation processes are given for step S200.

[0138] In some embodiments, please refer to Figures 7 to 17 Step S200 may include the following steps S210 to S250, and step S250 may include the following steps S251 to S257.

[0139] In step S251, please refer to Figure 7 A first sub-dielectric layer 211 is formed on the substrate 1 of the array region R1, for example, the first sub-dielectric layer 211 can be formed on the surface of the isolation layer 11. In this way, it is advantageous to etch and protect the isolation layer 11 through the first sub-dielectric layer 211.

[0140] Furthermore, it is understood that it is permissible for the first sub-dielectric layer 211 to be adaptively formed in any step prior to the subsequent formation of the second sub-dielectric layer 212.

[0141] In step S210, please refer to Figure 8 and Figure 9 A first mask layer YM1 is formed, which covers the substrate 1 of the array region R1 and exposes the substrate 1 of the peripheral region R2.

[0142] For example, the first mask layer YM1 includes, but is not limited to, a spin-coated mask layer.

[0143] For example, the first mask layer YM1 can be fully covered on the substrate 1, for example, covering the surface of the first sub-dielectric layer 211 of the array region R1 and the surface of the substrate 1 of the peripheral region R2 (e.g., the surface of the shallow trench isolation structure STI); then, the first mask layer YM1 of the peripheral region R2 is etched away by the pattern in the first photoresist pattern layer PR1 formed on the first mask layer YM1, so as to expose the substrate 1 of the peripheral region R2.

[0144] In step S220, please refer to Figure 10 A first conductive layer 31 is formed on the substrate 1 in the peripheral region R2.

[0145] For example, such as Figure 10 and Figure 11 As shown, with the first mask layer YM1 retained on the substrate 1 of the array region R1, the first conductive layer 31 can be deposited on the substrate 1 in its entirety, for example, covering the surface of the first mask layer YM1 in the array region R1 and the surface of the substrate 1 in the peripheral region R2; then, the first conductive layer 31 located in the peripheral region R2 is obtained by removing the first mask layer YM1 and the first conductive layer 31 thereon.

[0146] For example, the first conductive layer 31 includes, but is not limited to, a polysilicon layer. The first conductive layer 31 can be patterned to form the gate of a planar transistor on the peripheral region R2 substrate 1.

[0147] In step S230, please continue reading. Figure 10 A first protective layer 41 is formed on the first conductive layer 31. The orthographic projection of the first protective layer 41 on the substrate 1 overlaps with the orthographic projection of the first conductive layer 31 on the substrate 1.

[0148] For example, the first protective layer 41 includes, but is not limited to, a photoresist material layer.

[0149] In step S240, please refer to Figure 11 Remove the first mask layer YM1 to expose the first sub-dielectric layer 211 of the array region R1.

[0150] For example, the first mask layer YM1 can be removed using a wet etching process.

[0151] In step S252, please refer to Figure 12 Remove the first protective layer 41 to expose the first conductive layer 31 of the surrounding area R2.

[0152] In step S253, please refer to Figure 13 and Figure 14 A second mask layer YM2 is formed, which covers the first conductive layer 31 and exposes the first sub-dielectric layer 211.

[0153] For example, the second mask layer YM2 includes, but is not limited to, a spin-coated mask layer.

[0154] For example, the second mask layer YM1 can be formed entirely on the substrate 1, for example, covering the surface of the first sub-dielectric layer 211 of the array region R1 and the surface of the first conductive layer 31 of the peripheral region R2; then, the second mask layer YM2 of the array region R1 is etched away by the pattern in the second photoresist pattern layer PR2 formed on the second mask layer YM2, so that the second mask layer YM2 covers the first conductive layer 31 of the peripheral region R2 and exposes the first sub-dielectric layer 211 of the array region R1.

[0155] In step S254, please refer to Figure 15 and Figure 16 A second sub-dielectric layer 212 is formed on the first sub-dielectric layer 211.

[0156] For example, the first sub-dielectric layer 211 and the second sub-dielectric layer 212 are made of the same material.

[0157] For example, the materials of the first sub-dielectric layer 211 and the second sub-dielectric layer 212 include, but are not limited to, silicon nitride.

[0158] For example, such as Figure 15 and Figure 16 As shown, with the second mask layer YM2 remaining on the substrate 1 in the peripheral region R2, the second sub-dielectric layer 212 can be deposited on the substrate 1 in its entirety, for example, covering the surface of the first sub-dielectric layer 211 in the array region R1 and the surface of the second mask layer YM2 in the peripheral region R2; then, by removing the second mask layer YM2 and the second sub-dielectric layer 212 thereon, the second sub-dielectric layer 212 located in the array region R1 is obtained, and the second sub-dielectric layer 212 and the first sub-dielectric layer 211 together constitute the first dielectric layer 21.

[0159] In step S255, please refer to Figure 16 A second protective layer 42 is formed on the second sub-dielectric layer 212. The orthographic projection of the second protective layer 42 on the substrate 1 overlaps with the orthographic projection of the first dielectric layer 21 on the substrate 1.

[0160] For example, the second protective layer 42 includes, but is not limited to, a photoresist material layer.

[0161] In step S256, please refer to... Figure 16 Remove the second mask layer YM2 to expose the first conductive layer 31 of the peripheral region R2.

[0162] For example, the second mask layer YM2 can be removed using a wet etching process or a dry etching process.

[0163] In step S257, please refer to Figure 17 Remove the second protective layer 42 to expose the first dielectric layer 21 (e.g., the second sub-dielectric layer 212 facing away from the surface of the substrate 1) of the array region R1.

[0164] In other embodiments, please refer to Figure 7 , Figures 18-25 as well as Figure 17 Step S200 may include the following steps S210' to S280'.

[0165] For example, before performing step S210', please refer to Figure 7 Alternatively, the first sub-dielectric layer 211 can be formed on the substrate 1 of the array region R1 first, for example, the first sub-dielectric layer 211 can be formed on the surface of the isolation layer 11.

[0166] Based on this, in step S210', please refer to Figure 18 A first conductive material layer 310 is formed on the substrate 1.

[0167] Here, the first conductive material layer 310 can be located on the entire substrate 1, for example, covering the surface of the first sub-dielectric layer 211 of the array region R1 and the surface of the substrate 1 of the peripheral region R2 (e.g., the surface of the shallow trench isolation structure STI).

[0168] For example, the first conductive material layer 310 includes, but is not limited to, a polycrystalline silicon layer.

[0169] In step S220', please refer to Figure 19 A third protective layer 43 is formed on the first conductive material layer 310 in the surrounding area R2.

[0170] For example, the third protective layer 43 includes, but is not limited to, a photoresist material layer.

[0171] In step S230', please refer to Figure 20 Remove the first conductive material layer 310 of the array region R1, so that the first conductive material layer 310 of the peripheral region R2 constitutes the first conductive layer 31.

[0172] Here, it can be understood that the orthographic projection of the first conductive layer 31 on the substrate 1 overlaps with the orthographic projection of the third protective layer 43 on the substrate 1. The first conductive material layer 310 of the array region R1 can be removed by alignment using the third protective layer 43 as a mask. Furthermore, after removing the first conductive material layer 310 of the array region R1, the surface of the first sub-dielectric layer 211 within the array region R1 can also be exposed.

[0173] In step S240', please refer to Figure 21 and Figure 22A third mask layer YM3 is formed, which covers the first conductive layer 31 and exposes the substrate 1 of the array region R1.

[0174] For example, the third mask layer YM3 includes, but is not limited to, a spin-coated mask layer.

[0175] For example, such as Figure 21 and Figure 22 As shown, the third mask layer YM3 can be formed entirely on the substrate 1, for example, covering the surface of the first sub-dielectric layer 211 of the array region R1 and the surface of the first conductive layer 31 of the peripheral region R2; then, the third mask layer YM3 of the array region R1 is etched away by the pattern in the third photoresist pattern layer PR3 formed on the third mask layer YM3, so that the third mask layer YM3 covers the first conductive layer 31 of the peripheral region R2 and exposes the first sub-dielectric layer 211 of the array region R1.

[0176] In step S250', please combine Figures 23-25 It is understood that a first dielectric layer 21 is formed on the substrate 1 of the array region R1. Based on the previously formed first sub-dielectric layer 211, a second sub-dielectric layer 212 is formed on the surface of the first sub-dielectric layer 211 in step S250', thereby obtaining a first dielectric layer 21 composed of the first sub-dielectric layer 211 and the second sub-dielectric layer 212.

[0177] It is understood that different structures matching the first dielectric layer 21, and the first dielectric layer 21 being formed using other implementation methods, are all permissible.

[0178] For example, please refer to Figure 23 With the third mask layer YM3 retained on the substrate 1 in the peripheral region R2, the second sub-dielectric layer 212 can be deposited entirely on the substrate 1, for example, covering the surface of the first sub-dielectric layer 211 in the array region R1 and the surface of the second mask layer YM2 in the peripheral region R2; then, as Figure 24 and Figure 25 As shown, after performing steps S260' and S270', the third mask layer YM3 and its second sub-dielectric layer 212 can be removed synchronously to obtain the second sub-dielectric layer 212 located in the array region R1, and the second sub-dielectric layer 212 and the first sub-dielectric layer 211 can be used together to form the first dielectric layer 21.

[0179] In step S260', please refer to Figure 24 A fourth protective layer 44 is formed on the first dielectric layer 21.

[0180] For example, the fourth protective layer 44 includes, but is not limited to, a photoresist material layer.

[0181] In step S270', please refer to Figure 25 Remove the third mask layer YM3 to expose the first conductive layer 31 of the surrounding region R2.

[0182] For example, the second sub-dielectric layer 212 on the third mask layer YM3 can be removed synchronously in step S270'.

[0183] In step S280', please refer to Figure 17 After removing the fourth protective layer 44, the first dielectric layer 21 of the array region R1 (e.g., the second sub-dielectric layer 212 facing away from the surface of the substrate 1) can be exposed.

[0184] Therefore, after performing step S200, this embodiment of the present disclosure can obtain a structure in which the first dielectric layer 21 is exposed in the array region R1, and the first conductive layer 31 is exposed in the peripheral region R2, for example... Figure 17 As shown in the image.

[0185] In the above description of this specification, the terms "removal" and "etching" can be implemented as required by at least one etching process of wet etching and / or dry etching.

[0186] Based on this, please refer to Figure 26 and Figure 27 In step S300, a plurality of contact holes H are formed in the array region R1; the contact holes H penetrate the first dielectric layer 21 and expose the corresponding active region AA.

[0187] For example, please refer to Figure 26 A fourth mask layer YM4 is formed on the structure obtained after the formation of the first dielectric layer 21 and the first conductive layer 31. The fourth mask layer YM4 includes, for example, a pattern transfer layer 51 and a spin-coating mask layer SOH sequentially stacked in a direction away from the substrate 1, and mask patterns for defining the formation positions of contact holes H are formed in the pattern transfer layer 51 and the spin-coating mask layer SOH. See also... Figure 27 Based on the mask pattern in the fourth mask layer YM4, the first dielectric layer 21 can be patterned and a contact hole H that can expose the corresponding active region AA can be formed in the first dielectric layer 21.

[0188] In step S400, please refer to Figure 28 and Figure 29 A second conductive layer 32 is filled into the contact hole H.

[0189] For example, please refer to Figure 28 A second conductive material layer 320 is deposited on each contact hole H and the surface of the pattern transfer layer 51. (See also...) Figure 29 Remove the pattern transfer layer 51 and the second conductive material layer 320 above the surface of the first dielectric layer 21 so that the second conductive material layer 320 retained in the contact hole H forms the second conductive layer 32.

[0190] For example, the pattern transfer layer 51 and the second conductive material layer 320 above the surface of the first dielectric layer 21 can be removed by a polishing process.

[0191] For example, the second conductive material layer 320 includes, but is not limited to, a polycrystalline silicon material layer.

[0192] It is understood that in some embodiments, the surface of the first dielectric layer 21 and the surface of the first conductive layer 31 are substantially flush. Accordingly, after removing the pattern transfer layer 51 and the second conductive material layer 320 above the surface of the first dielectric layer 21, the surface of the first conductive layer 31 in the peripheral region R2 will be exposed.

[0193] In step S500, please refer to Figures 30-32 A third conductive layer 33 and a second dielectric layer 22 are formed by stacking the first dielectric layer 21, the first conductive layer 31 and the second conductive layer 32 on the side away from the substrate 1.

[0194] For example, the third conductive layer 33 includes a layer of metallic material, such as a tungsten metal layer.

[0195] For example, before forming the third conductive layer 33, a barrier layer 34 may be formed on the side of the first dielectric layer 21, the first conductive layer 31, and the second conductive layer 32 that is away from the substrate 1. Accordingly, the third conductive layer 33 is formed on the surface of the barrier layer 34 that is away from the substrate 1.

[0196] For example, the barrier layer 34 includes at least one of a titanium layer or a titanium nitride layer. In this way, the barrier layer 34 can both electrically connect the second conductive layer 32 and the third conductive layer 33 and prevent ion diffusion between the third conductive layer 33 and the second conductive layer 32. For example, it can effectively block tungsten metal from diffusing into the polycrystalline silicon material, thereby avoiding affecting the electrical properties of the second conductive layer 32.

[0197] For example, the second dielectric layer 22 includes a third sub-dielectric layer 221 and a fourth sub-dielectric layer 222 stacked along a direction away from the substrate 1; the third sub-dielectric layer 221 and the fourth sub-dielectric layer 222 are made of the same material, for example, silicon nitride. Furthermore, the third sub-dielectric layer 221 and the fourth sub-dielectric layer 222 can be formed in different steps, for example, the third sub-dielectric layer 221 can be formed first, such as... Figure 30 and Figure 31 As shown in the diagram, a fourth sub-dielectric layer 222 is formed after the gate structure is formed in the peripheral region R2, for example... Figure 32 As shown in the image.

[0198] In some examples, please refer to Figure 30After forming a barrier layer 34, a third conductive layer 33, and a third sub-dielectric layer 221 sequentially on the side of the first dielectric layer 21, the first conductive layer 31, and the second conductive layer 32 away from the substrate 1, the third sub-dielectric layer 221, the third conductive layer 33, the barrier layer 34, the first conductive layer 31, and the shallow trench isolation structure (STI) of the peripheral region R2 can be patterned first to form a gate structure in the peripheral region R2 and expose the active regions on both sides of the gate structure; wherein, the portion of the shallow trench isolation structure (STI) retained at the bottom of the gate structure will constitute the gate dielectric layer 61 between the gate structure and the corresponding active region; the third sub-dielectric layer 221 of the peripheral region R2 can be used as a hard mask layer when patterning the gate structure.

[0199] Please see Figure 31 A sidewall 62 is formed on the sidewall of the gate structure in the peripheral region R2. The sidewall 62 can be a single insulating layer or a multilayer insulating layer stacked structure. For example, the sidewall 62 includes a silicon nitride layer, a silicon oxide layer and a silicon nitride layer stacked sequentially along the direction away from the sidewall of the gate structure.

[0200] Please continue reading. Figure 31 An interlayer dielectric layer is formed covering the gate structure and sidewall 62. The interlayer dielectric layer can be a single insulating layer or a stacked structure of multiple insulating layers. For example, the interlayer dielectric layer includes a first interlayer dielectric layer 63 and a second interlayer dielectric layer 64, wherein the first interlayer dielectric layer 63 includes, but is not limited to, a silicon nitride layer, and the second interlayer dielectric layer 64 includes, but is not limited to, a silicon oxide layer.

[0201] Please see Figure 32 After forming the aforementioned interlayer dielectric layer, a fourth sub-dielectric layer 222 can be formed on the surface of the interlayer dielectric layer and the third sub-dielectric layer 221, and a mask structure for patterning and etching the second dielectric layer 22, the third conductive layer, the first dielectric layer 21 and the second conductive layer 32 can be formed on the surface of the fourth sub-dielectric layer 222, such as a hard mask layer 71, a first anti-reflection layer 72, a spin-coated mask layer SOH and a second anti-reflection layer 73 formed by stacking.

[0202] For example, the hard mask layer 71 includes, but is not limited to, an amorphous carbon layer (ACL).

[0203] In step S600, please refer to Figure 33 and Figure 34 The second dielectric layer 22, the third conductive layer 33, the first dielectric layer 21 and the second conductive layer 32 are patterned to form multiple bit line structures BL; wherein the second dielectric layer 22, the third conductive layer 33, the first dielectric layer 21 and the second conductive layer 32 are patterned in a preset order, and the first dielectric layer 21 and the second conductive layer 32 are patterned using different etching gases.

[0204] For example, please refer to Figure 33 After forming a mask pattern in the hard mask layer 71, the fourth sub-dielectric layer 222, the third sub-dielectric layer 221, the third conductive layer 33, the barrier layer 34, and the second conductive layer 32 can be etched sequentially within the contact hole H to form the first part BLA of the bit line structure BL; the fourth sub-dielectric layer 222, the third sub-dielectric layer 221, the third conductive layer 33, the barrier layer 34, and the first dielectric layer 21 can be etched sequentially outside the contact hole H to form the second part BLB of the bit line structure BL, for example... Figure 34 As shown in the image.

[0205] For example, please refer to Figure 35 During the formation of the bit line structure BL, the first dielectric layer 21 and the second conductive layer 32 are patterned using different etching gases; that is, the first dielectric layer 21 and the second conductive layer 32 are etched independently.

[0206] For example, such as Figure 35 The order of Figures (a) to (d) can be based on the mask pattern in the aforementioned hard mask layer 71. First, the second dielectric layer 22 is patterned, then the third conductive layer 33 and the barrier layer 34 are patterned, then the first dielectric layer 21 is patterned, and finally the second conductive layer 32 is patterned to obtain the bit line structure BL.

[0207] For example, the etching gas for the first dielectric layer 21 and the second dielectric layer 22 includes, but is not limited to, fluorine-containing gas or nitrogen.

[0208] For example, the etching gas of the second conductive layer 32 includes, but is not limited to, one or more of chlorine, hydrogen chloride, or hydrogen bromide.

[0209] This disclosure also provides a semiconductor structure that can be prepared using the methods described in some of the above embodiments. This semiconductor structure also possesses all the technical advantages of the aforementioned preparation methods.

[0210] Please see Figure 5 , Figure 6 and Figure 34 The semiconductor structure includes a substrate 1, a first conductive layer 31, and multiple bit line structures BL. The substrate 1 has an array region R1 and a peripheral region R2. The substrate 1 includes multiple active regions AA located within the array region R1 and multiple contact holes; the contact holes expose the corresponding active regions AA. The first conductive layer 31 is located in the peripheral region R2. The multiple bit line structures BL are disposed parallel to each other on the substrate 1.

[0211] The bitline structure BL includes: a first part BLA (e.g., a connection portion connecting the active region AA) and a second part BLB (e.g., an extension portion located above the substrate 1). The first part BLA is located within a contact hole and is electrically connected to the active region AA. The first part BLA includes: a second conductive layer 32, a third conductive layer 33, and a second dielectric layer 22 sequentially stacked along a direction away from the active region AA. The second part BLB is located on the substrate 1 and is electrically connected to the first part BLA. The second part BLB includes: a first dielectric layer 21, a third conductive layer 33, and a second dielectric layer 22 sequentially stacked along a direction away from the substrate 1, wherein the sidewalls of the first dielectric layer 21 are flush with the sidewalls of the third conductive layer 33, and the sidewalls of the first dielectric layer 21 are approximately perpendicular to the substrate 1.

[0212] In some embodiments, the first conductive layer 31 and the second conductive layer 32 include, but are not limited to, a polycrystalline silicon layer.

[0213] For example, the first conductive layer 31 is used to form a gate structure in the peripheral region R2 after patterning. However, it is understood that the gate structure in the peripheral region R2 may include the first conductive layer 31 and more film layers, as described in some of the foregoing embodiments, which will not be detailed here.

[0214] In some embodiments, the third conductive layer 33 includes a metal material layer, such as a tungsten metal layer. The bit line structure BL also includes a barrier layer 34 located on the surface of the third conductive layer 33 near the substrate 1; that is, a barrier layer 34 is provided between the third conductive layer 33 and the second conductive layer 32 of the first part BLA, and a barrier layer 34 is provided between the third conductive layer 33 and the first dielectric layer 21 of the second part BLB.

[0215] For example, the barrier layer 34 includes, but is not limited to, at least one of a titanium layer or a titanium nitride layer.

[0216] In some embodiments, the top surface of the first dielectric layer 21 away from the substrate 1 is substantially flush with the top surface of the second conductive layer 32 away from the substrate 1.

[0217] In some embodiments, the first dielectric layer 21 includes a first sub-dielectric layer 211 and a second sub-dielectric layer 212 stacked along a direction away from the substrate 1. The first sub-dielectric layer 211 and the second sub-dielectric layer 212 are made of the same material, such as, but not limited to, silicon nitride.

[0218] In some embodiments, the second dielectric layer 22 includes a third sub-dielectric layer 221 and a fourth sub-dielectric layer 222 stacked along a direction away from the substrate 1. The third sub-dielectric layer 221 and the fourth sub-dielectric layer 222 are made of the same material, for example, including but not limited to silicon nitride.

[0219] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0220] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0221] The embodiments described above are merely examples of several implementation methods of this disclosure, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate; the substrate has an array region and a peripheral region, and further comprises a plurality of active regions in the array region; forming a first dielectric layer in the array region and a first conductive layer in the peripheral region; after patterning the first conductive layer, a gate electrode is formed; forming a plurality of contact holes in the array region; the contact holes penetrate through the first dielectric layer and expose the corresponding active regions; filling the contact holes with a second conductive layer; stacking a third conductive layer and a second dielectric layer on the side of the first dielectric layer, the first conductive layer and the second conductive layer away from the substrate; patterning the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer to form a plurality of bit line structures; wherein the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer are patterned in a predetermined order, and the first dielectric layer and the second conductive layer are patterned by using different etching gases respectively.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The top surface of the first dielectric layer away from the substrate is substantially flush with the top surface of the second conductive layer away from the substrate.

3. The method of producing a semiconductor structure according to claim 1 or 2, characterized in that, The step of forming a first dielectric layer in the array region and a first conductive layer in the peripheral region comprises the following steps: forming a first mask layer covering the substrate in the array region and exposing the substrate in the peripheral region; forming the first conductive layer on the substrate in the peripheral region; forming a first protective layer on the first conductive layer; removing the first mask layer; forming the first dielectric layer on the substrate in the array region.

4. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: The step of forming the first dielectric layer on the substrate in the array region further comprises the following steps: forming a first sub-dielectric layer on the substrate in the array region; removing the first protective layer; forming a second mask layer covering the first conductive layer and exposing the first sub-dielectric layer; forming a second sub-dielectric layer on the first sub-dielectric layer; forming a second protective layer on the second sub-dielectric layer; removing the second mask layer; removing the second protective layer; wherein the first dielectric layer comprises the first sub-dielectric layer and the second sub-dielectric layer.

5. The method of claim 4, wherein the semiconductor structure is prepared by a method comprising: The first sub-dielectric layer and the second sub-dielectric layer are made of the same material.

6. The method of producing a semiconductor structure according to claim 1 or 2, wherein The step of forming a first dielectric layer in the array region and a first conductive layer in the peripheral region comprises the following steps: forming a first conductive material layer on the substrate; forming a third protective layer on the first conductive material layer in the peripheral region; removing the first conductive material layer in the array region, so that the first conductive material layer in the peripheral region constitutes the first conductive layer; forming a third mask layer covering the first conductive layer and exposing the substrate in the array region; forming the first dielectric layer on the substrate in the array region; forming a fourth protective layer on the first dielectric layer; removing the third mask layer; removing the fourth protective layer.

7. The method according to claim 1, wherein the etching gases of the first dielectric layer and the second dielectric layer comprise fluorine-containing gas or nitrogen. ​ The etching gas of the second conductive layer comprises one or more of chlorine, hydrogen chloride or hydrogen bromide.

8. A semiconductor structure formed using the method of any one of claims 1-7. The semiconductor structure comprises: a substrate having an array region and a peripheral region; the substrate comprises a plurality of active regions and a plurality of contact holes in the array region; the contact holes expose corresponding active regions; a first conductive layer in the peripheral region; a plurality of bit line structures arranged in parallel and spaced apart on the substrate; The bit line structure comprises: a first part in the contact hole and electrically connected to the active region; the first part comprises a second conductive layer, a third conductive layer and a second dielectric layer stacked in order away from the active region; a second part on the substrate and electrically connected to the first part; the second part comprises a first dielectric layer, a third conductive layer and a second dielectric layer stacked in order away from the substrate; the side wall of the first dielectric layer is flush with the side wall of the third conductive layer, and the side wall of the first dielectric layer is substantially perpendicular to the substrate.

9. The semiconductor structure of claim 8, wherein, The top surface of the first dielectric layer away from the substrate is substantially flush with the top surface of the second conductive layer away from the substrate.

10. The semiconductor structure of claim 8 or 9, wherein: The first dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer stacked away from the substrate; the first sub-dielectric layer and the second sub-dielectric layer are of the same material; The second dielectric layer comprises a third sub-dielectric layer and a fourth sub-dielectric layer stacked away from the substrate; the third sub-dielectric layer and the fourth sub-dielectric layer are of the same material.

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