IGBT device with power clamping function and manufacturing method thereof
By increasing the SBR trench gate structure and adjusting the P-zone doping concentration on the IGBT device, the problem of induced voltage shock when shutdown is solved, power clamping is achieved, which significantly reduces the maximum instantaneous power and improves service life.
Patent Information
- Application Number
- CN202510279453.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2025-06-06
AI Technical Summary
When a traditional IGBT device is turned off when a large current and a high switching frequency is high, it is prone to induction voltage impact, causing the maximum instantaneous power to exceed the maximum power allowed by the device, resulting in failure.
Power clamping is achieved by adding the SBR trench gate structure connected to the collector on the IGBT device and adjusting the doping concentration of the P region to appropriately adjust the hole injection amount, limit the conductance modulation, and achieve power clamping.
When subjected to a large voltage impact, the resistance reduction amplitude of the drift region is limited, the current increases are avoided, the maximum instantaneous power of the induced voltage is significantly reduced, and the service life of the IGBT device under harsh operating conditions is improved.
Smart Images
Figure CN120111907A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of power semiconductors, and in particular relates to an IGBT device with a power clamping function and a manufacturing method thereof. Background Art
[0002] IGBT (Insulated Gate Bipolar Transistor) is a composite fully controlled voltage-driven power semiconductor device composed of BJT (bipolar transistor) and MOS (insulated gate field effect transistor). It has the advantages of high input impedance of MOSFET and low on-state voltage drop of GTR (power transistor). In applications with the same voltage, GTR has low saturation voltage drop and high current density, but large driving current; MOSFET has low driving power and fast switching speed, but large on-state voltage drop and low current density. IGBT combines the advantages of the above two devices, with low driving power and low saturation voltage drop; therefore, IGBT is more suitable for use in converter systems with DC voltages of hundreds of volts or more, such as AC motors, inverters, switching power supplies, lighting circuits, traction drives and other fields.
[0003] Due to the large application current, the application of IGBT devices cannot avoid the inductive voltage impact caused by inductive loads or parasitic inductance during the switching process. When traditional IGBT devices are turned off under the condition of large current and high switching frequency, the ratio between the total voltage between the collector and the emitter and the power bus voltage, and the ratio between the current and the normal shutdown current, often reach a relatively large value, such as 2-3 times or even larger, so that the maximum instantaneous power is more likely to exceed the maximum power actually allowed by the IGBT device, causing the traditional IGBT to fail during its shutdown process. Summary of the invention
[0004] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide an IGBT device with a power clamping function and a manufacturing method thereof.
[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:
[0006] An IGBT device with a power clamping function comprises a P region, an N-type buffer region and an N-drift region which are arranged in sequence from bottom to top, wherein the P region is P-type doped, the N-type buffer region is N-type doped, and the N-drift region is N-lightly doped; a collector metal is arranged at the lower end of the P region, and the collector metal is connected to an SBR trench gate structure, and the SBR trench gate structure is used to suppress the resistance reduction of the drift region when there is a large induced voltage impact; a P-type body region is arranged at the upper part of the N-drift region, and the P-type body region is P-type doped; the P-type body region is arranged A front trench gate structure is provided, which penetrates downward through the P-type body region and extends into the N-drift region; an N+ region is respectively arranged on both sides of the upper part of the P-type body region corresponding to the front trench gate structure, and the N+ region is heavily doped with N type; a P+ region is arranged on the side of the N+ region away from the front trench gate structure, and the P+ region is heavily doped with P type; a dielectric layer is arranged at the upper end of the P-type body region, an emitter metal is arranged on the dielectric layer, and the emitter metal is connected to the P+ region and the N+ region through a contact hole opened in the dielectric layer.
[0007] Furthermore, the SBR trench gate structure includes a back trench that penetrates the P region from the lower end surface of the P region upward and extends into the N-type buffer zone, a back gate oxide layer formed on the groove wall of the back trench, and a back gate filled in the back trench.
[0008] Furthermore, the depth of the back side groove is 0.3 μm to 5 μm.
[0009] Furthermore, the thickness of the back gate oxide layer is 30 Å to 150 Å.
[0010] Furthermore, the doping concentration of the P region is 1E15cm -3 ~1E17cm -3 .
[0011] Furthermore, the front trench gate structure includes a front trench penetrating downwardly through the P-type body region and extending into the N-drift region, a front gate oxide layer formed on the trench wall of the front trench, and a front gate filled in the front trench.
[0012] Furthermore, the P region is provided with a plurality of SBR trench gate structures, and the center spacing between adjacent SBR trench gate structures is 0.5 μm to 10 μm.
[0013] A method for manufacturing an IGBT device with a power clamping function comprises the following steps:
[0014] S100, taking a wafer, the wafer having a front side and a back side that are arranged opposite to each other; making the front side of the wafer face upward, forming a front side trench gate structure, a dielectric layer and a contact hole on the front side of the wafer; and thinning the back side of the wafer;
[0015] S200, vertically flipping the wafer, and performing P-type impurity injection and activation on the back side of the wafer to form a P region;
[0016] S300, photolithography a back side groove on the back side of the wafer, wherein the back side groove penetrates the P region and extends into the N type buffer region;
[0017] S400, forming a back gate oxide layer on the groove wall of the back groove;
[0018] S500, depositing polysilicon in the back trench and etching back to form a back gate;
[0019] S600, depositing back metal on the back side of the wafer and performing heat treatment to form collector metal;
[0020] S700, flip the wafer vertically again to complete the subsequent IGBT device manufacturing process.
[0021] Furthermore, forming a front trench gate structure, a dielectric layer and a contact hole on the front side of the wafer includes the following steps:
[0022] S110, forming an N-type buffer region and an N-drift region;
[0023] S120, forming a front trench in the N-drift region;
[0024] S130, forming a front gate oxide layer on the groove wall of the front groove;
[0025] S140, filling polysilicon in the front trench and etching back to form a front gate;
[0026] S150, implanting into the upper part of the N-drift region to form a P-type body region, an N+ region and a P+ region;
[0027] S160, growing a dielectric layer on the surface of the wafer;
[0028] S170 , forming contact holes on the dielectric layer at positions corresponding to the N+ region and the P+ region.
[0029] Furthermore, the depth of the back side groove is 0.3 μm to 5 μm.
[0030] In the present invention, an SBR trench gate structure connected to the collector is added to the IGBT device, and the doping concentration of the P region is adjusted, so that the hole injection amount is adjusted at an appropriate time, and the conductivity modulation is limited to perform power clamping. When subjected to a large voltage shock, the resistance reduction amplitude of the drift region can be limited to avoid a significant increase in the current flowing through it; the maximum instantaneous power of the induced voltage can be significantly reduced, thereby achieving the effect of triggering power clamping, and improving the service life of the IGBT device under such harsh working conditions. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0032] Figure 1 FIG. 1 is a schematic structural diagram of an IGBT device with a power clamping function according to an embodiment of the present invention.
[0033] Figure 2 The present invention is a flow chart of an embodiment of a method for manufacturing an IGBT device with a power clamping function.
[0034] Figure 3 This is a schematic diagram of the structure after forming a front trench gate structure, a dielectric layer and contact holes on the front side of the wafer.
[0035] Figure 4 It is a schematic diagram of the structure after the P region is formed.
[0036] Figure 5 Schematic diagram of the structure after etching the back groove.
[0037] Figure 6 This is a schematic diagram of the structure after the SBR trench gate structure is completed.
[0038] Figure 7 Schematic diagram of the structure after the collector metal is made.
[0039] The accompanying drawings in the specification are numeraled as follows:
[0040] P region-100; N-type buffer region-210; N-drift region-220; P-type body region-310; P+ region-320; N+ region-330; dielectric layer-400; contact hole-410; front trench gate structure-500; front trench-510; front gate oxide layer-520; front gate-530; emitter metal-600; SBR trench gate structure-700; back trench-710; back gate oxide layer-720; back gate-730; collector metal-800. DETAILED DESCRIPTION
[0041] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.
[0042] When a conventional IGBT device is turned off under the condition of large current and high switching frequency, the instantaneous extreme value of the induced voltage generated may exceed the power bus voltage, and the total voltage between the collector and the emitter may exceed twice the power bus voltage. Since the pn junction voltage drop between the collector and the N-drift region will also increase to a certain extent, the amount of holes injected by the collector of the conventional IGBT into the N-drift region will also increase to a certain extent at this time, and the resistance of the N-drift region will be at risk of a sudden drop, which will lead to a significant reduction in the on-resistance of the conventional IGBT. In this way, when the conventional IGBT is turned off under the condition of large current and high switching frequency, the total voltage and current between the collector and the emitter will increase at the same time, so its instantaneous power is relatively high. If an extreme situation occurs, such as a harder turn-off signal at the gate drive end and there is no sufficiently effective power limitation for it in the specific application circuit, the ratio of the total voltage between the collector and the emitter to the power bus voltage, and the ratio of the current to the normal turn-off current, will often reach a relatively large value, such as 2-3 times or even larger. In this way, the maximum instantaneous power is likely to exceed the maximum power actually allowed by the traditional IGBT device, thereby causing the traditional IGBT to fail during its turn-off process.
[0043] See also Figure 1 , Figure 1 The schematic diagram of the structure of an embodiment of an IGBT device with a power clamping function of the present invention. The IGBT device with a power clamping function of this embodiment includes a P region 100, an N-type buffer region 210 and an N-drift region 220 arranged in sequence from bottom to top, wherein the P region 100 is P-type doped, the N-type buffer region 210 is N-type doped, and the N-drift region 220 is N-type lightly doped. The thickness range of the N-type buffer region 210 is generally 5μm to 25μm, and the thickness range of the N-drift region 220 is related to the withstand voltage of the IGBT device, which is generally 650V / 50uμm.
[0044] A collector metal 800 is disposed at the lower end of the P region 100 , and the collector metal 800 is connected to a SBR trench gate structure 700 . The SBR trench gate structure 700 is used to suppress the resistance reduction of the drift region when there is a large inductive voltage impact.
[0045] A P-type body region 310 is disposed on the upper portion of the N-drift region 220, and the P-type body region 310 is P-type doped; a front trench gate structure 500 is disposed on the P-type body region 310, and the front trench gate structure 500 penetrates downwardly through the P-type body region 310 and extends into the N-drift region 220. In this embodiment, the front trench gate structure 500 includes a front trench 510 that penetrates downwardly through the P-type body region 310 and extends into the N-drift region 220, a front gate oxide layer 520 formed on the groove wall of the front trench 510, and a front gate 530 filled in the front trench 510.
[0046] An N+ region 330 is respectively arranged on both sides of the upper part of the P-type body region 310 corresponding to the front trench gate structure 500, and the N+ region 330 is heavily doped with N type. A P+ region 320 is arranged on the side of the N+ region 330 away from the front trench gate structure 500, and the P+ region 320 is heavily doped with P type. A dielectric layer 400 is arranged on the upper end of the P-type body region 310, and an emitter metal 600 is arranged on the dielectric layer 400, and the emitter metal 600 is connected to the P+ region 320 and the N+ region 330 through a contact hole 410 opened on the dielectric layer 400.
[0047] In this embodiment, the SBR trench gate structure 700 includes a back trench 710 that penetrates the P region 100 from the lower end surface of the P region 100 upward and extends into the N-type buffer zone 210, a back gate oxide layer 720 formed on the groove wall of the back trench 710, and a back gate 730 filled in the back trench 710; by adding the SBR trench gate structure 700 to the back side of the IGBT device, an SBR (Super Barrier Rectifier) structure can be formed.
[0048] The turn-on voltage of the SBR structure can be adjusted by the depth of the SBR trench gate structure 700, the thickness of the back gate oxide layer 720 and the doping concentration of the P region 100. The thinner the depth of the SBR trench gate structure 700 and the thickness of the back gate oxide layer 720 or the lighter the doping concentration of the P region 100, the lower the turn-on voltage of the SBR structure. The P region 100 is generally provided with a plurality of SBR trench gate structures 700. The degree of inhibition of the SBR structure on the reduction of the drift region resistance can be adjusted by the turn-on voltage of the SBR and the Pitch of the SBR trench gate structure 700 (i.e., the center spacing between adjacent SBR trench gate structures 700). The lower the turn-on voltage of the SBR trench gate structure 700 or the smaller the Pitch of the SBR trench gate structure 700, the higher the degree of inhibition of the SBR trench gate structure 700 on the reduction of the drift region resistance, and the more obvious the power clamping effect. Therefore, the structure of the present embodiment can be optimized with corresponding structural parameters according to specific application requirements to achieve better application performance. After the Pitch of the SBR trench gate structure 700 is determined, the number of the SBR trench gate structures 700 is also determined.
[0049] The depth of the back trench 710 (i.e., the depth of the SBR trench gate structure 700) is generally 0.3 μm to 5 μm; the thickness of the P region 100 is less than the depth of the back trench 710. The thickness of the back gate oxide layer 720 is generally 30 Å to 150 Å; the doping concentration of the P region 100 is generally 1E15 cm -3 ~1E17cm -3 The center distance between adjacent backside trenches 710 (ie, the center distance between adjacent SBR trench gate structures 700 ) is generally 0.5 μm to 10 μm.
[0050] In this embodiment, when the induced voltage impact is small and insufficient to turn on the SBR structure, the IGBT device is in the corresponding working mode of the traditional IGBT device, that is, the working process is the same as that of the traditional IGBT device, and the SBR trench gate structure 700 does not work.
[0051] When the IGBT device is subjected to a large inductive voltage shock, the voltage drop between the collector metal 800 and the N-type buffer region 210 (or the N-drift region 220) increases. When the turn-on voltage of the SBR structure formed by the SBR trench gate structure 700 is reached, an N-type conductive channel is formed between the collector and the N-type buffer region 210 (or the N-drift region 220) and they are directly connected, thereby reducing the pn junction voltage drop between the collector and the N-type buffer region 210 (or the N-drift region 220). This limits the amount of holes injected by the collector into the N-drift region 220 and limits the resistance of the N-drift region 220 from continuing to decrease, thereby avoiding a continued increase in current. Compared with conventional IGBT devices, this achieves the effect of triggering power clamping.
[0052] When the voltage drop between the collector and the N Buffer (or the N-drift region 220 ) decreases below the turn-on voltage of the SBR structure, the SBR structure will be turned off immediately, and the performance of the IGBT device of this embodiment will return to the corresponding state of the traditional IGBT device.
[0053] The IGBT device is inevitably impacted by the induced voltage during the application process. The IGBT device using the structure of this embodiment can timely open the SBR structure integrated on the collector when it is impacted by a large voltage, limit the amount of holes injected by the collector into the N-drift region 220, and thus limit the resistance reduction amplitude of the drift region, thereby avoiding a significant increase in the current flowing through it. The maximum instantaneous power of the induced voltage can be significantly reduced, thereby achieving the effect of triggering power clamping, thereby widening the safe working area of the IGBT device and improving the service life of the IGBT device under such harsh working conditions. Reflected in specific parameter indicators, compared with traditional IGBT devices of the same specification, the structure of this embodiment can enable the collector and emitter of the IGBT device to withstand a larger dV / dt (voltage change rate), and at the same time, in a fixed voltage application or test environment, it can also increase the short-circuit time that can be tolerated because it can appropriately reduce the short-circuit current.
[0054] See also Figure 2 , Figure 2 The flowchart of an embodiment of a method for manufacturing an IGBT device with a power clamping function of the present invention. The method for manufacturing an IGBT device with a power clamping function of this embodiment comprises the following steps:
[0055] S100, please refer to Figure 3 , take a wafer, the wafer having a front side and a back side arranged opposite to each other; make the front side of the wafer face upward, form a front trench gate structure 500, a dielectric layer 400 and a contact hole 410 on the front side of the wafer; and thin the back side of the wafer. Forming the front trench gate structure 500, the dielectric layer 400 and the contact hole 410 on the front side of the wafer may include the following steps:
[0056] S110, forming an N-type buffer region 210 and an N-drift region 220 on the wafer. The thickness of the N-type buffer region 210 is generally in the range of 5 μm to 25 μm, and the thickness of the N-drift region 220 is related to the withstand voltage of the IGBT device, which is generally 650V / 50 μm.
[0057] S120 , etching a front trench 510 in the N-drift region 220 by a photolithography process, and starting to manufacture the front trench gate structure 500 .
[0058] S130, forming a front gate oxide layer 520 on the wall of the front trench 510 by thermal oxidation. Of course, an oxide layer will also be formed on the surface of the N-drift region 220 at this time, and the oxide layer can be removed in the subsequent process.
[0059] S140 , filling the front trench 510 with polysilicon and etching back to form a front gate 530 , thereby forming a front trench gate structure 500 .
[0060] S150, forming a P-type body region 310, an N+ region 330 and a P+ region 320 by implantation in sequence on the upper part of the N-drift region 220. The lower end of the P-type body region 310 is lower than the lower end of the front trench 510; the N+ region 330 and the P+ region 320 are located on the upper part of the P-type body region 310, and the lower ends of the N+ region 330 and the P+ region 320 are flush and higher than the lower end of the front trench 510.
[0061] S160 , growing a dielectric layer 400 on the surface of the wafer.
[0062] S170, forming contact holes 410 on the dielectric layer 400 at positions corresponding to the N+ region 330 and the P+ region 320. Figure 3 Only one cell region structure is illustrated in the subsequent drawings, and therefore only a portion of the contact hole 410 is shown in the drawings, and the entire contact hole 410 is not shown.
[0063] S200, please refer to Figure 4 , flip the wafer vertically so that the back of the wafer faces upward, and perform P-type impurities injection and activation on the back of the wafer to form a P region 100. The doping concentration of the P region 100 can be determined according to the voltage of the turn-on voltage of the SBR structure, which is generally 1E15cm -3 ~1E17cm -3 The thickness of the P region 100 needs to be smaller than the thickness of the back side trench 710 to be fabricated subsequently.
[0064] S300, see Figure 5 , a back groove 710 is photolithographically formed at the position where the SBR trench gate structure 700 needs to be made on the back of the wafer through a photolithography process, and the back groove 710 penetrates the P region 100 and extends into the N-type buffer region 210. A plurality of back grooves 710 are generally provided in each cell region. The depth of the back groove 710 (i.e., the depth of the SBR trench gate structure 700 formed subsequently) can be determined according to the voltage of the turn-on voltage of the SBR structure, which is generally 0.3 μm to 5 μm. The center spacing between adjacent back grooves 710 (i.e., the Pitch of the SBR trench gate structure 700 formed subsequently) can be determined according to the requirements of the degree of suppression of the drift region resistance reduction by the SBR structure.
[0065] S400, see Figure 6 , a back gate oxide layer 720 is formed on the wall of the back trench 710 by thermal oxidation, and the thickness of the back gate oxide layer 720 is generally 30A to 150A. Of course, an oxide layer will also be formed on the surface of the P region 100 at this time, and the oxide layer can be removed in the subsequent process.
[0066] S500, please continue to read Figure 6 , polysilicon is deposited in the back trench 710 and etched back to form a back gate 730; then, an oxide layer is wet-etched (the thickness is slightly greater than the back gate oxide layer 720 in the back trench 710), and then a rapid annealing process is performed to form an SBR trench gate structure 700.
[0067] S600, please refer to Figure 7 , a back metal is deposited on the back side of the wafer and heat treated to form a collector metal 800.
[0068] S700, please continue to read Figure 1 , and then flip the wafer vertically again, so that the front side of the wafer faces upward, and complete the subsequent IGBT device manufacturing process. Mainly includes:
[0069] S710 , depositing a front metal, and forming an emitter metal 600 by etching.
[0070] S720, depositing a passivation layer and etching, and depositing polyimide and etching. By depositing a passivation layer and etching, and depositing polyimide and etching, the pad area can be exposed, and the passivation layer and polyimide are covered in the non-pad area. The pad area is a package wire or patch area reserved on the chip for package leads and heat transfer. These are all existing technologies, so the above structure is not shown in the figure.
[0071] S730: After etching the polyimide and passivation layer on the back of the wafer, a single IGBT device is obtained through dicing and packaging.
[0072] The IGBT device manufactured by the method of this embodiment can limit the resistance reduction of the drift region when subjected to a large voltage shock, thereby avoiding a significant increase in the current flowing through it; it can significantly reduce the maximum instantaneous power of the induced voltage, thereby achieving the effect of triggering power clamping; it enables the collector and emitter of the IGBT device to withstand a larger dV / dt, and at the same time, in a fixed voltage application or test environment, because it can appropriately reduce the short-circuit current, it increases the short-circuit time that can be tolerated, thereby improving the service life of the IGBT device under such harsh working conditions.
[0073] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. An IGBT device with a power clamping function, characterized in that: The invention comprises a P region, an N-type buffer region and an N-drift region which are arranged in sequence from bottom to top, wherein the P region is P-type doped, the N-type buffer region is N-type doped, and the N-drift region is N-lightly doped; a collector metal is arranged at the lower end of the P region, and the collector metal is connected with an SBR trench gate structure, and the SBR trench gate structure is used to suppress the resistance reduction of the drift region when there is a large induced voltage impact; a P-type body region is arranged at the upper part of the N-drift region, and the P-type body region is P-type doped; the P-type body region is provided with a front A trench gate structure, wherein the front trench gate structure penetrates downwardly through the P-type body region and extends into the N-drift region; an N+ region is respectively arranged on both sides of the upper part of the P-type body region corresponding to the front trench gate structure, and the N+ region is heavily N-doped; a P+ region is arranged on the side of the N+ region away from the front trench gate structure, and the P+ region is heavily P-doped; a dielectric layer is arranged at the upper end of the P-type body region, an emitter metal is arranged on the dielectric layer, and the emitter metal is connected to the P+ region and the N+ region through a contact hole opened in the dielectric layer.
2. The IGBT device with power clamping function according to claim 1, characterized in that: The SBR trench gate structure includes a back trench that penetrates the P region from the lower end surface of the P region upward and extends into the N-type buffer zone, a back gate oxide layer formed on the groove wall of the back trench, and a back gate filled in the back trench.
3. The IGBT device with power clamping function according to claim 2, characterized in that: The depth of the back side groove is 0.3 μm to 5 μm.
4. The IGBT device with power clamping function according to claim 2, characterized in that: The thickness of the back gate oxide layer is 30A to 150A.
5. The IGBT device with power clamping function according to claim 2, characterized in that: The doping concentration of the P region is 1E15 cm -3 ~1E17cm -3 .
6. The IGBT device with power clamping function according to any one of claims 1 to 5, characterized in that: The front trench gate structure comprises a front trench penetrating downwardly through the P-type body region and extending into the N-drift region, a front gate oxide layer formed on the groove wall of the front trench, and a front gate filled in the front trench.
7. The IGBT device with power clamping function according to any one of claims 1 to 5, characterized in that: The P region is provided with a plurality of SBR trench gate structures, and the center spacing between adjacent SBR trench gate structures is 0.5 μm to 10 μm.
8. A method for manufacturing an IGBT device with a power clamping function, characterized in that: The following steps are involved: S100, taking a wafer, wherein the wafer has a front side and a back side that are oppositely arranged; The front side of the wafer is facing upwards, and a front trench gate structure, a dielectric layer and a contact hole are formed on the front side of the wafer; and the back side of the wafer is thinned; S200, vertically flipping the wafer, and performing P-type impurity injection and activation on the back side of the wafer to form a P region; S300, photolithography a back side groove on the back side of the wafer, wherein the back side groove penetrates the P region and extends into the N type buffer region; S400, forming a back gate oxide layer on the wall of the back trench; S500, depositing polysilicon in the back trench and etching back to form a back gate; S600, depositing back metal on the back side of the wafer and performing heat treatment to form collector metal; S700, flip the wafer vertically again to complete the subsequent IGBT device manufacturing process.
9. The method for manufacturing an IGBT device with a power clamping function according to claim 8, characterized in that: The process of forming a front trench gate structure, a dielectric layer and a contact hole on the front side of the wafer includes the following steps: S110, forming an N-type buffer region and an N-drift region; S120, forming a front trench in the N-drift region; S130, forming a front gate oxide layer on the groove wall of the front groove; S140, filling polysilicon in the front trench and etching back to form a front gate; S150, implanting into the upper part of the N-drift region to form a P-type body region, an N+ region and a P+ region; S160, growing a dielectric layer on the surface of the wafer; S170 , forming contact holes on the dielectric layer at positions corresponding to the N+ region and the P+ region.
10. The method for manufacturing an IGBT device with a power clamping function according to claim 8, characterized in that: The depth of the back side groove is 0.3 μm to 5 μm.