A trench-type IGBT device and a manufacturing method thereof

Abstract

The present invention relates to the field of semiconductor technology, and in particular to a trench-type IGBT device and a manufacturing method thereof. The method includes: a substrate, and a P-base region, a gate region, and an emitter region located on the substrate; the P-base region is located between the gate regions and is in contact with the gate regions; the emitter region includes: an N+ active region, a short-circuit region, a latch-up region, and an emitter metal region; the N+ active region is located on the P-base region, between the gate regions, and between the gate region and the short-circuit region; the short-circuit regions are distributed at intervals on the P-base region, above the latch-up region, and in contact with the latch-up region; the latch-up region is located in the P-base region, corresponding to the interval region between the short-circuit regions; the emitter metal region is filled in the interval region, covering the N+ active region, the short-circuit region, and the gate region. This device structure effectively reduces the saturation current of the IGBT device, greatly improves the short-circuit resistance of the IGBT, and at the same time improves the latch-up resistance of the IGBT device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a trench-type IGBT device and a manufacturing method thereof. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) devices are a kind of core power electronic devices, which are widely used and play a huge role in fields such as rail transit, smart grid, and new energy vehicles. Currently, trench technology is mainly adopted for IGBT devices. In order to pursue a lower saturation voltage drop, the trench density of IGBT devices is made larger and larger, resulting in a significant increase in the saturation current of IGBT devices. Therefore, the short-circuit resistance of existing IGBT devices becomes worse and worse, and optimization and improvement are needed.

[0003] In order to solve the problem of the deteriorated short-circuit resistance of existing IGBT devices, a light-doped N-ballast resistor is introduced into the emitter region of the IGBT device in the existing solution. This solution can reduce the saturation current to a certain extent and improve the short-circuit resistance of the IGBT device. However, the ballast resistor of this solution has a negative temperature coefficient. When the IGBT device is short-circuited and the temperature rises, the resistance value of the IGBT device decreases, resulting in a limited improvement effect on the short-circuit resistance. Therefore, existing IGBT devices still have the problem of poor short-circuit resistance. Summary of the Invention

[0004] Embodiments of the present application provide a trench-type IGBT device and a manufacturing method thereof, which solve the technical problem that existing IGBT devices still have poor short-circuit resistance in the prior art, and achieve technical effects such as effectively reducing the saturation current of the IGBT device, greatly improving the short-circuit resistance of the IGBT, and simultaneously improving the anti-latch-up ability of the IGBT device.

[0005] In a first aspect, an embodiment of the present invention provides a trench-type IGBT device, including: a substrate, and a P-base region, a gate region, and an emitter region located on the substrate;

[0006] The P-base region is located between the gate regions and is in contact with the gate regions;

[0007] The emitter region includes: an N+ active region, a short-circuit region, a latch-up region, and an emitter metal region;

[0008] The N+ active region is located on the P-base region, between the gate regions, and between the gate region and the short-circuit region;

[0009] The short - circuit regions are distributed at intervals on the P - base region, between the gate regions, above the latch region, and in contact with the latch region;

[0010] The latch region is located in the P - base region, between the gate regions, and correspondingly below the spaced - apart region between the short - circuit regions;

[0011] The emitter metal region is filled in the spaced - apart region and covers the N + active region, the short - circuit region, and the gate region.

[0012] Optionally, the short - circuit region includes: a short - circuit trench and short - circuit polysilicon; the short - circuit polysilicon is filled in the short - circuit trench so that the short - circuit region forms a ballast resistor to improve the short - circuit resistance of the IGBT device.

[0013] Optionally, the latch region includes: a latch trench and latch polysilicon, the latch polysilicon is filled in the latch trench so that the latch region serves as a polysilicon electrode to improve the latch - up resistance of the IGBT device.

[0014] Optionally, the junction depth of the N + active region is not less than the depth of the short - circuit trench.

[0015] Optionally, the depth of the short - circuit trench is less than the depth of the latch trench, and the width of the short - circuit trench is greater than the depth of the latch trench.

[0016] Optionally, the depth range of the short - circuit trench is 0.1 - 0.3 μm, and the width range of the short - circuit trench is 0.4 - 2 μm; the depth range of the latch trench is 0.2 - 1 μm, and the width range of the latch trench is 0.2 - 1.8 μm.

[0017] Optionally, the gate region includes: a gate trench, a gate oxide layer, and gate polysilicon;

[0018] The gate oxide layer is located on the inner wall of the gate trench;

[0019] The gate polysilicon is filled in the space formed by the gate oxide layer.

[0020] Optionally, it further includes: a dielectric layer; the dielectric layer is located above the gate region, the N + active region, and the short - circuit region, below the emitter metal region, and the perforations of the dielectric layer correspond to the spaced - apart region so that the emitter metal region is filled in the perforations.

[0021] Optionally, it further includes: an N - type field - stop region, a P - type collector region, and a collector metal region;

[0022] The N - type field - stop region is located under the substrate;

[0023] The P-type collector region is located under the N-type field stop region;

[0024] The collector metal region is located under the P-type collector region.

[0025] Based on the same inventive concept, in a second aspect, the present invention further provides a manufacturing method for a trench IGBT device for manufacturing the trench IGBT device as described in the first aspect. The method includes:

[0026] Form a gate region on a substrate;

[0027] Form a P-base region and an emitter region between the gate regions, wherein the P-base region is located between the gate regions and is in contact with the gate regions;

[0028] The emitter region includes: an N+ active region, a short-circuit region, a latch region, and an emitter metal region;

[0029] The N+ active region is located on the P-base region, between the gate regions, and between the gate region and the short-circuit region;

[0030] The short-circuit regions are distributed at intervals on the P-base region, between the gate regions, above the latch region, and in contact with the latch region;

[0031] The latch region is located in the P-base region, between the gate regions, and corresponding to the interval region between the short-circuit regions;

[0032] The emitter metal region fills the interval region and covers the N+ active region, the short-circuit region, and the gate region.

[0033] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0034] In an embodiment of the present invention, a short - circuit region is introduced into the emitter region to form a ballast resistor in the short - circuit region, thereby improving the short - circuit withstand ability of the IGBT device through the short - circuit region. Moreover, when the short - circuit temperature of the IGBT device rises, the resistance value of the short - circuit region becomes larger, which can greatly reduce the saturation current and improve the short - circuit withstand ability of the device. At the same time, a latch - up region is introduced into the emitter region. When the IGBT device is turned on, most of the holes will reach the emitter metal region of the IGBT device from the latch - up region, thereby reducing the hole concentration under the N + active region and making it difficult for the parasitic triode to conduct, improving the latch - up withstand ability of the IGBT device. In this way, by setting the emitter region on the P - base region between the gate regions, not only the structure of the IGBT device is improved, but also the short - circuit withstand ability of the IGBT device is improved, and the latch - up withstand ability of the device is enhanced. On the premise of the same short - circuit withstand ability of the IGBT device, compared with the conventional IGBT device, the IGBT device of this embodiment does not affect the forward conduction voltage drop and does not increase the conduction loss. Through the structure of the IGBT device in the embodiment of the present invention, the purpose of cost reduction and efficiency improvement is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0036] Figure 1 shows a schematic structural diagram of a trench - type IGBT device in an embodiment of the present invention;

[0037] Figure 2 shows a schematic structural diagram of forming a gate trench in a substrate in an embodiment of the present invention;

[0038] Figure 3 shows a schematic structural diagram of forming a short - circuit trench in an embodiment of the present invention;

[0039] Figure 4 shows a schematic structural diagram of forming a latch - up trench in an embodiment of the present invention;

[0040] Figure 5 shows a schematic structural diagram of forming a gate oxide layer in a gate trench in an embodiment of the present invention;

[0041] Figure 6 shows a schematic structural diagram of filling polysilicon in a gate trench, a short - circuit trench, and a latch - up trench in an embodiment of the present invention;

[0042] Figure 7 shows a schematic structural diagram of forming a P - base region, an N + active region, a dielectric layer, and an emitter metal region in an embodiment of the present invention;

[0043] Figure 8 shows the short - circuit current curve of the trench - type IGBT device in the embodiment of the present invention;

[0044] Figure 9 shows the equivalent circuit diagram of the trench - type IGBT device in the embodiment of the present invention;

[0045] Figure 10 shows the schematic flow chart of the manufacturing method of the trench - type IGBT device in the embodiment of the present invention.

[0046] In the drawings, 110 is the substrate; 111 is the P - base region; 120 is the gate region; 130 is the emitter region; 140 is the dielectric layer; 150 is the N - type field - stop region; 160 is the P - type collector region; 170 is the collector metal region;

[0047] 121 is the gate trench; 122 is the gate oxide layer; 123 is the gate polysilicon;

[0048] 131 is the N+ active region; 132 is the short - circuit region; 133 is the latch - up region; 134 is the emitter metal region; 1321 is the short - circuit trench; 1322 is the short - circuit polysilicon; 1331 is the latch - up trench; 1332 is the latch - up polysilicon. Detailed Embodiments

[0049] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0050] Embodiment 1

[0051] The first embodiment of the present invention provides a trench - type IGBT device, as Figure 1 shown, including: a substrate 110, and a P - base region 111, a gate region 120, and an emitter region 130 located on the substrate 110. The P - base region 111 is located between the gate regions 120, and the P - base region 111 is in contact with the gate regions 120.

[0052] The emitter region 130 includes: an N+ active region 131, a short-circuit region 132, a latch region 133, and an emitter metal region 134. The N+ active region 131 is located on the P- base region 111, between the gate regions 120, and between the gate region 120 and the short-circuit region 132. The short-circuit regions 132 are distributed at intervals on the P- base region 111, between the gate regions 120, above the latch region 133, and in contact with the latch region 133. The latch region 133 is located in the P- base region 111, between the gate regions 120, and correspondingly below the spaced region between the short-circuit regions 132. The emitter metal region 134 fills the spaced region and covers the N+ active region 131, the short-circuit region 132, and the gate region 120.

[0053] It should be noted that an N-type single-crystalline silicon material is used as the material of the substrate 110, which serves as the drift region of the IGBT device. The substrate 110 is an N-type lightly doped substrate. The P- base region 111 is a P-type lightly doped base region.

[0054] In this embodiment, in the emitter region 130, the short-circuit region 132 is introduced so that the short-circuit region 132 forms a ballast resistor, and the short-circuit resistance of the IGBT device is improved through the short-circuit region 132. Moreover, when the short-circuit temperature of the IGBT device rises, the resistance value of the short-circuit region 132 becomes larger, which can greatly reduce the saturation current and improve the short-circuit resistance of the device. At the same time, in the emitter region 130, the latch region 133 is introduced so that when the IGBT device is turned on, most of the holes will reach the emitter metal region 134 of the IGBT device from the latch region 133, thereby reducing the hole concentration below the N+ active region 131 and making it difficult for the parasitic triode to conduct, improving the latch-up resistance of the IGBT device. In this way, by arranging the emitter region 130 on the P- base region 111 between the gate regions 120, not only the structure of the IGBT device is improved, but also the short-circuit resistance of the IGBT device is improved, and the latch-up resistance of the device is enhanced. On the premise of the same short-circuit resistance of the IGBT device, compared with the conventional IGBT device, the IGBT device of this embodiment does not affect the forward conduction voltage drop and does not increase the conduction loss. Through the structure of the IGBT device of this embodiment, the purpose of cost reduction and efficiency improvement is achieved.

[0055] Next, in combination with Figure 1 to introduce in detail the specific structure of the trench IGBT device provided in this embodiment:

[0056] Figure 1 The structure shown is the minimum repeating unit structure of the IGBT device. In Figure 1Among them, the IGBT device of this embodiment includes: a substrate 110, and a P-base region 111, two gate regions 120, and an emitter region 130 located on the substrate 110. The P-base region 111 is located between the gate regions 120. The left side of the P-base region 111 is in contact with the left gate region 120, and the right side of the P-base region 111 is in contact with the right gate region 120.

[0057] The emitter region 130 includes: two N+ active regions 131, two short-circuit regions 132, a latch-up region 133, and an emitter metal region 134.

[0058] Specifically, the short-circuit region 132 includes: a short-circuit trench 1321 and a short-circuit polysilicon 1322. The short-circuit polysilicon 1322 is made of polysilicon material. The short-circuit polysilicon 1322 is filled in the short-circuit trench 1321 so that the short-circuit region 132 forms a ballast resistor to improve the short-circuit resistance of the IGBT device. As Figure 1 shown, the emitter region 130 of this embodiment includes two short-circuit regions 132, and these two short-circuit regions 132 are formed through the same short-circuit trench 1321 during the manufacturing process. In the same short-circuit trench 1321, polysilicon is filled on the left and right sides respectively to form two short-circuit regions 132 distributed at intervals. The empty region between the two short-circuit regions 132 is an interval region, and the depth of the interval region is less than the depth of the short-circuit trench 1321 to ensure the stability of the emitter. Among them, the depth range of the short-circuit trench 1321 is 0.1~0.3um, and the width range of the short-circuit trench 1321 is 0.4~2um.

[0059] Principle of the short-circuit region 132: In this embodiment, at the N+ active region 131 in the emitter region 130, a polysilicon resistor, that is, a positive temperature coefficient ballast resistor, is formed by etching the short-circuit trench 1321 and then depositing polysilicon. When the IGBT device is short-circuited, it is equivalent to the IGBT being connected in series with a resistor. Therefore, under the same bus voltage, the total resistance increases, thereby reducing the short-circuit current and improving the short-circuit resistance. The ballast resistor (i.e., the polysilicon resistor) of this embodiment is a positive temperature coefficient resistor. Compared with the negative temperature coefficient ballast resistor, when the IGBT device of this embodiment is short-circuited, as the short-circuit temperature rises, the ballast resistor will become larger, so that the short-circuit current is smaller, and the short-circuit resistance is improved more efficiently. In addition, the wider the width of the polysilicon resistor and the smaller the depth, the larger the polysilicon resistance value, the smaller the short-circuit current, and the stronger the short-circuit resistance.

[0060] In this embodiment, highly doped polysilicon is deposited in the short-circuit trench 1321 to introduce a highly doped polysilicon ballast resistor in the emitter region 130. Since the polysilicon ballast resistor is a positive temperature coefficient ballast resistor, when the IGBT device is short-circuited, as the short-circuit temperature rises, the polysilicon ballast resistor increases, which can greatly reduce the saturation current and improve the short-circuit resistance of the IGBT device.

[0061] Two N+ active regions 131 are located on the P- base region 111 and between the gate regions 120. The N+ active region 131 is an active region with a high N-type doping concentration. The left N+ active region 131 is located between the left gate region 120 and the left short- circuit region 132. The left side of the left N+ active region 131 contacts the left gate region 120, and the right side of the left N+ active region 131 contacts the left short- circuit region 132. Similarly, the right N+ active region 131 is located between the right gate region 120 and the right short- circuit region 132. The left side of the right N+ active region 131 contacts the right short- circuit region 132, and the right side of the right N+ active region 131 contacts the right gate region 120.

[0062] Wherein, the junction depth of the N+ active region 131 is not less than the depth of the short- circuit trench 1321 to improve the short- circuit resistance of the device. It should be noted that when the junction depth of the N+ active region 131 is greater than the depth of the short- circuit trench 1321, the N+ active region 131 wraps the short- circuit trench 1321, that is, the N+ active region 131 wraps the short- circuit region 132.

[0063] The latch region 133 is located in the P- base region 111 between the two gate regions 120, below the two short- circuit regions 132, and is correspondingly arranged with the interval region between the two short- circuit regions 132, and is also in contact with the two short- circuit regions 132 respectively. The latch region 133 includes: a latch trench 1331 and a latch polysilicon 1332. The latch polysilicon 1332 is made of polysilicon. The latch polysilicon 1332 is filled in the latch trench 1331 so that the latch region 133 serves as a polysilicon electrode to improve the latch- up resistance of the IGBT device. The short- circuit trench 1321 and the latch trench 1331 form a T- shaped trench. And highly doped polysilicon is deposited in the T- shaped trench to introduce a positive temperature coefficient polysilicon resistor and a polysilicon electrode in the emitter region 130.

[0064] Wherein, the depth of the short- circuit trench 1321 is less than the depth of the latch trench 1331, and the width of the short- circuit trench 1321 is greater than the depth of the latch trench 1331 to increase the ballast resistance value, which is more conducive to improving the short- circuit resistance. The depth of the short- circuit trench 1321 is less than or equal to the junction depth of the N+ active region 131, and the depth of the latch trench 1331 needs to be greater than the junction depth of the N+ active region 131, which is more conducive to improving the latch- up resistance. The depth range of the latch trench 1331 is 0.2~1um, and the width range of the latch trench 1331 is 0.2~1.8um. The bottom of the latch region 133 of the present application is close to the bottom of the P- base region 111. When the IGBT device is turned on, most of the holes will reach the emitter metal region 134 from the polysilicon electrode in the latch trench 1331, thereby reducing the hole concentration under the N+ active region 131, making it difficult for the parasitic triode to conduct, and improving the latch- up resistance.

[0065] Principle of the latch region 133: In the structure of a conventional IGBT device (i.e., the IGBT device structure without the latch region 133 of this embodiment), when the IGBT device is turned on, most of the holes will reach the emitter metal region 134 under the N+ active region 131, making it easy to turn on the P-N+ diode (i.e., the diode formed by the P-base region 111 and the N+ active region 131). This causes the N+P-N- parasitic triode (i.e., the triode formed by the N+ active region 131, the P-base region 111, and the N-substrate 110) to conduct, triggering the latch-up effect. By arranging the bottom of the polysilicon electrode in the latch trench 1331 to be close to the bottom of the P-base region 111, when the IGBT device is turned on, most of the holes will reach the emitter metal region 134 from the polysilicon electrode in the latch trench 1331, thereby reducing the hole concentration under the N+ active region 131, making it difficult for the parasitic triode to conduct, and improving the latch-up resistance. In addition, the greater the depth and the smaller the width of the polysilicon electrode formed by the latch trench 1331 and the polysilicon, the stronger the latch-up resistance.

[0066] It should be noted that the widths and depths of the short-circuit trench 1321 and the latch trench 1331 of the T-shaped trench can be set according to actual requirements to meet different short-circuit resistance and latch-up resistance.

[0067] The gate region 120 includes: a gate trench 121, a gate oxide layer 122, and a gate polysilicon 123. The gate oxide layer 122 is located on the inner wall of the gate trench 121, that is, the gate oxide layer 122 is located on the bottom wall and the inner side wall of the gate trench 121. The gate polysilicon 123 fills the space formed by the gate oxide layer 122.

[0068] The IGBT device of this embodiment further includes: a dielectric layer 140. The dielectric layer 140 is located above the gate region 120, the N+ active region 131, and the short-circuit region 132, and is located below the emitter metal region 134, and the perforations of the dielectric layer 140 correspond to the spacer regions, so that the emitter metal region 134 fills the perforations. The dielectric layer 140 is an ILD dielectric layer (InterLayerDielectric, interlayer dielectric layer), which plays a role of electrical isolation, can also improve the signal transmission speed and reduce power consumption, and provides physical support for the emitter metal region 134 to ensure the structural stability.

[0069] The IGBT device of this embodiment further includes: an N-type field stop region 150, a P-type collector region 160, and a collector metal region 170. The N-type field stop region 150 is located under the substrate 110. The N-type field stop region 150 is a field stop region with a high N-type doping concentration. The P-type collector region 160 is located under the N-type field stop region 150. The P-type collector region 160 is a collector region with a high P-type doping concentration. The collector metal region 170 is located under the P-type collector region 160.

[0070] Next, the manufacturing process of the IGBT device of this embodiment will be described in conjunction with Figure 1 :

[0071] As Figure 2 shown, a gate trench 121 is etched on the N-substrate 110. The depth range of the gate trench 121 is 3 - 6 μm, and the width range is 0.6 - 1.2 μm.

[0072] As Figure 3 shown, between two adjacent gate trenches 121, a short-circuit trench 1321 is etched on the N-substrate 110. The depth range of the short-circuit trench 1321 is 0.1 - 0.3 μm, and the width range is 0.4 - 2 μm.

[0073] As Figure 4 shown, a latch trench 1331 is etched in the short-circuit trench 1321. The depth range of the latch trench 1331 is 0.2 - 1 μm, and the width range is 0.2 - 1.8 μm.

[0074] As Figure 5 shown, a gate oxide layer is thermally grown on the inner wall of the gate trench 121 to obtain the gate oxide layer 122 in the gate trench 121. And the oxide layers on the surfaces of the short-circuit trench 1321, the latch trench 1331, and the N-substrate 110 are removed, and the gate oxide layer 122 in the gate trench 121 is retained.

[0075] As Figure 6 shown, highly doped polysilicon is deposited in the space formed by the gate oxide layer 122 in the gate trench 121, in the short-circuit trench 1321, and in the latch trench 1331 to obtain the gate region 120, the continuous short-circuit region 132 (i.e., the short-circuit trench 1321, the short-circuit polysilicon 1322), and the latch region 133 (i.e., the latch trench 1331, the latch polysilicon 1332). And etch-back is performed to make the surfaces of the gate region 120, the short-circuit trench 1321, and the N-substrate 110 be on the same horizontal plane. Among them, the doping concentration range of the polysilicon is 1E10 19 ~1E10 21 cm -3 .

[0076] AsFigure 7 As shown, an implantation and push-knot process is performed to form a P-base region 111 and an N+ active region 131 between two gate regions 120. The junction depth of the N+ active region 131 is greater than or equal to the depth of the short-circuit trench 1321, and the junction depth of the P-base region 111 is greater than the depth of the latch-up trench 1331. Then, a dielectric layer 140 is deposited, and holes are etched in the dielectric layer 140 and the polysilicon in the short-circuit trench 1321 (the depth of the holes is less than the depth of the short-circuit trench 1321), and then metal is deposited to obtain spaced short-circuit regions 132 and metal filled in the spaced regions formed through the holes, forming an emitter metal region 134. The emitter metal region 134 covers the N+ active region 131, the short-circuit region 132, and the gate region 120.

[0077] As Figure 1 shown, through conventional backside processes such as implanting ions, annealing, and depositing backside metal on the backside of the substrate 110, an N-type field-stop region 150, a P-type collector region 160, and a collector metal region 170 are sequentially formed on the backside of the substrate 110, and finally a complete IGBT device structure is formed.

[0078] The manufacturing process of this embodiment can be compatible with the existing process, improve the structure of the IGBT device, and realize the structures of the short-circuit region 132 and the latch-up region 133 in the emitter region 130. Therefore, through the short-circuit region 132, the short-circuit resistance of the IGBT is greatly improved, and at the same time, through the latch-up region 133, the latch-up resistance of the IGBT device is enhanced.

[0079] The principle of the trench-type IGBT device in this embodiment is, as Figure 8 shown, the short-circuit current curve diagram of the trench-type IGBT device in this embodiment and the trench-type IGBT device without the short-circuit region 132 and the latch-up region 133 (i.e., the comparison device). The abscissa represents time, and the ordinate represents the short-circuit current Ic of the device. Among them, the structures of the comparison device are the same as those of the trench-type IGBT device in this embodiment except that the short-circuit region 132 and the latch-up region 133 are not provided. P represents the short-circuit current curve of the trench-type IGBT device in this embodiment, and Q represents the short-circuit current curve of the comparison device. P1 and Q1 represent the inflection points when the short circuit occurs, that is, the device current starts to rise and reaches the saturation current point of the device. P2 and Q2 represent the failure inflection points, that is, after the device short circuit occurs, the device fails after a certain time, and the current keeps rising and is out of control. The short-circuit current of the trench-type IGBT device in this embodiment is much smaller than that of the comparison device, and the short-circuit withstand time is also much higher than that of the comparison device. Therefore, the structure of the trench-type IGBT device in this embodiment greatly improves the short-circuit resistance.

[0080] As Figure 9The equivalent circuit diagram of the trench IGBT device of this embodiment is shown. The parasitic NPN transistor is in the dashed box, and the transistor in the lower right corner represents the PNP transistor at the collector. By introducing the latch-up region 133 in the trench IGBT device of this embodiment, most of the holes flow into the emitter E (i.e., the emitter metal region 134) from the latch-up region 133, and only a small part of the holes pass directly under the N+ active region 131, thus greatly reducing the Rs resistance, further greatly reducing the conduction risk of the parasitic NPN transistor, and improving the latch-up resistance. Figure 9 In it, G represents the gate of the device, and C represents the collector of the transistor.

[0081] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0082] In the embodiments of the present invention, in the emitter region, a short-circuit region is introduced to form a ballast resistor in the short-circuit region, and the short-circuit resistance improves the short-circuit resistance of the IGBT device. And when the short-circuit temperature of the IGBT device rises, the resistance value of the short-circuit region becomes larger, which can greatly reduce the saturation current and improve the short-circuit resistance of the device. At the same time, in the emitter region, a latch-up region is introduced so that when the IGBT device is turned on, most of the holes will reach the emitter of the IGBT device from the latch-up region, thereby reducing the hole concentration under the N+ active region and making the parasitic transistor not easily turn on, improving the latch-up resistance of the IGBT device. In this way, by arranging the emitter region on the P-base region between the gate regions, not only the structure of the IGBT device is improved, but also the short-circuit resistance of the IGBT device is improved, and the latch-up resistance of the device is enhanced. On the premise of the same short-circuit resistance of the IGBT device, compared with the conventional IGBT device, the IGBT device of this embodiment does not affect the forward conduction voltage drop and does not increase the conduction loss. Through the structure of the IGBT device in the embodiments of the present invention, the purpose of cost reduction and efficiency improvement is achieved.

[0083] Embodiment 2

[0084] Based on the same inventive concept, the second embodiment of the present invention also provides a manufacturing method for a trench IGBT device for manufacturing the trench IGBT device as described in Embodiment 1, as Figure 10 shown, the method includes:

[0085] S201, forming a gate region on a substrate;

[0086] S202, forming a P-base region and an emitter region between the gate regions, where the P-base region is located between the gate regions and the P-base region is in contact with the gate regions;

[0087] The emitter region includes: an N+ active region, a short-circuit region, a latch-up region, and an emitter metal region;

[0088] The N+ active region is located on the P- base region, between the gate regions, and between the gate region and the short-circuit region;

[0089] The short-circuit regions are distributed at intervals on the P- base region, between the gate regions, above the latch region, and in contact with the latch region;

[0090] The latch region is located in the P- base region, between the gate regions, and correspondingly below the interval region between the short-circuit regions;

[0091] The emitter metal region is filled in the interval region and covers the N+ active region, the short-circuit region, and the gate region.

[0092] Since the manufacturing method of the trench IGBT device introduced in this embodiment is the manufacturing method adopted for the trench IGBT device in Embodiment 1 of the present application, based on the trench IGBT device introduced in Embodiment 1 of the present application, those skilled in the art can understand the specific implementation manners and various variations of the manufacturing method of the trench IGBT device in this embodiment. Therefore, the implementation of how the manufacturing method of the trench IGBT device realizes the trench IGBT device in Embodiment 1 of the present application will not be described in detail here. As long as those skilled in the art implement the manufacturing method adopted for the trench IGBT device in Embodiment 1 of the present application, it falls within the scope of protection of the present application.

[0093] Those skilled in the art should understand that although the preferred embodiments of the present invention have been described, once those skilled in the art know the basic creative concept, additional changes and modifications can be made to these embodiments. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0094] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A trench-type IGBT device, characterized in that, Comprising: a substrate, and a P-base region, a gate region, and an emitter region located on the substrate; the P-base region is located between the gate regions, and the P-base region is in contact with the gate regions; the emitter region includes: an N+ active region, a short-circuit region, a latch region, and an emitter metal region; the N+ active region is located on the P-base region, between the gate regions, and between the gate region and the short-circuit region; the short-circuit regions are distributed at intervals on the P-base region, between the gate regions, above the latch region, and in contact with the latch region; the latch region is located in the P-base region, between the gate regions, and corresponding to the interval region between the short-circuit regions; the bottom of the latch region is close to the bottom of the P-base region; the emitter metal region fills the interval region and covers the N+ active region, the short-circuit region, and the gate region; the short-circuit region includes: a short-circuit trench and short-circuit polysilicon; the short-circuit polysilicon fills the short-circuit trench to form a ballast resistor in the short-circuit region, improving the short-circuit resistance of the IGBT device; the latch region includes: a latch trench and latch polysilicon, and the latch polysilicon fills the latch trench to make the latch region serve as a polysilicon electrode, improving the anti-latch-up ability of the IGBT device.

2. The device according to claim 1, characterized in that, The junction depth of the N+ active region is not less than the depth of the short-circuit trench.

3. The device according to claim 1, characterized in that, The depth of the short-circuit trench is less than the depth of the latch trench, and the width of the short-circuit trench is greater than the depth of the latch trench.

4. The device according to claim 3, characterized in that, The depth range of the short-circuit trench is 0.1 - 0.3 um, and the width range of the short-circuit trench is 0.4 - 2 um; the depth range of the latch trench is 0.2 - 1 um, and the width range of the latch trench is 0.2 - 1.8 um.

5. The device according to claim 1, characterized in that, The gate region includes: a gate trench, a gate oxide layer, and gate polysilicon; the gate oxide layer is located on the inner wall of the gate trench; the gate polysilicon fills the space formed by the gate oxide layer.

6. The device according to claim 1, wherein, Further comprising: a dielectric layer; the dielectric layer is located above the gate region, the N+ active region, and the short-circuit region, below the emitter metal region, and the through holes of the dielectric layer correspond to the interval region, so that the emitter metal region fills the through holes.

7. The device according to claim 1, wherein, Further comprising: an N-type field stop region, a P-type collector region, and a collector metal region; the N-type field stop region is located under the substrate; the P-type collector region is located under the N-type field stop region; the collector metal region is located under the P-type collector region.

8. A manufacturing method of a trench-type IGBT device, characterized in that, For manufacturing the trench-type IGBT device according to any one of claims 1 - 7, the method includes: forming a gate region on the substrate; forming a P-base region and an emitter region between the gate regions, wherein the P-base region is located between the gate regions and the P-base region is in contact with the gate regions; the emitter region includes: an N+ active region, a short-circuit region, a latch region, and an emitter metal region; The N+ active region is located on the P- base region, between the gate regions, and between the gate region and the short-circuit region; The short-circuit regions are distributed at intervals on the P- base region, between the gate regions, above the latch region, and in contact with the latch region; The latch region is located in the P- base region, between the gate regions, and correspondingly below the interval region between the short-circuit regions; The emitter metal region is filled in the interval region and covers the N+ active region, the short-circuit region, and the gate region.

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