A four-terminal SiC MOSFET device of radiation-hardened design and a method of manufacturing the same

Abstract

This invention relates to a radiation-hardened four-terminal SiC MOSFET device and its manufacturing method. Based on the original three electrodes of a MOSFET device, a fourth control electrode is added to control the potential barrier of the P-base region, adjust the electric field within the P-base region and the depletion width of the JFET region, and simultaneously provide an elimination path for minority carriers, improving the reliability of the MOSFET device and circuit under extreme environments such as irradiation, high temperature, and high pressure. The device includes: a SiC substrate, an N-type epitaxial layer, a P-base region, an N+ source region, a P+ short-circuit region, an oxide layer, a gate polysilicon layer, an interlayer dielectric, a source metal, a drain metal, and a control electrode. This invention, by controlling the fourth control electrode, suppresses the conduction of parasitic BJTs and allows the device to operate flexibly in different states, suitable for various irradiation environments.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically to a radiation-hardened four-terminal SiCMOSFET device and its manufacturing method. Background Technology

[0002] Silicon carbide (SiC), as a typical representative of third-generation wide-bandgap semiconductor materials, possesses excellent properties such as a wide bandgap, high thermal conductivity, and strong breakdown field. This enables 4H-SiC devices, especially SiC MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), to exhibit radiation resistance, high voltage, high current, high power, and high-temperature operating characteristics. With the increasing application of SiC devices in extreme environments such as aerospace, the requirements for their application conditions and stability are becoming increasingly stringent, especially the reliability under extreme operating conditions. However, SiC MOSFET devices in space are affected by space radiation effects, with single-event effects being one of the most significant radiation effects.

[0003] Single-event effects (SEE) in semiconductor devices refer to the series of reactions caused by high-energy particles colliding with atoms in the device's crystal lattice when they pass through the material, generating electron-hole pairs and transferring some energy into the device. SEE include gate breakdown, burn-out, lock-in, and flip-flop, among which burn-out and gate breakdown are permanent and irreversible damage. Due to the parasitic transistor structure in SiC MOSFETs, under single-event irradiation, the parasitic transistor conducts and ionizes upon impact with the high electric field at the substrate-epitaxy interface, creating positive feedback that leads to device burn-out and failure. Therefore, SEE has become a critical factor limiting its application in space. To meet the requirements of space applications, device ruggedization design is essential.

[0004] The traditional SiC MOSFET device structure currently used is as follows: Figure 1 As shown, when the MOSFET is in the blocking state, heavy ion bombardment generates a large number of electron-hole pairs on the incident track. Holes drift towards the gate oxide-SiC interface under the influence of the drain-source voltage, and are then attracted by the lateral electric field generated by the P-base region and the N-type epitaxial layer, entering the P-base region. The holes entering the P-base region increase the potential at the edge of the P-base region, leading to an increase in the transistor's leakage current. Simultaneously, a high electric field is generated at the substrate-epitaxy layer, increasing collisional ionization and generating more electron-hole pairs. These holes then drift towards the gate oxide-SiC interface, increasing the transistor's electron current and creating positive feedback. This causes the device temperature to rise rapidly, eventually leading to thermal runaway.

[0005] This invention introduces a new terminal (control electrode) and adjusts its potential to extract irradiated carriers. Simultaneously, by adjusting the control electrode potential, the barrier height and width of the P-base region are increased, resulting in fewer N+ source electrons diffusing into the P-base region, reducing leakage current and suppressing positive feedback. Furthermore, when the device is in the on-state, the control electrode potential can be forward-biased, allowing both the BJT and MOSFET structures to conduct simultaneously, thereby increasing the forward current. When the device is in the off-state, the control electrode potential can be flexibly adjusted according to the surrounding irradiation environment, making it suitable for environments with different radiation intensities. Summary of the Invention

[0006] In view of the above problems, the present invention provides a radiation-hardened four-terminal SiC MOSFET device, comprising: an N-type semiconductor substrate; a drain located at the bottom of the substrate; an epitaxial layer located on the substrate; a P-base region located in the epitaxial layer; an N+ source region located in the P-base region; a P+ short-circuit region located in the P-base region; an oxide layer located on the epitaxial layer and adjacent to the N+ source region; a gate located on the oxide layer; a control electrode located on the P+ short-circuit region; an interlayer dielectric located around the gate and on the control electrode; and an N+ source located on a portion of the source region.

[0007] According to an embodiment of the present invention, a control electrode is added to the above-mentioned P-base region.

[0008] According to an embodiment of the present invention, the control electrode and the source electrode are separated by an interlayer dielectric with a thickness of 10~500nm.

[0009] The present invention also provides a method for manufacturing a radiation-hardened four-terminal SiC MOSFET device, comprising the following steps: forming an epitaxial layer on a substrate; forming a P-base region on the epitaxial layer; forming an N+ source region in the P-base region; etching a trench in the P-base region; forming a P+ short-circuit region at the bottom of the trench; forming an oxide layer on the epitaxial layer next to the N+ source region; forming a gate polysilicon on the oxide layer; forming a control electrode on the P+ short-circuit region; forming an interlayer dielectric on the gate polysilicon and the control electrode; forming a source and a drain to obtain a radiation-hardened four-terminal SiC MOSFET device.

[0010] According to an embodiment of the present invention, the depth of the etching trench can be adjusted according to the depth and concentration of the source region and the P-base region.

[0011] According to an embodiment of the present invention, the junction depth of the P+ short-circuit region is 0.2~0.6μm, and the junction depth of the P+ short-circuit region is 0.1~1.5μm smaller than the junction depth of the P-base region, with a peak doping concentration of 5×10⁻⁶. 18 cm -3 ~5×1020 cm -3 .

[0012] According to an embodiment of the present invention, the above-mentioned formation of a control electrode on the P+ short-circuit region includes: etching a groove in the region above the P+ short-circuit region by photolithography and etching, isolating the base region by an oxide layer; removing the interlayer dielectric above the P+ short-circuit region by photolithography and etching, depositing a control electrode material in the etched region, and forming an ohmic contact with the semiconductor material, i.e., the control electrode, wherein the electrode material of the control electrode is polycrystalline silicon.

[0013] According to embodiments of the present invention, the above-described devices or methods are not only applicable to SiC materials, but also suitable for power MOSFET devices and circuits of individual material systems such as Si-based, C-based, GaN-based, AlGaN-based, AlN-based, BN-based, ZnO-based, and Ga2O3-based, as well as power MOSFET devices and circuits of heterogeneous fusion systems such as Si-based, C-based, GaN-based, AlGaN-based, AlN-based, BN-based, ZnO-based, and Ga2O3-based.

[0014] According to embodiments of the present invention, the above-described devices or methods are suitable not only for power MOSFET devices, but also for IGBT semiconductor discrete devices that also have a gate oxide layer.

[0015] According to embodiments of the present invention, the above-described device or method, by introducing a new control electrode, controls the electric field in the P-base region, suppresses the conduction of parasitic BJTs, provides a path for holes to escape, avoids the accumulation of holes in the P-base region, and adjusts the electric field in the P-base region and the depletion width of the JFET region, thereby deriving holes from the control electrode under the combined stress of irradiation, temperature, and voltage.

[0016] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0017] 1. This invention introduces a new control electrode, which can attract and drive holes, preventing holes from accumulating at the far end of the P-base region. The new control electrode makes it more difficult for the parasitic transistor to turn on, thereby increasing the single-event burn-out threshold.

[0018] 2. This invention, by introducing a new control electrode, can effectively adjust the potential distribution of the P-base region and enhance the potential control capability at the far end of the P-base region. Simultaneously, this design can increase the electron barrier height, thereby reducing the leakage current of the NPN transistor and suppressing positive feedback.

[0019] 3. By introducing a new control electrode, the potential of the control electrode can be flexibly adjusted according to the surrounding irradiation environment, making it suitable for environments with different radiation intensities.

[0020] 4. This invention improves single-event gate penetration capability by introducing a new control electrode to attract electron-hole pairs generated by irradiation and simultaneously deplete the carriers in the JFET region.

[0021] 5. This invention has good compatibility with traditional SiC MOSFET device fabrication processes, and mass production can be achieved without special adjustments to the SiC process. Attached Figure Description

[0022] The above-described features, other objects, and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0023] Figure 1 A schematic cross-sectional view of a conventional MOSFET device is shown.

[0024] Figure 2 A structural diagram of a radiation-hardened four-terminal SiC MOSFET device according to an embodiment of the present invention is shown.

[0025] Figure 3 A flowchart illustrating a method for fabricating a radiation-hardened four-terminal SiC MOSFET device according to an embodiment of the present invention is shown.

[0026] Figures 4A-4J It shows Figure 3 The diagram shows a cross-sectional view of the device structure formed after some operations are performed in the method flow shown.

[0027] Figure 5 A comparison chart of device burn-out thresholds according to an embodiment of the present invention is shown.

[0028] Figure 6 A comparison graph of device burn-out thresholds according to another embodiment of the present invention is shown.

[0029] [Explanation of Figure Markers]:

[0030] 1-Substrate, 2-Epipolar layer, 3-P-base region, 4-N+ ​​source region, 5-P+ short-circuit region, 6-Oxide layer, 7-Gate, 8-Interlayer dielectric, 9-Source, 10-Drain, 11-Control electrode. Detailed Implementation

[0031] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0033] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0034] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0035] Figure 2 A structural diagram of a multi-terminal MOSFET device according to an embodiment of the present invention is shown.

[0036] like Figure 2 As shown, the radiation-hardened four-terminal SiC MOSFET device of this embodiment may include: an N-type semiconductor substrate 1; a drain 10 located at the bottom of the substrate 1; an epitaxial layer 2 located on the substrate 1; a P-base region 3 located in the epitaxial layer 2; an N+ source region 4 located in the P-base region 3; a P+ short-circuit region 5 located in the P-base region 3; an oxide layer 6 located on the epitaxial layer 2 and next to the N+ source region 4; a gate 7 located on the oxide layer 6; a control electrode 11 located on the P+ short-circuit region 5; an interlayer dielectric 8 located around the gate 7 and on the control electrode 11; and a source 9 located on a portion of the N+ source region 4.

[0037] According to an embodiment of the present invention, a control electrode 11 is added to the P-base region 3.

[0038] According to an embodiment of the present invention, the control electrode 11 and the source electrode 9 are separated by an interlayer dielectric 8, the thickness of which is 10~500nm. This thickness can be adaptively adjusted according to actual needs.

[0039] Optionally, the layout of the P-base region, N+ source region, and P+ short-circuit region described above can be at least one of square, hexagonal, or lattice array.

[0040] Figure 3A flowchart illustrating a method for fabricating a radiation-hardened four-terminal SiC MOSFET device according to an embodiment of the present invention is shown.

[0041] like Figure 3 As shown, the method may include operations S301 to S310.

[0042] In operation S301, an epitaxial layer is formed on the substrate.

[0043] In operation S302, a P-base region is formed on the epitaxial layer.

[0044] During operation of S303, an N+ source region is formed in the P base region.

[0045] In operation S304, trenches are etched in the P-base region.

[0046] When operating S305, a P+ short-circuit zone is formed at the bottom of the trench.

[0047] In operation S306, an oxide layer is formed on the epitaxial layer next to the N+ source region.

[0048] In operation S307, gate polysilicon is formed on the oxide layer.

[0049] When operating S308, a control electrode is formed in the P+ short-circuit region.

[0050] In operation S309, an interlayer dielectric is formed on the gate polysilicon and the control electrode.

[0051] By operating S310, the source and drain are formed, resulting in a radiation-hardened four-terminal SiC MOSFET device.

[0052] The following combination Figures 4A-4J right Figure 3 The preparation method shown is described below.

[0053] like Figure 4A As shown, an N-type epitaxial layer 2 can be formed on an N-type SiC substrate 1 using an epitaxial process. The resistivity of the N-type SiC substrate 1 can be 0.01 Ω·cm ~ 0.03 Ω·cm, and the thickness can be 100 μm ~ 500 μm. The doping concentration of the N-type epitaxial layer 2 can be 5 × 10⁻⁶. 14 cm -3 ~5×10 16 cm -3 The thickness can be 8~20μm.

[0054] like Figure 4B As shown, a P-based region 3 can be formed above the N-epitaxial layer 2 using photolithography and ion implantation processes. The junction depth of the P-based region 3 can be 0.2 μm to 2.5 μm, and the peak implantation concentration can be 1 × 10⁻⁶.17 cm -3 ~5×10 19 cm -3 The depth and concentration of the P-base region are adjusted and matched.

[0055] Continue to refer to Figure 4B An N+ source region 4 can be formed in the P-based region 3 using photolithography and ion implantation processes. The junction depth of the N+ source region 4 can be 0.1 μm to 0.5 μm, and the junction depth of the N+ source region 4 can be 0.1 μm to 1.5 μm smaller than that of the P-based region 3. The peak doping concentration can be 5 × 10⁻⁶. 18 cm -3 ~5×10 20 cm -3 .

[0056] like Figure 4C As shown, after forming the N+ source region 4, a trench can be etched next to the N+ source region 4 in the P-based region 3 using photolithography and etching processes. The trench depth can be 0.1 μm to 0.5 μm. The trench depth can be adaptively adjusted and matched according to the depth and concentration of the source region and the P-based region.

[0057] like Figure 4D As shown, at the bottom of the trench, a P+ short-circuit region 5 can be formed in the P-based region 3 using photolithography and ion implantation processes. The junction depth of the P+ short-circuit region 5 can be 0.2 μm to 0.6 μm, and the junction depth of the P+ short-circuit region 5 can be 0.1 μm to 1.5 μm smaller than the junction depth of the P-based region 3. The peak doping concentration can be 5 × 10⁻⁶. 18 cm -3 ~5×10 20 cm -3 .

[0058] like Figure 4E As shown, an oxide layer 6 can be generated on the device surface using thermal oxidation or deposition processes. The thickness of the oxide layer 6 can be 10nm to 200nm. Excess gate oxide layer is removed by photolithography and etching.

[0059] like Figure 4F As shown, a deposition process can be used to deposit a layer of polysilicon on top of the oxide layer 6 as the gate 7. The excess polysilicon can be removed by photolithography and etching processes. After removal, the overlap between the gate 7 and the N+ source region 4 can be 0.05μm ~ 0.2μm.

[0060] like Figure 4GAs shown, the control electrode 11 can be formed using deposition, photolithography, and etching processes. The depth of the control electrode is 0.1~0.5μm, matching the trench depth, the P-base region depth, and the N+ source region depth. The process of forming the control electrode on the P+ short-circuit region can include the following operations: etching a groove in the region above the P+ short-circuit region by photolithography and etching, isolating the base region by an oxide layer; removing the interlayer dielectric above the P+ short-circuit region by photolithography and etching, depositing the control electrode material in the etched region to form an ohmic contact with the semiconductor material, i.e., the control electrode. The electrode material of the control electrode is polycrystalline silicon.

[0061] like Figure 4H As shown, deposition, photolithography and etching processes can be used to deposit interlayer dielectric 8 above the polysilicon gate 7 and oxide layer 6 and above the control electrode 11, and remove excess interlayer dielectric 8 by photolithography and etching.

[0062] like Figure 4I As shown, the source electrode 9 is formed using deposition, photolithography, and etching processes.

[0063] like Figure 4J As shown, the back of the device can be formed by laser annealing, metal thickening and deposition processes to form the device drain 10, thus obtaining a radiation-hardened four-terminal SiC MOSFET device.

[0064] To illustrate this solution more clearly, the process flow diagram only shows the layered layout relevant to the patent. The dimensions in the diagram (including lateral dimensions, layout dimensions, dielectric thickness, metal thickness, junction depth, etc.) do not represent actual dimensions but are only for illustrating the patent concept. The structure and method of this invention are merely examples and can also be applied to planar MOSFETs, planar IGBTs (Insulated Gate Bipolar Transistors), and JBSs (Junction Barrier Schottky Diodes); the substrate material can be not only SiC but also Si, GaN, C, and Ga2O3, etc.

[0065] This invention extends the power MOSFET device from a three-terminal device to a four-terminal device structure and its fabrication method. It is not only applicable to SiC material, but also suitable for power MOSFET devices and circuits based on individual material systems such as Si-based, C-based, GaN-based, AlGaN-based, AlN-based, BN-based, ZnO-based, and Ga2O3-based. It can also be applied to power MOSFET devices and circuits based on heterogeneous fusion systems of Si-based, C-based, GaN-based, AlGaN-based, AlN-based, BN-based, ZnO-based, and Ga2O3-based materials. Furthermore, it can be applied to other types of discrete semiconductor devices with gate oxide layers, such as IGBTs.

[0066] Figure 5 A comparison chart of device burn-out thresholds according to an embodiment of the present invention is shown.

[0067] like Figure 5 As shown, the horizontal axis represents time, and the vertical axis represents leakage current. This comparison examines the burn-off thresholds between a conventional MOSFET device (CN-MOSFET) and the MOSFET device (4T-MOSFET) of this embodiment, both with a drain bias of 750V. At a drain bias of 750V, the burn-off threshold of the CN-MOSFET is approximately 1 × 10⁻⁶. -8 With a control bias voltage of 0V, the burn-out threshold of a 4T-MOSFET is approximately 1×10⁻⁶. -7 s, with a control bias voltage of -5V, the 4T-MOSFET in the 1×10 diagram is shown. -13 s~1×10 -6 The material will not burn out between s, meaning the burnout threshold is greater than 1×10. -6 s.

[0068] Figure 6 A comparison graph of device burn-out thresholds according to another embodiment of the present invention is shown.

[0069] like Figure 6 As shown, the horizontal axis can represent time, and the vertical axis can represent the maximum gate dielectric electric field. A comparison of the burn-out thresholds between a conventional MOSFET device (CN-MOSFET) and the MOSFET device (4T-MOSFET) of this embodiment is presented, with a drain bias of slightly 750V. With a drain bias of slightly 750V, the burn-out threshold of the CN-MOSFET is 1×10⁻⁶. -7 s~1×10 -8 Between 1 and 10, with the control bias voltage at 0V, the burn-out threshold of the 4T-MOSFET is 1×10⁻⁶. -6 s ~1×10 -7 Between s, with a control bias voltage of -5V, the 4T-MOSFET in the 1×10 diagram is shown. -13 s~1×10 -6 The material will not burn out between s, meaning the burnout threshold is greater than 1×10. -6 s.

[0070] The radiation-hardened four-terminal SiC MOSFET device provided in this embodiment of the invention, by introducing a control electrode, can attract and remove holes, preventing their accumulation at the far end of the P-base region, making the transistor more difficult to turn on, thereby increasing the single-event burn-out threshold. This embodiment of the invention, by introducing a control electrode, can effectively adjust the potential distribution of the P-base region and enhance the potential control capability at the far end of the P-base region. Simultaneously, this design can increase the electron barrier height and width, thereby reducing the leakage current of the NPN transistor and suppressing positive feedback. In one example, such as... Figure 5 and Figure 6 As shown, by increasing the control electrode, the transistor can be made more difficult to turn on. When the control electrode potential of the 4T-MOSFET is -5V, it can be seen that the leakage current and the electric field at the substrate-epitaxy layer interface are not out of control, that is, the occurrence of positive feedback of the device is suppressed, thereby increasing the burn-out threshold.

[0071] This invention, through adding a control electrode structure in the P-base region and separating the interlayer dielectric structure between the control electrode and the source electrode, controls the electric field in the P-base region, suppresses the conduction of parasitic BJTs, provides a path for holes to escape, avoids the accumulation of holes in the P-base region, and adjusts the electric field in the P-base region and the depletion width of the JFET region, thereby allowing holes to be extracted from the control electrode under combined stresses such as irradiation, high temperature, and high pressure.

[0072] This invention, by introducing a control electrode, allows for flexible adjustment of the control electrode potential based on the surrounding irradiation environment, making it suitable for environments with varying radiation intensities. For example, when the device is in the on-state, the control electrode potential can be set to 0V, thereby increasing the specific on-resistance. When the device is in the off-state, the control electrode potential can be adjusted according to the drain-source voltage and the surrounding radiation environment, thereby controlling the potential and electric field distribution within the P-base region, increasing the attraction of holes and the obstruction of electrons. This invention, by introducing a control electrode, can attract electron-hole pairs generated by irradiation while simultaneously depleting carriers in the JFET region, improving single-event gate penetration capability. This invention exhibits good compatibility with traditional SiC MOSFET device fabrication processes, enabling mass production without special adjustments to the SiC process.

[0073] It should be noted that, unless it is explicitly stated that there is a sequential order of execution between different operations, or that there is a sequential order of execution between different operations in terms of technical implementation, the execution order between multiple operations may not be significant, and multiple operations may be executed simultaneously.

[0074] Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0075] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method for manufacturing a radiation-hardened four-terminal SiC MOSFET device, characterized in that, Includes the following steps: An epitaxial layer is formed on the substrate; A P-base region is formed on the epitaxial layer; An N+ source region is formed in the P base region; Trenches are etched in the P-base region; A P+ short-circuit region is formed at the bottom of the trench; An oxide layer is formed on the epitaxial layer, next to the N+ source region; Gate polysilicon is formed on the oxide layer; A control electrode is formed in the P+ short-circuit region; An interlayer dielectric is formed on the gate polysilicon and the control electrode; By forming the source and drain, a radiation-hardened four-terminal SiC MOSFET device is obtained.

2. The manufacturing method according to claim 1, characterized in that, The depth of the etching trench can be adjusted according to the depth and concentration of the source region and the P-base region.

3. The manufacturing method according to claim 1, characterized in that, The P+ short-circuit region junction depth is 0.2~0.6μm, and the P+ short-circuit region junction depth is 0.1~1.5μm smaller than the P-base region junction depth. The peak doping concentration is 5×10⁻⁶. 18 cm -3 ~5×10 20 cm -3 .

4. The manufacturing method according to any one of claims 1-3, characterized in that, The formation of a control electrode in the P+ short-circuit region includes: A groove is etched above the P+ short-circuit region using photolithography and etching, and the base region is isolated by an oxide layer. The interlayer dielectric above the P+ short-circuit region is removed by photolithography and etching. The control electrode material is deposited in the etched area to form an ohmic contact with the semiconductor material, i.e., the control electrode. The control electrode material is polycrystalline silicon.

5. The manufacturing method according to any one of claims 1-4, characterized in that, It is not only applicable to SiC materials, but also suitable for power MOSFET devices and circuits based on individual materials such as Si, C, GaN, AlGaN, AlN, BN, ZnO, and Ga2O3, as well as power MOSFET devices and circuits based on heterogeneous fusion systems of Si, C, GaN, AlGaN, AlN, BN, ZnO, and Ga2O3.

6. The manufacturing method according to any one of claims 1-4, characterized in that, It is suitable not only for power MOSFET devices, but also for IGBT semiconductor discrete devices that also have a gate oxide layer.

7. The manufacturing method according to any one of claims 1-4, characterized in that, By introducing a new control electrode, the electric field in the P-base region is controlled, the conduction of parasitic BJTs is suppressed, a path for holes to be discharged is provided, and the accumulation of holes in the P-base region is avoided. The electric field in the P-base region and the depletion width of the JFET region are adjusted, thereby allowing holes to be discharged from the control electrode under the combined stress of irradiation, temperature and voltage.

8. A radiation-hardened four-terminal SiC MOSFET device manufactured using the manufacturing method according to any one of claims 1-4, characterized in that, include: N-type semiconductor substrate; The drain electrode is located at the bottom of the substrate; Epitaxial layer located on the substrate; The P-base region is located in the epitaxial layer; The N+ source region is located in the P base region; The P+ short-circuit region is located in the P base region; The oxide layer located on the epitaxial layer and next to the N+ source region; The gate located on the oxide layer; The control electrode is located on the P+ short-circuit region; Interlayer dielectric located around the gate and on the control electrode; The source electrode is located on a portion of the N+ source region; Based on the original three electrodes of the MOSFET device, the potential barrier of the P-base region is controlled, the electric field in the P-base region and the depletion width of the JFET region are adjusted, and at the same time, an elimination path is provided for minority carriers to improve reliability.

9. A radiation-hardened four-terminal SiC MOSFET device according to claim 8, characterized in that, A control electrode was added to the P-base region.

10. A radiation-hardened four-terminal SiC MOSFET device according to claim 8, characterized in that, The control electrode and the source electrode are separated by an interlayer dielectric with a thickness of 10~500nm.

11. The device according to any one of claims 8-10, characterized in that, It is not only applicable to SiC materials, but also suitable for power MOSFET devices and circuits based on individual materials such as Si, C, GaN, AlGaN, AlN, BN, ZnO, and Ga2O3, as well as power MOSFET devices and circuits based on heterogeneous fusion systems of Si, C, GaN, AlGaN, AlN, BN, ZnO, and Ga2O3.

12. The device according to any one of claims 8-10, characterized in that, It is suitable not only for power MOSFET devices, but also for IGBT semiconductor discrete devices that also have a gate oxide layer.

13. The device according to any one of claims 8-10, characterized in that, By introducing a new control electrode, the electric field in the P-base region is controlled, the conduction of parasitic BJTs is suppressed, a path for holes to be discharged is provided, and the accumulation of holes in the P-base region is avoided. The electric field in the P-base region and the depletion width of the JFET region are adjusted, thereby allowing holes to be discharged from the control electrode under the combined stress of irradiation, temperature and voltage.

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