Semiconductor structure and preparation method thereof

Abstract

The present invention relates to a semiconductor structure and a method for fabricating the same, comprising: a semiconductor substrate, a gate structure, and a source and drain region of a second conductivity type. The semiconductor substrate comprises a well region of a first conductivity type; the source and drain regions are located on the upper surface of the well region; the gate structure is located on the upper surface of the well region, and the drain and source regions are located on either side of the gate structure in a first direction. The gate structure comprises a sequentially stacked gate dielectric layer, a semiconductor layer, and a first doped region of a second conductivity type and a second doped region of the first conductivity type located within the semiconductor layer, wherein the width of the second doped region in the first direction is smaller than that of the first doped region. The first and second doped regions are located on one side of the gate structure near the drain and source regions, respectively, and are both located on the upper surface of the semiconductor layer, and have a first preset depth and a second preset depth greater than the first preset depth. The semiconductor structure and method for fabricating the same of the present invention can prevent pre-pinch-off during device operation and reduce the Miller platform time.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the advancement of semiconductor technology, the ideal MOSFET (metal-oxide-semiconductor field-effect transistor) drive waveform is a square wave, indicating that when the gate-source voltage (Vgs) reaches the threshold voltage, the MOSFET rapidly enters the saturated conduction state. However, in practical applications, the gate drive process of the MOSFET presents a voltage plateau known as the Miller plateau, preventing the MOSFET from rapidly entering the saturated conduction state. Further analysis of the specific process by which the Miller plateau forms reveals that the Miller plateau occurs when the drain voltage (Vds) begins to drop when the MOSFET turns on. This causes the gate-drain capacitance (Cgd) to discharge through the MOSFET. This capacitance is then reversely charged by the drive voltage, sharing the drive current and slowing the voltage rise on the gate-source capacitance (Cgs), forming a plateau known as the Miller plateau. During the Miller plateau, the slower increase in Vgs (gate-source voltage) prevents the MOSFET from rapidly entering the saturation region, increasing energy loss during the turn-on process and reducing the switching speed of the device. Summary of the Invention

[0003] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the problem in the prior art that the Miller platform appears during the conduction process of the MOS device, which leads to large turn-on loss and reduced device switching speed.

[0004] In order to achieve the above objectives, the present invention provides a semiconductor structure, comprising:

[0005] a semiconductor substrate having a well region of a first conductivity type therein;

[0006] a source region of a second conductivity type and a drain region of a second conductivity type, wherein the source region and the drain region are located on an upper surface layer of the well region;

[0007] A gate structure is located on the upper surface of the well region, and the source region and the drain region are respectively located on both sides of the gate structure in the first direction, the gate structure includes a gate dielectric layer and a semiconductor layer stacked in sequence, and includes a first doped region of the second conductivity type and a second doped region of the first conductivity type located in the semiconductor layer, the first doped region is located on the side of the gate structure close to the drain region in the first direction, the second doped region is located on the side of the gate structure close to the source region in the first direction, the width of the first doped region in the first direction is greater than the width of the second doped region in the first direction, the first doped region is located on the upper surface of the semiconductor layer and has a first preset depth, the second doped region is located on the upper surface of the semiconductor layer and has a second preset depth, and the second preset depth is greater than the first preset depth.

[0008] In one embodiment, the first doping region is connected to the second doping region in the first direction.

[0009] In one embodiment, the first doped region extends from one end of the second doped region in the first direction to an edge of the semiconductor layer in the first direction close to the drain region.

[0010] In one embodiment, the second doping region extends away from one end of the first doping region in the first direction to an edge of the semiconductor layer in the first direction close to the source region.

[0011] In one embodiment, the second predetermined depth is smaller than the thickness of the semiconductor layer in the second direction.

[0012] In one embodiment, on a plane defined by the first direction and the second direction, a cross-sectional area of ​​the second doped region is 1 / 4 to 1 / 2 of a cross-sectional area of ​​the semiconductor layer.

[0013] In one embodiment, the first preset depth is 30% to 50% of the second preset depth.

[0014] In one embodiment, the semiconductor layer is made of polysilicon.

[0015] In one embodiment, the width of the first doping region in the first direction is 2 to 3 times the width of the second doping region in the first direction.

[0016] The present invention also provides a method for preparing a semiconductor structure, comprising the following steps:

[0017] Providing a semiconductor substrate, wherein a well region of a first conductivity type is formed in the semiconductor substrate;

[0018] forming a gate structure on the upper surface of the well region, wherein the gate structure comprises a gate dielectric layer and a semiconductor layer stacked in sequence;

[0019] Doping the upper surface layer of the semiconductor layer with first ions of the second conductivity type at a first predetermined depth to form a first doped region;

[0020] Doping the upper surface layer of the semiconductor layer with second ions of the first conductivity type at a second preset depth to form a second doped region, wherein the second preset depth is greater than the first preset depth, and the width of the first doped region in the first direction is greater than the width of the second doped region in the first direction;

[0021] A drain region of the second conductivity type and a source region of the second conductivity type are respectively formed on the upper surface layer of the well region and are located on both sides of the gate structure in the first direction, and the first doped region is located on the side of the gate structure close to the drain region in the first direction, and the second doped region is located on the side of the gate structure close to the source region in the first direction.

[0022] In one embodiment, forming the second doped region further comprises the following steps:

[0023] forming a patterned shielding layer on the upper surface of the semiconductor layer after the first ion doping;

[0024] Based on the patterned shielding layer, doping the first doping region and the semiconductor layer below the first doping region to obtain the second doping region;

[0025] The masking layer is removed.

[0026] As described above, the present invention provides a semiconductor structure and a method for preparing the same, which have the following unexpected beneficial effects: a first doping region and a second doping region with opposite conductivity types and different doping depths are provided in the semiconductor layer, thereby realizing the regulation of the performance of the gate structure. The second doping region of the first conductivity type is located on the side of the semiconductor layer close to the source region and has a second preset depth with a deeper doping depth. Therefore, by introducing additional majority carriers with a deeper doping depth, the carrier concentration in the channel can be more effectively regulated, and the second doping region with opposite conductivity types can optimize the electric field distribution of the conductive channel during the conduction process of the device, thereby suppressing the occurrence of the pre-pinch-off phenomenon and avoiding affecting the conductive performance of the device. The first doping region of the second conductivity type is located on the side close to the drain region and has a first preset depth with a shallower doping depth. Therefore, the first doped region can serve as the gate of the device, and the first doped region with a shallow doping depth will make it easier to form a depletion layer in the semiconductor layer, which is equivalent to adding a part of the potential drop area on the gate dielectric layer, which is equivalent to increasing the effective oxide thickness, reducing the parasitic capacitance between the gate and the drain, and effectively alleviating the Miller platform effect that occurs during the device conduction process, thereby reducing the device's turn-on loss and accelerating the device's switching speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor structure provided in one embodiment;

[0029] Figure 2 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0030] Figure 3 is a schematic diagram of a cross-sectional structure after a well region is formed in one embodiment;

[0031] Figure 4 is a schematic diagram of a cross-sectional structure after forming a gate dielectric layer and a semiconductor layer in one embodiment;

[0032] Figure 5 is a schematic diagram of a cross-sectional structure after doping with the first ion in one embodiment;

[0033] Figure 6 Schematic diagram of the cross-sectional structure after doping with second ions in one embodiment.

[0034] Description of reference numerals:

[0035] 1-semiconductor substrate, 11-well region, 12-isolation structure, 2-gate structure, 21-gate dielectric layer, 22-semiconductor layer, 23-first doping region, 24-second doping region, 3-source region, 4-drain region, 5-shielding layer. DETAILED DESCRIPTION

[0036] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0038] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0039] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0040] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0042] See also Figure 1The present invention provides a semiconductor structure, comprising: a semiconductor substrate 1, a gate structure 2, a source region 3 of a second conductivity type, and a drain region 4 of a second conductivity type, wherein the semiconductor substrate 1 has a well region 11 of a first conductivity type; the source region 3 and the drain region 4 are located on the upper surface layer of the well region 11; the gate structure 2 is located on the upper surface of the well region 11, and the source region 3 and the drain region 4 are located on both sides of the gate structure 2 in a first direction, respectively; the gate structure 2 includes a gate dielectric layer 21 and a semiconductor layer 22 stacked in sequence, and includes a first doped region 23 of the second conductivity type and a second doped region 24 of the first conductivity type located in the semiconductor layer 22. The first doped region 23 is located on a side of the gate structure 2 close to the drain region 4 in the first direction, the second doped region 24 is located on a side of the gate structure 2 close to the source region 3 in the first direction, the width of the first doped region 23 in the first direction is greater than the width of the second doped region 24 in the first direction, the first doped region 23 is located on the upper surface of the semiconductor layer 22 and has a first preset depth, the second doped region 24 is located on the upper surface of the semiconductor layer 22 and has a second preset depth, and the second preset depth is greater than the first preset depth (wherein the first direction is a direction perpendicular to the stacking of the gate dielectric layer 21 and the semiconductor layer 22, i.e., a horizontal direction).

[0043] In the above example, a first doping region 23 and a second doping region 24 of opposite conductivity types and different doping depths are provided in the semiconductor layer 22, thereby realizing precise control of the performance of the gate structure 2. The second doping region 24 of the first conductivity type is located on the side of the semiconductor layer 22 close to the source region 3 and has a second preset depth with a deeper doping depth. Therefore, by introducing additional majority carriers with a deeper doping depth, the carrier concentration in the channel can be more effectively controlled, and the second doping region 24 of opposite conductivity type can optimize the electric field distribution of the conductive channel during the conduction process of the device, thereby suppressing the occurrence of pre-pinch-off phenomenon and avoiding affecting the conductive performance of the device. The first doping region 23 of the second conductivity type is located on the side close to the drain region 4 and has a first preset depth with a shallower doping depth. Therefore, the first doped region 23 can serve as the gate of the device, and the first doped region 23 with a shallow doping depth makes it easier for the semiconductor layer 22 to form a depletion layer, which is equivalent to adding a part of the potential drop area on the gate dielectric layer 21, which is equivalent to increasing the effective oxide thickness, reducing the parasitic capacitance between the gate and the drain, and effectively alleviating the Miller platform effect that occurs during the device conduction process, thereby reducing the device's turn-on loss and accelerating the device's switching speed.

[0044] Specifically, the first conductivity type includes one of N-type and P-type, and the second conductivity type includes one of N-type and P-type. The first conductivity type is opposite to the second conductivity type, and the N-type dopant may be phosphorus or arsenic, and the P-type dopant may be boron. In this embodiment, the first conductivity type is P-type and the second conductivity type is N-type.

[0045] The semiconductor substrate 1 is used to provide physical support for the semiconductor structure and is the supporting platform for all other structural layers in the semiconductor structure. The material of the semiconductor substrate 1 includes silicon, germanium, carbon silicon, germanium silicon, gallium arsenide, gallium nitride, silicon on insulator or other suitable semiconductor materials. The size of the semiconductor substrate 1 can be selected according to actual conditions and is not limited here.

[0046] Specifically, an isolation structure 12 is formed in the semiconductor substrate 1. This structure isolates the semiconductor substrate 1 into multiple well regions 11. Isolation structures 12 ensure electrical isolation between devices, preventing current leakage and interference between devices, and are crucial for improving circuit stability and reliability. Well regions 11 are regions within the device that conduct and control current, and their specific locations are primarily defined by isolation structures 12.

[0047] The gate dielectric layer 21 provides the necessary insulation and capacitance, while the semiconductor layer 22 controls channel formation and current flow. The gate dielectric layer 21 can be made of silicon dioxide, silicon oxynitride, or other suitable materials; the semiconductor layer 22 can be made of polysilicon or other suitable materials. Using polysilicon as the semiconductor layer 22 facilitates the subsequent formation of the first doped region 23 and the second doped region 24 within the semiconductor layer 22, while also being suitable for subsequent high-temperature processes and improving device fabrication precision.

[0048] The source region 3 and drain region 4 work together with the gate structure 2 to control the device's on and off. Both the source region 3 and the drain region 4 are heavily doped regions. The doping concentrations of the source region 3 and the drain region 4 can be selected based on actual conditions, provided that the performance of the semiconductor structure is met, and are not limited here.

[0049] The Miller platform effect occurs because the driving current begins to reversely charge the gate-drain capacitance, but the gate-source voltage does not increase. Therefore, if you want to reduce the time of the Miller platform, you can do so by reducing the gate-drain capacitance. According to the capacitance formula , where ε is the dielectric constant, S is the area, and d is the thickness of the dielectric layer, that is, the effective oxide thickness. The gate-drain capacitance can be reduced by increasing the effective oxide thickness. Therefore, the first doped region 23 of the second conductivity type is located on the upper surface of the semiconductor layer 22 and has a first preset depth with a relatively shallow doping depth. The first doped region 23 can serve as the device gate to form a conductive channel during the device conduction process. The first doped region with a relatively shallow doping depth makes it easier for the semiconductor layer 22 to form a depletion layer, which is equivalent to adding a portion of the potential drop area on the gate dielectric layer 21, which is equivalent to increasing the effective oxide thickness, reducing the parasitic capacitance between the gate and the drain, and effectively alleviating the Miller platform effect that occurs during the device conduction process, thereby reducing the turn-on loss of the device and accelerating the switching speed of the device.

[0050] Among them, the first doped region 23 is a heavily doped region. While meeting the performance of the semiconductor structure, the doping concentration of the first doped region 23 can be selected according to actual conditions and is not limited here; the value of the first preset depth can be selected according to actual conditions and is not limited here.

[0051] Specifically, the second doped region 24 of the first conductivity type is located on a side of the semiconductor layer 22 near the source region 3 and has a second, deeper, predetermined depth. Therefore, by introducing additional majority carriers with a deeper doping depth, the carrier concentration in the channel can be more effectively regulated. Furthermore, the second doped region 24 of the opposite conductivity type can optimize the electric field distribution in the conductive channel during device conduction, thereby suppressing the occurrence of pre-pinch-off and avoiding affecting the conductive performance of the device.

[0052] Therefore, by providing the first doping region 23 and the second doping region 24 with opposite conductivity types and different doping depths in the semiconductor layer 22 , precise control of the performance of the gate structure 2 is achieved.

[0053] Among them, the second doped region 24 is a heavily doped region. While meeting the performance of the semiconductor structure, the doping concentration of the second doped region 24 can be selected according to actual conditions and is not limited here; the value of the second preset depth can be selected according to actual conditions and is not limited here.

[0054] At the same time, the second preset depth is less than the thickness of the semiconductor layer 22 in the second direction (wherein the second direction is perpendicular to the first direction), that is, by setting the second doping region 24 not to penetrate the semiconductor layer 22 and the gate dielectric layer 21, the impact on the gate dielectric layer 21 and the semiconductor substrate 1 during the manufacturing process is reduced, and the control capability of the gate structure 2 is optimized.

[0055] In some embodiments, the first doping region 23 and the second doping region 24 are connected in the first direction. By setting the first doping region 23 and the second doping region 24 to be connected in the first direction, the difficulty of manufacturing the first doping region 23 and the second doping region 24 can be effectively reduced while ensuring the performance of the gate structure 2. In particular, while ensuring the performance of the gate structure 2, the first doping region 23 and the second doping region 24 can also be spaced apart and can be set according to actual conditions to meet flexible structural design requirements.

[0056] In some embodiments, on the plane determined by the first direction and the second direction, the cross-sectional area of ​​the second doping region 24 is 1 / 4 to 1 / 2 of the cross-sectional area of ​​the semiconductor layer 22. Exemplarily, the cross-sectional area of ​​the second doping region 24 is 1 / 3 of the cross-sectional area of ​​the semiconductor layer 22. That is, by precisely controlling the distribution area of ​​the second doping region 24 in the semiconductor layer 22, precise control of the threshold voltage and the working area of ​​the device is achieved, thereby further enhancing the control capability of the gate structure 2 over the channel carriers and enhancing the device performance.

[0057] In some embodiments, the first predetermined depth is 30% to 50% of the second predetermined depth. By setting the first predetermined depth to 30% to 50% of the second predetermined depth, the doping depths of the first doping region 23 and the second doping region 24 are further precisely controlled, thereby further optimizing the precise control of the performance of the semiconductor layer 22 by the first doping region 23 and the second doping region 24, thereby ensuring optimal device performance.

[0058] In some embodiments, the first doped region 23 extends from one end of the second doped region 24 in the first direction to an edge of the semiconductor layer 22 in the first direction that is close to the drain region 4. By arranging the first doped region 23 as close as possible to the drain region 4, it is possible to ensure that the first doped region 23 effectively controls the gate structure 2 and effectively alleviate the Miller plateau effect.

[0059] In other embodiments, an end of the first doped region 23 in the first direction away from the second doped region 24 is spaced a first preset distance from an edge of the semiconductor layer 22 in the first direction close to the drain region 4. While satisfying the performance of the gate structure 2, the first doped region 23 may also be configured such that an end of the first doped region 23 in the first direction away from the second doped region 24 is spaced a first preset distance from an edge of the semiconductor layer 22 in the first direction close to the drain region 4 to meet flexible structural design requirements.

[0060] In some embodiments, the second doped region 24 extends from one end of the first doped region 23 in the first direction to an edge of the semiconductor layer 22 in the first direction that is close to the source region 3. By arranging the second doped region 24 as close as possible to the source region 3, it is possible to ensure that the second doped region 24 effectively controls the gate structure 2, effectively preventing pre-pinch-off.

[0061] In some embodiments, an end of the second doping region 24 in the first direction away from the first doping region 23 is spaced a second preset distance from an edge of the semiconductor layer 22 in the first direction close to the source region 3. While satisfying the performance of the gate structure 2, the second doping region 24 may also be configured such that an end of the second doping region 24 in the first direction away from the first doping region 23 is spaced a second preset distance from an edge of the semiconductor layer 22 in the first direction close to the source region 3 to meet flexible structural design requirements.

[0062] In some embodiments, the width of the first doping region 23 in the first direction is 2 to 3 times the width of the second doping region 24 in the first direction, wherein the first doping region 23 is used to reduce the parasitic capacitance of the semiconductor layer 22 itself. By further setting the width of the first doping region 23 in the first direction to be 2 to 3 times the width of the second doping region 24, the charge distribution range can be effectively expanded and the charge density per unit area can be reduced, so as to effectively achieve the goal of reducing the parasitic capacitance. At the same time, it can avoid the second doping region 24 being too wide, resulting in a significant increase in the threshold voltage of the entire semiconductor device, which in turn makes the device difficult to turn on and affects the normal working performance of the device.

[0063] Specifically, a source metal layer (not shown), a drain metal layer (not shown), and a gate metal layer (not shown) are formed on the upper surfaces of the source region 3, the drain region 4, and the semiconductor layer 22, respectively. A back electrode (not shown) is also formed on the lower surface of the semiconductor substrate 1. The source metal layer, the drain metal layer, the gate metal layer, and the back electrode are used to ensure that the semiconductor device can effectively connect to external circuits. While meeting the performance requirements of the semiconductor structure, the materials of the source metal layer, the drain metal layer, the gate metal layer, and the back electrode can be selected based on actual conditions and are not limited here.

[0064] See also Figure 2 The present invention also provides a method for preparing a semiconductor structure. Figure 2 The method for manufacturing the semiconductor structure shown is applicable to Figure 1 The semiconductor structure shown includes the following steps:

[0065] S1: providing a semiconductor substrate 1, wherein a well region 11 of a first conductivity type is formed in the semiconductor substrate 1;

[0066] S2: forming a gate structure 2 on the upper surface of the well region 11 , wherein the gate structure 2 includes a gate dielectric layer 21 and a semiconductor layer 22 stacked in sequence;

[0067] S3: doping the upper surface layer of the semiconductor layer 22 with first ions of the second conductivity type at a first predetermined depth to form a first doped region 23;

[0068] S4: doping the upper surface layer of the semiconductor layer 22 with second ions of the second conductivity type to a second predetermined depth to form a second doping region 24, wherein the second predetermined depth is greater than the first predetermined depth, and the width of the first doping region 23 in the first direction is greater than the width of the second doping region 24 in the first direction;

[0069] S5: A drain region 4 of the second conductivity type and a source region 3 of the second conductivity type are respectively formed on the upper surface layer of the well region 11 and are located on both sides of the gate structure 2 in the first direction, and the first doped region 23 is located on the side of the gate structure 2 close to the drain region 4 in the first direction, and the second doped region 24 is located on the side of the gate structure 2 close to the source region 3 in the first direction.

[0070] See also Figure 3 , performing step S1, providing a semiconductor substrate 1, wherein a well region 11 of a first conductivity type is formed in the semiconductor substrate 1.

[0071] In some embodiments, step S1 further includes steps S11 and S12, and forming the isolation structure 12 and the well region 11 includes the following steps:

[0072] S11: A semiconductor substrate 1 is provided, and a plurality of spaced trenches are formed in the semiconductor substrate 1. The trenches open from the upper surface of the semiconductor substrate 1 and have bottoms spaced from the lower surface of the semiconductor substrate 1. The trenches can be formed by dry etching, wet etching, or other suitable methods. The depth and number of the trenches can be selected based on actual conditions and are not limited herein.

[0073] S12: forming an isolation layer filling the trench to obtain an isolation structure 12, and the semiconductor substrate 1 between two adjacent isolation structures 12 is defined as a well region 11. Methods for forming the isolation layer include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0074] See also Figure 4 , performing step S2 to form a gate structure 2 on the upper surface of the well region 11 , the gate structure 2 including a gate dielectric layer 21 and a semiconductor layer 22 stacked in sequence.

[0075] In some embodiments, step S2 further includes steps S21 and S22 , and forming the gate dielectric layer 21 and the semiconductor layer 22 on the upper surface of the well region 11 includes the following steps:

[0076] S21: A gate dielectric material layer (not shown) and a semiconductor material layer (not shown) are formed above the well region 11, covering the upper surface of the well region 11 and stacked in sequence. The gate dielectric material layer and the semiconductor material layer are basic material layers for forming the gate dielectric layer 21 and the semiconductor layer 22. The method for forming the gate dielectric material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods; the method for forming the semiconductor material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods; the use of chemical vapor deposition or physical vapor deposition can control the thickness and uniformity of the formed gate dielectric material layer and semiconductor material layer, which helps to achieve the production of high-performance and high-reliability devices. The thickness of the formed gate dielectric material layer can be selected according to actual conditions and is not limited here; the thickness of the formed semiconductor material layer can be selected according to actual conditions and is not limited here. It is generally set to be that the thickness of the gate dielectric material layer is less than the thickness of the semiconductor material layer.

[0077] S22: Etching the gate oxide material layer and the gate material layer to obtain a semiconductor layer 22 and a gate dielectric layer 21 stacked in sequence, wherein the semiconductor layer 22 and the gate dielectric layer 21 constitute a gate structure 2. The etching method for the gate oxide material layer and the semiconductor material layer includes dry etching, wet etching, or other suitable etching methods. The desired etching method can be selected according to actual conditions to obtain the desired gate structure 2.

[0078] See also Figure 5 , executing step S3 , doping the upper surface layer of the semiconductor layer 22 with the first ions of the second conductivity type at a first preset depth to form a first doping region 23 .

[0079] Exemplarily, the method for doping the surface layer of the semiconductor layer 22 with the first ions includes ion implantation. By doping the first ions through ion implantation, the implantation energy and implantation concentration can be precisely controlled, thereby achieving precise regulation of the first predetermined depth and the doping region, and enabling precise regulation of the performance of the semiconductor layer 22 by the first doping region 23 to achieve optimal device performance. For example, the first ions can be doped throughout the semiconductor layer 22, or in specific regions of the semiconductor layer 22, depending on the actual situation. The first ions include phosphorus, arsenic, antimony, or other suitable ions of the first conductivity type.

[0080] In addition, by forming the first doping region 23 by an ion implantation method and by regulating the injection energy and the injection area during the ion implantation, the edge position of the first doping region 23 in the first direction can also be regulated. For example, the first doping region 23 extends from one end of the second doping region 24 in the first direction to the edge of the semiconductor layer 22 in the first direction close to the drain region 4, or the first doping region 23 extends from one end of the second doping region 24 in the first direction to the edge of the semiconductor layer 22 in the first direction close to the drain region 4 by a first preset distance, so as to achieve a more flexible structural design.

[0081] See also Figure 6 , execute steps S4-S5, perform doping of second ions of the second conductivity type at a second preset depth on the upper surface layer of the semiconductor layer 22 to form a second doping region 24, the second preset depth is greater than the first preset depth, and the width of the first doping region 23 in the first direction is greater than the width of the second doping region 24 in the first direction; and form a drain region 4 of the second conductivity type and a source region 3 of the second conductivity type on both sides of the gate structure 2 in the first direction on the upper surface layer of the well region 11, and the first doping region 23 is located on the side of the gate structure 2 close to the drain region 4 in the first direction, and the second doping region 24 is located on the side of the gate structure 2 close to the source region 3 in the first direction.

[0082] In some embodiments, step S4 further includes steps S41 to S43, and forming the second doping region 24 further includes the following steps:

[0083] S41: A patterned shielding layer 5 (not shown) is formed on the upper surface of the semiconductor layer 22 after the first ion doping. The shielding layer 5 is used to restrict the formation of the second doped region 24 to specific areas to avoid affecting subsequent process steps. The shielding layer 5 includes a photoresist or other suitable shielding material.

[0084] S42: Based on the patterned shielding layer 5, the first doping region 23 and the semiconductor layer 22 below the first doping region 23 are doped to obtain the second doping region 24. When doping the first doping region 23 and the semiconductor layer 22 below the first doping region 23, the first ion is doped on the entire surface of the semiconductor layer 22, and then the first doping region 23 and the semiconductor layer 22 below the first doping region 23 are doped. This achieves the effective production of the first doping region 23 and the second doping region 24 while simplifying the preparation process. The method of doping the surface layer of the semiconductor layer 22 with the second ion includes an ion implantation method. By doping the second ion with the ion implantation method, the implantation energy and implantation concentration can be controlled to achieve precise control of the depth and regional distribution of the second doping region 24, and to achieve precise control of the performance of the semiconductor layer 22 to achieve optimal device performance. Exemplarily, the ion implantation method used when doping the second ion is high-dose ion implantation, which can quickly and accurately form a deeper doping region of the second doping region 24. The second ion includes boron or other suitable ions of the second conductivity type.

[0085] In addition, by forming the second doping region 24 by an ion implantation method and by regulating the injection energy and the injection area during ion implantation, the edge position of the second doping region 24 in the first direction can also be regulated. For example, the second doping region 24 extends from one end of the first doping region 23 in the first direction to the edge of the semiconductor layer 22 in the first direction close to the source region 3, or the second doping region 24 extends from one end of the first doping region 23 in the first direction to the edge of the semiconductor layer 22 in the first direction close to the source region 3 by a first preset distance, so as to achieve a more flexible structural design.

[0086] S43: removing the shielding layer 5. Removing the shielding layer 5 can ensure that the subsequent process is not affected, and removing the shielding layer 5 is a conventional technical means, which will not be described in detail here.

[0087] Specifically, the method for forming the source region 3 includes ion implantation or other suitable methods; the method for forming the drain region 4 includes ion implantation or other suitable methods. While satisfying the performance of the semiconductor structure, the implantation energy and implantation concentration of the source region 3 and the drain region 4 using the ion implantation method can be selected based on actual conditions and are not limited herein. Exemplarily, the ion implantation method used to form the source region 3 and the drain region 4 is high-dose ion implantation, which can quickly and accurately form precise doped regions of the source region 3 and the drain region 4.

[0088] In some embodiments, the method for preparing a semiconductor structure further includes the following steps S6-S7:

[0089] S6: Annealing the semiconductor substrate 1 after forming the source region 3 and the drain region 4, and the semiconductor layer 22 after forming the first doped region 23 and the second doped region 24. The annealing process can repair the lattice loss of the semiconductor substrate 1 and the semiconductor layer 22 caused by the ion implantation process and activate the doped ions. Specifically, a rapid thermal annealing process can be used to anneal the semiconductor substrate 1 and the semiconductor layer 22 after the ion implantation. Compared with conventional annealing processes, the rapid thermal annealing process has a shorter annealing time, can avoid the diffusion of doped ions caused by prolonged high temperature, and can reduce the instantaneous enhanced diffusion of doped ions.

[0090] S7: Forming a source metal layer (not shown), a drain metal layer, and a gate metal layer on the source region 3, the drain region 4, and the upper surface of the semiconductor layer 22, respectively, and forming a back electrode on the lower surface of the semiconductor substrate 1. The method for forming the source metal layer includes chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for forming the drain metal layer includes chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for forming the gate metal layer includes chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for forming the back electrode includes electroplating, physical vapor deposition, or other suitable methods. The use of chemical vapor deposition or physical vapor deposition can control the thickness and uniformity of the formed metal layer, which helps to achieve the production of high-performance and high-reliability devices.

[0091] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 2 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0092] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0093] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: a semiconductor substrate having a well region of a first conductivity type therein; a source region of a second conductivity type and a drain region of a second conductivity type, wherein the source region and the drain region are located on an upper surface layer of the well region; A gate structure is located on the upper surface of the well region, and the source region and the drain region are respectively located on both sides of the gate structure in the first direction. The gate structure includes a gate dielectric layer and a semiconductor layer stacked in sequence, and includes a first doped region of the second conductivity type and a second doped region of the first conductivity type located in the semiconductor layer. The first doped region is located on a side of the gate structure close to the drain region in the first direction, and the second doped region is located on a side of the gate structure close to the source region in the first direction. The width of the first doped region in the first direction is greater than the width of the second doped region in the first direction. The first doped region is located on the upper surface of the semiconductor layer and has a first preset depth. The second doped region is located on the upper surface of the semiconductor layer and has a second preset depth. The second preset depth is greater than the first preset depth. In a plane determined by the first direction and the second direction, the cross-sectional area of ​​the second doped region is 1 / 4 to 1 / 2 of the cross-sectional area of ​​the semiconductor layer, and the second direction is perpendicular to the first direction.

2. The semiconductor structure according to claim 1, wherein: The first doping region is connected to the second doping region in the first direction.

3. The semiconductor structure according to claim 1, wherein: The first doping region extends from one end of the second doping region in the first direction to an edge of the semiconductor layer in the first direction close to the drain region.

4. The semiconductor structure according to claim 1, wherein: The second doping region extends away from one end of the first doping region in the first direction to an edge of the semiconductor layer in the first direction close to the source region.

5. The semiconductor structure according to claim 1, wherein: The second preset depth is smaller than the thickness of the semiconductor layer in the second direction. The semiconductor structure according to claim 1 , wherein: The first preset depth is 30% to 50% of the second preset depth.

7. The semiconductor structure according to claim 1, wherein: The width of the first doping region in the first direction is 2 to 3 times the width of the second doping region in the first direction.

8. The semiconductor structure according to claim 1, wherein: The semiconductor layer is made of polysilicon.

9. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a semiconductor substrate, wherein a well region of a first conductivity type is formed in the semiconductor substrate; forming a gate structure on the upper surface of the well region, wherein the gate structure comprises a gate dielectric layer and a semiconductor layer stacked in sequence; Doping the upper surface layer of the semiconductor layer with first ions of the second conductivity type at a first predetermined depth to form a first doped region; Doping the upper surface layer of the semiconductor layer with second ions of the first conductivity type at a second preset depth to form a second doped region, wherein the second preset depth is greater than the first preset depth, and the width of the first doped region in the first direction is greater than the width of the second doped region in the first direction; A drain region of the second conductivity type and a source region of the second conductivity type are respectively formed on the upper surface layer of the well region and are located on both sides of the gate structure in the first direction, and the first doped region is located on the side of the gate structure close to the drain region in the first direction, and the second doped region is located on the side of the gate structure close to the source region in the first direction. On the plane determined by the first direction and the second direction, the cross-sectional area of ​​the second doped region is 1 / 4 to 1 / 2 of the cross-sectional area of ​​the semiconductor layer, and the second direction is perpendicular to the first direction.

10. The method for preparing a semiconductor structure according to claim 9, wherein: Forming the second doped region further includes the following steps: forming a patterned shielding layer on the upper surface of the semiconductor layer after the first ion doping; Based on the patterned shielding layer, doping the first doping region and the semiconductor layer below the first doping region to obtain the second doping region; The masking layer is removed.

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