SONOS device and preparation method thereof
By growing the silicon hafnium dipole layer on the surface of the storage layer of the SONOS device, the problem of insufficient data retention capability of SONOS devices in the prior art is solved, and more efficient charge storage and lower operating voltage are achieved.
Patent Information
- Application Number
- CN202510266274.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-06
- Publication Date
- 2025-06-06
AI Technical Summary
The existing SONOS devices lack data retention capabilities in high temperature scenarios and have high operating voltages, which affects the performance of the memory.
Grow a silicon hafnium dipole layer on the surface of the storage layer to improve quantum tunneling efficiency during programming and erasing, and maintain polarity after the external electric field is removed, improving the stability of charge storage.
Improves the data retention capability of SONOS devices, reduces operating voltage, and improves memory performance and reliability.
Smart Images
Figure CN120111945A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductor manufacturing and relates to a SONOS device and a preparation method thereof. Background Art
[0002] Semiconductor memories include volatile memories and non-volatile memories. Among them, since the data in volatile memories are easily lost when the power is interrupted, while the data in non-volatile memories will be retained even when the power is interrupted, non-volatile memories are widely used in electronic products such as mobile communications, memory cards, and computers.
[0003] SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) devices are charge-capture type non-volatile memories that use a dual-transistor structure (2T, a storage tube and a selection tube). SONOS devices control the "on" or "off" of transistors by capturing and releasing charges in traps in the silicon nitride layer, thereby representing the two storage states of "1" and "0". Among them, the programming of SONOS is: applying a positive voltage to the gate, holes are injected into silicon nitride, electrons are injected into silicon nitride from the inversion region, and after silicon nitride stores negative charges, the threshold voltage increases and the transistor is "turned off". The erasing of SONOS is: applying a negative voltage to the gate, holes are injected into silicon nitride from the accumulation region, silicon nitride stores positive charges, the threshold voltage decreases, and the transistor is "turned on".
[0004] The traditional SONOS process uses defects in the silicon nitride trap layer to achieve programming and erasing operations under the action of high electric fields. It is widely used in consumer electronic storage modules. However, with the widespread use of devices in high-temperature scenarios, the shallow energy level trap decay in silicon nitride is very obvious, so it is very important to optimize the device structure to reduce the operating voltage and improve the data retention ability of the memory.
[0005] Therefore, it is necessary to provide a SONOS device and a method for preparing the same. Summary of the invention
[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a SONOS device and a method for manufacturing the same, so as to solve the problem of data retention capability of the memory in the prior art.
[0007] To achieve the above objectives and other related objectives, the present invention provides a SONOS device, the SONOS device comprising:
[0008] Semiconductor substrate;
[0009] A storage structure, the storage structure is located on the surface of the semiconductor substrate, including a tunneling dielectric layer, a storage layer located on the surface of the tunneling dielectric layer, a hafnium silicon oxide dipole layer located on the surface of the storage layer, and a top dielectric layer located on the surface of the hafnium silicon oxide dipole layer;
[0010] A gate electrode layer is located on the surface of the storage structure.
[0011] Optionally, the thickness of the hafnium silicon oxide dipole layer is
[0012] Optionally, a titanium nitride barrier layer is further included between the top dielectric layer and the hafnium silicon oxide dipole layer.
[0013] The present invention also provides a method for preparing a SONOS device, comprising the following steps:
[0014] providing a semiconductor substrate;
[0015] Forming a storage structure on the surface of the semiconductor substrate, wherein the step of forming the storage structure includes forming a tunnel dielectric layer, forming a storage layer on the surface of the tunnel dielectric layer, forming a silicon hafnium oxide dipole layer on the surface of the storage layer, and forming a top dielectric layer on the surface of the silicon hafnium oxide dipole layer;
[0016] A gate electrode layer is formed on the surface of the storage structure.
[0017] Optionally, the step of forming the hafnium silicon oxide dipole layer comprises:
[0018] forming a silicon oxide layer on the surface of the storage layer;
[0019] forming a hafnium oxide layer on the surface of the silicon oxide bottom layer;
[0020] An annealing process is performed to form the hafnium silicon oxide dipole layer on the surface of the tunnel dielectric layer.
[0021] Optionally, the temperature range of the annealing process is 900°C to 1100°C.
[0022] Optionally, the annealing process is performed in an atmosphere of oxygen or nitric oxide.
[0023] Optionally, between the step of forming the hafnium oxide layer and the step of performing the annealing process, a step of forming a titanium nitride barrier layer on the surface of the hafnium oxide layer is further included.
[0024] Optionally, the thickness of the silicon oxide layer is The thickness of the hafnium oxide layer is The thickness of the titanium nitride barrier layer is
[0025] Optionally, the thickness of the formed hafnium silicon oxide dipole layer is
[0026] As described above, the SONOS device and the preparation method thereof of the present invention, the SONOS device includes a semiconductor substrate, a storage structure and a gate electrode layer, wherein the storage structure includes a tunneling dielectric layer, a storage layer, a hafnium silicon oxide dipole layer and a top dielectric layer.
[0027] The invention can improve the quantum tunneling efficiency in the programming and erasing process by growing a hafnium silicon oxide dipole layer on the surface of the storage layer. After the external electric field is removed, the hafnium silicon oxide dipole layer still maintains polarity, making it easier to store charges in the storage layer, thereby improving the data retention capability of the SONOS device. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 It shows the structure of a SONOS device in a comparative example of the present invention.
[0029] Figure 2 Shown is a schematic diagram of the process flow of preparing a SONOS device in an embodiment of the present invention.
[0030] Figure 3 It is a schematic diagram of the structure after forming a silicon oxide tunneling dielectric layer in an embodiment of the present invention.
[0031] Figure 4 It is a schematic diagram of the structure after forming a silicon nitride storage layer in an embodiment of the present invention.
[0032] Figure 5 It is a schematic diagram of the structure after forming a hafnium silicon oxide dipole layer and a titanium nitride barrier layer in an embodiment of the present invention.
[0033] Figure 6 It is a schematic diagram of the structure after forming a silicon oxide dielectric layer in an embodiment of the present invention.
[0034] Figure 7 It is a schematic diagram of the structure after forming a polysilicon gate electrode layer in an embodiment of the present invention.
[0035] Figure 8 The figure shows a comparison of data retention performance of a SONOS device with a hafnium silicon oxide dipole layer and a SONOS device without a hafnium silicon oxide dipole layer according to an embodiment of the present invention.
[0036] Description of Reference Numerals
[0037] 110 Semiconductor Substrate
[0038] 210 ONO laminated structure
[0039] 211 Tunneling dielectric layer
[0040] 212 Captured Charge Layer
[0041] 213 Top dielectric layer
[0042] 310 gate electrode layer
[0043] 100 Silicon substrate
[0044] 200 Storage Structure
[0045] 201 Silicon oxide tunneling dielectric layer
[0046] 202 Silicon nitride storage layer
[0047] 203 Hafnium Silicon Oxide Dipole Layer
[0048] 204 Titanium Nitride Barrier Layer
[0049] 205 Silicon oxide dielectric layer
[0050] 300 Polysilicon gate electrode layer DETAILED DESCRIPTION
[0051] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0052] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.
[0053] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.
[0054] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0055] Comparative Example
[0056] like Figure 1 This comparative example provides a SONOS device, which mainly includes: a semiconductor substrate 110, a tunneling dielectric layer 211 located on the surface of the semiconductor substrate 110, a charge trapping layer 212 located on the surface of the tunneling dielectric layer 211, a top dielectric layer 213 located on the surface of the charge trapping layer 212, and a gate electrode layer 310 located on the surface of the top dielectric layer 213. The material of the tunneling dielectric layer 211 is silicon oxide, the material of the charge trapping layer 212 is silicon nitride, the material of the top dielectric layer 213 is silicon oxide, the material of the gate electrode layer 310 is polysilicon, and the tunneling dielectric layer 211, the charge trapping layer 212 and the top dielectric layer 213 constitute an ONO (oxide-nitride-oxide) stacked structure 210.
[0057] Example
[0058] like Figure 2 This embodiment provides a method for preparing a SONOS device, comprising the following steps:
[0059] S1, providing a semiconductor substrate;
[0060] S2, forming a storage structure on the surface of the semiconductor substrate, wherein the steps of forming the storage structure include forming a tunnel dielectric layer, forming a storage layer on the surface of the tunnel dielectric layer, and forming hafnium silicon oxide (HfSiO 4 ) a dipole layer, and forming a top dielectric layer on the surface of the hafnium silicon oxide dipole layer;
[0061] S3, forming a gate electrode layer on the surface of the storage structure.
[0062] In this embodiment, by growing the hafnium silicon oxide dipole layer on the surface of the storage layer, the quantum tunneling efficiency during programming and erasing can be improved. After the external electric field is removed, the hafnium silicon oxide dipole layer still maintains polarity, making it easier to store charges in the storage layer, thereby improving the data retention capability of the SONOS device.
[0063] Specifically, Figure 8As shown in the figure, after baking at 125°C for 150 hours, the programming threshold voltage (Program Vt) of the structure without the hafnium silicon oxide dipole layer in the comparative example is reduced by about 30%, while the programming threshold voltage of the structure with the hafnium silicon oxide dipole layer in this embodiment is reduced by only 10%. Therefore, the presence of the hafnium silicon oxide dipole layer can significantly improve the data retention performance of the SONOS device.
[0064] The following is in conjunction with the instruction manual Figure 2 to Figure 7 , further introducing the preparation of the SONOS device.
[0065] First, see Figure 2 and Figure 3 , execute step S1, provide a semiconductor substrate.
[0066] Specifically, in this embodiment, the semiconductor substrate adopts a silicon substrate 100, but the type of the semiconductor substrate is not limited thereto. As needed, the semiconductor substrate may also include a silicon carbide substrate or a III-V compound substrate, or the semiconductor substrate may also adopt a silicon on insulator (SOI) substrate.
[0067] Next, see Figure 2 and Figure 3 to Figure 6 , executing step S2, forming a storage structure 200 on the surface of the semiconductor substrate, wherein the steps of forming the storage structure 200 include:
[0068] forming a tunneling dielectric layer;
[0069] forming a storage layer on the surface of the tunnel dielectric layer;
[0070] forming a hafnium silicon oxide dipole layer 203 on the surface of the storage layer;
[0071] A top dielectric layer is formed on the surface of the hafnium silicon oxide dipole layer 203 .
[0072] Among them, see Figure 3 , the tunnel dielectric layer is formed on the surface of the semiconductor substrate first, and the tunnel dielectric layer is used to isolate the semiconductor substrate and the storage layer.
[0073] In this embodiment, the tunnel dielectric layer is a silicon oxide tunnel dielectric layer 201, and the formation method may include an in-situ steam generation (ISSG) process, but the type of the tunnel dielectric layer is not limited thereto, and may also be an aluminum oxide tunnel dielectric layer or a hafnium oxide tunnel dielectric layer. The thickness of the silicon oxide tunnel dielectric layer 201 may include, for example, wait.
[0074] Then, see Figure 4 , forming the storage layer on the surface of the tunneling dielectric layer, wherein the storage layer is used to capture electrons and complete the electron tunneling programming operation.
[0075] In this embodiment, the storage layer is a silicon nitride storage layer 202, and the preparation method is a deposition method, but the type of the storage layer is not limited thereto, and may also be a polysilicon storage layer or a germanium storage layer. The thickness of the silicon nitride storage layer 202 may include wait.
[0076] Then, see Figure 5 The hafnium silicon oxide dipole layer 203 is formed on the surface of the storage layer. The hafnium silicon oxide dipole layer 203 can reduce the power supply voltage required for quantum tunneling. When the external electric field is removed, the residual electric field of the hafnium silicon oxide dipole layer 203 will retain the polarity, so that the charge can be more stably retained in the storage layer, which is beneficial to the reliability of memory data retention. The hafnium silicon oxide dipole layer 203 is formed to enhance the ability of the storage layer to capture electrons, thereby enhancing the performance of the storage device.
[0077] As an example, the step of forming the hafnium silicon oxide dipole layer 203 may include:
[0078] forming a silicon oxide layer (not shown) on the surface of the storage layer;
[0079] forming a hafnium oxide layer (not shown) on the surface of the silicon oxide bottom layer;
[0080] An annealing process is performed to form the hafnium silicon oxide dipole layer 203 on the surface of the tunnel dielectric layer.
[0081] The silicon oxide layer can be grown on the silicon nitride storage layer 202 by consuming silicon nitride using an ISSG process, and then the high dielectric hafnium oxide layer is deposited. The temperature range of the annealing process can be 900°C to 1100°C, such as 900°C, 950°C, 1000°C, 1050°C, 1100°C, etc. The silicon oxide layer can react with the hafnium oxide layer through high temperature annealing to prepare the silicon hafnium oxide dipole layer 203.
[0082] Among them, it is preferred that the annealing process is carried out in an atmosphere of oxygen or nitric oxide to perform oxidation treatment to further optimize the interface characteristics.
[0083] Further, such as Figure 5Between the step of forming the hafnium oxide layer and the step of performing the annealing process, a step of forming a titanium nitride barrier layer 204 on the surface of the hafnium oxide layer by a deposition method may be further included.
[0084] The titanium nitride barrier layer 204 can act as a diffusion barrier at high temperatures to block oxygen distribution and diffusion of metal ions, which is crucial to the work function of the hafnium silicon oxide dipole layer 203 and can effectively avoid the shift of the device programming threshold voltage and the decrease of reliability.
[0085] In this embodiment, after the hafnium oxide layer is formed, the titanium nitride barrier layer 204 is formed on the surface of the hafnium oxide layer, and the preparation of the hafnium silicon oxide dipole layer 203 and the titanium nitride barrier layer 204 can be completed based on a single high-temperature annealing process, which can improve the adhesion of the titanium nitride barrier layer 204 and reduce interface defects.
[0086] Wherein, the thickness of the silicon oxide layer can be like etc.; the thickness of the hafnium oxide layer may be like The thickness of the titanium nitride barrier layer 204 may be like The thickness of the formed hafnium silicon oxide dipole layer 203 may be like wait.
[0087] Then, see Figure 6 , a top dielectric layer is formed on the surface of the hafnium silicon oxide dipole layer 203. In this embodiment, due to the presence of the titanium nitride barrier layer 204, the top dielectric layer is formed on the surface of the titanium nitride barrier layer 204 by a deposition method. The top dielectric layer is used to isolate the gate electrode layer and the storage structure 200. In this embodiment, the top dielectric layer is a silicon oxide dielectric layer 205, but it is not limited thereto. The top dielectric layer may also be an aluminum oxide dielectric layer or a hafnium oxide dielectric layer. The thickness of the silicon oxide dielectric layer 205 may be like wait.
[0088] Next, see Figure 2 and Figure 7 , executing step S3 to form a gate electrode layer on the surface of the storage structure 200 .
[0089] Specifically, the gate electrode layer in this embodiment adopts a polysilicon gate electrode layer 300, and the preparation method may include a deposition method, but the type of the gate electrode layer is not limited thereto. The gate electrode layer may also include a tungsten metal gate electrode layer, a copper metal gate electrode layer, a silver metal gate electrode layer, etc.
[0090] See also Figure 3 to Figure 7 This embodiment further provides a SONOS device, wherein the SONOS device can be prepared using the above-mentioned preparation process, but is not limited thereto. In this embodiment, the above-mentioned process is directly used to prepare the SONOS device. Therefore, the specific preparation process, material, etc. of the SONOS device are not described in detail herein.
[0091] Wherein, the SONOS device comprises:
[0092] Semiconductor substrate;
[0093] A storage structure 200, the storage structure 200 is located on the surface of the semiconductor substrate, including a tunneling dielectric layer, a storage layer located on the surface of the tunneling dielectric layer, a hafnium silicon oxide dipole layer 203 located on the surface of the storage layer, and a top dielectric layer located on the surface of the hafnium silicon oxide dipole layer 203;
[0094] A gate electrode layer, wherein the gate electrode layer is located on a surface of the storage structure 200 .
[0095] Specifically, in this embodiment, the semiconductor substrate is a silicon substrate 100; the tunnel dielectric layer is a silicon oxide tunnel dielectric layer 201, and the thickness of the silicon oxide tunnel dielectric layer 201 may include: The storage layer is a silicon nitride storage layer 202, and the thickness of the silicon nitride storage layer 202 may include like The top dielectric layer is a silicon oxide dielectric layer 205, and the thickness of the silicon oxide dielectric layer 205 can be like The gate electrode layer is a polysilicon gate electrode layer 300. The selection of the specific material, thickness, etc. of the semiconductor substrate, the storage structure 200 and the gate electrode layer is not excessively limited here.
[0096] As an example, the thickness of the hafnium silicon oxide dipole layer 203 may be like wait.
[0097] Specifically, the hafnium silicon oxide dipole layer 203 can reduce the power supply voltage required for quantum tunneling. When the external electric field is removed, the residual electric field of the hafnium silicon oxide dipole layer 203 will retain its polarity, so that the charge can be more stably retained in the storage layer, which is beneficial to the reliability of memory data retention. The hafnium silicon oxide dipole layer 203 formed can improve the ability of the storage layer to capture electrons, thereby improving the performance of the storage device.
[0098] As an example, a titanium nitride barrier layer 204 may be further included between the top dielectric layer and the hafnium silicon oxide dipole layer 203 .
[0099] Specifically, the titanium nitride barrier layer 204 can act as a diffusion barrier to block the diffusion of oxygen distribution and metal ions, which is crucial to the work function of the hafnium silicon oxide dipole layer 203 and can effectively avoid the shift of the device programming threshold voltage and the decrease of reliability. The thickness of the titanium nitride barrier layer 204 can be like wait.
[0100] In summary, the SONOS device and the preparation method thereof of the present invention include a semiconductor substrate, a storage structure and a gate electrode layer, wherein the storage structure includes a tunneling dielectric layer, a storage layer, a hafnium silicon oxide dipole layer and a top dielectric layer.
[0101] The invention can improve the quantum tunneling efficiency in the programming and erasing process by growing a hafnium silicon oxide dipole layer on the surface of the storage layer. After the external electric field is removed, the hafnium silicon oxide dipole layer still maintains polarity, making it easier to store charges in the storage layer, thereby improving the data retention capability of the SONOS device.
[0102] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A SONOS device, characterized in that: The SONOS device comprises: Semiconductor substrate; A storage structure, the storage structure is located on the surface of the semiconductor substrate, including a tunneling dielectric layer, a storage layer located on the surface of the tunneling dielectric layer, a hafnium silicon oxide dipole layer located on the surface of the storage layer, and a top dielectric layer located on the surface of the hafnium silicon oxide dipole layer; A gate electrode layer is located on the surface of the storage structure.
2. The SONOS device according to claim 1, characterized in that: The thickness of the hafnium silicon oxide dipole layer is 3. The SONOS device according to claim 1, characterized in that: A titanium nitride barrier layer is also included between the top dielectric layer and the hafnium silicon oxide dipole layer.
4. A method for preparing a SONOS device, characterized in that: The following steps are involved: providing a semiconductor substrate; Forming a storage structure on the surface of the semiconductor substrate, wherein the step of forming the storage structure includes forming a tunnel dielectric layer, forming a storage layer on the surface of the tunnel dielectric layer, forming a silicon hafnium oxide dipole layer on the surface of the storage layer, and forming a top dielectric layer on the surface of the silicon hafnium oxide dipole layer; A gate electrode layer is formed on the surface of the storage structure.
5. The method for preparing a SONOS device according to claim 4, characterized in that: The step of forming the hafnium silicon oxide dipole layer comprises: forming a silicon oxide layer on the surface of the storage layer; forming a hafnium oxide layer on the surface of the silicon oxide bottom layer; An annealing process is performed to form the hafnium silicon oxide dipole layer on the surface of the tunnel dielectric layer.
6. The method for preparing a SONOS device according to claim 5, characterized in that: The temperature range of the annealing process is 900°C to 1100°C.
7. The method for preparing a SONOS device according to claim 5, characterized in that: The annealing process is performed in an oxygen or nitrogen monoxide atmosphere.
8. The method for preparing a SONOS device according to claim 5, characterized in that: Between the step of forming the hafnium oxide layer and the step of performing an annealing process, the method further includes the step of forming a titanium nitride barrier layer on the surface of the hafnium oxide layer.
9. The method for preparing a SONOS device according to claim 8, characterized in that: The thickness of the silicon oxide layer is The thickness of the hafnium oxide layer is The thickness of the titanium nitride barrier layer is 10. The method for preparing a SONOS device according to claim 4, characterized in that: The thickness of the formed hafnium silicon oxide dipole layer is