Method for forming semiconductor device

Abstract

A method for forming a semiconductor device is provided. The method includes performing front face processing including forming a transistor structure (100) on a front face (300a) of a substrate (300), the transistor structure (100) including a first source / drain body (110) and a second source / drain body (120) located in first and second source / drain regions (115, 125), respectively, and a channel structure (130) located between the first source / drain body (110) and the second source / drain body (120), wherein the first source / drain body (110) and the second source / drain body (120) have a first doping concentration; after the front surface processing, back surface processing is performed, including: exposing the first source / drain body (110) from the back surface (300b) of the substrate (300); and processing the first source / drain body (110) to form a replacement source / drain body (112) having a second doping concentration different from the first doping concentration in the first source / drain region (115).

Description

Technical Field

[0001] The present disclosure generally relates to a method for forming a semiconductor device. Background Art

[0002] The use of high mobility channel materials has long been of great interest in the semiconductor industry because high mobility channel materials have body mobilities that exceed those of Si, the most commonly used channel material. For example, Ge has a body mobility of 4.4 times for holes and 2.4 times for electrons compared to Si. This high body mobility typically results in high drive capabilities with high on-current ION, such as Ge FETs. However, such high mobility channel material devices typically suffer from significantly higher band-to-band tunneling BTBT, such as higher off-state leakage current IOFF due to their smaller band gaps. Therefore, there is a need to be able to manufacture high mobility channel material devices that exhibit lower off-state leakage currents while still utilizing high drive capabilities and, thus, high on-state currents. Summary of the invention

[0003] In view of the foregoing, it is an object of the present invention to provide a method for forming a semiconductor device that alleviates at least some of the problems associated with high mobility channel material devices.

[0004] It is therefore an object of the present invention to provide a method for forming a semiconductor device which enables the formation of a high mobility channel material semiconductor device having a reduced off-state leakage current.

[0005] Another object is to provide a method for forming a semiconductor device which enables the formation of a high mobility channel material semiconductor device having a high drive capability and thus a high on-current while having a reduced off-state leakage current.

[0006] Yet another object is to provide a method for forming a semiconductor device which enables the formation of a high mobility channel material semiconductor device with reduced contact resistance.

[0007] Yet another object is to provide a method for forming a semiconductor device which requires fewer process steps.

[0008] Yet another object is to provide a less complex method for forming a semiconductor device.

[0009] Yet another object is to provide a more cost-effective method for forming a semiconductor device.

[0010] These and other objects are achieved by a semiconductor device according to the independent claims. Embodiments of the invention are defined in the dependent claims.

[0011] Therefore, according to one aspect of the present invention, a method for forming a semiconductor device is provided, the method comprising: performing front side processing, comprising forming a transistor structure on the front side of a substrate, the transistor structure comprising a first source / drain body and a second source / drain body respectively located in a first and a second source / drain region, and a channel structure located between the first source / drain body and the second source / drain body, wherein the first source / drain body and the second source / drain body have a first doping concentration; after the front side processing, performing back side processing, comprising: exposing the first source / drain body from the back side of the substrate; and processing the first source / drain body to form a replacement source / drain body having a second doping concentration different from the first doping concentration in the first source / drain region.

[0012] Thus, the present invention is based on the recognition that by processing a first source / drain body to form a replacement source / drain body having a different doping concentration than a second source / drain body, an asymmetric semiconductor device, i.e. a device having asymmetric doping of the source / drain body, can be formed. In particular, an asymmetric high mobility channel material semiconductor device or a high mobility device can be formed.

[0013] In this regard, in order to provide a high mobility device (which provides high drive capability and low off-state current), the device typically has a high source doping, which allows for a high on-state current, while having a low drain doping, which allows for a low off-state leakage current.

[0014] In addition, the present method can form an asymmetric high mobility channel material semiconductor device or a high mobility device while using fewer process steps than conventional methods. More specifically, by processing the first source / drain body during backside processing, which may anyway involve accessing the first source / drain body to contact the backside power delivery network, asymmetric doping can be provided without adding additional process steps during frontside processing. Therefore, the present method may be particularly beneficial in manufacturing semiconductor devices including a backside power delivery network.

[0015] Furthermore, the present method may allow for the formation of an asymmetric high mobility channel material semiconductor device or high mobility device in a less complex manner at a lower cost.

[0016] The first source / drain body and the second source / drain body may be a source body and a drain body, respectively. Alternatively, the first source / drain body and the second source / drain body may be a drain body and a source body, respectively. This applies accordingly to the term "first and second source / drain regions".

[0017] In practice, where the first source / drain body and the first source / drain region are the source body and the source region, respectively, the method enables the formation of an asymmetric device by increasing the doping concentration in the source region by forming a replacement source body having a higher doping concentration than the drain body.

[0018] On the contrary, in practice, where the first source / drain body and the first source / drain region are the drain body and the drain region, respectively, the present method enables the doping concentration in the drain region to be reduced by forming a replacement drain body having a lower doping concentration than the source body, thereby forming an asymmetric device.

[0019] More generally, therefore, the method enables the fabrication of an asymmetric device by increasing or decreasing the doping concentration in a first source / drain region while not affecting or in principle not affecting the doping concentration in a second source / drain region.

[0020] More specifically, by the present method, a doping concentration difference between the replacement source / drain body and the second source / drain body is achieved by processing the first source / drain body to form a replacement source / drain body having a second doping concentration different from the first doping concentration in the first source / drain region. Thus, an asymmetric transistor structure, i.e., a non-uniform transistor structure with asymmetric source / drain doping, is formed.

[0021] Therefore, by forming a first source / drain body and a second source / drain body with a first doping concentration during front processing, and then processing the first source / drain body during back processing to form a replacement source body having a second doping concentration different from the first doping concentration, the asymmetry of the formed semiconductor device can be customized by customizing the first and second doping concentrations.

[0022] "Replacement source / drain body" herein refers to a source / drain body having different properties than the first source / drain body formed during front processing. Specifically, the replacement source / drain body can have a higher doping concentration than the first source / drain body formed during front processing, or the replacement source / drain body can have a lower doping concentration than the first source / drain body formed during front processing.

[0023] The replacement source / drain body may include material from the first source / drain body formed during front processing. The replacement source / drain body may include a material different from the material of the first source / drain body formed during front processing. Therefore, the replacement source / drain body may be formed, for example, by changing the first source / drain body formed during front processing. The replacement source / drain body may be formed, for example, by changing a portion of the first source / drain body formed during front processing. The replacement source / drain body may be formed, for example, by partially replacing the first source / drain body formed during front processing. The replacement source / drain body may be formed, for example, by replacing the first source / drain body formed during front processing. The replacement source / drain body may be formed, for example, by adding material to the first source / drain body formed during front processing. The replacement source / drain body may be formed, for example, by a combination of the above techniques.

[0024] According to some embodiments, processing the first source / drain body may include epitaxially growing a doped source / drain material in the first source / drain region, which is advantageous because the replacement source / drain body may be formed from an epitaxial material having a higher or lower doping concentration than the first source / drain body. By epitaxially growing a doped source / drain material having a doping concentration higher than the first doping concentration, the replacement source / drain body may be formed to have a higher doping concentration than the first source / drain body. In this way, the overall or average doping concentration of the replacement source / drain body may be increased relative to the first and second source / drain bodies. Alternatively, by epitaxially growing a doped source / drain material having a doping concentration lower than the first doping concentration, the replacement source / drain body may be formed to have a lower doping concentration than the first source / drain body. In this way, the overall or average doping concentration of the replacement source body may be reduced relative to the first and second source / drain bodies.

[0025] According to some embodiments, the doped source / drain material may be grown on the exposed surface of the first source / drain body, which is advantageous because the first source / drain body may be at least partially retained in the first source / drain region. This may facilitate processing because less material of the first source / drain body needs to be removed.

[0026] According to some embodiments, processing the first source / drain body may further include: removing at least a portion of the first source / drain body or at least a major portion of the first source / drain body to form a source / drain body cavity in the first source / drain region, wherein the doped source / drain material is subsequently epitaxially grown in the source / drain body cavity. By removing at least a portion of the first source / drain body, a source / drain body cavity corresponding to at least a portion of the first source / drain body may be formed in the first source / drain region. By subsequently epitaxially growing the doped source / drain material in the source / drain body cavity, the resulting replacement source / drain body may be formed to have a second doping concentration. The effective doping concentration of the composite replacement source / drain body (formed by the remaining portion of the first source / drain body and the epitaxial source / drain material) may therefore be controlled by varying the amount of material removed from the first source / drain body. Similarly, by removing at least a major portion of the first source / drain body, a source / drain body cavity corresponding to at least a portion of the first source / drain body can be formed in the first source / drain region. By subsequently epitaxially growing a doped source / drain material in the source / drain body cavity, the resulting replacement source / drain body can be formed to have a second doping concentration. Thus, the second doping concentration can be provided in a larger portion of the replacement source / drain body.

[0027] According to some embodiments, the first source / drain body may include a semiconductor liner disposed at least at an interface between the first source / drain body and the channel structure, wherein the semiconductor liner is formed of a material different from the first source / drain body, which is advantageous because the liner may protect the channel structure during backside processing. For example, the liner may protect the channel structure when forming the source / drain body cavity. In addition, the liner may protect the channel structure during frontside processing.

[0028] According to some embodiments, at least a portion or at least a major portion of the first source / drain body can be removed using an etching process that selectively etches the material of the first source / drain body relative to the material of the semiconductor liner, which is advantageous because the extension of the source / drain body cavity can be controlled by the presence of the liner. In addition, the liner can prevent or counteract the channel structure from being affected by the etchant used to form the source / drain body cavity.

[0029] According to some embodiments, exposing the first source / drain body may include thinning the substrate from a back side.

[0030] According to some embodiments, exposing the first source / drain body may include forming an opening in the substrate below the first source / drain body to expose the first source / drain body, wherein the first source / drain body is processed from the opening in the substrate.

[0031] According to some embodiments, forming the opening in the substrate may include thinning the substrate to expose a dummy contact plug disposed under the first source / drain body, and removing the dummy contact plug to expose the first source / drain body.

[0032] According to various embodiments, the method may further include: after forming an opening in the substrate, forming an insulating liner covering the substrate and the exposed first source / drain body; and opening the insulating liner in the opening in the substrate to expose the first source / drain body, wherein the first source / drain body is processed from the opening in the insulating liner, which is advantageous because the insulating liner can protect the substrate during back side processing.

[0033] According to some embodiments, the doped source / drain material may be epitaxially grown through the openings in the insulating liner, which is advantageous because the insulating liner may inhibit the doped source / drain material from growing on the substrate while it epitaxially grows through the openings in the insulating liner. Thus, the insulating liner may be used as an epitaxial mask, inhibiting deposition of the source / drain material in regions other than the first source / drain region.

[0034] According to some embodiments, at least a portion or at least a major portion of the first source / drain body can be removed by etching from an opening in the insulating liner, which is advantageous because the insulating liner can prevent or offset the substrate from being affected by the etching. Therefore, when etching the first source / drain body, the insulating liner can be used as an etching mask. According to some embodiments, exposing the first source / drain body can include: removing the substrate below the transistor structure to expose the first source / drain body and the second source / drain body; forming a bottom isolation layer covering the first source / drain body and the second source / drain body; and forming an opening in the bottom isolation layer to expose the first source / drain body; wherein the first source / drain body is processed from the opening in the bottom isolation layer, which is advantageous because the bottom isolation layer can protect the transistor structure when processing the first source / drain body from the opening in the bottom isolation layer. According to some embodiments, the opening in the bottom isolation layer can be formed by removing a dummy contact plug disposed below the first source / drain body, which is advantageous because the opening in the bottom isolation layer can be formed in a self-aligned manner.

[0035] According to some embodiments, processing the first source / drain body may include increasing the doping concentration in the first source / drain body, wherein increasing the doping concentration includes: implanting a dopant into the first source / drain body and / or diffusing a dopant into the first source / drain body. Thus, by selectively introducing a dopant into the first source / drain body (but not the second source / drain body), the doping concentration in the replacement source / drain body may be increased.

[0036] According to various embodiments, the method may further include: forming a source / drain contact on the replacement source / drain body, which is advantageous because a reduced contact resistance can be achieved between the replacement source / drain body and the source / drain contact compared to if the source / drain contact were to be formed on the first source / drain body.

[0037] According to some embodiments, front side processing may further include forming source / drain contacts on the second source / drain bodies.

[0038] According to some embodiments, the front side processing may further include forming a gate stack on the channel structure.

[0039] According to some embodiments, the channel structure may include one or more layers of a germanium-containing channel material. According to some embodiments, the channel structure may include one or more layers of a silicon-germanium-containing channel material. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] This and other aspects of the present invention will now be described in more detail, with reference to the appended drawings showing embodiments of the invention.

[0041] Figure 1-4 The device structure is schematically shown at different stages of a method for forming a semiconductor device.

[0042] Figure 5 It is schematically shown how a replacement source / drain body may be formed according to various embodiments.

[0043] Figure 6-8 The device structure is schematically shown at different stages of a method for forming a semiconductor device.

[0044] Fig. 9 It is schematically shown how source / drain contacts may be formed according to various embodiments.

[0045] Figure 10-13 The device structure is schematically shown at different stages of a method for forming a semiconductor device.

[0046] Fig.14 A device structure including a dummy contact plug is schematically shown.

[0047] Fig.15 A device structure is schematically shown in which the first source / drain body comprises a semiconductor liner layer. DETAILED DESCRIPTION

[0048] The following is a detailed description of various method embodiments for forming a semiconductor device. More specifically, the method includes, after front side processing, performing back side processing, including processing a first source / drain (S / D) body to form a replacement S / D body in a first S / D region having a doping concentration different from that of the first S / D body. Hereinafter, each method will be described with reference to the accompanying drawings.

[0049] The accompanying drawings are schematic diagrams only, and the relative sizes of some structures and layers may be exaggerated and not drawn to scale. On the contrary, the size can be adjusted to make the illustration clear and easy to understand. When appearing in the accompanying drawings, the indicated axes X and Y consistently represent the horizontal or lateral direction and the vertical direction, respectively. As used herein, the terms "horizontal" and "lateral" refer to the direction parallel to the substrate (main surface) on which the semiconductor device is formed / from which it is formed. The term "vertical" refers to the direction parallel to the normal direction of the substrate (main surface) on which the semiconductor device is formed / from which it is formed, that is, transverse to the substrate. In addition, the (positive) vertical direction refers to the direction pointing to what is generally regarded as the front side of the substrate.

[0050] First, refer to Figure 1 Briefly describing a transistor structure 100 according to various embodiments, which may be formed by performing front-side processing. Figure 1 In the embodiment, transistor structure 100 forms part of a complementary field effect transistor (CFET) structure 10, which can be formed by performing front-side processing. CFET structure 10 is formed Figure 1 A portion of the device structure 1 is shown. Therefore, the device structure 1 includes Figure 1 . Hereinafter, the device structure 1 will be described at different stages of the method embodiment with reference to the accompanying drawings. As known in the art, a CFET generally includes a PMOS transistor structure 100 and an NMOS transistor structure 200 stacked vertically on each other. In the following description, the transistor structure 100 closest to the substrate 300 will be described, but for completeness and clarity of the description, the transistor structure 200 will also be shown in the various drawings. Figure 1 The device structure or structure 1 also includes structures 400 formed during the middle process (MOL) and the back end process (BEOL) processes. For completeness and clarity of the description, these structures 400 will also be shown in the various figures. However, the transistor structure 200 and the structure 400 will not be described in more detail.

[0051] Furthermore, it will be understood that the present disclosure is equally applicable to non-stacked semiconductor structures 100 , such as non-stacked nanosheet FET devices and fin FET devices.

[0052] like Figure 1As shown, the transistor structure 100 has been formed on the front side 300a of the substrate 300. The substrate 300 may be a conventional semiconductor substrate suitable for complementary FETs. The substrate 300 may be a single-layer semiconductor substrate, for example formed by a bulk substrate such as a Si substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate. However, multi-layer / composite substrates are also possible, such as epitaxially grown semiconductor layers on a bulk substrate or a semiconductor-on-insulator (SOI) substrate, such as a Si-on-insulator substrate, a Ge-on-insulator substrate, or a SiGe-on-insulator substrate.

[0053] The transistor structure 100 includes a first S / D body 110 and a second S / D body 120. The first S / D body 110 is located in a first S / D region 115. The second S / D body 120 is located in a second S / D region 125.

[0054] The first S / D body 110 and the second S / D body 120 may be formed by epitaxially growing the first S / D body 110 and the second S / D body 120. The first S / D body 110 and the second S / D body 120 may be formed, for example, by epitaxially growing doped Si, Si-C, SiGe, Ge, Ge-Sn, or SiGe-Sn.

[0055] The channel structure 130 is disposed between the first S / D body 110 and the second S / D body 120. The depicted channel structure 130 includes a channel layer 132 in the form of a nanosheet channel layer 132. Figure 1 The nanosheet channel layer 132 is shown extending between the first S / D body 110 and the second S / D body 120. Figure 1 , for clarity, only two nanosheet channel layers 132 are shown, but the channel structure 130 may include any number of channel layers 32. The channel layer 132 of the channel structure 130 may include a high mobility channel material. According to various embodiments, the channel structure 132 may include one or more layers 132 of a germanium-containing channel material. According to various embodiments, the channel structure 132 may include one or more layers 132 of germanium as a channel material. According to various embodiments, the channel structure 132 may include one or more layers 132 of silicon-germanium-containing channel material. In the case where the channel layer 132 includes a channel material containing SiGe, the Ge concentration may be equal to or higher than 70% to provide a high mobility channel. However, the present disclosure is also applicable to lower Ge concentrations. Similarly, the present disclosure is also applicable to silicon-based channel materials.

[0056] Furthermore, according to various embodiments, the channel region 130 may include a single channel in the channel region. Furthermore, the channel region 130 may include a channel in the form of a nanowire.

[0057] The depicted channel layer 132 of the channel structure 130 is surrounded by a gate stack 140. The gate stack 140 is schematically drawn and may include a gate dielectric and one or more gate metal layers as known in the art. The gate stack will not be described in more detail. However, it will be understood that any type of suitable gate stack 140 may be used. Furthermore, according to various embodiments, for example in the case of a single channel in the channel region 130, the gate stack 140 may be disposed directly on top of the channel region 130.

[0058] Furthermore, the depicted gate stack 140 is separated from the first S / D body 110 and the second S / D body 120 by an internal spacer 150. The internal spacer 150 is known per se and may be formed according to known techniques.

[0059] The first S / D body 110 and the second S / D body 120 have a first doping concentration. The first doping concentration may be between 1 and 10 per cubic centimeter. 17 -1 10 22 The first S / D body 110 and the second S / D body 120 may be doped with P, As, Sb, Ga, or B. The first S / D body 110 and the second S / D body 120 may generally be formed simultaneously using the same processing steps to achieve the first doping concentration.

[0060] Now also turn to Figure 2 . Figure 2 Shows Figure 1 How the complete structure 1 is bonded to a carrier substrate or wafer 350 via a bonding layer 360. The carrier substrate may be a silicon wafer. The bonding layer may be an oxide or nitride bonding layer, or any other conventional type of bonding layer suitable for CMOS processes. In addition, the entire structure has been flipped so that Figure 1 The substrate 300 shown at the bottom is now located at the top, as shown in FIG. Figure 2 The flip of the complete structure 1 is also shown by Figure 2 The Y axis is relative to Figure 1 By changing the direction of Figure 1 The completed structure 1 is bonded to the carrier substrate 350 and the completed structure 1 is turned over, and the completed structure 1 is ready to be processed on the back side.

[0061] The following will describe Figure 1 and Figure 2300b of the substrate 300, and how the first S / D body 110 is exposed from the back side 300b of the substrate 300, and how the first S / D body 110 is processed to form a replacement S / D body 112 in the first S / D region 115, wherein the replacement S / D body 112 has a second doping concentration different from the first doping concentration. In other words, how to form a replacement S / D body 112 having a doping concentration different from the first S / D body 110 in the first S / D region 115 by back side processing of the transistor structure 100 will be described below. As previously described, the first S / D body 110 may define a source body 110, and the second S / D body 120 may define a drain body, wherein a replacement source body 112 having a doping concentration different from (e.g., higher than) the original source body 110 may be formed. However, the first S / D body 110 may define a drain body 110 and the second S / D body 120 may define a source body, wherein a replacement source body 112 having a doping concentration different (eg, lower) than the original drain body may be formed.

[0062] Reference Figure 1-5 A first method of forming a replacement S / D body 112 is disclosed. Then, reference is made to Figure 6-8 A second method of forming a replacement S / D body 112 is disclosed. Figure 10-13 A third method of forming a replacement S / D body 112 is disclosed.

[0063] Now also turn to Figure 3 . Figure 3 It is shown how the substrate 300 is thinned from its back side 300b so that only a limited part of the substrate 300 is left under the transistor structure 100. In practice, the substrate 300 may be thinned by grinding or chemical mechanical polishing (CMP) and / or etching back (e.g. anisotropic dry etching, wet etching, gas chemical etching processes like siconi or certas type processes).

[0064] Now also turn to Figure 4 , showing that the opening 310 has been formed in the substrate 300. Figure 4 As shown, the opening 310 exposes the first S / D body 110 from the back side 300b of the substrate 300. Figure 4 As shown, an opening 310 has been formed in the substrate 300 below the first S / D body 110. The opening 310 can be formed in the substrate by conventional photolithography and etching processes. For example, a photomask can be formed on the back side of the thinned substrate 300 and used as an etching mask to form the opening 310 in the substrate 300.

[0065] The first S / D body 110 may be processed from the opening 310 to form a replacement S / D body 112 in the first S / D region 115 (see, for example, Figure 5 ). As described above, processing of the first S / D body 110 may be directed to forming a replacement S / D body 112 having a second doping concentration different from the first doping concentration. In this way, an asymmetric transistor structure, i.e., a non-uniform transistor structure with asymmetric source-drain doping, may be formed.

[0066] Figure 5 1 shows the structure 1 after the first S / D body 110 is processed to form a replacement S / D body 112 in the first S / D region 115. More specifically, Figure 5 The replacement S / D body 112 is formed by increasing the doping concentration in the first S / D body 110. In other words, the material of the first S / D body 110 has been modified by increasing the doping concentration in the material of the first S / D body. Figure 5 As shown by the arrows in , the doping concentration of the first S / D body 110 can be increased by injecting dopants into the first S / D body 110 and / or diffusing dopants into the first S / D body 100. The doping concentration of the first S / D body 110 can be increased by injecting or diffusing P, As, Sb, Ga, or B into the first S / D body 100. Figure 5 The doping concentration of the replacement S / D body 112 may be higher than the doping concentration of the first S / D body 110, and ... 17 -1 10 22 within a portion of the range of the dopant.

[0067] Figure 6 The structure 1 is shown after further processing steps before processing the first S / D body 110 to form the replacement S / D body 112. Figure 4 The structure 1. Figure 6 , an insulating liner 320 has been formed covering the substrate and the exposed first S / D body 115. The insulating liner 320 may be formed by conformally depositing a dielectric material such as an insulating oxide or nitride on the back side 300b of the substrate 300 and the inner surface of the opening 310 (including the exposed portion of the exposed first S / D body 110). The insulating liner 320 may include silicon dioxide or silicon nitride.

[0068] exist Figure 7In the embodiment, the insulating liner 320 has been opened in the opening 310 in the substrate 300 (i.e., opened through or from the opening 310), thereby forming an opening 311 in the insulating liner 320. By opening the insulating liner 320 in the opening 310 of the substrate 300, the first S / D body 110 has been exposed through the openings 310 and 311. A portion of the insulating liner 320 can be removed by conventional patterning and etching processes. For example, the patterned resist can be used as an etching mask to open the insulating liner 320 in the opening 310 of the substrate 300.

[0069] In addition, Figure 7 1, the first S / D body 110 has been substantially completely removed to form an S / D body cavity 117 in the first S / D region 115. Alternatively, as shown by the hatched lines in the S / D body cavity 117 of the first S / D region 115, at least a portion of the first S / D body 110 or at least a major portion of the first S / D body 110 may be removed to form the S / D body cavity 117 in the first S / D region 115. Here, it will be understood that the shape of the hatched lines is merely schematic. For example, the S / D body cavity 117 may instead be formed in a central portion of the first S / D body 110 so that portions of the first S / D body 110 remain adjacent to the channel layer 132 and the inner spacer 150.

[0070] Now also turn to Figure 8 . Figure 8 Shows Figure 7 structure 1. However, in Figure 8 middle, Figure 7 The structure has undergone further processing steps. Figure 8 , the doped S / D material has been epitaxially grown in the first S / D region 115. Thus, the doped S / D material has been epitaxially grown through the opening in the insulating liner 320. That is, the doped S / D material has been epitaxially grown in the S / D body cavity 117. Thus, the first S / D body has been processed from the opening in the insulating liner 320 to form a replacement S / D body 112 having a second doping concentration different from the first doping concentration. In this way, an asymmetric transistor structure, i.e., a non-uniform transistor structure with asymmetric source and drain doping, has been formed. . The S / D material may be doped with P, As, Sb, Ga or B. The doped S / D material may be grown by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. Figure 8 The doping concentration of the replacement S / D body 112 may be between 1 and 10 per cubic centimeter. 17 -1 10 22 The doped S / D material may include the same material or materials as the first S / D body, but with a different doping concentration.

[0071] In the case where the first S / D body 110 has not been completely removed, and the doped S / D material has grown on the exposed surface of the first S / D body 110, the replacement S / D body 112 formed will actually be formed in part from the original first S / D body 110 and in part from the epitaxially grown doped S / D material. In addition, the replacement S / D body 112 formed will have a different doping concentration than the first S / D body because the doping concentration of the doped S / D material is different from the doping concentration of the first S / D body.

[0072] exist Fig. 9 In the embodiment, the S / D contact 114 has been formed on the replacement S / D body 112. Therefore, the S / D contact 114 has been formed from the back side 300b of the substrate 300. The S / D contact 114 can be formed using conventional methods.

[0073] Now also turn to Fig.10 , will be Figure 2 Another way of forming a semiconductor device according to various embodiments is described starting with structure 1. Thus, Fig.10 Shows Figure 2 structure 1. However, in Fig.10 middle, Figure 2 The structure has undergone further processing steps. Fig.10 , the substrate 300 under the transistor structure 100 has been removed to expose the first S / D body 110 and the second S / D body 120. The substrate 300 under the transistor structure 100 may be removed using conventional processes including grinding or CMP and / or etching (such as dry etching, wet etching, gas chemical etching processes such as siconi or certas).

[0074] exist Fig.11 In the embodiment, a bottom isolation layer 330 covering the first S / D body 110 and the second S / D body 120 has been formed. Fig.11 As shown, the bottom isolation layer 330 may be formed by depositing or growing silicon dioxide or silicon nitride so that the bottom isolation layer 330 covers the first S / D body 110 and the second S / D body. The bottom isolation layer 330 may be formed, for example, by CVD or physical vapor deposition (PVD).

[0075] exist Fig.12 In the embodiment, an opening 340 has been formed in the bottom isolation layer 330 to expose the first S / D body 110. By forming the opening 340 in the bottom isolation layer 330, the first S / D body 110 has been exposed through the opening 330. The opening 340 in the bottom isolation layer 330 can be formed by conventional patterning and etching processes. For example, a patterned resist can be used as an etching mask to form the opening 340.

[0076] In addition, Fig.12 In the embodiment, the first S / D body 110 has been substantially completely removed. Therefore, removing the first S / D body can result in the formation of the S / D body cavity 117. Figure 7 (See also Figure 7 ) describes the formation process of the S / D body cavity 117. In addition, as combined Figure 7 Alternatively, at least a portion of the first S / D body 110 or at least a major portion of the first S / D body 110 may be removed to form an S / D body cavity 117 in the first S / D region 115 .

[0077] exist Fig.13 In the embodiment, the first S / D body 110 has been processed from the opening 340 in the bottom isolation layer 330. More specifically, the first S / D body 110 can be combined with the above Figure 8 The S / D body 112 is processed to form a replacement S / D body 112 having a second doping concentration different from the first doping concentration. Therefore, please refer to the above. In addition, as described above in conjunction with Fig. 9 As described above, the S / D contacts 114 may be formed on the replacement S / D body 112 .

[0078] Now also turn to Fig.14 . Fig.14 Shown with Fig.11 The structure of 1 is highly similar to that of 1. However, Fig.14 In Fig.14 As shown, a dummy contact plug 335 is provided under the first S / D body 110 . Fig.14 The dummy contact plug 335 has been formed in the front processing before the back processing. By providing the dummy contact plug, the dummy contact plug 335 can be removed to form the same Fig.11 In other words, the opening 340 in the bottom isolation layer 330 may be formed by removing the dummy contact plug 335 disposed under the first S / D body 110 .

[0079] The dummy contact plug 335 may be formed, for example, by forming a recess in the substrate 300 with a well-controlled coverage relative to the S / D region 115 and forming the dummy contact plug 335 in the recess, during front-side processing prior to forming the transistor structure 100. The dummy contact plug 335 may be formed of, for example, amorphous silicon, an epitaxial semiconductor material (e.g., Ge, Si, or SiGe), a dielectric material, or more generally any suitable dummy material that may be selectively removed relative to the bottom isolation layer 330 and is compatible with the preceding steps of front-side and back-side processing (e.g., in terms of thermal budget).

[0080] By providing the dummy contact plug 335 , the opening 340 may be formed in a self-aligned manner with respect to the first S / D body 110 .

[0081] In the case where the dummy contact plug 335 is recessed in the substrate 300, the opening 310 may be formed in the substrate 300 by removing the dummy contact plug 335. Figure 4 As shown, an opening 310 may be formed in the substrate. In practice, the formation of such an opening 310 may include thinning the substrate 300 to expose the dummy contact plug 335 disposed under the first S / D body 110 and removing the dummy contact plug 335 to expose the first S / D body 110.

[0082] Once the opening 310 or the opening 340 is formed, the Figure 5 , 8 As described in or 13, the structure 1 can be processed to form a replacement S / D body 112 having a second doping concentration different from the first doping concentration. In addition, as described above in conjunction with Fig. 9 As described above, the S / D contacts 114 may be formed on the replacement S / D body 112 .

[0083] Now also turn to Fig.15 . Fig.15 Shown with Fig.11 The structure of 1 is highly similar to that of 1. However, Fig.15 In the embodiment, the first S / D body 110 includes a semiconductor liner 111. Fig.15 As shown, the semiconductor liner 111 is at least disposed at the interface between the first S / D body 11 and the channel structure 130. The semiconductor liner 111 may also be disposed below the first S / D body, such as Fig.15 The semiconductor liner 111 may be formed of a material different from that of the first S / D body 110. The semiconductor liner 111 may be formed, for example, of silicon germanium having a lower silicon or germanium content than the first S / D body 110. In this regard, when the semiconductor liner 111 is formed of silicon germanium, the germanium content may generally be lower than the germanium content of the first S / D body 110 if the first S / D body is also made of silicon germanium.

[0084] By providing a semiconductor liner 111 formed of a material different from that of the first S / D body 110, the first S / D body 110 can be selectively etched relative to the semiconductor liner 111. In practice, at least a portion or at least a major portion of the first S / D body 110 can be removed using an etching process that selectively etches the material of the first S / D body relative to the material of the semiconductor liner 111. In this way, Fig.12A source body cavity 117 corresponding to the source body cavity of the first S / D body 110 may be formed. In addition, by providing a semiconductor liner 111 formed of a material different from that of the first S / D body 110, removal or partial removal of the first S / D body may be performed with reduced risk of damaging the channel structure 130. For example, the semiconductor liner 111 may be formed of a silicon germanium material having a germanium concentration that differs by 10% or more (e.g., greater or less than at least 10%) from that of the material of the first S / D body.

[0085] Those skilled in the art will appreciate that the present invention is by no means limited to the above-described embodiments. On the contrary, many modifications and variations are possible within the scope of the appended claims. For example, the replacement S / D body may include more than one material or material composition. In this regard, the replacement S / D body may include two or more layers of different material compositions. For example, the replacement S / D body may include two or more layers of SiGe with different Ge concentrations. In addition, the dummy contact plug 335 may be used in conjunction with the first S / D body including the semiconductor liner 111. In addition, the dummy contact plug 335 may be used in conjunction with the insulating layer 320. In addition, the S / D contact 114 may be formed on any of the above-mentioned replacement S / D bodies 112.

[0086] Furthermore, after forming the replacement S / D bodies 112 and S / D contacts 114 according to any of the above methods, additional backside processing steps may be applied to the structure 10. For example, the method may continue to form a backside interconnect structure for routing signals or power to the transistor structure 100, such as through the S / D contacts 114 and to any other devices (e.g., CFETs) of the device structure 1. The backside interconnect structure may be formed using conventional techniques used in the BEOL to form frontside interconnect structures, such as damascene processing. The specific layout and details of the backside interconnect structure are beyond the scope of the present method and are therefore not discussed further herein.

Claims

1. A method for forming a semiconductor device, comprising: Performing front processing, including forming a transistor structure (100) on a front side (300a) of a substrate (300), the transistor structure (100) comprising a first source / drain body (110) and a second source / drain body (120) respectively located in a first source / drain region (115) and a second source / drain region (125), and a channel structure (130) located between the first source / drain body (110) and the second source / drain body (120), wherein the first source / drain body (110) and the second source / drain body (120) have a first doping concentration; After the front side processing, back side processing is performed, and the back side processing includes: Exposing the first source / drain body (110) from the back side (300b) of the substrate (300); as well as The first source / drain body (110) is processed to form a replacement source / drain body (112) having a second doping concentration different from the first doping concentration in the first drain / source region (115).

2. The method according to claim 1, characterized in that Processing the first source / drain body (110) includes epitaxially growing a doped source / drain material in the first source / drain region (115).

3. The method according to claim 2, characterized in that The doped source / drain material is grown on the exposed surface of the first source / drain body (110).

4. The method according to any one of claims 2 to 3, characterized in that: Processing the first source / drain body (110) also includes: At least a portion of the first source / drain body (110) or at least a major portion of the first source / drain body (110) is removed to form a source / drain body cavity (117) in the first source / drain region (115), wherein the doped source / drain material is subsequently epitaxially grown in the source / drain body cavity (117).

5. The method according to any one of the preceding claims, characterized in that The first source / drain body (110) comprises a semiconductor liner (111) at least arranged at an interface between the first source / drain body (100) and the channel structure (130), wherein the semiconductor liner (111) is formed of a material different from that of the first source / drain body (110).

6. The method according to claim 5, when referring to claim 4, characterized in that The at least a portion or the at least a major portion of the first source / drain body (110) is removed using an etching process that selectively etches the material of the first source / drain body (110) relative to the material of the semiconductor liner (111).

7. The method according to any one of the preceding claims, characterized in that Exposing the first source / drain body (110) includes thinning the substrate (300) from the back side (300b).

8. The method according to any one of the preceding claims, characterized in that Exposing the first source / drain body (110) includes forming an opening (310) in the substrate (300) below the first source / drain body (100) to expose the first source / drain body (10), wherein the first source / drain body (110) is processed from the opening in the substrate.

9. The method according to claim 8, characterized in that Also includes: After forming the opening (310) in the substrate (300), forming an insulating liner (320) covering the substrate (300) and the exposed first source / drain body (110); as well as The insulating liner (320) is opened in the opening (310) in the substrate (300) to expose the first source / drain body (110), The first source / drain body (110) is processed from the opening in the insulating liner (320).

10. The method according to claim 9, when referring to claim 2, characterized in that The doped source / drain material is epitaxially grown through the opening in the insulating liner (320).

11. The method according to claim 10, when referring to claim 4, characterized in that The at least a portion or the at least a major portion of the first source / drain body (110) is removed by etching from the opening in the insulating liner (320).

12. The method according to any one of claims 1 to 7, characterized in that: Exposing the first source / drain body (110) includes: Removing the substrate (300) below the transistor structure (100) to expose the first source / drain body (110) and the second source / drain body (120); forming a bottom isolation layer (330) covering the first source / drain body (110) and the second source / drain body (120); and forming an opening (340) in the bottom isolation layer (330) to expose the first source / drain body (110); The first source / drain body (110) is processed from the opening (340) in the bottom isolation layer (330).

13. The method according to claim 12, characterized in that The opening (340) in the bottom isolation layer (330) is formed by removing a dummy contact plug (335) disposed below the first source / drain body (110).

14. The method according to claim 1, characterized in that Processing the first source / drain body (110) includes increasing a doping concentration in the first source / drain region (110), and wherein increasing the doping concentration includes: implanting dopants into the first source / drain body (110), and / or Dopants are diffused into the first source / drain body (110).

15. The method according to any one of the preceding claims, characterized in that The method further comprises: A source / drain contact (114) is formed on the replacement source / drain body (112).

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