Display panel and display device

Abstract

The present disclosure provides a display panel and a display device, wherein the display panel comprises a display area and a non-display area, the non-display area comprises a special-shaped non-display area, the edge of the special-shaped non-display area comprises a curved portion; the display panel further comprises: a plurality of pixel driving circuits, the plurality of pixel driving circuits are located in the display area and are arranged in an array along a first direction and a second direction, the first direction and the second direction intersect; the pixel driving circuit comprises a first type of transistor, the first type of transistor comprises an oxide transistor; a first wire, the first wire is located at least in the special-shaped non-display area; the material of the first wire comprises titanium and molybdenum; the first wire receives a fixed potential signal. The present disclosure can alleviate the occurrence of bright spots in the special-shaped display area of the display panel at low gray scale, and prevent the first wire from being electrostatically shocked.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] Currently, the LTPO (Low Temperature Polycrystalline Oxide) display panel, in the irregular display area, due to the design difference between the wiring condition of the bias adjustment signal line and the main display area, the IGZO (Indium-Gallium-Zinc-Oxide) transistor characteristics at the edge of the irregular display area are affected, and then the irregular display area occurs bright spot at low gray scale.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] Therefore, the present disclosure provides a display panel and a display device to at least solve the problem that the irregular display area of the existing display panel occurs bright spot at low gray scale.

[0005] In one aspect, the embodiments of the present disclosure provide a display panel, comprising a display area and a non-display area, the non-display area comprising an irregular non-display area, the edge of the irregular non-display area comprising a curved portion; the display panel further comprises: a plurality of pixel driving circuits, the plurality of pixel driving circuits being located in the display area and arranged in a first direction and a second direction, the first direction and the second direction being perpendicular to each other; the pixel driving circuit comprising a first type of transistor, the first type of transistor comprising an oxide transistor; a first wire, the first wire being located at least in the irregular non-display area; the material of the first wire comprising titanium and molybdenum; the first wire receiving a fixed potential signal.

[0006] In another aspect, the embodiments of the present disclosure further provide a display device comprising the above-mentioned display panel.

[0007] Compared with the prior art, the present disclosure has at least the following technical effects:

[0008] The display panel and the display device provided by the present disclosure can set a first wire including titanium metal and molybdenum metal in the special-shaped non-display area of the display panel. Due to the lateral growth of the titanium metal crystal and the vertical growth of the molybdenum metal crystal, the first wire can strengthen the blocking effect of hydrogen elements in the oxide transistor near the edge of the display area of the special-shaped non-display area, reduce the leakage current of the oxide transistor, and reduce the negative bias of the threshold voltage of the oxide transistor, thereby solving the problem of the bright spot of the display panel near the edge of the display area of the special-shaped non-display area at a low gray scale. By receiving a fixed potential signal, the first wire can be prevented from floating and being damaged by static electricity. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure. It is to be clearly understood that the drawings are merely some embodiments of the present disclosure, and other drawings can be obtained by those of ordinary skill in the art without creative effort based on these drawings.

[0010] Figure 1 is a region division schematic diagram of a display panel in the related art;

[0011] Figure 2 is Figure 1 is a partial enlarged view of a special-shaped display area in

[0012] Figure 3 is Figure 1 is a partial enlarged view of another special-shaped display area in

[0013] Figure 4 is a region division schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0014] Figure 5 is a circuit wire distribution schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0015] Figure 6 is a circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0016] Figure 7 is a cross-sectional structure schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0017] Figure 8 is a circuit wire distribution schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0018] Figure 9 is a first wire distribution schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0019] Figure 10 is a first wire distribution schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0020] Figure 11 is Figure 10 is a partial enlarged view of a first irregular non-display area in

[0021] Figure 12 is Figure 10 is a partial enlarged view of a second irregular non-display area in

[0022] Figure 13 is Figure 9 is a partial enlarged view of a second irregular non-display area in

[0023] Figure 14 is a structural schematic diagram of a display device provided by an embodiment of the present disclosure;

[0024] Reference signs:

[0025] 100, display panel;

[0026] 110, display area;

[0027] 111, main display area;

[0028] 112, irregular display area;

[0029] 113, round-corner display area;

[0030] 114, first irregular display area;

[0031] 115, second irregular display area;

[0032] 120, non-display area;

[0033] 121, irregular non-display area;

[0034] 122, first irregular non-display area;

[0035] 123, light-transmitting hole;

[0036] 124, second irregular non-display area;

[0037] 130, pixel driving circuit;

[0038] 131, first type transistor;

[0039] 132, first gate;

[0040] 133, channel;

[0041] 134, second gate;

[0042] 140, first wire;

[0043] 150, substrate;

[0044] 160, second trace;

[0045] 161, first sub-trace;

[0046] 162, second sub-trace;

[0047] 170, third trace;

[0048] 180, bonding area;

[0049] 190, first semiconductor layer;

[0050] DVH, bias adjustment signal line;

[0051] X, first direction;

[0052] Y, second direction;

[0053] 200, display device. DETAILED DESCRIPTION

[0054] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided as non-limiting examples so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and descriptions of the same elements will not be repeated.

[0055] The terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are used to identify different components. In addition, in the description of the disclosure, the terms "upper", "lower", and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, which is only for the convenience of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the disclosure.

[0056] It should be noted that the features of the embodiments of the disclosure and the features in different embodiments can be combined with each other without conflict.

[0057] LTPO display panels combine the mainstream LTPS (Low Temperature Poly-silicon) transistor technology used in OLED (Organic Light-Emitting Diode) display panels with the IGZO (Indium-Gallium-Zinc-Oxide) transistor technology. LTPO display panels can achieve lower refresh rates and reduce power consumption, making them widely popular.

[0058] In related technologies, the hydrogen concentration in the IGZO transistors of LTPO display panels is relatively high. Existing bias adjustment signal lines have a blocking effect on the hydrogen in the IGZO transistors, preventing leakage current in the IGZO transistors and avoiding negative bias of the threshold voltage (Vth) of the IGZO transistors. This can avoid the problem of bright spots in the display area 110 of the LTPO display panel at low gray levels.

[0059] However, as Figure 1 As shown, the display panel includes a display area 110 and a non-display area 120. The display area 110 includes a main display area 111 and an irregular display area 112. The irregular display area 112 includes a rounded corner display area located at the edge of the display area 110 and areas located on both sides of the cutout inside the display area 110.

[0060] like Figure 2 and Figure 3 As shown, in the irregular display area 112 of the LTPO display panel, the wiring of the bias adjustment signal line DVH differs from that of the main display area 111. This difference in wiring of the bias adjustment signal line DVH in the irregular display area 112 leads to a decrease in the blocking effect of the bias adjustment signal line DVH on hydrogen elements within the IGZO transistor. This results in leakage current in the IGZO transistor within the irregular display area 112, causing a negative bias in the threshold voltage (Vth) of the IGZO transistor. Consequently, bright spots appear in the irregular display area 112 at low grayscale levels.

[0061] In LTPO display panels, if there is sufficient space in the non-display area 120 adjacent to the irregular display area 112, redundant pixels or sub-pixels can be added to the non-display area 120 to ensure that the wiring and aperture density of the IGZO transistors in the irregular display area 112 are consistent with those in the main display area 111, thereby avoiding the aforementioned problems. However, with the increasing demand for narrow bezels in display panels, the space in the non-display area 120 is limited, making it impossible to arrange redundant pixels or sub-pixels, thus making it impossible to avoid the problem of bright spots appearing in the irregular display area 112 at low grayscale levels.

[0062] In view of this, on the one hand, such as Figure 4 ,Figure 5 and Figure 6 As shown in FIG. 1, an embodiment of the present disclosure provides a display panel 100, which comprises a display area 110 and a non-display area 120, the non-display area 120 comprising a special-shaped non-display area 121, the edge of the special-shaped non-display area 121 comprising a curved portion. The display panel 100 further comprises a plurality of pixel driving circuits 130 and a first wire 140. The plurality of pixel driving circuits 130 are located in the display area 110 and arranged in a first direction X and a second direction Y, the first direction X and the second direction Y intersecting; the pixel driving circuit 130 comprises a first type of transistor 131, the first type of transistor 131 comprising an oxide transistor. The first wire 140 is at least located in the special-shaped non-display area 121; the material of the first wire 140 comprises titanium and molybdenum; the first wire 140 receives a fixed potential signal.

[0063] Specifically, when the display panel 100 is a rounded rectangle, the special-shaped non-display area 121 can comprise an R corner area located at the four rounded corner positions of the rounded rectangle and a cutout area located inside the display area 110. When the display panel 100 is a circle, the special-shaped non-display area 121 can comprise a non-display area 120 surrounding the display area 110. The display panel 100 can also be other shapes, and accordingly, the special-shaped non-display area 121 can also comprise other areas with curved edges, which are not limited in the present application.

[0064] Due to the existence of the special-shaped non-display area 121, part of the display area 110 is also special-shaped. In the special-shaped part of the display area 110, the distribution of the pixel driving circuits 130 will be different from other areas, and accordingly, the distribution of the bias adjustment signal lines electrically connected to each pixel driving circuit 130 will also be different from other areas. For example, the bias adjustment signal lines at the rounded corner positions of the display area 110 will be shorter than those in other areas, the bias adjustment signal lines on both sides of the cutout area of the display area 110 will not be connected due to the existence of the cutout area, and the bias adjustment signal lines on the same side of the cutout area can also be of different lengths according to the shape of the cutout. Therefore, the wiring of the bias adjustment signal lines near the edge of the display area 110 close to the special-shaped non-display area 121 is different from other parts of the display area 110. In addition, the oxide transistor (e.g. T4 and T5 transistors in FIG. 1) included in the pixel driving circuit 130 can be an IGZO transistor. The T5 transistor can be an N-type MOS transistor (MOS is the abbreviation of MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor). For the T5 transistor, the over scan signal S1N can be adjusted to be always low, and the first reference signal Vref1 can be gradually raised, so that the brightness of the bright spot of the display panel 100 is reduced, and thus it can be judged that the T5 transistor is leaking. Figure 6 ​

[0065] also, Figure 6 The pixel driving circuit 130 in this disclosure is merely an example, and the pixel driving circuit 130 of the display panel 100 may include various types, and is not limited thereto.

[0066] This embodiment provides a first trace 140 made of titanium and molybdenum in the irregular non-display area 121 of the display panel 100. Since titanium crystals grow laterally and molybdenum crystals grow vertically, the first trace 140 enhances the blocking effect on hydrogen elements in the oxide transistors near the edge of the display area 110 of the irregular non-display area 121, reducing leakage current in the oxide transistors and minimizing negative bias in the threshold voltage of the oxide transistors. This alleviates the problem of bright spots appearing at low grayscale levels in the display area 110 near the edge of the irregular non-display area 121. Furthermore, by having the first trace 140 receive a fixed potential signal, this embodiment prevents the first trace 140 from floating and avoids electrostatic discharge damage.

[0067] In some embodiments, such as Figure 7 As shown, the first type of transistor 131 includes a first gate 132, and a first trace 140 is disposed on the same layer as the first gate 132. The fact that the first trace 140 and the first gate 132 are disposed on the same layer does not mean that they are the same in absolute height, but rather that they are fabricated using the same film layer. In this embodiment, the first trace 140 is fabricated using the existing film layer of the first gate 132, which allows for the reuse of existing film layers and simplifies the fabrication process of the first trace 140.

[0068] In some embodiments, continue to refer to Figure 7 The display panel 100 includes a substrate 150 and a first semiconductor layer 190. The channel 133 of the first type transistor 131 is located in the first semiconductor layer 190, and the first gate 132 is located on the side of the first semiconductor layer 190 away from the substrate 150. Specifically, the material of the first semiconductor layer 190 can be IGZO (indium gallium zinc oxide), and the first gate 132 can be the top gate of the first type transistor 131.

[0069] In some embodiments, continue to refer to Figure 7 The first type of transistor 131 also includes a second gate 134, which is located on the side of the first semiconductor layer 190 near the substrate 150. Specifically, the first type of transistor 131 can be a dual-gate transistor, and the second gate 134 can be the bottom gate of the first type of transistor 131.

[0070] In some embodiments, continue to refer to Figure 5 and Figure 6The pixel driving circuit 130 comprises a driving transistor and a bias adjustment transistor, the bias adjustment transistor is electrically connected with the source and / or drain of the driving transistor, and the bias adjustment transistor is electrically connected with the second wire 160. The second wire 160 is located in the display area 110, the first wire 140 is electrically connected with the second wire 160; the second wire 160 transmits a bias adjustment signal, and the fixed potential signal comprises the bias adjustment signal.

[0071] The driving transistor can be a M3 transistor, and the bias adjustment transistor can be a M8 transistor. The source of the driving transistor M3 can be the second node N2, and the drain can be the third node N3; or the source of the driving transistor M3 can be the third node N3, and the drain can be the second node N2.

[0072] Specifically, in the pixel driving circuit 130, the driving transistor M3 is used to provide a driving current for the light emitting element, and the driving transistor M3 can determine the size of the driving current according to the gate potential, so as to adjust the light emitting brightness of the light emitting element by controlling the gate voltage of the driving transistor M3. In the case of long-time use, the pixel driving circuit 130 will be affected by the bias voltage due to the long-time voltage control of the driving transistor M3, which will cause the driving transistor M3 to be in a voltage bias state, thereby affecting the control effect of the light emitting element. Therefore, the pixel driving circuit 130 further comprises a bias adjustment transistor M8, which can pull up the source or drain potential of the driving transistor M3, i.e. the second node N2 or the third node N3, thereby improving the voltage bias state of the driving transistor M3.

[0073] Further, the control end of the bias adjustment transistor M8 is electrically connected with a bias voltage control signal line SPX, the first end of the bias adjustment transistor M8 is electrically connected with the second node N2, and the second end of the bias adjustment transistor M8 is electrically connected with a bias adjustment signal line DVH. The bias voltage control signal line SPX inputs a bias voltage control signal, and the bias adjustment signal line DVH inputs a bias adjustment signal. The bias voltage control signal comprises an enable level and a non-enable level, the enable level can make the bias adjustment transistor M8 conduct, and the non-enable level can make the bias adjustment transistor M8 turn off. When the bias voltage control signal line SPX controls the bias adjustment transistor M8 to conduct, the bias adjustment transistor M8 can transmit the bias adjustment signal transmitted by the bias adjustment signal line DVH to the control end of the driving transistor M3, i.e. the first node N1, so as to reset the bias state of the driving transistor M3, eliminate the influence of the data signal written in the last frame on the device characteristics (i.e. threshold voltage) of the driving transistor M3, and improve the voltage bias state of the driving transistor M3.

[0074] The second trace 160 may include a bias adjustment signal line DVH, which is connected to a bias adjustment signal. The bias adjustment signal line DVH extends along the first direction X in the display area 110 and is arranged along the second direction Y. Each bias adjustment signal line DVH is electrically connected to a row of pixel driving circuits 130 along the first direction X. The first trace 140 is also connected to the bias adjustment signal through electrical connection with the second trace 160, which prevents the first trace 140 from floating and prevents electrostatic discharge damage to the first trace 140.

[0075] In some embodiments, such as Figure 8 As shown, the display panel 100 also includes a third trace 170 and a bonding area 180 located in the non-display area 120. The bonding area 180 includes bonding terminals. The third trace 170 is electrically connected to the bonding terminals and to the second trace 160 and the first trace 140. At least a portion of the third trace 170 is disposed on a different layer from the first trace 140. Specifically, the third trace 170 extends in the non-display area 120 along a second direction Y. Each third trace 170 extending along the second direction Y is electrically connected to a second trace 160 extending along a first direction X. The third trace 170 is directly electrically connected to the first trace 140 or electrically connected to the first trace 140 through the second trace 160. The first trace 140 and the second trace 160 can receive a fixed potential signal through the third trace 170. The bonding area 180 includes a flexible circuit board or a driver chip, and the bonding terminals can be located on the flexible circuit board or the driver chip. The third trace 170 receives a fixed potential signal through the bonding terminals. At least a portion of the third trace 170 is disposed on a different layer from the first trace 140 to reduce the width of the non-display area 120, that is, to reduce the bezel width of the display panel 100.

[0076] In some embodiments, such as Figure 9 As shown, the display area 110 includes a main display area 111 and an irregular display area 112. The length of the irregular display area 112 in the first direction X is less than the length of the main display area 111 in the first direction X. The irregular display area 112 includes a rounded corner display area 113, the edge of which is curved away from the display area 110. The irregular non-display area 121 includes a first irregular non-display area 122 corresponding to the rounded corner display area 113, at least a portion of the first trace 140 is located in the first irregular non-display area 122. And / or, the display panel 100 also includes a light-transmitting hole 123, the irregular non-display area 121 includes a second irregular non-display area 124 located between the light-transmitting hole 123 and the display area 110, at least a portion of the first trace 140 is located in the second irregular non-display area 124. Since the irregular display area 112 includes rounded corner display area 113, the length of the irregular display area 112 in the first direction X is less than the length of the main display area 111 in the first direction X.

[0077] Due to the irregular shape of the rounded display area 113, the wiring condition of the bias adjustment signal line DVH in the rounded display area 113 is different from that in the main display area 111, which in turn causes the blocking effect of the bias adjustment signal line DVH on the hydrogen element in the oxide transistor in the rounded display area 113 to be poor. The first wire 140 is at least partially located in the first irregular non-display area 122 corresponding to the rounded display area 113, which can enhance the blocking effect on the hydrogen element in the oxide transistor in the rounded display area 113 close to the first irregular non-display area 122, thereby alleviating the problem of bright spots in the rounded display area 113 at low gray scale.

[0078] The light transmission hole 123 of the display panel 100 can be used to transmit natural light for front camera of the display panel 100, or to transmit infrared light for face recognition. Due to the existence of the light transmission hole 123, the display area 110 of the display panel 100 includes an irregular display area 112 around the light transmission hole 123. Accordingly, in the irregular display area 112 around the light transmission hole 123, the wiring condition of the bias adjustment signal line DVH is different from that in the main display area 111, which in turn causes the blocking effect of the bias adjustment signal line DVH on the hydrogen element in the oxide transistor in the irregular display area 112 around the light transmission hole 123 to be poor. At least part of the first wire 140 is located in the second irregular non-display area 124 between the light transmission hole 123 and the display area 110, which can enhance the blocking effect on the hydrogen element in the oxide transistor in the irregular display area 112 around the light transmission hole 123 close to the second irregular non-display area 124, thereby alleviating the problem of bright spots in the irregular display area 112 around the light transmission hole 123 at low gray scale.

[0079] In some embodiments, continuing to refer to Figure 9, at least part of the first wire 140 is located in the first irregular non-display area 122, the first wire 140 comprises a closed loop line, and a projection of the first wire 140 on the substrate 150 of the display panel 100 surrounds the display area 110; and / or, at least part of the first wire 140 is located in the second irregular non-display area 124, the first wire 140 comprises a closed loop line, and a projection of the first wire 140 on the substrate 150 of the display panel 100 surrounds a projection of the light-transmitting hole 123 on the substrate 150. The closed loop line of the first wire 140 in the embodiment can simplify the patterning design of the first wire 140 and reduce the preparation difficulty of the first wire 140; the projection of the first wire 140 on the substrate 150, at least part of which is located in the first irregular non-display area 122, surrounds the display area 110, which can avoid the problem of bright spots at low gray levels that may exist in the main display area 111, while increasing the electrostatic protection capability of the non-display area 120 near the main display area 111; the projection of the first wire 140 on the substrate 150, at least part of which is located in the second irregular non-display area 124, surrounds the projection of the light-transmitting hole 123 on the substrate 150, which can avoid the problem of bright spots at low gray levels of the irregular display area 112 near the second irregular non-display area 124, while increasing the electrostatic protection capability of the second irregular non-display area 124.

[0080] In some embodiments, as shown in Figure 10 , Figure 11 and Figure 12 , the first wire 140 is located in the first irregular non-display area 122, the first wire 140 comprises an independent arc line corresponding to each first irregular non-display area 122, and the center direction of the arc line is towards the round-cornered display area 113; and / or, the first wire 140 is located in the second irregular non-display area 124, the first wire 140 comprises an independent arc line corresponding to the bending area of each second irregular non-display area 124, and the center direction of the arc line is away from the irregular display area 112 near the bending area. The independent arc line of the first wire 140 located in the first irregular non-display area 122 in the embodiment can reduce the material use of the first wire 140, while avoiding the first wire 140 occupying the space of the non-display area 120 and reducing the frame width of the display panel 100. The independent arc line of the first wire 140 located in the second irregular non-display area 124 in the embodiment can reduce the material use of the first wire 140, while avoiding the first wire 140 occupying the space of the second irregular non-display area 124, reducing the hole digging area of the display panel 100, and improving the screen-to-body ratio of the display panel 100.

[0081] In some embodiments, as shown in Figure 6 and Figure 13As shown, the irregular display area 112 includes a first irregular display area 114 and a second irregular display area 115 located on both sides of the light-transmitting hole 123 along the first direction X; the pixel driving circuit 130 includes a driving transistor and a bias adjusting transistor, the bias adjusting transistor is electrically connected with the source and / or drain of the driving transistor, and the bias adjusting transistor is electrically connected with the second wire 160; the second wire 160 includes a first sub-wire 161 located in the first irregular display area 114 and a second sub-wire 162 located in the second irregular display area 115, and the first sub-wire 161 and the second sub-wire 162 are electrically connected through the first wire 140 located in the second irregular non-display area 124. The first sub-wire 161 and the second sub-wire 162 of the embodiment are electrically connected through the first wire 140 located in the second irregular non-display area 124, which can avoid the problems that the first sub-wire 161 and the second sub-wire 162 need to be separately connected with the third wire 170 in the non-display area 120 to make the first sub-wire 161 and the second sub-wire 162 respectively access the fixed potential signal, so as to reduce the number of the third wire 170 in the non-display area 120, and further reduce the frame width of the display panel 100.

[0082] In some embodiments, for example, with continued reference to Figure 11 The distance between the edge of the display area 110 and the first wire 140 in the irregular non-display area 121 is H1, and the distance between the edge of the display area 110 and the first wire 140 in the irregular non-display area 121 is H2; wherein H1

[0083] In some embodiments, for example, with continued reference to Figure 11The distance between the edge of the irregular non-display area 121 near the display area and the first trace 140 is H1, where H1 ≤ 30 micrometers. Specifically, the value of H1 can be any one of 5 micrometers, 10 micrometers, 15 micrometers, 20 micrometers, 25 micrometers, or 30 micrometers, and this disclosure does not impose any limitation on this. The above-described arrangement in this embodiment allows the first trace 140 to be close to the oxide transistor located within the display area 110, thereby improving the blocking effect of the first trace 140 on hydrogen elements within the oxide transistor.

[0084] In some embodiments, the first trace 140 includes a molybdenum metal film and a titanium metal film. The molybdenum metal film is located on the side of the titanium metal film closer to the light-emitting direction of the display panel 100, and the ratio of the thickness of the molybdenum metal film to the thickness of the titanium metal film is in the range of 4 to 8. Specifically, since the first trace 140 and the second trace 160 are disposed in the same layer, that is, the first trace 140 and the second trace 160 are prepared using the same metal film layer. The ratio of the thickness of the molybdenum metal film to the thickness of the titanium metal film can be any value of 4, 5, 6, 7 or 8, and this disclosure does not limit this. The above-mentioned arrangement in this embodiment can further improve the blocking effect of the first trace 140 on hydrogen elements in the oxide transistor located in the display area 110 near the irregular non-display area 121, based on the crystal growth characteristics of the molybdenum metal film and the titanium metal film.

[0085] In some embodiments, the linewidth of the first trace 140 is 3 micrometers to 10 micrometers. Specifically, the linewidth of the first trace 140 can be any value among 3 micrometers, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, 9 micrometers, or 10 micrometers, and this disclosure does not limit this. The above-described configuration of this embodiment can further improve the blocking effect of the first trace 140 on hydrogen elements in the oxide transistor located near the irregular non-display area 121, while avoiding excessive occupation of the space of the non-display area 120 and reducing the bezel width of the display panel 100.

[0086] In some embodiments, the linewidth of the second trace 160 is 2 to 3 micrometers. The above-described configuration of this embodiment can further improve the blocking effect of the second trace 160 on hydrogen elements in the oxide transistor located in the display area 110 (e.g., rounded corner display area 113, first irregular display area 114, or second irregular display area 115) near the irregular non-display area 121.

[0087] On the other hand, such as Figure 14 As shown, embodiments of this disclosure also provide a display device 200, including the display panel described above. The display device 200 can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0088] The specific embodiments and technical effects of the display device of the present disclosure can refer to the specific embodiments of the display panel described above, and the repeated parts will not be described again.

[0089] In summary, the display panel and the display device of the present disclosure can set the first trace including titanium metal and molybdenum metal in the special-shaped non-display area of the display panel. Due to the lateral growth of the titanium metal crystal and the vertical growth of the molybdenum metal crystal, the first trace can strengthen the blocking effect of hydrogen elements in the oxide transistor near the edge of the display area of the special-shaped non-display area, reduce the oxide transistor leakage current, and reduce the negative shift of the threshold voltage of the oxide transistor, thereby alleviating the problem of bright spots at low gray levels near the edge of the display area of the special-shaped non-display area of the display panel. By making the first trace receive a fixed potential signal, the first trace can be prevented from floating and being electrostatically damaged.

[0090] The above is a further detailed description of the present disclosure in combination with specific optional embodiments, and the specific implementation of the present disclosure cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the present disclosure belongs, without departing from the concept of the present disclosure, a number of simple deductions or substitutions can be made, which should be considered as falling within the protection scope of the present disclosure.

Claims

1. A display panel, characterized by, The display panel comprises a display area and a non-display area, the non-display area comprises a special-shaped non-display area, and an edge of the special-shaped non-display area comprises a curved portion; The display panel further comprises: a plurality of pixel driving circuits, the plurality of pixel driving circuits are located in the display area and are arranged in an array along a first direction and a second direction, the first direction and the second direction intersect; the pixel driving circuit comprises a first type of transistor, and the first type of transistor comprises an oxide transistor; a first wire, the first wire is located at least in the special-shaped non-display area; a material of the first wire comprises titanium and molybdenum; the first wire receives a fixed potential signal; the pixel driving circuit comprises a driving transistor and a bias adjusting transistor, the bias adjusting transistor is electrically connected with a source electrode and / or a drain electrode of the driving transistor, and the bias adjusting transistor is electrically connected with a second wire; the second wire is located in the display area, the first wire is electrically connected with the second wire; the second wire transmits a bias adjusting signal, and the fixed potential signal comprises the bias adjusting signal.

2. The display panel of claim 1, wherein, the first type of transistor comprises a first gate electrode, and the first wire is arranged in the same layer as the first gate electrode.

3. The display panel of claim 2, wherein, the display panel comprises a substrate and a first semiconductor layer, a channel of the first type of transistor is located in the first semiconductor layer, and the first gate electrode is located on a side of the first semiconductor layer away from the substrate.

4. The display panel of claim 3, wherein, the first type of transistor further comprises a second gate electrode, and the second gate electrode is located on a side of the first semiconductor layer close to the substrate.

5. The display panel of claim 1, wherein, the display panel further comprises a third wire and a binding area located in the non-display area; the binding area comprises a binding terminal, the third wire is electrically connected with the binding terminal, and is electrically connected with the second wire and the first wire; at least part of the third wire is arranged in a layer different from the first wire.

6. The display panel of claim 1, wherein the display area comprises a main display area and a special-shaped display area, a length of the special-shaped display area in the first direction is less than a length of the main display area in the first direction; the special-shaped display area comprises a round-corner display area, an edge of the round-corner display area is curved away from the display area; the special-shaped non-display area comprises a first special-shaped non-display area corresponding to the round-corner display area, and at least part of the first wire is located in the first special-shaped non-display area; and / or, the display panel further comprises a light-transmitting hole, the special-shaped non-display area comprises a second special-shaped non-display area located between the light-transmitting hole and the display area, and at least part of the first wire is located in the second special-shaped non-display area.

7. The display panel of claim 6, wherein at least part of the first wire is located in the first special-shaped non-display area, the first wire comprises a closed loop wire, and a normal projection of the first wire on a substrate of the display panel surrounds the display area; and / or, at least part of the first wire is located in the second special-shaped non-display area, the first wire comprises a closed loop wire, and a normal projection of the first wire on the substrate of the display panel surrounds a normal projection of the light-transmitting hole on the substrate.

8. The display panel of claim 6, wherein, The irregular display area includes a first irregular display area and a second irregular display area located on two sides of the light transmission hole along a first direction; The pixel driving circuit includes a driving transistor and a bias adjusting transistor, the bias adjusting transistor is electrically connected with the source and / or drain of the driving transistor, and the bias adjusting transistor is electrically connected with a second trace; The second trace includes a first sub-trace located in the first irregular display area and a second sub-trace located in the second irregular display area, and the first sub-trace and the second sub-trace are electrically connected by the first trace located in the second irregular non-display area.

9. The display panel of claim 1, wherein, The distance between the irregular non-display area close to the edge of the display area and the first trace is H1, and the distance between the irregular non-display area away from the edge of the display area and the first trace is H2; wherein H1 10. The display panel of claim 1, wherein, The distance between the irregular non-display area close to the edge of the display area and the first trace is H1, and H1≤30 microns.

11. The display panel of claim 1, wherein, The first trace includes a molybdenum metal film and a titanium metal film, the molybdenum metal film is located on the side of the titanium metal film close to the light emission direction of the display panel, and the ratio of the film thickness of the molybdenum metal film and the titanium metal film ranges from 4 to 8.

12. The display panel of claim 1, wherein, The line width of the first trace is 3 microns to 10 microns.

13. A display device comprising: The display panel according to any one of claims 1 to 12.

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