Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes a plurality of pixel driving circuits; wherein each pixel driving circuit (PDC) of the plurality of pixel driving circuits includes a driving transistor (Td), a first light emitting control transistor (T3), and a third reset transistor (Tr3); an active layer (ACTd, ACT3, ACTr3) of the driving transistor (Td), the first light emitting control transistor (T3), and the third reset transistor (Tr3) is located in a first semiconductor material layer (SML1); a first electrode of the driving transistor (Td), a second electrode of the first light emitting control transistor (T3), and a second electrode (D3) of the third reset transistor (Tr3) are located in the first semiconductor material layer (SML1); the first electrode (Sd) of the driving transistor (Td), the second electrode (D3) of the first light emitting control transistor (T3), and the second electrode (Dr) of the third reset transistor (Tr3) are part of an integral structure; and the first electrode (Sd) of the driving transistor (Td), the second electrode (D3) of the first light emitting control transistor (T3), and the second electrode (Dr3) of the third reset transistor (Tr3) are connected to each other through one or more portions of the first semiconductor material layer (SML1).

Description

TECHNICAL FIELD

[0001] The present application relates to display technology, and in particular to an array substrate and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) display is one of the hotspots in the field of flat panel display research today. The OLED is driven by a driving current that needs to be kept constant to control the brightness. An OLED display panel includes a plurality of pixel units configured with pixel driving circuits arranged in a plurality of rows and a plurality of columns. SUMMARY

[0003] In a first aspect, the present application provides an array substrate, comprising a plurality of pixel driving circuits; wherein each pixel driving circuit of the plurality of pixel driving circuits comprises a driving transistor, a first light emitting control transistor, and a third reset transistor; an active layer of the driving transistor, the first light emitting control transistor, and the third reset transistor is located in a first semiconductor material layer; a first electrode of the driving transistor, a second electrode of the first light emitting control transistor, and a second electrode of the third reset transistor are located in the first semiconductor material layer; the first electrode of the driving transistor, the second electrode of the first light emitting control transistor, and the second electrode of the third reset transistor are part of an integral structure; and the first electrode of the driving transistor, the second electrode of the first light emitting control transistor, and the second electrode of the third reset transistor are connected to each other through one or more parts of the first semiconductor material layer.

[0004] In some embodiments of the present application, the array substrate further comprises: a first light emitting control electrode pad located on the first semiconductor material layer; and a plurality of light emitting control signal lines located on a side of the first light emitting control electrode pad away from the first semiconductor material layer; wherein the first light emitting control electrode pad comprises a gate of the first light emitting control transistor; and each light emitting control signal line of the plurality of light emitting control signal lines is connected to the first light emitting control electrode pad through a via.

[0005] In some embodiments of the present application, the array substrate further comprises: a second light emitting control electrode pad located on the first semiconductor material layer; and a plurality of light emitting control signal lines located on a side of the second light emitting control electrode pad away from the first semiconductor material layer; wherein each pixel driving circuit further comprises a second light emitting control transistor; the second light emitting control electrode pad comprises a gate of the second light emitting control transistor; and each light emitting control signal line of the plurality of light emitting control signal lines is connected to the second light emitting control electrode pad through a via.

[0006] In some embodiments of the present disclosure, the respective pixel driving circuit further comprises a storage capacitor comprising a first capacitor electrode and a second capacitor electrode; the first light emitting control electrode pad and the first capacitor electrode are located at a first gate metal layer; the second capacitor electrode is located at a second gate metal layer, the second gate metal layer is located at a side of the first gate metal layer away from the first semiconductor material layer; and the plurality of light emitting control signal lines are located at a first signal line layer, the first signal line layer is located at a side of the second gate metal layer away from the first gate metal layer.

[0007] In some embodiments of the present disclosure, the respective pixel driving circuit further comprises a compensation transistor; an active layer of the compensation transistor is located at a second semiconductor material layer, the second semiconductor material layer is located at a side of the second gate metal layer away from the first gate metal layer; at least a part of a gate of the compensation transistor is located at a third gate metal layer, the third gate metal layer is located at a side of the second semiconductor material layer away from the second gate metal layer; and the plurality of light emitting control signal lines are located at the first signal line layer, the first signal line layer is located at a side of the third gate metal layer away from the second semiconductor material layer.

[0008] In some embodiments of the present disclosure, the array substrate further comprises: a first voltage connection pad and a plurality of first voltage supply lines; wherein the active layer of the first light emitting control transistor, the first voltage connection pad and the plurality of first voltage supply lines are located at three different layers; and a respective first voltage supply line of the plurality of first voltage supply lines is connected to the first voltage connection pad, and the first voltage connection pad is connected to a first electrode of the first light emitting control transistor.

[0009] In some embodiments of the present disclosure, a projection of the second electrode of the third reset transistor on a substrate substrate at least partially overlaps with a projection of the first voltage connection pad on the substrate substrate.

[0010] In some embodiments of the present disclosure, the array substrate further comprises: a plurality of light emitting control signal lines; wherein each light emitting control signal line of the plurality of light emitting control signal lines is configured to provide a light emitting control signal to a gate of the first light emitting control transistor; and the first voltage connection pad and the plurality of light emitting control signal lines are located at the same layer.

[0011] In some embodiments of the present disclosure, the first voltage connection pad is connected to first electrodes of first light emitting control transistors in two adjacent pixel driving circuits located at the same row.

[0012] In some embodiments of the present disclosure, each of the first voltage supply lines comprises a main body and a plurality of extensions extending away from the main body; each of the plurality of extensions is connected to the first voltage connection pad; and the first voltage connection pad is connected to the first electrode of the first light-emitting control transistor.

[0013] In some embodiments of the present disclosure, each of the pixel driving circuits further comprises a compensation transistor; an active layer of the compensation transistor is located in a second semiconductor material layer, the second semiconductor material layer is located on a side of the first semiconductor material layer away from the substrate; a projection of the main body on the substrate substantially covers a projection of the active layer of the compensation transistor on the substrate.

[0014] In some embodiments of the present disclosure, a projection of the main body on the substrate substantially covers projections of the first electrode, the active layer and the second electrode of the compensation transistor on the substrate.

[0015] In some embodiments of the present disclosure, each of the pixel driving circuits further comprises a first reset transistor and a second reset transistor; wherein the array substrate further comprises: a plurality of third reset signal lines configured to provide a third reset signal to a first electrode of the third reset transistor in the plurality of pixel driving circuits; and a plurality of first reset signal lines configured to provide a first reset signal to a first electrode of the first reset transistor in the plurality of pixel driving circuits, and / or a plurality of second reset signal lines configured to provide a second reset signal to a first electrode of the second reset transistor in the plurality of pixel driving circuits; wherein the plurality of first reset signal lines, the plurality of second reset signal lines and the plurality of third reset signal lines extend along a direction substantially parallel to the first direction.

[0016] In some embodiments of the present disclosure, the array substrate further comprises: a plurality of third reset signal lines configured to provide a third reset signal to a first electrode of a third reset transistor in the plurality of pixel driving circuits; a plurality of first low voltage supply lines; a plurality of fourth reset signal lines; a plurality of fifth reset signal lines; a plurality of sixth reset signal lines; and a plurality of second low voltage supply lines; wherein the plurality of third reset signal lines and the plurality of first low voltage supply lines extend along a direction substantially parallel to a first direction; the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines, and the plurality of second low voltage supply lines extend along a direction substantially parallel to a second direction; the second direction is different from the first direction; and the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines, and the plurality of second low voltage supply lines are located on the same layer and on a side of the plurality of third reset signal lines and the plurality of first low voltage supply lines away from the first semiconductor material layer.

[0017] In some embodiments of the present disclosure, the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines, and the plurality of second low voltage supply lines are arranged alternately.

[0018] In some embodiments of the present disclosure, the plurality of pixel driving circuits are arranged into J columns, J being a positive integer; the J columns include an (8j-7)th column among the J columns, an (8j-6)th column among the J columns, an (8j-5)th column among the J columns, an (8j-4)th column among the J columns, an (8j-3)th column among the J columns, an (8j-2)th column among the J columns, an (8j-1)th column among the J columns, and an (8j)th column among the J columns, j being a positive integer, 1≤j≤(J / 8); one of a respective fourth reset signal line among the plurality of fourth reset signal lines, a respective fifth reset signal line among the plurality of fifth reset signal lines, a respective sixth reset signal line among the plurality of sixth reset signal lines, and a respective second low-voltage supply line among the plurality of second low-voltage supply lines is located between the (8j-7)th column and the (8j-6)th column; another of the respective fourth reset signal line, the respective fifth reset signal line, the respective sixth reset signal line, and the respective second low-voltage supply line is located between the (8j-5)th column and the (8j-4)th column; a further one of the respective fourth reset signal line, the respective fifth reset signal line, the respective sixth reset signal line, and the respective second low-voltage supply line is located between the (8j-3)th column and the (8j-2)th column; and a still further one of the respective fourth reset signal line, the respective fifth reset signal line, the respective sixth reset signal line, and the respective second low-voltage supply line is located between the (8j-1)th column and the (8j)th column.

[0019] In some embodiments of the present disclosure, the array substrate further includes: a first respective anode, a second respective anode, a third respective anode, and a fourth respective anode; wherein the first respective anode is an anode of a sub-pixel of a first color, the second respective anode is an anode of a sub-pixel of a second color, the third respective anode and the fourth respective anode are anodes of two sub-pixels of a third color; a normal projection of the third respective anode on the substrate substrate at least partially overlaps a normal projection of two adjacent second voltage supply lines among the plurality of second voltage supply lines on the substrate substrate, and at least partially overlaps a normal projection of one of a respective fourth reset signal line, a respective fifth reset signal line, a respective sixth reset signal line, and a respective second low-voltage supply line on the substrate substrate; and a normal projection of the fourth respective anode on the substrate substrate at least partially overlaps a normal projection of two adjacent second voltage supply lines among the plurality of second voltage supply lines on the substrate substrate, and at least partially overlaps a normal projection of one of a respective fourth reset signal line, a respective fifth reset signal line, a respective sixth reset signal line, and a respective second low-voltage supply line on the substrate substrate.

[0020] In some embodiments of the present disclosure, a projection of at least one of the first respective anode, the second respective anode, the third respective anode, or the fourth respective anode on the substrate substrate at least partially overlaps with a projection of the second electrode of the third reset transistor on the substrate substrate.

[0021] In a second aspect, the present disclosure provides an array substrate comprising a plurality of pixel driving circuits, wherein each pixel driving circuit of the plurality of pixel driving circuits comprises a second node connection line, a first light emitting control transistor, a third reset transistor, and a second node connection line; the second node connection line is connected to a second electrode of the first light emitting control transistor and connected to a second electrode of the third reset transistor; and the second node connection line is located in the same layer as active layers of the first light emitting control transistor and the third reset transistor.

[0022] In some embodiments of the present disclosure, the array substrate further comprises a plurality of light emitting control signal lines; wherein each light emitting control signal line of the plurality of light emitting control signal lines is configured to provide a control signal to a gate of the first light emitting control transistor; and the plurality of light emitting control signal lines are spaced apart from the second node connection line by at least three insulating layers.

[0023] In some embodiments of the present disclosure, the each pixel driving circuit further comprises a first node connection line, a storage capacitor, and a compensation transistor; the first node connection line is connected to a first capacitor electrode of the storage capacitor and connected to a first electrode of the compensation transistor; and the plurality of light emitting control signal lines and the first node connection line are located in the same layer.

[0024] In a third aspect, the present disclosure provides a display device comprising the array substrate and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF DRAWINGS

[0025] According to various disclosed embodiments, the following drawings are merely examples for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0026] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0027] Figure 2A is a circuit diagram showing a structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0028] Figure 2B is a timing diagram showing an operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0029] Figure 3AFIG. 1 is a schematic diagram illustrating a structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0030] Figure 3B FIG. 2 is a schematic diagram illustrating a structure of a first semiconductor material layer in an array substrate according to some embodiments of the present disclosure. Figure 3A FIG. 3 is a schematic diagram illustrating a structure of a first gate metal layer in an array substrate according to some embodiments of the present disclosure.

[0031] Figure 3C FIG. 4 is a schematic diagram illustrating a structure of a second gate metal layer in an array substrate according to some embodiments of the present disclosure. Figure 3A FIG. 5 is a schematic diagram illustrating an arrangement of pixel driving circuits of an array substrate according to some embodiments of the present disclosure.

[0032] Figure 3D FIG. 6 is a schematic diagram illustrating a structure of a second semiconductor material layer in an array substrate according to some embodiments of the present disclosure. Figure 3A FIG. 7 is a schematic diagram illustrating a structure of a third gate metal layer in an array substrate according to some embodiments of the present disclosure.

[0033] Figure 3E FIG. 8 is a schematic diagram illustrating a structure of a passivation layer in an array substrate according to some embodiments of the present disclosure. Figure 3A FIG. 9 is a schematic diagram illustrating a structure of a first signal line layer in an array substrate according to some embodiments of the present disclosure.

[0034] Figure 3F FIG. 10 is a schematic diagram illustrating a structure of a first planarization layer in an array substrate according to some embodiments of the present disclosure. Figure 3A FIG. 11 is a schematic diagram illustrating a structure of a second signal line layer in an array substrate according to some embodiments of the present disclosure.

[0035] Figure 3G FIG. 12 is a schematic diagram illustrating a structure of a second planarization layer in an array substrate according to some embodiments of the present disclosure. Figure 3A FIG. 13 is a schematic diagram illustrating a structure of a third planarization layer in an array substrate according to some embodiments of the present disclosure.

[0036] Figure 3H FIG. 14 is a schematic diagram illustrating a structure of a fourth planarization layer in an array substrate according to some embodiments of the present disclosure. Figure 3A FIG. 15 is a schematic diagram illustrating a structure of a fifth planarization layer in an array substrate according to some embodiments of the present disclosure.

[0037] Figure 3I FIG. 16 is a schematic diagram illustrating a structure of a sixth planarization layer in an array substrate according to some embodiments of the present disclosure. Figure 3A FIG. 17 is a schematic diagram illustrating a structure of a seventh planarization layer in an array substrate according to some embodiments of the present disclosure.

[0038] Figure 3J FIG. 18 is a schematic diagram illustrating a structure of an eighth planarization layer in an array substrate according to some embodiments of the present disclosure. Figure 3A FIG. 19 is a schematic diagram illustrating a structure of a ninth planarization layer in an array substrate according to some embodiments of the present disclosure.

[0039] Figure 3K FIG. 20 is a schematic diagram illustrating a structure of a tenth planarization layer in an array substrate according to some embodiments of the present disclosure. Figure 3A FIG. 21 is a schematic diagram illustrating a structure of a first flat layer in an array substrate according to some embodiments of the present disclosure.

[0040] Figure 3L FIG. 22 is a schematic diagram illustrating a structure of a second flat layer in an array substrate according to some embodiments of the present disclosure. Figure 3A FIG. 23 is a schematic diagram illustrating a structure of a third flat layer in an array substrate according to some embodiments of the present disclosure.

[0041] Figure 3M FIG. 24 is a schematic diagram illustrating a structure of a fourth flat layer in an array substrate according to some embodiments of the present disclosure.Figure 3A schematic diagram of a structure of a second planarization layer in an array substrate shown in

[0042] Figure 3N is a schematic diagram showing Figure 3A schematic diagram of a structure of a third signal line layer in an array substrate shown in

[0043] Figure 3O is a schematic diagram showing Figure 3A schematic diagram of a structure of an anode layer in an array substrate shown in

[0044] Figure 4A is a cross-sectional view along Figure 3A line A-A' in

[0045] Figure 4B is a cross-sectional view along Figure 3A line B-B' in

[0046] Figure 5 shows a voltage supply path in an array substrate according to some embodiments of the present disclosure.

[0047] Figure 6 is a schematic diagram showing a structure of a respective first voltage supply line in an array substrate according to some embodiments of the present disclosure.

[0048] Figure 7 is a schematic diagram showing Figure 3A a structure of a second semiconductor material layer and a respective first voltage supply line in an array substrate shown in

[0049] Figure 8A is a schematic diagram showing a structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0050] Figure 8B is a schematic diagram showing Figure 8A an arrangement of a pixel driving circuit in an array substrate shown in

[0051] Figure 8C is a schematic diagram showing Figure 8A a structure of a first semiconductor material layer in an array substrate shown in

[0052] Figure 8D is a schematic diagram showing Figure 8A a structure of a first gate metal layer in an array substrate shown in

[0053] Figure 8E is a schematic diagram showing Figure 8A a structure of a second gate metal layer in an array substrate shown in

[0054] Figure 8F is a schematic diagram showingFigure 8A schematic diagram of the structure of the second semiconductor material layer in the array substrate shown in FIG. 2B.

[0055] Figure 8G is a schematic diagram of the structure of the third gate metal layer in the array substrate shown in FIG. 2C. Figure 8A

[0056] Figure 8H is a schematic diagram of the structure of the passivation layer in the array substrate shown in FIG. 2D. Figure 8A

[0057] Figure 8I is a schematic diagram of the structure of the first signal line layer in the array substrate shown in FIG. 2E. Figure 8A

[0058] Figure 8J is a schematic diagram of the structure of the first planarization layer in the array substrate shown in FIG. 2F. Figure 8A

[0059] Figure 8K is a schematic diagram of the structure of the second signal line layer in the array substrate shown in FIG. 2G. Figure 8A

[0060] Figure 8L is a schematic diagram of the structure of the second planarization layer in the array substrate shown in FIG. 2H. Figure 8A

[0061] Figure 8M is a schematic diagram of the structure of the third signal line layer in the array substrate shown in FIG. 2I. Figure 8A

[0062] Figure 8N is a schematic diagram of the structure of the anode layer in the array substrate shown in FIG. 2J. Figure 8A

[0063] Figure 8O is a schematic diagram of the structure of the third signal line layer and the anode layer in the array substrate shown in FIG. 2K. Figure 8A

[0064] Figure 8P is a schematic diagram of the structure of the first semiconductor material layer and the anode layer in the array substrate shown in FIG. 2L. Figure 8A

[0065] shows a first interconnect reset signal network in some embodiments of the present disclosure. Figure 9A

[0066] shows a first interconnect reset signal network in some embodiments of the present disclosure. Figure 9B

[0067] Figure 10A ​​​​​​​​​​A second interconnect reset signal network in some embodiments according to the present disclosure is shown.

[0068] Figure 10B A second interconnect reset signal network in some embodiments according to the present disclosure is shown.

[0069] Figure 11 A third interconnect reset signal network in some embodiments according to the present disclosure is shown.

[0070] Figure 12 An interconnect low voltage supply network in some embodiments according to the present disclosure is shown.

[0071] Figure 13 is a schematic diagram showing Figure 3A is a schematic diagram showing a structure of a first semiconductor material layer in an array substrate shown in DETAILED DESCRIPTION

[0072] The present disclosure will now be described in greater particularity with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is merely illustrative and is in no way limiting. It is not exhaustive or limited to the precise forms disclosed.

[0073] The present disclosure provides, among other things, an array substrate and a display device that substantially overcome one or more problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits. Optionally, each pixel driving circuit of the plurality of pixel driving circuits includes a driving transistor, a data write transistor, a first light emitting control transistor, and a third reset transistor. Optionally, an active layer of the driving transistor, the data write transistor, the first light emitting control transistor, and the third reset transistor is located at a first semiconductor material layer. Optionally, a second electrode of the data write transistor, a first electrode of the driving transistor, a second electrode of the first light emitting control transistor, and a second electrode of the third reset transistor are located at the first semiconductor material layer. Optionally, the second electrode of the data write transistor, the first electrode of the driving transistor, the second electrode of the first light emitting control transistor, and the second electrode of the third reset transistor are part of a unitary structure. Optionally, the second electrode of the data write transistor, the first electrode of the driving transistor, the second electrode of the first light emitting control transistor, and the second electrode of the third reset transistor are connected to each other by one or more portions of the first semiconductor material layer.

[0074] Various suitable pixel drive circuits can be used in the array substrate described in the present disclosure. Examples of suitable drive circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each of the plurality of pixel drive circuits is an 8T1C drive circuit. Various suitable light emitting elements can be used in the array substrate described in the present disclosure. Examples of suitable light emitting elements include organic light emitting diodes, quantum dot light emitting diodes, and micro light emitting diodes. Optionally, the light emitting element is a micro light emitting diode. Optionally, the light emitting element is an organic light emitting diode including an organic light emitting layer.

[0075] Figure 1 is a plan view of an array substrate in some embodiments according to the present disclosure. Referring to Figure 1 , the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes electronic components, e.g., including a light emitting element. In one example, the light emitting element is driven by a corresponding pixel drive circuit PDC. The array substrate includes a plurality of first gate lines (e.g., a corresponding first gate line GL1), a plurality of second gate lines (e.g., a corresponding second gate line GL2), a plurality of data lines (e.g., a corresponding data line DL), a plurality of high voltage supply lines (e.g., a corresponding high voltage supply line Vdd), and a plurality of low voltage supply lines (e.g., a corresponding low voltage supply line Vss). Each sub-pixel Sp emits light driven by a corresponding pixel drive circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the corresponding pixel drive circuit PDC connected to an anode of the light emitting element through a corresponding high voltage supply line Vdd in the plurality of high voltage supply lines; a low voltage signal (e.g., a VSS signal) is input to a cathode of the light emitting element through a low voltage supply line. The voltage difference between the high voltage signal (e.g., a VDD signal) and the low voltage signal (e.g., a VSS signal) is a driving voltage AV, which drives the light emitting element to emit light.

[0076] Figure 2A is a circuit diagram showing the structure of a pixel drive circuit in some embodiments according to the present disclosure. Referring to Figure 2AIn some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a respective second reset control signal line rst2 of a plurality of second reset control signal lines, a first electrode connected to a respective second reset signal line Vint2 of a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a respective first gate line GL1 of a plurality of first gate lines, a first electrode connected to a respective data line DL of a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a respective first reset control signal line rst1 of a plurality of first reset control signal lines, a first electrode connected to a respective third reset signal line Vint3 of a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; a second transistor T2 having a gate connected to a respective second gate line GL2 of a plurality of second gate lines, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and a gate of the driving transistor Td, and a second electrode connected to a second electrode of the driving transistor Td; a third transistor T3 having a gate connected to a respective emission control signal line em of a plurality of emission control signal lines, a first electrode connected to a respective voltage supply line Vdd of a plurality of voltage supply lines, and a second electrode connected to a first electrode of the driving transistor Td and a second electrode of the first transistor T1; a fourth transistor T4 having a gate connected to a respective emission control signal line em of a plurality of emission control signal lines, a first electrode connected to a second electrode of the driving transistor Td and the second transistor T2, and a second electrode connected to an anode of the light emitting element LE; and a first reset transistor Tr1 having a gate connected to a respective first reset control signal line rst1 of a plurality of first reset control signal lines, a first electrode connected to a respective first reset signal line Vint1 of a plurality of first reset signal lines, and a second electrode connected to a second electrode of the fourth transistor T4 and an anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to a respective voltage supply line and a first electrode of the third transistor T3.

[0077] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data write transistor (e.g., the first transistor T1), a compensation transistor (e.g., the second transistor T2), two emission control transistors (e.g., the third transistor T3 and the fourth transistor T4), and three reset transistors (e.g., the first reset transistor Tr1, the second reset transistor Tr2, and the third reset transistor Tr3).

[0078] As used herein, the first electrode or the second electrode refers to one of the first terminal and the second terminal of the transistor, the first terminal and the second terminal being connected to the active layer of the transistor. The direction of the current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal, and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal, and the first electrode is configured to output an output signal.

[0079] The pixel driving circuit further includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light emitting element LE.

[0080] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a respective first sub-pixel, a respective second sub-pixel, and a respective third sub-pixel. Optionally, a respective pixel of the array substrate includes a respective first sub-pixel, a respective second sub-pixel, and a respective third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes an S1-S2-S3 format repeating array, where S1 represents a respective first sub-pixel, S2 represents a respective second sub-pixel, and S3 represents a respective third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, where C1 represents a respective first sub-pixel of a first color, C2 represents a respective second sub-pixel of a second color, and C3 represents a respective third sub-pixel of a third color. In another example, the C1-C2-C3 format is an R-G-B format, where the respective first sub-pixel is a red sub-pixel, the respective second sub-pixel is a green sub-pixel, and the respective third sub-pixel is a blue sub-pixel.

[0081] In another example, the array of the plurality of sub-pixels comprises a S1-S2-S3-S4 format repeating array, where S1 represents a respective first sub-pixel, S2 represents a respective second sub-pixel, S3 represents a respective third sub-pixel, and S4 represents a respective fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents a respective first sub-pixel of a first color, C2 represents a respective second sub-pixel of a second color, C3 represents a respective third sub-pixel of a third color, and C4 represents a respective fourth sub-pixel of a fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, where C1 represents a respective first sub-pixel of a first color, C2 represents a respective second sub-pixel of a second color, C3 represents a respective third sub-pixel of a third color, and C2' represents a respective fourth sub-pixel of a second color. In another example, the C1-C2-C3-C2' format is a R-G-B-G format, where the respective first sub-pixel is a red sub-pixel, the respective second sub-pixel is a green sub-pixel, the respective third sub-pixel is a blue sub-pixel, and the respective fourth sub-pixel is a green sub-pixel.

[0082] In some embodiments, the minimum repeating unit of the plurality of sub-pixels of the array substrate comprises a respective first sub-pixel, a respective second sub-pixel, and a respective third sub-pixel. Optionally, each of the respective first sub-pixel, the respective second sub-pixel, and the respective third sub-pixel comprises a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0083] In alternative embodiments, the minimum repeating unit of the plurality of sub-pixels of the array substrate comprises a respective first sub-pixel, a respective second sub-pixel, a respective third sub-pixel, and a respective fourth sub-pixel. Optionally, each of the respective first sub-pixel, the respective second sub-pixel, the respective third sub-pixel, and the respective fourth sub-pixel comprises a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0084] The present disclosure can be implemented in a pixel driving circuit having various types of transistors, including a pixel driving circuit having p-type transistors, a pixel driving circuit having n-type transistors, and a pixel driving circuit having one or more p-type transistors and one or more n-type transistors. Referring to FIG. 1, a pixel driving circuit 100 having p-type transistors is illustrated. The pixel driving circuit 100 includes a first sub-pixel 110, a second sub-pixel 120, and a third sub-pixel 130. Figure 2A, the second transistor T2 is an n-type transistor, for example a metal oxide transistor, and the other transistors are p-type transistors, for example polysilicon transistors. For a p-type transistor, an active control signal (e.g. a turn-on control signal) is a low voltage signal, and an inactive control signal (e.g. a turn-off control signal) is a high voltage signal. For an n-type transistor, an active control signal (e.g. a turn-on control signal) is a high voltage signal, and an inactive control signal (e.g. a turn-off control signal) is a low voltage signal.

[0085] Figure 2B is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. Referring to Figure 2A With reference to Figure 2B During a frame of image, the operation of the pixel driving circuit comprises a reset sub-phase tl, a data write sub-phase t2 and a light emission sub-phase t3. In the initial sub-phase to, a turn-off reset control signal is provided to the gate of the second reset transistor Tr2 through the corresponding second reset control signal line rst2 to turn off the second reset transistor Tr2. A turn-off reset control signal is provided to the gate of the first reset transistor Trl and the gate of the third reset transistor Tr3 through the corresponding first reset control signal line rstl to turn off the first reset transistor Trl and the third reset transistor Tr3. In the initial sub-phase to, the corresponding first gate line GLl is provided with a turn-off signal, thus the first transistor Tl is turned off.

[0086] In the reset sub-phase tl, a turn-on reset control signal is provided to the gate of the first reset transistor Trl through the corresponding first reset control signal line rstl to turn on the first reset transistor Trl; an initialization voltage signal from the corresponding first reset signal line Vintl is allowed to pass from the first electrode of the first reset transistor Trl to the second electrode of the first reset transistor Trl; and in turn to the node N4. The anode of the light emitting element LE is initialized. A turn-on reset control signal is provided to the gate of the third reset transistor Tr3 through the corresponding first reset control signal line rstl to turn on the third reset transistor Tr3; an initialization voltage signal from the corresponding third reset signal line Vint3 is allowed to pass from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3; and in turn to the node N2. The node N2 is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding voltage supply line Vdd. The first capacitor electrode Cel is charged in the reset sub-phase tl due to the increase in voltage difference between the first capacitor electrode Cel and the second capacitor electrode Ce2. In the reset sub-phase tl, the corresponding first gate line GLl is provided with a turn-off signal, thus the first transistor Tl is turned off. The corresponding light emission control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0087] In the data write sub-stage t2, a turn-on reset control signal is provided to the gate of the second reset transistor Tr2 through the second reset control signal line rst2 to turn on the second reset transistor Tr2; the initialization voltage signal from the corresponding second reset signal line Vint2 is allowed to pass from the first electrode of the second reset transistor Tr2 to the second electrode of the second reset transistor Tr2, and further to the second electrode of the driving transistor Td. The second electrode of the driving transistor Td is initialized.

[0088] In the data write sub-stage t2, a turn-off reset control signal is provided to the gate of the first reset transistor Tr1 and the gate of the third reset transistor Tr3 through the corresponding first reset control signal line rst1 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. The corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with turn-on signals, so that the first transistor T1 and the second transistor T2 are turned on. The first electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Since the second transistor T2 is turned on in the data write sub-stage t2, the gate and the second electrode of the driving transistor Td are connected and short-circuited, and only the PN junction between the gate and the first electrode of the driving transistor Td is effective, so that the driving transistor Td is in diode connection mode. The first transistor T1 is turned on in the data write sub-stage t2. The data voltage signal transmitted through the corresponding data line DL is received by the first electrode of the first transistor T1 and transmitted to the first electrode of the driving transistor Td in turn, which is connected to the second electrode of the first transistor T1. The node N2 connected to the first electrode of the driving transistor Td has a voltage level of the data voltage signal. Since only the PN junction between the gate and the first electrode of the driving transistor Td is effective, the voltage level of the N1 node gradually rises to (Vdata+Vth) in the data write sub-stage t2, where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 is reduced to a relatively small value, the storage capacitor Cst is discharged. The corresponding light emission control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0089] In the light emitting sub-stage t3, a turn-off reset control signal is provided to the gate of the second reset transistor Tr2 through the corresponding second reset control signal line rst2 to turn off the second reset transistor Tr2. A turn-off reset control signal is provided to the gate of the first reset transistor Tr1 and the gate of the third reset transistor Tr3 through the corresponding first reset control signal line rst1 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. The corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with turn-off signals respectively, and the first transistor T1 and the second transistor T2 are turned off. The corresponding light emitting control signal line em is provided with a low voltage signal to turn on the third transistor T3 and the fourth transistor T4. In the light emitting sub-stage t3, the voltage level of the node N1 is maintained at (Vdata+Vth), and the driving transistor Td is turned on by the voltage level and works in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, the fourth transistor T4 to the light emitting element LE. The driving transistor Td generates a driving current for driving the light emitting element LE to emit light. The voltage level at the node N3 connected to the second electrode of the driving transistor Td is equal to the light emitting voltage of the light emitting element LE.

[0090] Figure 3A FIG. 1 is a schematic diagram showing a structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 3B FIG. 2 is a schematic diagram showing a structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 3A FIG. 3 is a schematic diagram showing a structure of a first semiconductor material layer in an array substrate shown in FIG. 2. Figure 3C FIG. 4 is a schematic diagram showing a structure of a first gate metal layer in an array substrate shown in FIG. 2. Figure 3A FIG. 5 is a schematic diagram showing an arrangement of a pixel driving circuit of an array substrate shown in FIG. 2. Figures 3A to 3C FIG. 6 shows a portion of an array substrate having two adjacent pixel driving circuits (including PDC1 and PDC2).

[0091] Figure 3D FIG. 7 is a schematic diagram showing a structure of a second semiconductor material layer in an array substrate shown in FIG. 2. Figure 3A FIG. 8 is a schematic diagram showing a structure of a second gate metal layer in an array substrate shown in FIG. 2. Figure 3E FIG. 9 is a schematic diagram showing a structure of a third gate metal layer in an array substrate shown in FIG. 2. Figure 3A FIG. 10 is a schematic diagram showing a structure of a first gate metal layer in an array substrate shown in FIG. 2. Figure 3F FIG. 11 is a schematic diagram showing a structure of a second gate metal layer in an array substrate shown in FIG. 2. Figure 3A FIG. 12 is a schematic diagram showing a structure of a second semiconductor material layer in an array substrate shown in FIG. 2. Figure 3G FIG. 13 is a schematic diagram showing a structure of a third gate metal layer in an array substrate shown in FIG. 2. Figure 3A FIG. 14 is a schematic diagram showing a structure of a second semiconductor material layer in an array substrate shown in FIG. 2. Figure 3H FIG. 15 is a schematic diagram showing a structure of a third gate metal layer in an array substrate shown in FIG. 2. Figure 3A FIG. 16 is a schematic diagram showing a structure of a third gate metal layer in an array substrate shown in FIG. 2. Figure 3I FIG. 17 is a schematic diagram showing a structure of a third gate metal layer in an array substrate shown in FIG. 2. Figure 3AA schematic view of a structure of a passivation layer of an array substrate shown in FIG. 1. Figure 3J A schematic view of a structure of a first signal line layer in an array substrate shown in FIG. 2. Figure 3A A schematic view of a structure of a first planarization layer in an array substrate shown in FIG. 3. Figure 3K A schematic view of a structure of a second signal line layer in an array substrate shown in FIG. 4. Figure 3A A schematic view of a structure of a second planarization layer in an array substrate shown in FIG. 5. Figure 3L A schematic view of a structure of a third signal line layer in an array substrate shown in FIG. 6. Figure 3A A schematic view of a structure of an anode layer in an array substrate shown in FIG. 7. Figure 3M A cross-sectional view along the A-A' line in FIG. 2. Figure 3A A cross-sectional view along the B-B' line in FIG. 4. Figure 3N A cross-sectional view along the C-C' line in FIG. 6. Figure 3A A cross-sectional view along the D-D' line in FIG. 7. Figure 3O A cross-sectional view along the E-E' line in FIG. 8. Figure 3A A cross-sectional view along the F-F' line in FIG. 9. Figure 4A A cross-sectional view along the G-G' line in FIG. 10. Figure 3A A cross-sectional view along the H-H' line in FIG. 11. Figure 4B A cross-sectional view along the I-I' line in FIG. 12. Figure 3A A cross-sectional view along the J-J' line in FIG. 13.

[0092] Reference is made to Figures 3A to 3N , Figure 4A and Figure 4BIn some embodiments, the array substrate includes a substrate BS; a buffer layer BUF on the substrate BS; a first semiconductor material layer SML1 on a side of the buffer layer BUF distal from the substrate BS; a gate insulating layer GI on a side of the first semiconductor material layer SML1 distal from the substrate BS; a first gate metal layer Gate1 on a side of the gate insulating layer GI distal from the first semiconductor material layer SML1; an insulating layer IN on a side of the first gate metal layer Gate1 distal from the gate insulating layer GI; a second gate metal layer Gate2 on a side of the insulating layer IN distal from the first gate metal layer Gate1; a first interlayer dielectric layer ILD1 on a side of the second gate metal layer Gate2 distal from the insulating layer IN; a second semiconductor material layer SML2 on a side of the first interlayer dielectric layer ILD1 distal from the second gate metal layer SML2; a second interlayer dielectric layer ILD2 on a side of the second semiconductor material layer SML2 distal from the first interlayer dielectric layer ILD1; a third gate metal layer Gate3 on a side of the second interlayer dielectric layer ILD2 distal from the second semiconductor material layer SML2; a passivation layer PVX on a side of the third gate metal layer Gate3 distal from the second interlayer dielectric layer ILD2; a first signal line layer SD1 on a side of the passivation layer PVX distal from the third gate metal layer Gate3; a first planarization layer PLN1 on a side of the first signal line layer SD1 distal from the passivation layer PVX; a second signal line layer SD2 on a side of the first planarization layer PLN1 distal from the first signal line layer SD1; a second planarization layer PLN2 on a side of the second signal line layer SD2 distal from the first planarization layer PLN1; a third signal line layer SD3 on a side of the second planarization layer PLN2 distal from the second signal line layer SD2; a third planarization layer PLN3 on a side of the third signal line layer SD3 distal from the second planarization layer PLN2; and an anode layer ADL on a side of the third planarization layer PLN3 distal from the third signal line layer SD3.

[0093] Referring to Figure 2A , Figure 3A , Figure 3D , Figure 4A and Figure 4BIn some embodiments, the first semiconductor material layer SML1 includes at least active layers of the plurality of transistors of the pixel driving circuit (including the first transistor T1, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td). Optionally, the first semiconductor material layer SML1 further includes at least respective portions of first electrodes of the plurality of transistors of the pixel driving circuit (including the first transistor T1, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td). Optionally, the first semiconductor material layer SML1 further includes at least respective portions of second electrodes of the plurality of transistors of the pixel driving circuit (including the first transistor T1, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td). Optionally, the first semiconductor material layer SML1 includes the active layers, the first electrodes, and the second electrodes of the plurality of transistors of the pixel driving circuit (including the first transistor T1, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td). Various suitable semiconductor materials can be used to fabricate the first semiconductor material layer SML1. Examples of semiconductor materials used to fabricate the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polysilicon, monocrystalline silicon, and amorphous silicon.

[0094] In Figure 3D corresponding to the pixel driving circuit PDC2 in Figure 3C The pixel driving circuit corresponding to PDC2 in is annotated with labels that represent components of each of the plurality of transistors (T1, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0095] Optionally, the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr2, ACT3, and ACTd), the first electrodes (S1, S3, S4, Sr1, Sr2, Sr3, and Sd), and the second electrodes (D1, D3, D4, Dr1, Dr2, Dr3, and Dd) of the respective transistors (T1, T3, T4, Tr1, Tr2, Tr3, and Td) are located in the same layer.

[0096] In some embodiments, at least part of the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr3, and ACTd), at least part of the first electrodes (S1, S3, S4, Sr1, Sr3, and Sd), and at least part of the second electrodes (D1, D3, D4, Dr1, Dr3, and Dd) of the plurality of transistors (T1, T3, T4, Tr1, Tr3, and Td) in the pixel driving circuit are part of an integral structure. Optionally, in the same pixel driving circuit, a portion (ACTr2, Sr2, Dr2) of the second reset transistor Tr2 located in the second semiconductor material layer is spaced apart from the integral structure (T1, T3, T4, Tr1, and Td). As shown in FIG. 1A, in some embodiments, at least part of the active layers (ACT1, ACT3, ACT4, ACT1, ACT3, and ACTd), at least part of the first electrodes (S1, S3, S4, Sr1, Sr3, and Sd), and at least part of the second electrodes (D1, D3, D4, Dr1, Dr3, and Dd) of the plurality of transistors (T1, T3, T4, Tr1, Tr3, and Td) in adjacent two pixel driving circuits are part of an integral structure. Figure 3D

[0097] Referring to Figure 2A , Figure 3A , Figure 3E , Figure 4A , and Figure 4B In some embodiments, the first gate metal layer Gate1 includes a plurality of first gate lines (e.g., respective first gate lines GL1), a plurality of first reset control signal lines (e.g., respective first reset control signal lines rst1), a plurality of second reset control signal lines (e.g., respective second reset control signal lines rst2), a first light-emitting control electrode pad emP1, a second light-emitting control electrode pad emP2, and a first capacitor electrode Ce1 of a storage capacitor Cst in the pixel driving circuit.

[0098] ​In some embodiments, the first light-emitting control electrode pad emP1 includes the gate G3 of the third transistor T3. Optionally, the first light-emitting control electrode pad emP1 includes the gates of the third transistors of the first and second adjacent pixel driving circuits in the same row. In some embodiments, the second light-emitting control electrode pad emP2 includes the gate G4 of the fourth transistor T4. Optionally, the second light-emitting control electrode pad emP2 includes the gates of the fourth transistors of the first and third adjacent pixel driving circuits in the same row. The third, first, and second adjacent pixel driving circuits are arranged in sequence in the same row.

[0099] Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first gate metal layer Gate1. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of first gate lines (e.g., the respective first gate lines GL1), the plurality of first reset control signal lines (e.g., the respective first reset control signal lines rst1), the plurality of second reset control signal lines (e.g., the respective second reset control signal lines rst2), the first light-emitting control electrode pad emP1, the second light-emitting control electrode pad emP2, and the first capacitor electrode Ce1 of the storage capacitor Cst in the pixel driving circuit are located in the same layer.

[0100] As used herein, the term “same layer” refers to a relationship between layers that are formed at the same time in the same step. In one example, the plurality of first gate lines and the first capacitor electrode Ce1 are located in the same layer when the plurality of first gate lines and the first capacitor electrode Ce1 are formed due to one or more steps of the same patterning process performed in the same material layer. In another example, the plurality of first gate lines and the first capacitor electrode Ce1 can be formed in the same layer by performing the steps of forming the plurality of first gate lines and the steps of forming the first capacitor electrode Ce1 at the same time. The term “same layer” does not always mean that the thickness of the layers or the height of the layers is the same in a cross-sectional view.

[0101] In some embodiments, with reference to Figure 3A , Figure 3B , Figure 3E , Figure 3J and Figure 4AThe first light emitting control electrode pad emP1 and the second light emitting control electrode pad emP2 are connected to a respective light emitting control signal line em of the plurality of light emitting control signal lines. Optionally, the first light emitting control electrode pad emP1 and the second light emitting control electrode pad emP2 are located at the first gate metal layer Gate1. Optionally, each light emitting control signal line em is located at the first signal line layer SD1. In one example, the respective light emitting control signal line em is connected to the first light emitting control electrode pad emP1 through a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the insulating layer IN. In another example, the respective light emitting control signal line em is connected to the second light emitting control electrode pad emP2 through a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the insulating layer IN.

[0102] Referring to Figure 2A , Figure 3A , Figure 3F , Figure 4A and Figure 4B In some embodiments, the second gate metal layer Gate2 includes at least part of the plurality of second gate lines (e.g., a respective second gate line first branch GL2-1) in the pixel driving circuit, the plurality of second reset signal lines (e.g., a respective second reset signal line Vint2), and the second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable electrode materials and various suitable fabrication methods can be used to fabricate the second gate metal layer Gate2. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for fabricating the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, at least part of the plurality of second gate lines (e.g., a respective second gate line first branch GL2-1) in the pixel driving circuit, the plurality of second reset signal lines (e.g., a respective second reset signal line Vint2), and the second capacitor electrode Ce2 of the storage capacitor Cst are located at the same layer.

[0103] Referring to Figure 2A , Figure 3A , Figure 3G , Figure 4A and Figure 4BIn some embodiments, the second semiconductor material layer SML2 includes at least an active layer ACT2 of a second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 further includes at least a portion of a first electrode S2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 further includes at least a portion of a second electrode D2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 includes the active layer ACT2, the first electrode S2 and the second electrode D2 of the second transistor T2. In the present array substrate, at least the active layer ACT2 of the second transistor T2 is located in a layer different from at least the active layers of the other transistors in the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the second semiconductor material layer SML2. Examples of the semiconductor material used to fabricate the second semiconductor material layer SML2 include metal oxide-based semiconductor materials (e.g., indium gallium zinc oxide) and metal oxynitride-based semiconductor materials (e.g., zinc oxynitride).

[0104] In Figure 3G , the pixel driving circuit corresponding to PDC1 in Figure 3B is annotated with labels indicating components of the second transistor in the pixel driving circuit. For example, the second transistor T2 includes an active layer ACT2, a first electrode S2 and a second electrode D2. Optionally, the active layer ACT2, the first electrode S2 and the second electrode D2 of the second transistor T2 are located in the same layer.

[0105] Referring to Figure 2A , Figure 3A , Figure 3H , Figure 4A and Figure 4B , in some embodiments, the third gate metal layer Gate3 includes at least a portion of the plurality of second gate lines (e.g., a respective second gate line second branch GL2-2), the plurality of first reset signal lines (e.g., a respective first reset signal line Vint1) and the plurality of third reset signal lines (e.g., a respective third reset signal line Vint3). Various suitable electrode materials and various suitable fabrication methods can be used to fabricate the third gate metal layer Gate3. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials used to fabricate the third gate metal layer Gate3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc.

[0106] Figure 3I The via extending through the passivation layer in the array substrate shown in Figure 3A is shown.

[0107] Referring to Figure 2A ,Figure 3A 、 Figure 3J 、 Figure 4A and Figure 4B In some embodiments, the first signal line layer SD1 includes a plurality of light emission control signal lines (e.g., respective light emission control signal lines em); a first voltage connection pad VCP1; a second voltage connection pad VCP2; a first data connection pad DCP1; a first node connection line Cln1; a third node connection line Cln3; a first relay electrode RE1; a first reset signal connection line Cli1; a second reset signal connection line Cli2; and a third reset signal connection line Cli3.

[0108] Various suitable conductive materials and various suitable fabrication methods can be used to fabricate the first signal line layer SD1. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the first signal line layer includes a plurality of sub-layers stacked together. In one example, the first signal line layer includes a stacked titanium / aluminum / titanium multi-layer structure. In another example, the first signal line layer includes a stacked molybdenum / aluminum / molybdenum multi-layer structure. Optionally, the plurality of light emission control signal lines (e.g., respective light emission control signal lines em); the first voltage connection pad VCP1; the second voltage connection pad VCP2; the first data connection pad DCP1; the first node connection line Cln1; the third node connection line Cln3; the first relay electrode RE1; the first reset signal connection line Cli1; the second reset signal connection line Cli2; and the third reset signal connection line Cli3 are located in the same layer.

[0109] In some embodiments, the first node connection line Cln1 connects a plurality of components of the pixel driving circuit to the node N1. Referring to Figure 4A , the first node connection line Cln1 is connected to the first capacitor electrode Ce1 through a first via v1 and to the second transistor T2 (e.g., to the first electrode S2 of the second transistor T2) through a second via v2. Optionally, the first node connection line Cln1 corresponds to the node N1 described in Figure 2A .

[0110] In some embodiments, the second electrode Dr3 of the third reset transistor Tr3 has a footprint on the substrate BS that at least partially overlaps with a footprint of the first voltage connection pad VCP1 on the substrate BS. The inventors of the present disclosure have found that this structure helps stabilize the voltage level at the node N2 by keeping the voltage at the first voltage connection pad VCP1 constant.

[0111] Referring toFigure 2A 、 Figure 3A 、 Figure 3E 、 Figure 3F 、 Figure 4A and Figure 4B In some embodiments, in the hole region H, a portion of the second capacitor electrode Ce2 is absent. Optionally, in addition to the hole region H where the portion of the second capacitor electrode Ce2 is absent, a footprint of the second capacitor electrode Ce2 on the substrate base BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and is larger than a footprint of the first capacitor electrode Cel on the substrate base BS. Optionally, the first via vl extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the hole region H, and the insulating layer IN.

[0112] In some embodiments, the first node connection line Clnl intersects with a respective second gate line among the plurality of second gate lines. As shown in Figure 3A 、 Figure 3B and Figure 4A , the first node connection line Clnl intersects with a respective second gate line first branch GL2-1 in the second gate metal layer Gate2 and a respective second gate line second branch GL2-2 in the third gate metal layer Gate3.

[0113] In some embodiments, referring to Figure 4B , the third node connection line Cln3 is connected to the second electrode Dr2 of the second reset transistor Tr2 through a third via v3, to the second electrode D2 of the second transistor T2 through a fourth via v4, and to the second electrode Dd of the drive transistor Td and the first electrode S4 of the fourth transistor T4 through a fifth via v5. Optionally, the third node connection line Cln3 corresponds to the node N3 described in Figure 2A . Optionally, the third node connection line Cln3 intersects with a respective second gate line among the plurality of second gate lines. As shown in Figure 3A 、 Figure 3B and Figure 4B , the third node connection line Cln3 intersects with a respective second gate line first branch GL2-1 in the second gate metal layer Gate2 and a respective second gate line second branch GL2-2 in the third gate metal layer Gate3.

[0114] In some embodiments, a projection of the third node connection line Cln3 onto the substrate BS at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) overlaps with a projection of the active layer ACT2 of the second transistor T2 onto the substrate BS. Optionally, the third node connection line Cln3 extends along a direction substantially parallel to a direction in which the active layer ACT2 of the second transistor T2 extends. Optionally, a projection of the third node connection line Cln3 onto the substrate BS at least partially overlaps with a projection of the first electrode S2 of the second transistor T2 onto the substrate BS. Optionally, a projection of the third node connection line Cln3 onto the substrate BS at least partially overlaps with a projection of the second electrode D2 of the second transistor T2 onto the substrate BS. As used herein, the term “substantially parallel” refers to an angle in a range from 0 degrees to about 45 degrees, such as from 0 degrees to about 5 degrees, from 0 degrees to about 10 degrees, from 0 degrees to about 15 degrees, from 0 degrees to about 20 degrees, from 0 degrees to about 25 degrees, from 0 degrees to about 30 degrees.

[0115] In the present array substrate, the second electrode D1 of the first transistor T1, the first electrode Sd of the drive transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are located at the same layer, e.g., at the first semiconductor material layer SML1. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the drive transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are part of an integral structure. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the drive transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other in the first semiconductor material layer SML1. The second electrode D1 of the first transistor T1, the first electrode Sd of the drive transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other by one or more portions of the first semiconductor material layer SML1, e.g., without any connection lines in a layer different from the first semiconductor material layer SML1.

[0116] In some embodiments, a respective light emission control signal line em of the plurality of light emission control signal lines is connected to a first light emission control electrode pad emP1 and a second light emission control electrode pad emP2 in the first gate metal layer Gate1.

[0117] Figure 3K The array substrate shown in Figure 3A The via shown in the array substrate shown in

[0118] Referring to Figure 2A , Figure 3A , Figure 3B , Figure 3L , Figure 4A and Figure 4B In some embodiments, the second signal line layer SD2 includes a plurality of first voltage supply lines (e.g., respective first voltage supply lines Vddh), a plurality of first low voltage supply lines (e.g., respective first low voltage supply lines Vssl), second relay electrodes RE2, and second data connection pads DCP2. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer SD2. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for fabricating the second signal line layer SD2 include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multi-layer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multi-layer structure. Optionally, the plurality of first voltage supply lines (e.g., respective first voltage supply lines Vddh), the second relay electrodes RE2, and the second data connection pads DCP2 are located in the same layer.

[0119] Figure 3M A via extending through the second planarization layer in the array substrate is shown. Figure 3A

[0120] Referring to Figure 2A , Figure 3A , Figure 3N , Figure 4A and Figure 4B In some embodiments, the third signal line layer SD3 includes a plurality of second voltage supply lines (e.g., respective second voltage supply lines Vddv), anode contact pads ACP, a plurality of data lines (e.g., respective data lines DL), a plurality of fourth reset signal lines (e.g., respective fourth reset signal lines Vint4), a plurality of fifth reset signal lines (e.g., respective fifth reset signal lines Vint5), a plurality of sixth reset signal lines (e.g., respective sixth reset signal lines Vint6), and a plurality of second low voltage supply lines (e.g., respective second low voltage supply lines Vss2). In some embodiments, the respective first voltage supply lines Vddh and the respective second voltage supply lines Vddv are configured to provide a first reference voltage signal (e.g., a high reference voltage signal). Optionally, the respective low voltage supply lines VSS are configured to provide a second reference voltage signal (e.g., a low reference voltage signal). Optionally, the first reference voltage signal is a constant voltage signal, the second reference voltage signal is a constant voltage signal, and the voltage level of the first reference voltage signal is higher than the voltage level of the second reference voltage signal.​​​

[0121] Various suitable conductive materials and various suitable fabrication methods can be used to fabricate the third signal line layer SD3. For example, the conductive material can be deposited on the substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third signal line layer SD3 include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multi-layer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multi-layer structure. Optionally, the plurality of second voltage supply lines (e.g., respective second voltage supply lines Vddv), the anode contact pad ACP, the plurality of data lines (e.g., respective data lines DL), the plurality of fourth reset signal lines (e.g., respective fourth reset signal lines Vint4), the plurality of fifth reset signal lines (e.g., respective fifth reset signal lines Vint5), the plurality of sixth reset signal lines (e.g., respective sixth reset signal lines Vint6), and the plurality of low voltage supply lines (e.g., respective low voltage supply lines Vss) are located in the same layer.

[0122] Referring to Figure 2A , Figure 3A , Figure 3O , Figure 4A and Figure 4B In some embodiments, the anode layer ADL includes a plurality of anodes AD.

[0123] Referring to Figure 2A , Figure 3A , Figure 3B , Figure 3J , Figure 3L , Figure 3N , Figure 4A and Figure 4B In some embodiments, the plurality of first voltage supply lines and the plurality of second voltage supply lines are interconnected with each other, forming a voltage supply network. A respective first voltage supply line Vddh in the plurality of first voltage supply lines is connected to a first voltage connection pad VCP1, which is connected to the first electrode of the third transistor T3, thereby providing a voltage supply signal to the first electrode of the third transistor T3. Each first voltage supply line Vddh in the plurality of first voltage supply lines is connected to a second voltage connection pad VCP2, which is connected to the second capacitor electrode Ce2 of the storage capacitor Cst, thereby providing a voltage supply signal to the second capacitor electrode Ce2 of the storage capacitor Cst.

[0124] In some embodiments, the first reset signal connection line Clil connects a respective first reset signal line Vintl of the plurality of first reset signal lines to the first electrode Sr1 of the first reset transistor Trl. The first reset signal connection line Clil is configured to transmit a reset signal from the respective first reset signal line Vintl to the first electrode Sr1 of the first reset transistor Trl.

[0125] In some embodiments, the second reset signal connection line Clil2 connects a respective second reset signal line Vint2 of the plurality of second reset signal lines to the first electrode Sr2 of the second reset transistor Tr2. The second reset signal connection line Clil2 is configured to transmit a reset signal from the respective second reset signal line Vint2 to the first electrode Sr1 of the second reset transistor Tr2.

[0126] In some embodiments, the third reset signal connection line Clil3 connects a respective third reset signal line Vint3 of the plurality of third reset signal lines to the first electrode Sr3 of the third reset transistor Tr3. The third reset signal connection line Clil3 is configured to transmit a reset signal from the respective third reset signal line Vint3 to the first electrode Sr3 of the third reset transistor Tr3. In an example, the third reset signal connection line Clil3 is connected to the first electrodes of the third reset transistors in two adjacent pixel driving circuits in the same row and is configured to transmit a reset signal from the respective third reset signal line Vint3 to the first electrodes of the third reset transistors in the two adjacent pixel driving circuits in the same row.

[0127] In some embodiments, the first relay electrode RE1 is connected to the second electrode D4 of the fourth transistor T4 (and / or the second electrode Dr1 of the first reset transistor Trl) and to the second relay electrode RE2. The second relay electrode is connected to the first relay electrode RE1 and to the anode contact pad ACP. In an example, the anode contact pad ACP is located at the third signal line layer SD3, the second relay electrode RE2 is located at the second signal line layer SD2, and the first relay electrode RE1 is located at the first signal line layer SD1. In another example, the anode contact pad ACP is connected to the second relay electrode RE2 through a via extending through the second planarization layer PLN2, the second relay electrode RE2 is connected to the first relay electrode RE1 through a via extending through the first planarization layer PLN1, and the first relay electrode RE1 is connected to the second electrode D4 of the fourth transistor T4 (and / or the second electrode Dr1 of the first reset transistor Trl) through a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI.

[0128] In some embodiments, the first data connection pad DCP1 is connected to the first electrode S1 of the first transistor T1 and to a second data connection pad DCP2. The second data connection pad DCP2 is connected to the first data connection pad DCP1 and to a respective data line DL of the plurality of data lines. In one example, the first data connection pad DCP1 is located at the first signal line layer SD1, the second data connection pad DCP2 is located at the second signal line layer SD2, and the respective data line DL is located at the third signal line layer SD3. In another example, the respective data line DL is connected to the second data connection pad DCP2 through a via extending through the second planarization layer PLN2, the second data connection pad DCP2 is connected to the first data connection pad DCP1 through a via extending through the first planarization layer PLN1, and the first data connection pad DCP1 is connected to the first electrode S1 of the first transistor T1 through a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI.

[0129] In the present array substrate, each light emission control signal line em is not located at the first gate metal layer but at the first signal line layer. In the present array substrate, referring to Figure 3A Figure 3B and Figure 3D , the second electrode D1 of the first transistor T1, the first electrode Sd of the drive transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are located at the same layer, for example, at the first semiconductor material layer SML1. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the drive transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are part of an integral structure. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the drive transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other in the first semiconductor material layer SML1. The second electrode D1 of the first transistor T1, the first electrode Sd of the drive transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other through one or more portions of the first semiconductor material layer SML1, for example, without any connecting lines in layers other than the first semiconductor material layer SML1.

[0130] The inventors of the present disclosure found that the unique and complex structure of the present array substrate results in a significant reduction of parasitic capacitance between components located at the first signal line layer and components located at the first gate metal layer, thereby resulting in a significant improvement in display quality.

[0131] In some embodiments, referring to Figures 3A to 3N ​, directly adjacent to each other and at a current stage (e.g., located in the same row) of a first pixel driving circuit (e.g., Figure 3C PDC1) and a corresponding layer of a second pixel driving circuit (e.g., Figure 3C PDC2) in the same row, e.g., with respect to a plane that is perpendicular to a major surface of the array substrate and substantially parallel to the plurality of data lines, have a mirror symmetry with respect to each other that is substantial (e.g., at least 80% symmetric, at least 85% symmetric, at least 90% symmetric, at least 95% symmetric, at least 98% symmetric, at least 99% symmetric, or perfectly symmetric).

[0132] As used herein, the term “a corresponding layer of a first pixel driving circuit and a corresponding layer of a second pixel driving circuit” is not intended to include layers that are not part of a pixel driving circuit. For example, “a corresponding layer of a first pixel driving circuit and a corresponding layer of a second pixel driving circuit” does not include an anode layer or a pixel defining layer. In some embodiments, “a corresponding layer of a first pixel driving circuit and a corresponding layer of a second pixel driving circuit” does not include a third signal line layer. In some embodiments, “a corresponding layer of a first pixel driving circuit and a corresponding layer of a second pixel driving circuit” does not include a second signal line layer. In some embodiments, “a corresponding layer of a first pixel driving circuit and a corresponding layer of a second pixel driving circuit” does not include a first signal line layer. In some embodiments, “a corresponding layer of a first pixel driving circuit and a corresponding layer of a second pixel driving circuit” does not include a third gate metal layer. In some embodiments, “a corresponding layer of a first pixel driving circuit and a corresponding layer of a second pixel driving circuit” does not include a second gate metal layer.

[0133] In one example, “a corresponding layer of a first pixel driving circuit and a corresponding layer of a second pixel driving circuit” refers to at least one conductive layer of a first pixel driving circuit and at least one conductive layer of a second pixel driving circuit. In one specific example, “a corresponding layer” includes at least one of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, a second signal line layer, or a third signal line layer. In another specific example, “a corresponding layer” further includes at least one of a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, or a second planarization layer. In another specific example, “a corresponding layer of a first pixel driving circuit and a corresponding layer of a second pixel driving circuit” includes a first semiconductor material layer. In another specific example, “a corresponding layer of a first pixel driving circuit and a corresponding layer of a second pixel driving circuit” includes a first gate metal layer. In another specific example, “a corresponding layer of a first pixel driving circuit and a corresponding layer of a second pixel driving circuit” includes a second semiconductor material layer.

[0134] In a related array substrate, the plurality of light emission control signal lines are typically located at the first gate metal layer, and a respective light emission control signal line of the plurality of light emission control signal lines typically includes gates of the third transistor and the fourth transistor. The related array substrate typically includes a voltage connection line crossing the respective light emission control signal line. The voltage connection line is connected to one or more voltage supply lines, and connected to the first electrode of the third transistor. The inventors of the present disclosure found that in the related array substrate, there is a relatively large parasitic capacitance between the voltage connection line (e.g., located at the first signal line layer) and the respective light emission control signal line located at the first gate metal layer, which adversely affects the display quality.

[0135] In the present array substrate, each light emission control signal line em is not located at the first gate metal layer, but at the first signal line layer. A first light emission control electrode pad emP1 and a second light emission control electrode pad emP2 are connected to a respective light emission control signal line em of the plurality of light emission control signal lines. Optionally, the first light emission control electrode pad emP1 and the second light emission control electrode pad emP2 are located at the first gate metal layer. Optionally, the respective light emission control signal line em is located at the first signal line layer. The inventors of the present disclosure found that this unique and complex structure greatly reduces the parasitic capacitance between the first gate metal layer and the first signal line layer, thereby significantly improving the display quality.

[0136] Figure 5 A voltage supply path in an array substrate according to some embodiments of the present disclosure is shown. Referring to Figure 5 、 Figure 3D 、 Figure 3J and Figure 3L , in some embodiments, the array substrate includes a third transistor configured to receive a voltage supply signal; a first voltage connection pad VCP1; and a respective first voltage supply line Vddh of a plurality of first voltage supply lines; wherein an active layer of the third transistor, the first voltage connection pad VCP1, and the respective first voltage supply line Vddh are located at three different layers. Optionally, the active layer of the third transistor is located at a first semiconductor material layer; the first voltage connection pad VCP1 is located at a first signal line layer, and the respective first voltage supply line Vddh is located at a second signal line layer. In some embodiments, the respective first voltage supply line Vddh is connected to the first voltage connection pad VCP1, and the first voltage connection pad VCP1 is connected to a first electrode S3 of the third transistor.

[0137] In some embodiments, referring to Figure 5 、 Figure 3D 、 Figure 3J and Figure 3LThe array substrate also includes a corresponding light emission control signal line em configured to provide a light emission control signal to the gate of the third transistor. In some embodiments, the corresponding light emission control signal line em and the first voltage connection pad VCP1 are located on the same layer.

[0138] In some embodiments, the first voltage connection pad VCP1 is connected to the first electrode of the third transistor in two adjacent pixel driving circuits located in the same row. Figure 5 The Chinese characters are labeled as S3 and S3').

[0139] Figure 6 This is a schematic diagram illustrating the structure of a corresponding first voltage supply line in an array substrate according to some embodiments of the present disclosure. Reference Figure 6 In some embodiments, the corresponding first voltage supply line Vddh includes a body MB and a plurality of extensions ET extending in a direction away from the body MB. Optionally, the plurality of extensions ET extend in the same direction away from the body MB. In some embodiments, a corresponding extension ET of the plurality of extensions ET is connected to a first voltage connection pad VCP1, and the first voltage connection pad VCP1 is connected to the first electrode S3 of the third transistor. Optionally, two adjacent extensions ET of the plurality of extensions ET are connected to the first voltage connection pad VCP1, and the first voltage connection pad VCP1 is connected to the first electrode of the third transistor in two adjacent pixel driving circuits located in the same row. Figure 5 The Chinese inscription is indicated as S3 and S3').

[0140] Figure 7 It is shown Figure 3A A schematic diagram of the structure of the second semiconductor material layer and the corresponding first voltage supply line in the array substrate shown. (Refer to...) Figure 7 In some embodiments, the orthographic projection of the body MB onto the substrate substantially covers (e.g., covers at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the active layer ACT2 of the second transistor T2 onto the substrate. Optionally, the orthographic projection of the body MB onto the substrate substantially covers (e.g., covers at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projections of the first electrode S2, the active layer ACT2, and the second electrode D2 of the second transistor T2 onto the substrate. The inventors of this disclosure have found that the unique and complex structure of this array substrate contributes to enhanced stability of the second transistor T2.

[0141] Figure 8A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 8B It is shown Figure 8AA schematic diagram showing the arrangement of pixel drive circuits in the array substrate shown in FIG. 1. Figure 8C is a schematic diagram showing the structure of a first semiconductor material layer in the array substrate shown in FIG. 1. Figure 8A is a schematic diagram showing the structure of a first gate metal layer in the array substrate shown in FIG. 1. Figure 8D is a schematic diagram showing the structure of a second gate metal layer in the array substrate shown in FIG. 1. Figure 8A is a schematic diagram showing the structure of a second semiconductor material layer in the array substrate shown in FIG. 1. Figure 8E is a schematic diagram showing the structure of a third gate metal layer in the array substrate shown in FIG. 1. Figure 8A is a schematic diagram showing the structure of a passivation layer in the array substrate shown in FIG. 1. Figure 8F is a schematic diagram showing the structure of a first signal line layer in the array substrate shown in FIG. 1. Figure 8A is a schematic diagram showing the structure of a first planarization layer in the array substrate shown in FIG. 1. Figure 8G is a schematic diagram showing the structure of a second signal line layer in the array substrate shown in FIG. 1. Figure 8A is a schematic diagram showing the structure of a second planarization layer in the array substrate shown in FIG. 1. Figure 8H is a schematic diagram showing the structure of a third signal line layer in the array substrate shown in FIG. 1. Figure 8A is a schematic diagram showing the structure of an anode layer in the array substrate shown in FIG. 1. Figure 8I shows a portion of an array substrate having twelve adjacent pixel drive circuits (including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7, PDC8, PDC9, PDC10, PDC11, and PDC12). Figure 8A PDC1 and PDC2 depicted in FIG. 1 correspond to Figure 8J PDC1 and PDC2 depicted in FIG. 1. Figure 8A Figure 8K Referring to Figure 8A Figure 8L Figure 8A Figure 8M Figure 8A Figure 8N Figure 8A Figures 8A to 8N shows a portion of an array substrate having twelve adjacent pixel drive circuits (including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7, PDC8, PDC9, PDC10, PDC11, and PDC12). Figure 8B PDC1 and PDC2 depicted in FIG. 1 correspond to Figure 3C PDC1 and PDC2 depicted in FIG. 1.

[0142] Referring to Figures 8A to 8N ​​​​​​​​In some embodiments, the array substrate includes pixel driving circuits arranged in J columns, J being a positive integer. The array substrate includes a plurality of fourth reset signal lines (e.g., respective fourth reset signal lines Vint4), a plurality of fifth reset signal lines (e.g., respective fifth reset signal lines Vint5), a plurality of sixth reset signal lines (e.g., respective sixth reset signal lines Vint6), and a plurality of second low voltage supply lines (e.g., respective second low voltage supply lines Vss2). In some embodiments, the J columns include an (8j-7)th column C(8j-7) among the J columns, an (8j-6)th column C(8j-6) among the J columns, an (8j-5)th column C(8j-5) among the J columns, an (8j-4)th column C(8j-4) among the J columns, an (8j-3)th column C(8j-3) among the J columns, an (8j-2)th column C(8j-2) among the J columns, an (8j-1)th column C(8j-1) among the J columns, and an (8j)th column C(8j) among the J columns, J and j being positive integers, 1≤j≤J / 8.

[0143] In some embodiments, one of the respective fourth reset signal lines Vint4, the respective fifth reset signal lines Vint5, the respective sixth reset signal lines Vint6, and the respective second low voltage supply lines Vss2 is located between the (8j-7)th column C(8j-7) among the J columns and the (8j-6)th column C(8j-6) among the J columns; another of the respective fourth reset signal lines Vint4, the respective fifth reset signal lines Vint5, the respective sixth reset signal lines Vint6, and the respective second low voltage supply lines Vss2 is located between the (8j-5)th column C(8j-5) among the J columns and the (8j-4)th column C(8j-4) among the J columns; another of the respective fourth reset signal lines Vint4, the respective fifth reset signal lines Vint5, the respective sixth reset signal lines Vint6, and the respective second low voltage supply lines Vss2 is located between the (8j-3)th column C(8j-3) among the J columns and the (8j-2)th column C(8j-2) among the J columns; and another of the respective fourth reset signal lines Vint4, the respective fifth reset signal lines Vint5, the respective sixth reset signal lines Vint6, and the respective second low voltage supply lines Vss2 is located between the (8j-1)th column C(8j-1) among the J columns and the (8j)th column C(8j) among the J columns.

[0144] In some embodiments, the array substrate includes pixel driving circuits arranged in J columns, J being a positive integer. The array substrate includes a plurality of fourth reset signal lines (e.g., respective fourth reset signal lines Vint4), a plurality of fifth reset signal lines (e.g., respective fifth reset signal lines Vint5), a plurality of sixth reset signal lines (e.g., respective sixth reset signal lines Vint6), and a plurality of second low voltage supply lines (e.g., respective second low voltage supply lines Vss2). In some embodiments, the J columns include an (8j-7)th column C(8j-7) among the J columns, an (8j-6)th column C(8j-6) among the J columns, an (8j-5)th column C(8j-5) among the J columns, an (8j-4)th column C(8j-4) among the J columns, an (8j-3)th column C(8j-3) among the J columns, an (8j-2)th column C(8j-2) among the J columns, an (8j-1)th column C(8j-1) among the J columns, and an (8j)th column C(8j) among the J columns, J and j being positive integers, 1≤j≤J / 8. Figures 8A to 8NIn one example shown, the corresponding sixth reset signal line Vint6 is located between the (8j-7)th column C(8j-7) of the J columns and the (8j-6)th column C(8j-6) of the J columns; the corresponding fourth reset signal line Vint4 is located between the (8j-5)th column C(8j-5) of the J columns and the (8j-4)th column C(8j-4) of the J columns; the corresponding second low-voltage supply line Vss2 is located between the (8j-3)th column C(8j-3) of the J columns and the (8j-2)th column C(8j-2) of the J columns; and the corresponding fifth reset signal line Vint5 is located between the (8j-1)th column C(8j-1) of the J columns and the (8j)th column C(8j) of the J columns. The corresponding sixth reset signal line Vint6, the corresponding fourth reset signal line Vint4, the corresponding second low-voltage supply line Vss2, and the corresponding fifth reset signal line Vint5 are arranged in sequence.

[0145] As used herein, the terms "8th(8j-7) column", "8th(8j-6) column", "8th(8j-5) column", "8th(8j-4) column", "8th(8j-3) column", "8th(8j-2) column", "8th(8j-1) column", "8th(8j) column" are used in the context of J columns. The array substrate can or can not include additional columns before the first column of the J columns and / or additional columns after the last column of the J columns. In the context of the array substrate, the terms "8th(8j-7) column", "8th(8j-5) column", "8th(8j-3) column", "8th(8j-1) column" do not necessarily denote odd columns, and the terms "8th(8j-6) column", "8th(8j-4) column", "8th(8j-2) column", "8th(8j) column" do not necessarily denote even columns. In one example, the 8th(8j-7) column is an odd column in the context of the J columns, but can be an even column in the context of the array substrate. In another example, the 8th(8j-7) column is an odd column in the context of the J columns and is also an odd column in the context of the array substrate. In one example, the 8th(8j-6) column is an even column in the context of the J columns, but can be an odd column in the context of the array substrate. In another example, the 8th(8j-6) column is an even column in the context of the J columns and is also an even column in the context of the array substrate. In one example, the 8th(8j-5) column is an odd column in the context of the J columns, but can be an even column in the context of the array substrate. In another example, the 8th(8j-5) column is an odd column in the context of the J columns and is also an odd column in the context of the array substrate. In one example, the 8th(8j-4) column is an even column in the context of the J columns, but can be an odd column in the context of the array substrate. In another example, the 8th(8j-4) column is an even column in the context of the J columns and is also an even column in the context of the array substrate. In one example, the 8th(8j-3) column is an odd column in the context of the J columns, but can be an even column in the context of the array substrate. In another example, the 8th(8j-3) column is an odd column in the context of the J columns and is also an odd column in the context of the array substrate. In one example, the 8th(8j-2) column is an even column in the context of the J columns, but can be an odd column in the context of the array substrate. In another example, the 8th(8j-2) column is an even column in the context of the J columns and is also an even column in the context of the array substrate. In one example, the 8th(8j-1) column is an odd column in the context of the J columns, but can be an even column in the context of the array substrate. In another example, the 8th(8j-1) column is an odd column in the context of the J columns and is also an odd column in the context of the array substrate. In one example, the 8th(8j) column is an even column in the context of the J columns, but can be an odd column in the context of the array substrate. In another example, the 8th(8j) column is an even column in the context of the J columns and is also an even column in the context of the array substrate.

[0146] Referring to Figure 8N In some embodiments, the anode layer includes a first respective anode RAD1, a second respective anode RAD2, a third respective anode RAD3, and a fourth respective anode RAD4. In one example, the first respective anode RAD1 is an anode of a sub-pixel of a first color (e.g., a red sub-pixel), the second respective anode RAD2 is an anode of a sub-pixel of a second color (e.g., a blue sub-pixel), and the third respective anode RAD3 and the fourth respective anode RAD4 are anodes of two sub-pixels of a third color (e.g., two green sub-pixels). In some embodiments, the array of the plurality of sub-pixels in the array substrate includes a repeating array in the form of R-G-B-G, where R represents a red sub-pixel, B represents a blue sub-pixel, and G represents a green sub-pixel.

[0147] In some embodiments, the first respective anode RAD1 includes a first main anode portion MAP1 and a first extension E1 extending in a direction away from the first main anode portion MAP1. The first extension E1 connects the first main anode portion MAP1 with the first corresponding anode connection pad. In some embodiments, the second respective anode RAD2 includes a second main anode portion MAP2 and a second extension E2 extending in a direction away from the second main anode portion MAP2. The second extension E2 connects the second main anode portion MAP2 with the second corresponding anode connection pad. In some embodiments, the third respective anode RAD3 includes a third main anode portion MAP3 and a third extension E3 extending in a direction away from the third main anode portion MAP3. The third extension E3 connects the third main anode portion MAP3 with the third corresponding anode connection pad. In some embodiments, the fourth respective anode RAD4 includes a fourth main anode portion MAP4 and a fourth extension E4 extending in a direction away from the fourth main anode portion MAP4. The fourth extension E4 connects the fourth main anode portion MAP4 with the fourth corresponding anode connection pad. Optionally, the first extension E1 extends in a direction away from the first main anode portion MAP1 along a direction substantially parallel to the first direction DR1. Optionally, the second extension E2 extends in a direction away from the second main anode portion MAP2 along a direction substantially parallel to the first direction DR1. Optionally, the third extension E3 extends in a direction away from the third main anode portion MAP3 along a direction substantially parallel to the second direction DR2. Optionally, the fourth extension E4 extends in a direction away from the fourth main anode portion MAP4 along a direction substantially parallel to the second direction DR2.

[0148] Figure 8O is a schematic diagram showing the structure of the third signal line layer and the anode layer in the array substrate shown in Figure 8A In some embodiments, referring to Figure 8M ,Figure 8N with Figure 8O Optionally, the orthogonal projection of the first main anode portion MAP1 on the substrate is at least partially overlapped with the orthogonal projection of adjacent two of the plurality of data lines on the substrate. Optionally, the orthogonal projection of the first main anode portion MAP1 on the substrate is at least partially overlapped with the orthogonal projection of adjacent two of the plurality of second voltage supply lines on the substrate. In some embodiments, the orthogonal projection of the second main anode portion MAP2 on the substrate is at least partially overlapped with the orthogonal projection of adjacent two of the plurality of data lines on the substrate. Optionally, the orthogonal projection of the second main anode portion MAP2 on the substrate is at least partially overlapped with the orthogonal projection of adjacent two of the plurality of second voltage supply lines on the substrate. Optionally, the adjacent two data lines are configured to provide data signals to pixel driving circuits in the (8j-k1)th column and the (8j-(k1+1))th column, where J is a positive integer, 1≤j≤(J / 8), and k1 is a positive integer and 1≤k1<j. Optionally, the adjacent two second voltage supply lines are configured to provide voltage supply signals to pixel driving circuits in the (8j-k1)th column and the (8j-(k1+1))th column, where J is a positive integer, 1≤j≤(J / 8), and k1 is an odd positive integer and 1≤k1<j. Examples of the (8j-k1)th column and the (8j-(k1+1))th column include the (8j-1)th column C(8j-1) and the (8j-2)th column C(8j-2), the (8j-3)th column C(8j-3) and the (8j-4)th column C(8j-4), the (8j-5)th column C(8j-5) and the (8j-6)th column C(8j-6).

[0149] In some embodiments, the orthogonal projection of the first main anode portion MAP1 on the substrate is not overlapped at all with the orthogonal projection of the plurality of fourth reset signal lines on the substrate, not overlapped at all with the orthogonal projection of the plurality of fifth reset signal lines on the substrate, not overlapped at all with the orthogonal projection of the plurality of sixth reset signal lines on the substrate, and not overlapped at all with the orthogonal projection of the plurality of second low voltage supply lines on the substrate. In some embodiments, the orthogonal projection of the second main anode portion MAP2 on the substrate is not overlapped at all with the orthogonal projection of the plurality of fourth reset signal lines on the substrate, not overlapped at all with the orthogonal projection of the plurality of fifth reset signal lines on the substrate, not overlapped at all with the orthogonal projection of the plurality of sixth reset signal lines on the substrate, and not overlapped at all with the orthogonal projection of the plurality of second low voltage supply lines on the substrate.

[0150] In some embodiments, the third main anode portion MAP3 has a footprint on the substrate that at least partially overlaps with footprints on the substrate of adjacent two of the plurality of second voltage supply lines, and at least partially overlaps with footprints on the substrate of one of the respective fourth reset signal line Vint4, the respective fifth reset signal line Vint5, the respective sixth reset signal line Vint6, and the respective second low voltage supply line Vss2. In some embodiments, the fourth main anode portion MAP4 has a footprint on the substrate that at least partially overlaps with footprints on the substrate of adjacent two of the plurality of second voltage supply lines, and at least partially overlaps with footprints on the substrate of one of the respective fourth reset signal line Vint4, the respective fifth reset signal line Vint5, the respective sixth reset signal line Vint6, and the respective second low voltage supply line Vss2. Optionally, the adjacent two of the plurality of second voltage supply lines are configured to provide voltage supply signals to pixel driving circuits in an (8j-k2)th column and an (8j-(k2+1))th column, where J is a positive integer, 1≤j≤(J / 8), k2 is zero or an even positive integer, and 0≤k2<j. Examples of the (8j-k2)th column and the (8j-(k2+1))th column include the (8j)th column C(8j) and the (8j-1)th column C(8j-1), the (8j-2)th column C(8j-2) and the (8j-3)th column C(8j-3), the (8j-4)th column C(8j-4) and the (8j-5)th column C(8j-5), the (8j-6)th column C(8j-6) and the (8j-7)th column C(8j-7).

[0151] Figure 8P is a schematic diagram showing a structure of a first semiconductor material layer and an anode layer in an array substrate shown in Figure 8A Figure 8C , Figure 8N , Figure 8P , Figure 3D and Figure 3O , the first main anode portion MAP1 has a footprint on the substrate that at least partially overlaps with footprints on the substrate of active layers of third reset transistors in two adjacent columns of pixel driving circuits. Optionally, the two adjacent columns of pixel driving circuits include an (8j-k1)th column and an (8j-(k1+1))th column, where J is a positive integer, 1≤j≤(J / 8), k1 is a positive integer, and 1≤k1<j. Examples of the (8j-k1)th column and the (8j-(k1+1))th column include the (8j-1)th column C(8j-1) and the (8j-2)th column C(8j-2), the (8j-3)th column C(8j-3) and the (8j-4)th column C(8j-4), the (8j-5)th column C(8j-5) and the (8j-6)th column C(8j-6).

[0152] ​In some embodiments, the first respective anode RAD1, the second respective anode RAD2, the third respective anode RAD3, or the fourth respective anode RAD4 has a footprint on the substrate that at least partially overlaps with a footprint of the second electrode Dr3 of the third reset transistor Tr3 on the substrate.

[0153] Figure 9A A first interconnection reset signal network according to some embodiments of the present disclosure is shown. Reference is made to FIG. 1A. Figure 9A In some embodiments, the array substrate includes a first interconnection reset signal network configured to provide a first reset signal to the plurality of pixel driving circuits. For example, the first interconnection reset signal network is configured to provide the first reset signal to a first electrode of a first reset transistor in the plurality of pixel driving circuits. In some embodiments, the first interconnection reset signal network includes a plurality of first reset signal lines respectively extending along a direction substantially parallel to a first direction DR1; and a plurality of fourth reset signal lines extending along a direction substantially parallel to a second direction DR2; wherein the plurality of first reset signal lines respectively cross the plurality of fourth reset signal lines. As used herein, the term “substantially parallel” refers to an angle in a range from 0 degree to about 45 degrees, for example, 0 degree to about 5 degrees, 0 degree to about 10 degrees, 0 degree to about 15 degrees, 0 degree to about 20 degrees, 0 degree to about 25 degrees, 0 degree to about 30 degrees.

[0154] Optionally, each first reset signal line Vint1 in the plurality of first reset signal lines is connected to at least a plurality of fourth reset signal lines; and each fourth reset signal line Vint4 in the plurality of fourth reset signal lines is connected to at least a plurality of first reset signal lines.

[0155] In some embodiments, each first reset signal line Vint1 includes a plurality of first portions P1 and a plurality of second portions P2 arranged alternately. Adjacent two second portions in the plurality of second portions P2 are connected by a first portion in the plurality of first portions P1. Adjacent two first portions in the plurality of first portions P1 are connected by a second portion in the plurality of second portions P2. A respective second portion in the plurality of second portions P2 is connected to a respective fourth reset signal line Vint4.

[0156] In some embodiments, the plurality of first portions P1, the plurality of second portions P2, and each fourth reset signal line Vint4 are respectively located at three different layers. In one particular example, the plurality of first portions P1 is located at a third gate metal layer, the plurality of second portions P2 is located at a first signal line layer, and each fourth reset signal line Vint4 is located at a third signal line layer. The inventors of the present disclosure have found that the unique and complex structure of the first interconnection reset signal network optimizes the layout of the signal lines in the array substrate.

[0157] Figure 9B A first interconnection reset signal network in some embodiments according to the present disclosure is shown. Referring to Figure 9B The respective first reset signal line Vint1 includes a first main line portion MLP1 and a plurality of second portions P2. The first main line portion MLP1 is a continuous line portion which is connected to the plurality of second portions P2. A respective second portion of the plurality of second portions P2 is connected to a respective fourth reset signal line Vint4.

[0158] Figure 10A A second interconnection reset signal network in some embodiments according to the present disclosure is shown. Referring to Figure 10A In some embodiments, the array substrate includes a second interconnection reset signal network configured to provide a second reset signal to the plurality of pixel driving circuits. For example, the second interconnection reset signal network is configured to provide the second reset signal to a first electrode of a second reset transistor in the plurality of pixel driving circuits. In some embodiments, the second interconnection reset signal network includes a plurality of second reset signal lines respectively extending along a direction substantially parallel to the first direction DR1; and a plurality of fifth reset signal lines respectively extending along a direction substantially parallel to the second direction DR2; wherein the plurality of second reset signal lines respectively cross the plurality of fifth reset signal lines.

[0159] Optionally, each second reset signal line Vint2 of the plurality of second reset signal lines is connected to at least a plurality of the plurality of fifth reset signal lines; and each fifth reset signal line Vint5 of the plurality of fifth reset signal lines is connected to at least a plurality of the plurality of second reset signal lines.

[0160] In some embodiments, each second reset signal line Vint2 includes a plurality of third portions P3 and a plurality of fourth portions P4 arranged alternately. Two adjacent fourth portions of the plurality of fourth portions P4 are connected by a third portion of the plurality of third portions P3. Two adjacent third portions of the plurality of third portions P3 are connected by a fourth portion of the plurality of fourth portions P4. A respective fourth portion of the plurality of fourth portions P4 is connected to a respective fifth reset signal line Vint5.

[0161] In some embodiments, the plurality of third portions P3, the plurality of fourth portions P4 and each fifth reset signal line Vint5 are respectively located at three different layers. In one particular example, the plurality of third portions P3 are located at a second gate metal layer, the plurality of fourth portions P4 are located at a first signal line layer, and each fifth reset signal line Vint5 is located at a third signal line layer. The inventors of the present disclosure have found that the unique and complex structure of the second interconnection reset signal network optimizes the layout of the signal lines in the array substrate.

[0162] Figure 10BA second interconnection reset signal network in some embodiments according to the present disclosure is shown. Referring to Figure 10B The respective second reset signal line Vint2 includes a second main line portion MLP2 and a plurality of fourth portions P4. The second main line portion MLP2 is a continuous line portion which is connected to the plurality of fourth portions P4. A respective fourth portion of the plurality of fourth portions P4 is connected to a respective fifth reset signal line Vint5.

[0163] Figure 11 A third interconnection reset signal network in some embodiments according to the present disclosure is shown. Referring to Figure 11 In some embodiments, the array substrate includes a third interconnection reset signal network configured to provide a third reset signal to the plurality of pixel driving circuits. For example, the third interconnection reset signal network is configured to provide the third reset signal to a first electrode of a third reset transistor in the plurality of pixel driving circuits. In some embodiments, the third interconnection reset signal network includes a plurality of third reset signal lines respectively extending along a direction substantially parallel to the first direction DR1; and a plurality of sixth reset signal lines respectively extending along a direction substantially parallel to the second direction DR2; wherein the plurality of third reset signal lines respectively cross the plurality of sixth reset signal lines.

[0164] Optionally, each third reset signal line Vint3 of the plurality of third reset signal lines is connected to at least a plurality of the plurality of sixth reset signal lines; and each sixth reset signal line Vint6 of the plurality of sixth reset signal lines is connected to at least a plurality of the plurality of third reset signal lines.

[0165] In some embodiments, the array substrate further includes a plurality of reset connection pads. Each reset connection pad RCP is connected to a separate third reset signal line of the plurality of third reset signal lines and to a separate sixth reset signal line of the plurality of sixth reset signal lines.

[0166] In some embodiments, each third reset signal line Vint3, each sixth reset signal line Vint6 and each reset connection pad RCP are respectively located at three different layers. In one particular example, each third reset signal line Vint3 is located at a third gate metal layer, each reset connection pad RCP is located at a first signal line layer, and each sixth reset signal line Vint6 is located at a third signal line layer.

[0167] Figure 12 An interconnection low voltage supply network in some embodiments according to the present disclosure is shown. Referring to Figure 12In some embodiments, the array substrate includes an interconnect low voltage supply network configured to provide a low voltage supply signal to the plurality of pixel driving circuits. For example, the interconnect low voltage supply network is configured to provide the low voltage supply signal to the cathodes in the plurality of pixel driving circuits. In some embodiments, the interconnect low voltage supply network includes a plurality of first low voltage supply lines each extending along a direction substantially parallel to the first direction DR1; and a plurality of second low voltage supply lines each extending along a direction substantially parallel to the second direction DR2; wherein the plurality of first low voltage supply lines each intersects the plurality of second low voltage supply lines.

[0168] Optionally, each of the plurality of first low voltage supply lines Vss1 is connected to at least a plurality of the plurality of second low voltage supply lines; and each of the plurality of second low voltage supply lines Vss2 is connected to at least a plurality of the plurality of first low voltage supply lines.

[0169] In some embodiments, each of the first low voltage supply lines Vss1 and each of the second low voltage supply lines Vss2 are located at two different layers, respectively. In one particular example, each of the first low voltage supply lines Vss1 is located at the second signal line layer, and each of the second low voltage supply lines Vss2 is located at the third signal line layer.

[0170] In a related array substrate, the reset signal lines along the second direction are typically located at the first signal line layer, which is close to the first gate metal layer. The proximity of the reset signal lines along the second direction to the gate lines located at the first gate metal layer results in a relatively large parasitic capacitance, which in turn results in an increased load in the gate lines. The increased load in the gate lines requires an increased driving load for the gate scan circuit (e.g., the on-array gate circuit). The inventors of the present disclosure found that by providing the reset signal lines along the second direction in the third signal line layer, which is spaced apart from the first gate metal layer by several layers, the requirement for the driving load of the gate scan circuit can be reduced.

[0171] In some embodiments, the array substrate includes a plurality of first gate lines configured to provide gate scan signals to gates of first transistors in the plurality of pixel driving circuits; a plurality of first voltage supply lines located at a side of the plurality of first gate lines distal to the substrate, the plurality of first voltage supply lines configured to provide voltage supply signals to first electrodes of third and fourth transistors in the plurality of pixel driving circuits; and a plurality of fourth reset signal lines, a plurality of fifth reset signal lines, or a plurality of sixth reset signal lines located at a side of the plurality of first voltage supply lines distal to the plurality of first gate lines. The plurality of fourth reset signal lines, the plurality of fifth reset signal lines, or the plurality of sixth reset signal lines extend along the second direction.

[0172] In the related array substrate, the reset signal lines along the second direction (e.g., the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, or the plurality of sixth reset signal lines) are arranged alternately, and the reset signal lines along the second direction are generally located on the side of the plurality of first voltage supply lines close to the plurality of first gate lines, e.g., generally located on the first signal line layer. The layout of the reset signal lines along the second direction in the related array substrate results in different capacitances of the nodes (e.g., the node N1, the node N2, or the node N3) in the pixel driving circuits of different columns, resulting in display non-uniformity in the array substrate. The inventors of the present disclosure found that by spacing the reset signal lines along the second direction from the plurality of first gate lines by the plurality of first voltage supply lines, the plurality of first voltage supply lines shield the nodes from the reset signal lines along the second direction, thereby significantly improving display uniformity.

[0173] In the related array substrate, the plurality of light emission control signal lines are generally located on the first gate metal layer, and each of the plurality of light emission control signal lines generally includes a gate of the third transistor and the fourth transistor. The related array substrate generally includes a second node connection line (e.g., located on the first signal line layer) connecting the second electrode D3 of the third transistor T3 to the second electrode Dr3 of the third reset transistor Tr3. The inventors of the present disclosure found that in the related array substrate, the presence of the second node connection line results in relatively large parasitic capacitance between the second node connection line located on the first signal line layer and each of the light emission control signal lines located on the first gate metal layer, thereby adversely affecting display quality. In addition, the related array substrate requires a relatively large number of vias to connect the second node connection line located on the first signal line layer and the elements located on the first semiconductor material layer, affecting the layout of the signal lines in the related array substrate.

[0174] Figure 13 is a schematic diagram showing the structure of the first semiconductor material layer in the array substrate shown in Figure 3A Figure 13 In some embodiments, each of the plurality of pixel driving circuits includes a second node connection line Cln2 connected to the second electrode D3 of the first light emission control transistor T3 and connected to the second electrode Dr3 of the third reset transistor Tr3. In the present array substrate, the second node connection line Cln2 is located on the same layer as the active layers of the first light emission control transistor T3 and the third reset transistor Tr3.

[0175] In some embodiments, referring to Figure 4A and Figure 13 ​In some embodiments, the plurality of light emitting control signal lines em and the first node connection line Clnl are on the same layer. In some embodiments, referring to FIG. 1, the plurality of light emitting control signal lines em and the first node connection line Clnl are on the same layer. In some embodiments, referring to FIG. 2, the plurality of light emitting control signal lines em and the first node connection line Clnl are on the same layer.

[0176] The inventors of the present disclosure found that by spacing the plurality of light emitting control signal lines em and the second node connection line Cln2 by at least three insulating layers, the parasitic capacitance between the second node connection line Cln2 and the plurality of light emitting control signal lines em can be significantly reduced, thereby achieving improved display quality.

[0177] In some embodiments, referring to FIG. 1, Figure 4A In some embodiments, referring to FIG. 1, Figure 4A and Figure 13 In some embodiments, the first node connection line Clnl and the second node connection line Cln2 are spaced apart by at least three insulating layers, such as three insulating layers, four insulating layers, or five insulating layers. In some embodiments, the first node connection line Clnl and the second node connection line Cln2 are spaced apart by at least three of the gate insulating layer GI, the insulating layer IN, the first interlayer dielectric layer ILD1, the second interlayer dielectric layer ILD2, or the passivation layer PVX. In one example, the first node connection line Clnl and the second node connection line Cln2 are spaced apart by the gate insulating layer GI, the insulating layer IN, the first interlayer dielectric layer ILD1, the second interlayer dielectric layer ILD2, and the passivation layer PVX.

[0178] In another aspect, the present disclosure provides a display device comprising the array substrate described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a micro light emitting diode display device. Optionally, the display device is a mini light emitting diode display device.

[0179] In another aspect, the present disclosure provides a method of manufacturing an array substrate. In some embodiments, the method includes forming a plurality of pixel driving circuits. Optionally, forming each of the plurality of pixel driving circuits includes forming a drive transistor, forming a data write transistor, forming a first light emission control transistor, and forming a third reset transistor. Optionally, the active layers of the drive transistor, the data write transistor, the first light emission control transistor, and the third reset transistor are formed in a first semiconductor material layer. Optionally, the second electrodes of the data write transistor, the first electrodes of the drive transistor, the second electrodes of the first light emission control transistor, and the second electrodes of the third reset transistor are formed in the first semiconductor material layer. Optionally, the second electrodes of the data write transistor, the first electrodes of the drive transistor, the second electrodes of the first light emission control transistor, and the second electrodes of the third reset transistor are formed as part of a unitary structure. Optionally, the second electrodes of the data write transistor, the first electrodes of the drive transistor, the second electrodes of the first light emission control transistor, and the second electrodes of the third reset transistor are connected to each other by one or more portions of the first semiconductor material layer.

[0180] The foregoing description of embodiments of the application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed. The description was presented as illustrative of the broadest aspects of the application that are and can be claimed as it is and only limited by the appended claims. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to explain the principles of the application and its best mode of practical application to thereby enable others skilled in the art to understand the application for various embodiments and with various modifications that are suited to the particular use or implementation. The scope of the application is to be defined by the claims and their equivalents, where all terms are meant to be construed in their broadest reasonable sense, unless otherwise indicated. Thus, the terms "the invention," "the present invention," or similar referents used in the context of the detailed description are not intended to be limiting of the claimed subject matter, and will be included in the scope of the claims along with the equivalents thereof. The present invention is only limited by the claims appended hereto and encompasses all variations falling within the scope of the claims, which are to be interpreted in accordance with the principles of patent law. Furthermore, these claims can refer to "a," "an" or "the" article, which is intended to be interpreted to mean "at least one" or "one or more." Also, any application recitations of "first," "second," or "third" or similar language are not intended to be construed as limiting the number or order of elements. Any advantages and benefits provided by the described embodiments can not apply in all instances. It should be understood that various changes can be made by those skilled in the art which would be apparent to one skilled in the art. Such changes are not to be considered limiting of the scope of the application as defined by the appended claims and their equivalents. Furthermore, elements and components of the disclosure can be arranged and designed in a wide variety of different configurations, all of which are intended to fall within the scope of the present disclosure. Also, the elements and components of the disclosure can be interchanged with other elements and components that serve the same function or are otherwise suitable for the purposes contemplated by the disclosure.

Claims

1. An array substrate, comprising a plurality of pixel driving circuits; wherein each of the plurality of pixel driving circuits comprises a driving transistor, a first light emitting control transistor, and a third reset transistor; the active layers of the driving transistor, the first light emitting control transistor, and the third reset transistor are located on a first semiconductor material layer; a first electrode of the driving transistor, a second electrode of the first light emitting control transistor, and a second electrode of the third reset transistor are located on the first semiconductor material layer; the first electrode of the driving transistor, the second electrode of the first light emitting control transistor, and the second electrode of the third reset transistor are part of an integral structure; the first electrode of the driving transistor, the second electrode of the first light emitting control transistor, and the second electrode of the third reset transistor are connected to each other through one or more portions of the first semiconductor material layer; the array substrate further comprises: a first light emitting control electrode pad located on the first semiconductor material layer; and a plurality of light emitting control signal lines located on a side of the first light emitting control electrode pad away from the first semiconductor material layer; wherein the first light emitting control electrode pad comprises a gate of the first light emitting control transistor; and each of the plurality of light emitting control signal lines is connected to the first light emitting control electrode pad through a via hole; each of the pixel driving circuits further comprises a storage capacitor, the storage capacitor comprising a first capacitor electrode and a second capacitor electrode; the first light emitting control electrode pad and the first capacitor electrode are located on a first gate metal layer; the second capacitor electrode is located on a second gate metal layer, which is located on a side of the first gate metal layer away from the first semiconductor material layer; the plurality of light emitting control signal lines are located on a first signal line layer, which is located on a side of the second gate metal layer away from the first gate metal layer. 2.The array substrate of claim 1, further comprising: a second light emitting control electrode pad located on the first semiconductor material layer; and a plurality of light emitting control signal lines located on a side of the second light emitting control electrode pad away from the first semiconductor material layer; wherein each of the pixel driving circuits further comprises a second light emitting control transistor; the second light emitting control electrode pad comprises a gate of the second light emitting control transistor; and each of the plurality of light emitting control signal lines is connected to the second light emitting control electrode pad through a via hole. each of the pixel driving circuits further comprises a compensation transistor; 3. The array substrate of claim 1, wherein, an active layer of the compensation transistor is located on a second semiconductor material layer, which is located on a side of the second gate metal layer away from the first gate metal layer; at least a portion of a gate of the compensation transistor is located on a third gate metal layer, which is located on a side of the second semiconductor material layer away from the second gate metal layer; and ​ ​ The plurality of light emitting control signal lines are located at the first signal line layer, and the first signal line layer is located at a side of the third gate metal layer away from the second semiconductor material layer.

4. The array substrate of claim 1, further comprising a first voltage connection pad and a plurality of first voltage supply lines; wherein The active layer of the first light emitting control transistor, the first voltage connection pad, and the plurality of first voltage supply lines are located at three different layers; And A respective first voltage supply line of the plurality of first voltage supply lines is connected to the first voltage connection pad, and the first voltage connection pad is connected to the first electrode of the first light emitting control transistor.

5. The array substrate according to claim 4, wherein, The first electrode of the third reset transistor is connected to the first voltage connection pad.

6. The array substrate according to claim 4, wherein, Each of the plurality of light emitting control signal lines is configured to provide a light emitting control signal to a gate of the first light emitting control transistor. And The first voltage connection pad is located at the same layer as the plurality of light emitting control signal lines.

7. The array substrate according to claim 4, wherein, The first voltage connection pad is connected to the first electrodes of the first light emitting control transistors in two adjacent pixel driving circuits located at the same row.

8. The array substrate of claim 4, wherein, Each of the first voltage supply lines comprises a main body and a plurality of extensions extending away from the main body; Each of the plurality of extensions is connected to the first voltage connection pad; and The first voltage connection pad is connected to the first electrode of the first light emitting control transistor.

9. The array substrate of claim 8, wherein, Each of the pixel driving circuits further comprises a compensation transistor. The active layer of the compensation transistor is located at a second semiconductor material layer, and the second semiconductor material layer is located at a side of the first semiconductor material layer away from a substrate. The main body substantially covers the active layer of the compensation transistor on the substrate.

10. The array substrate according to claim 9, wherein, The main body substantially covers the first electrode, the active layer, and the second electrode of the compensation transistor on the substrate.

11. The array substrate of claim 1, wherein, Each of the pixel driving circuits further comprises a first reset transistor and a second reset transistor. The array substrate further comprises: a plurality of third reset signal lines configured to provide a third reset signal to the first electrodes of the third reset transistors in the plurality of pixel driving circuits; and a plurality of first reset signal lines configured to provide a first reset signal to the first electrodes of the first reset transistors in the plurality of pixel driving circuits, and / or a plurality of second reset signal lines configured to provide a second reset signal to the first electrodes of the second reset transistors in the plurality of pixel driving circuits; The plurality of first reset signal lines, the plurality of second reset signal lines, and the plurality of third reset signal lines extend along a direction substantially parallel to the first direction.

12. The array substrate of claim 1, wherein, The array substrate further comprises: a plurality of third reset signal lines configured to provide a third reset signal to the first electrodes of the third reset transistors in the plurality of pixel driving circuits; a plurality of first low voltage supply lines; a plurality of fourth reset signal lines; and a plurality of fifth reset signal lines. a plurality of fourth reset signal lines; a plurality of sixth reset signal lines; and a plurality of second low voltage supply lines; wherein the plurality of third reset signal lines and the plurality of first low voltage signal lines extend along a direction substantially parallel to a first direction; the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines and the plurality of second low voltage supply lines extend along a direction substantially parallel to a second direction; the second direction is different from the first direction; and the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines and the plurality of second low voltage supply lines are located on a same layer and are located on a side of the plurality of third reset signal lines and the plurality of first low voltage signal lines away from the first semiconductor material layer.

13. The array substrate of claim 12, wherein, the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines and the plurality of second low voltage supply lines are arranged alternately.

14. The array substrate of claim 12, wherein, the plurality of pixel driving circuits are arranged into J columns, J being a positive integer; the J columns include an (8j-7)th column among the J columns, an (8j-6)th column among the J columns, an (8j-5)th column among the J columns, an (8j-4)th column among the J columns, an (8j-3)th column among the J columns, an (8j-2)th column among the J columns, an (8j-1)th column among the J columns and an (8j)th column among the J columns, j being a positive integer, 1≤j≤(J / 8); one of a respective fourth reset signal line among the plurality of fourth reset signal lines, a respective fifth reset signal line among the plurality of fifth reset signal lines, a respective sixth reset signal line among the plurality of sixth reset signal lines and a respective second low voltage supply line among the plurality of second low voltage supply lines is located between the (8j-7)th column and the (8j-6)th column; another one of the respective fourth reset signal line, the respective fifth reset signal line, the respective sixth reset signal line and the respective second low voltage supply line is located between the (8j-5)th column and the (8j-4)th column; a further one of the respective fourth reset signal line, the respective fifth reset signal line, the respective sixth reset signal line and the respective second low voltage supply line is located between the (8j-3)th column and the (8j-2)th column; and a yet one of the respective fourth reset signal line, the respective fifth reset signal line, the respective sixth reset signal line and the respective second low voltage supply line is located between the (8j-1)th column and the (8j)th column.

15. The array substrate of claim 1, further comprising a first respective anode, a second respective anode, a third respective anode and a fourth respective anode; wherein, the first respective anode is an anode of a sub-pixel of a first color, the second respective anode is an anode of a sub-pixel of a second color, the third respective anode and the fourth respective anode are anodes of two sub-pixels of a third color; the first respective anode is an anode of a sub-pixel of a first color, the second respective anode is an anode of a sub-pixel of a second color, the third respective anode and the fourth respective anode are anodes of two sub-pixels of a third color; a third respective anode has a footprint on the substrate that at least partially overlaps a footprint of two adjacent second voltage supply lines on the substrate and a footprint of one of the respective fourth reset signal line, the respective fifth reset signal line, the respective sixth reset signal line, and the respective second low voltage supply line on the substrate; and a fourth respective anode has a footprint on the substrate that at least partially overlaps a footprint of two adjacent second voltage supply lines on the substrate and a footprint of one of the respective fourth reset signal line, the respective fifth reset signal line, the respective sixth reset signal line, and the respective second low voltage supply line on the substrate.

16. The array substrate of claim 15, wherein, at least one of the first respective anode, the second respective anode, the third respective anode, or the fourth respective anode has a footprint on the substrate that at least partially overlaps a footprint of the second electrode of the third reset transistor on the substrate.

17. An array substrate comprising a plurality of pixel driving circuits: wherein each pixel driving circuit of the plurality of pixel driving circuits comprises a second node connection line, a first light emitting control transistor, a third reset transistor; the second node connection line is connected to a second electrode of the first light emitting control transistor and to a second electrode of the third reset transistor; and the second node connection line and active layers of the first light emitting control transistor and the third reset transistor are in the same layer; the array substrate further comprises: a plurality of light emitting control signal lines; wherein each light emitting control signal line of the plurality of light emitting control signal lines is configured to provide a control signal to a gate of the first light emitting control transistor; and the plurality of light emitting control signal lines are spaced apart from the second node connection line by at least three insulating layers.

18. The array substrate of claim 17, wherein, each pixel driving circuit further comprises a first node connection line, a storage capacitor, and a compensation transistor; the first node connection line is connected to a first capacitor electrode of the storage capacitor and to a first electrode of the compensation transistor; and the plurality of light emitting control signal lines and the first node connection line are in the same layer.

19. A display device comprising the array substrate of any one of claims 1 to 18 and one or more integrated circuits connected to the array substrate.

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