Semiconductor device

Abstract

The invention relates to a semiconductor device (100) comprising a die layer (110), the die layer (110) forming one or more unit cells (120), the one or more unit cells (120) being distributed side by side on a top surface (111) of the die layer (110). Each unit cell includes a first electrode (121), a second electrode (122), and a third electrode (123) formed on the top surface (111) of the die layer (110). The second electrode (122) is arranged so as to surround the first electrode (121). Each of the first electrode (121) and the second electrode (122) is arranged so as to surround the third electrode (123). The semiconductor device (100) comprises a first metal trace (131) formed in electrical contact with the first electrode (121); a second metal trace (132) formed in electrical contact with the second electrode (122); and a third metal trace (133) formed in electrical contact with the third electrode (123). The first metal trace (131), the second metal trace (132), and the third metal trace (133) are formed over the top surface (111) of the die layer (110) by a same metal interconnect layer level (M1).

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology for power device applications, in particular wide bandgap power devices. The present invention particularly relates to a semiconductor device and a method for manufacturing such a semiconductor device. Specifically, a hexagonal lateral GaN (gallium nitride)-eHEMT (enhanced high electron mobility transistor) is disclosed, the transistor having active bond current extraction. Background Art

[0002] For the development of wide bandgap power devices with voltage ratings below 600V and / or low-ohmic devices, standard packaging schemes based on bond pad configurations outside the active area are less suitable. In these topologies, there are dedicated bond pads on the side of the active area to guarantee space for the soldering process that usually uses bond wires or clips to connect the device to the package. This configuration may have the following disadvantages: the current for the source and drain terminals must flow from all device areas to one side of the die, where the current is collected. This may cause current crowding, parasitic resistance and inductance; the lower the ohmic rating of the device, the worse the situation may be. The area loss caused by the space allocated to the bond pads not being used as active area may reduce area and cost effectiveness. In addition, such a design is less compatible with advanced packaging schemes. Summary of the invention

[0003] The present invention provides a technical solution for overcoming the limitations of the above packaging solutions.

[0004] Specifically, the present invention provides a technical solution for providing an active bonding packaging solution suitable for wide bandgap power devices, especially low voltage and / or low ohmic devices.

[0005] The above and other objects are achieved by the features of the independent claims. Other implementations are apparent from the dependent claims, the description and the drawings.

[0006] In the present invention, a novel semiconductor device, especially a wide bandgap power device, such as a GaN-HEMT (HEMT means high electron mobility transistor) device, is proposed, which is suitable for active bonding packaging design and provides the following advantages: reduced constraints on metallization caused by small pitch; improved area / cost; reduced parasitics; and conforming to advanced and efficient packaging solutions.

[0007] The proposed semiconductor device is based on a unit cell configuration, such as hexagonal, with a complete layout and metallization scheme suitable for active bonding packaging.

[0008] In the present invention, semiconductor devices are described, especially HEMT devices and GaN-HEMT devices. HEMT is a field effect transistor that combines the junction between two different band gap materials, for example, a heterojunction as a channel instead of a doped region (usually for MOSFET). Commonly used material combinations are GaAs, AlGaAs, InGaAs and GaN. GaN-HEMT is particularly suitable due to its high power performance. They can be used in a wide range of applications such as power supplies, DC-DC converters, motor controllers and many other applications.

[0009] Due to the lateral configuration of GaN-HEMTs, the three terminals of the device (i.e., source, drain, and gate) are located on the front side of the device. Current extraction for each terminal is achieved by a separate connection from the terminal itself to its external package pin. This is achieved through a combination of vias and metal tracks: the metal tracks are located on different levels and separated by a dielectric. The via serves as a local electrical connection between two consecutive metal levels. Using these technologies and design frameworks, GaN-HEMT designs can be implemented in the following ways: (A) either using (at least) three metal levels; this approach is costly and requires the development of a suitable back-end in the semiconductor factory; and / or (B) by routing the three terminals in the following way: the low voltage pins (gate and source) are located on one side of the device and the high voltage pin (drain) is located on the other side of the device: then the use of bond pads is required. In addition, the final packaging solution usually requires the introduction of bond routing to connect the bond pads to the relevant pins of the package. The latter technical solution can be suitable for high voltage applications, but is not efficient for medium and low voltages (e.g., below 600V) for the reasons mentioned in the background section.

[0010] The proposed semiconductor device, in particular the novel GaN-HEMT device disclosed below, solves the above problems and provides a design where the complete fabrication of the device can be achieved in only two metal levels and is compatible with the active bonding scheme as shown below.

[0011] The semiconductor device introduced in the present invention can be produced by using a variety of technologies (meaning buffer), for example, GaN-on-Si, GaN-on-GaN, GaN-on-SiC, GaN-on-SOI, GaN-on-QST, etc.

[0012] The embodiments described in this invention introduce full metallization compatible with active bonding packaging schemes by using special metal routing for all terminals as described below and by using gate runners compatible with closed unit cell designs. The embodiments described in this invention provide a full product layout that can be based on staggered or aligned unit cells.

[0013] According to a first aspect, the present invention relates to a semiconductor device, comprising: a tube core layer, comprising a top surface and a bottom surface opposite to the top surface; wherein the tube core layer forms one or more unit cells, and the one or more unit cells are distributed side by side on the top surface of the tube core layer, wherein each unit cell comprises a first electrode, a second electrode and a third electrode formed on the top surface of the tube core layer; wherein the second electrode is arranged to surround the first electrode; wherein each of the first electrode and the second electrode is arranged to surround the third electrode; a first metal trace for routing a first current of the first electrode of the one or more unit cells, The first metal trace is arranged above the first electrode and formed to be electrically contacted with the first electrode; a second metal trace is used to route a second current of the second electrode of the one or more unit cells, and the second metal trace is arranged above the second electrode and formed to be electrically contacted with the second electrode; a third metal trace is used to route a third current of the third electrode of the one or more unit cells, and the third metal trace is arranged above the third electrode and formed to be electrically contacted with the third electrode, wherein the first metal trace, the second metal trace and the third metal trace are formed above the top surface of the tube core layer through the same metal interconnect layer level M1.

[0014] The proposed semiconductor device provides a bonding pad configuration that can be used within the active area of ​​the semiconductor device, whereas in conventional devices, packaging can only be achieved using a bonding pad configuration outside the active area.

[0015] Another advantage is that full metallization of all terminals can be achieved using only one metallization level. It should be understood that this includes adding an additional metallization level for the final routing.

[0016] The chip layer may include a diode or a MOSFET or an IGBT. The first electrode and the second electrode may be electrodes of a diode or two electrodes (eg, a gate and a source) of a transistor.

[0017] In an exemplary implementation of the semiconductor device, the second electrode forms a closed geometric outline around the first electrode. Similarly, the first electrode and the second electrode can form a closed geometric outline around the third electrode. Therefore, the unit cell can be implemented in a space-efficient manner. In addition, multiple unit cells can be placed side by side without wasting die layers.

[0018] In an exemplary implementation of the semiconductor device, at least one of the first electrode, the second electrode, and the third electrode extends in a direction along the top surface of the tube core layer. The space on the tube core layer can be efficiently utilized. For example, the extended electrode can easily adapt to the tube core area formed by a rectangular shape.

[0019] The extension is performed in a direction along the top surface of the tube core layer. For example, in the case of a hexagon, this direction can be any of the three symmetry axes of the hexagon between two corners of the hexagon. In the example of a circle, this can be any direction along the top surface, converting the circle into an elongated circle, for example, two semicircles connected by equal length straight lines, for example, as shown in the racetrack shape in the figure below.

[0020] In an exemplary implementation of the semiconductor device, the closed geometric profile is symmetrical about one or more directions along the top surface of the tube core layer; the closed geometric profile has at least one sharp angle, at least one rounded corner and / or at least one cut corner or any combination thereof. This provides flexible design and management of the final electric field peak at the sharp corner. The profile of the unit cell can be adapted to the available shape of the tube core layer.

[0021] In the exemplary implementation of the semiconductor device, the closed geometric outline is a hexagon, an octagon, a triangle, a square, a rectangle or a circle, thereby providing a flexible design. Various different designs can be implemented as needed.

[0022] In an exemplary implementation of the semiconductor device, the first metal trace is formed to be in electrical contact with the first electrode of each unit cell through a corresponding first through hole, the corresponding first through hole being formed on top of the first electrode; the second metal trace is formed to be in electrical contact with the second electrode of each unit cell through a corresponding second through hole, the corresponding second through hole being formed on top of the second electrode; the third metal trace is formed to be in electrical contact with the third electrode of each unit cell through a corresponding third through hole, the corresponding third through hole being formed on top of the third electrode. Therefore, efficient electrical connection between the electrode and the metal trace is achieved through the corresponding through hole.

[0023] The vias may be implemented as direct contacts between a metallization level (eg M2) and a corresponding electrode. However, it should be understood that this is only a simplification. A person having ordinary skills in the art will understand that different connections are possible through the vias.

[0024] In an exemplary implementation of the semiconductor device, the first metal trace extends over a portion of the first electrode and leaves space for the third metal trace to extend over the first electrode; and / or the second metal trace extends over a portion of the second electrode and leaves space for the first metal trace and the third metal trace to extend over the second electrode. By utilizing the available die area, the electrodes can be efficiently connected to the corresponding metal traces.

[0025] In an exemplary implementation of the semiconductor device, the width of the first electrode is wider or narrower than the width of the first metal trace; the width of the second electrode is wider or narrower than the width of the second metal trace; and / or the width of the third electrode is wider or narrower than the width of the third metal trace. Flexible design, such as compact design and / or forming a field plate for electric field shaping is possible.

[0026] In an exemplary implementation of the semiconductor device, the first electrode is not aligned toward the first metal trace; the second electrode is not aligned toward the second metal trace; and / or the third electrode is not aligned toward the third metal trace. Due to this flexible design of the semiconductor device, the available space on the die can be efficiently utilized and a field plate can be formed.

[0027] In one exemplary implementation of the semiconductor device, a shape of each of the first metal trace and the second metal trace over the one or more unit cells corresponds to a zigzag pattern.

[0028] Therefore, the first metal trace and the second metal trace can adapt their shapes to the geometric outline of the unit cell, especially the hexagonal unit cell.Then, the first metal trace and the second metal trace can be placed directly above their corresponding electrodes to reduce the line length.

[0029] In an exemplary implementation of the semiconductor device, the first metal trace includes a portion surrounding the one or more unit cells. Gate runner elements can be efficiently implemented, for example, traces that surround one or more unit cells and are easily accessible from outside the unit cells.

[0030] In an exemplary implementation of the semiconductor device, the shape of the third metal trace above the one or more unit cells corresponds to a zigzag line or a straight line. The third metal trace can adapt its shape to the geometric outline of the unit cell, especially the hexagonal unit cell. Then, the third metal trace can be placed directly above their corresponding electrodes to reduce the line length.

[0031] In an exemplary implementation of the semiconductor device, the one or more unit cells are arranged on the top surface of the tube core layer in a staggered pattern without forming an area of ​​the tube core layer or a sub-area thereof at least not occupied by the unit cells between the unit cells. The area of ​​the tube core layer is efficiently utilized without leaving unused space between the unit cells.

[0032] In an exemplary implementation of the semiconductor device, the one or more unit cells are aligned relative to each other so that a region of the die layer or at least a sub-region thereof not occupied by a unit cell is formed between the unit cells. The unit cells can be flexibly designed, for example, from the perspective of metallization and spacing.

[0033] Even in a staggered pattern or layout, there may be areas of the die that are not occupied by the unit cells, particularly at the edges of the blocks.

[0034] The regions of the die layer between the unit cells may cover the entire region between the unit cells of the unit block, or only cover a portion of the entire region, in which case these regions are represented as sub-regions. These sub-regions may be interconnected and / or isolated from each other.

[0035] In an exemplary implementation of the semiconductor device, the one or more unit cells are arranged in a periodic pattern on the top surface of the die layer, wherein the periodic pattern is interrupted by one or more empty unit cells or unit cells that are not arranged in the periodic pattern. This allows efficient use of the die area without being too restricted in design considerations.

[0036] Even if the concept of staggering or alignment aims at a periodic pattern, it needs to be understood that it is also possible to include interruptions of the periodic pattern: in other words, it is possible to replace one or several unit cells with an empty unit cell or another unit cell.

[0037] In an exemplary implementation of the semiconductor device, a distance is formed between the second electrode and the first electrode of the unit cell according to a voltage level below 1.2 kV and / or an ohm level below 500 mΩ. Therefore, the semiconductor device can be particularly used in low voltage and / or low ohm applications.

[0038] In an exemplary implementation of the semiconductor device, the semiconductor device includes a gallium-nitride high electron mobility transistor (GaN HEMT) device. Such a semiconductor device can be applied to a wide bandgap transistor device.

[0039] In an exemplary implementation of the semiconductor device, the tube core layer forms one or more unit blocks, and the one or more unit blocks are distributed side by side on the top surface of the tube core layer, wherein each unit block includes at least one unit cell of the one or more unit cells; the semiconductor device includes: a second metal level M2 for routing current of the one or more unit blocks, and the second metal level M2 is arranged above the first metal level M1. When the second metal level M2 is arranged above the first metal level M1, a flexible and space-saving design is achieved.

[0040] In one exemplary implementation of the semiconductor device, the second metal level M2 includes one or more first metal pads formed to electrically contact the first electrode of each unit cell through corresponding vias formed between the first metal trace and the one or more first metal pads. Thus, a flexible and space-efficient electrical contact with the first electrode is achieved.

[0041] In one exemplary implementation of the semiconductor device, the second metal level M2 includes one or more second metal pads, the one or more second metal pads being formed to electrically contact the second electrode of each unit cell through corresponding vias, the corresponding vias being formed between the second metal traces and the one or more second metal pads, thereby achieving flexible and space-efficient electrical contact with the second electrode.

[0042] In one exemplary implementation of the semiconductor device, the second metal level M2 includes one or more third metal pads formed to electrically contact the third electrode of each unit cell through corresponding vias formed between the third metal trace and the one or more third metal pads. Thus, a flexible and space-efficient electrical contact with the third electrode is achieved.

[0043] According to a second aspect, the present invention relates to a method for manufacturing a semiconductor device, the method comprising: forming a tube core layer, the tube core layer comprising a top surface and a bottom surface opposite to the top surface; forming one or more unit cells in the tube core layer, the one or more unit cells are distributed side by side on the top surface of the tube core layer; forming a first electrode, a second electrode and a third electrode on the top surface of the tube core layer in each unit cell, wherein the second electrode is arranged to surround the first electrode, and each of the first electrode and the second electrode is arranged to surround the third electrode; forming a first metal trace, the first metal trace is used to route a first current of the first electrode of the one or more unit cells, the A first metal trace is arranged above the first electrode and formed to be in electrical contact with the first electrode; a second metal trace is formed, the second metal trace is used to route a second current of the second electrode of the one or more unit cells, the second metal trace is arranged above the second electrode and formed to be in electrical contact with the second electrode; a third metal trace is formed, the third metal trace is used to route a third current of the third electrode of the one or more unit cells, the third metal trace is arranged above the third electrode and formed to be in electrical contact with the third electrode, wherein the first metal trace, the second metal trace and the third metal trace are formed above the top surface of the tube core layer through the same metal interconnect layer level M1.

[0044] For example, the first metal trace, the second metal trace and the third metal trace may be formed on the first metal level M1 or on other metal levels M2, M3, ..., or at least one metal trace may be formed on different metal levels. Interconnection of different metal levels may also be achieved.

[0045] The advantages of this method are to provide an active bonding packaging solution suitable for wide bandgap power devices, especially low voltage and / or low ohmic devices, and the production of corresponding semiconductor devices.

[0046] The semiconductor device manufactured by this method provides the following advantages: a bonding pad configuration within the active area of ​​the semiconductor device can be used, while in conventional devices, packaging can only be achieved using a bonding pad configuration outside the active area.

[0047] Another advantage is that complete metallization of all terminals can be achieved using only one metallization level. It will be appreciated that the final metal cladding also comprises an additional metal level.

[0048] The advantages of the method are the same as those of the corresponding implementations of the above-described device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Other embodiments of the present invention will be described in conjunction with the following drawings, in which:

[0050] Figure 1 A schematic diagram of a semiconductor device 100 provided by the present invention;

[0051] Figure 2a A schematic top view of a unit cell 120a in a closed cell configuration provided for a first embodiment;

[0052] Figure 2b A schematic top view of a unit cell 120b in a closed cell configuration provided for a second embodiment;

[0053] Figure 2c A schematic top view of a unit cell 120c in a closed cell configuration provided for a third embodiment;

[0054] Figure 2d A schematic top view of a unit cell 120d in a closed cell configuration provided for a fourth embodiment;

[0055] Figure 2e Shows Figure 2a A schematic top view of a unit cell 120 is shown for use with Figure 2f The unit cell 120f is shown for comparison;

[0056] Figure 2f A schematic top view of a unit cell 120f in a closed cell configuration provided for a fifth embodiment;

[0057] Figure 3a A schematic top view of a unit cell 140 as a basic building block of the disclosed semiconductor device provided for a first embodiment, the unit cell including an exemplary number of 16 unit cells 120 in a staggered cell configuration;

[0058] Figure 3b 1 shows a schematic top view of a cell block 140, wherein a through hole 321 is provided on the top of the drain contact 123, wherein the circular shape is only exemplary, and any other geometric shapes may be applied, such as rectangle, triangle, hexagon, stripe, etc.;

[0059] Figure 3c shows a schematic top view of a cell block 140, wherein a drain metal track 133 extends over a via 321;

[0060] Figure 3d 1 shows a schematic top view of a cell block 140 , wherein a source metal line 132 extends over a source contact line 122 ;

[0061] Figure 3e1 shows a schematic top view of a cell block 140 , wherein a gate metal line 131 follows a gate terminal line 121 and a gate runner 131 c ;

[0062] Figure 3f A schematic top view of the metallization of the cell block 140 is shown, without showing the unit cell 120;

[0063] Figure 4 A schematic top view of an exemplary layout of a semiconductor device 200 provided by the present invention is shown, wherein there are an exemplary number of four unit blocks 140 and a second metallization level;

[0064] Figure 5a shows a schematic cross section of a semiconductor device 500a having a first metallization level M1 according to one embodiment;

[0065] Figure 5b shows a schematic cross section of a semiconductor device 500b having a first metallization level M1 and a second metallization level M2 provided by one embodiment;

[0066] Figure 5c shows a schematic cross section of a semiconductor device 500 c having a first metallization level M1 and a second metallization level M2 provided by another embodiment;

[0067] Figure 5d shows a schematic cross section of a semiconductor device 500d having a first metallization level M1 and a second metallization level M2 provided by another embodiment;

[0068] Figure 6a Shown for use with Figure 6b and Figure 6c For comparison Figure 5a A schematic cross section of a semiconductor device 500a is shown in FIG.

[0069] Figure 6b shows a schematic cross section of a semiconductor device 600 c having a first metallization level M1 according to another embodiment;

[0070] Figure 6c shows a schematic cross section of a semiconductor device 600d having a first metallization level M1 according to another embodiment;

[0071] Figure 7a Shown for use with Figure 7b For comparison Figure 5b A schematic cross section of a semiconductor device 500b is shown in FIG.

[0072] Figure 7bshows a schematic cross section of a semiconductor device 700 b having a first metallization level M1 and a second metallization level M2 provided by another embodiment;

[0073] Figure 8a A schematic top view of a cell block 140 including an exemplary number of 16 unit cells 120 in an aligned cell configuration provided for a second embodiment;

[0074] Figure 8b A schematic top view of an exemplary metallization of a cell block 140 in a metal level M1 is shown, without showing the unit cells 120;

[0075] Fig. 9 A schematic top view of another exemplary metallization of a unit block 140 in a metal level M1 provided in the third embodiment is shown, without showing the unit cell 120;

[0076] Fig.10a A schematic top view of another exemplary metallization of a unit block 140 in a metal level M1 provided in a fourth embodiment is shown, without showing the unit cell 120;

[0077] Fig.10b A schematic top view of another exemplary metallization of a unit block 140 in a metal level M1 provided in a fifth embodiment is shown, without showing the unit cell 120;

[0078] Fig.11a A schematic top view of another exemplary metallization of a unit block 140 in a metal level M1 provided in the sixth embodiment is shown, without showing the unit cell 120;

[0079] Fig.11b A schematic top view of another exemplary metallization of a unit block 140 in a metal level M1 provided in the seventh embodiment is shown, without showing the unit cell 120;

[0080] Fig.12a A schematic top view of an exemplary layout of a semiconductor device 300 a provided in the first embodiment is shown, wherein there are an exemplary number of six unit blocks 140 and a second metallization level;

[0081] Figure 12b A schematic top view of an exemplary layout of a semiconductor device 300 b provided in the second embodiment is shown, wherein there are an exemplary number of six unit blocks 140 and a second metallization level;

[0082] Fig.13 A schematic diagram of a method 800 for manufacturing a semiconductor device provided by the present invention. DETAILED DESCRIPTION

[0083] The following detailed description is provided in conjunction with the accompanying drawings, which are a part of the description and show, by way of illustration, specific aspects in which the present invention may be implemented. It will be appreciated that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description should not be understood in a restrictive sense, and the scope of the present invention is defined by the appended claims.

[0084] It is understood that comments related to the described method are also applicable to the corresponding device or system for performing the method, and vice versa. For example, if specific method steps are described, the corresponding device may include units for performing the described method steps, even if such units are not explicitly described or shown in the drawings. In addition, it should be understood that the features of the various exemplary aspects described herein may be combined with each other unless otherwise explicitly stated.

[0085] Figure 1 Schematic diagram of a semiconductor device 100 provided by the present invention.

[0086] The semiconductor device 100 includes a core layer 110, the core layer 110 including a top surface 111 and a bottom surface 112 opposite to the top surface 111. The core layer 110 forms one or more unit cells 120 distributed side by side on the top surface 111 of the core layer 110. Each unit cell 120 includes a first electrode 121, a second electrode 122, and a third electrode 123 formed on the top surface 111 of the core layer 110.

[0087] The second electrode 122 is arranged to surround the first electrode 121. Each of the first electrode 121 and the second electrode 122 is arranged to surround the third electrode 123.

[0088] The semiconductor device 100 includes a first metal trace 131 for routing a first current of a first electrode 121 of one or more unit cells 120. The first metal trace 131 is disposed above the first electrode 121 and is formed to be in electrical contact with the first electrode 121.

[0089] The semiconductor device 100 includes a second metal trace 132 for routing a second current of the second electrode 122 of one or more unit cells 120. The second metal trace 132 is disposed above the second electrode 122 and is formed to be in electrical contact with the second electrode 122.

[0090] The semiconductor device 100 includes a third metal trace 133 for routing a third current of a third electrode 123 of one or more unit cells 120. The third metal trace 133 is disposed over the third electrode 123 and is formed to be in electrical contact with the third electrode 123.

[0091] First metal trace 131 , second metal trace 132 , and third metal trace 133 are formed over top surface 111 of die layer 110 through the same metal interconnect layer level M1 .

[0092] An advantage of this semiconductor device 100 is that a bonding pad configuration within the active area of ​​the semiconductor device can be used, whereas in conventional devices, encapsulation can only be achieved using a bonding pad configuration outside the active area. Another advantage is that full metallization of all terminals can be achieved using only one metallization level. It should be understood that the final metal enclosure may require an additional metal level.

[0093] The die layer may include a MOSFET or an IGBT.The first electrode, the second electrode, and the third electrode may be electrodes (eg, a gate, a source, and a drain) of a transistor.

[0094] Notice, Figure 1 The metal traces 131, 132, 133 shown may be wider than the electrodes 121, 122, 123, respectively, e.g. Figure 6c As shown. Figure 1 In the figure, they are drawn with the same width, but this is only for illustration purposes. In addition, the metal traces 131, 132, 133 can each have a different width, for example, Figure 6b and Figure 6c As shown. Electrodes 121, 122, 123 may also each have a different width. In one example, one or more of metal traces 131, 132, 133 may even be smaller than one or more of electrodes 121, 122, 123, for example, Figure 6b shown.

[0095] First metal trace 131 , second metal trace 132 , and third metal trace 133 may be a stack of metal layers and / or alloys of different metal materials, eg, with different percentages of each material in the alloy composition.

[0096] A metal stack is a series of metal layers that form electrical contacts for a terminal (drain, source or gate). The metal (metal stack) used can be a stack of any metal material or an alloy of metal materials, such as (but not limited to) Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, WSi, Ti / Al, Ti / Al / Ti, TiN / Al / TiN, Al / Cu, etc.

[0097] exist Figure 1 In the example shown, the drain electrode 123 is shown as an internal electrode, for example, located in an internal unit cell. It should be understood that Figure 1Similarly, the source (or gate) electrodes 121 and 122 may be located in the inner unit cell, and the drain electrode 123 may be located outside.

[0098] The electrodes 121, 122, 123 may be implemented in such a way that they act as metal field plates. These metal field plates may be located at any terminal (not shown for clarity) using any metal level.

[0099] The second electrode 122 may form a closed geometric outline around the first electrode 121, such as Figure 1 , where a hexagonal outline is shown as an example.

[0100] Similarly, the first electrode 121 and the second electrode 122 may form a closed geometric outline around the third electrode 123 .

[0101] At least one of the first electrode 121, the second electrode 122, and the third electrode 123 may extend along the top surface of the tube core layer 110 in the direction 205. Figure 2b , Figure 2d and Figure 2f as shown in .

[0102] The extension may be performed along the top surface of the tube core layer in direction 205, for example, see Figure 2a and Figure 2b .

[0103] The closed geometric contour may be symmetrical about one or more directions 205, 206 along the top surface of the tube core layer 110, for example, Figure 2a and Figure 2b The closed geometric contour has at least one sharp angle, at least one rounded angle and / or at least one cut angle or any combination thereof, for example, Figure 2a to Figure 2f Cutting corners means that the corners of a geometric figure are cut off to form a different geometric figure. For example, the corners of a unit square are cut off to form a regular polygon with eight sides.

[0104] For example, the closed geometric outline may be a hexagon, an octagon, a triangle, a square, a rectangle or a circle.

[0105] The first metal trace 131 may be formed to electrically contact the first electrode 121 of each unit cell 120 through a corresponding first via 141 formed on top of the first electrode 121, e.g., as shown in FIG. Figure 1 The cross-sectional area of ​​the unit cell 120 is shown at the lower right.

[0106] Similarly, the second metal trace 132 may be formed to electrically contact the second electrode 122 of each unit cell 120 through a corresponding second via 142 formed on top of the second electrode 122, such as Figure 1 The cross-sectional area of ​​the unit cell 120 is shown at the lower right.

[0107] Similarly, the third metal trace 133 may be formed to electrically contact the third electrode 123 of each unit cell 120 through a corresponding third via 143 formed on top of the third electrode 123, for example, as shown in FIG. Figure 1 The cross-sectional area of ​​the unit cell 120 is shown on the lower right side.

[0108] The via 143 may be implemented as a metallization level (eg, M1 or M2) and a corresponding electrode (eg, Figure 1 For M1 or Figure 7a and Figure 7b The direct contact between 133 and 123 shown in M2 is shown. However, it should be understood that this is just a simplification. It can be understood by those skilled in the art that (for example) 133 can be connected by, for example Figure 7b One or more vias 143a, 143b are shown connected to 123. The same applies to vias 142 and 141 and any components separated by more than one metallization level.

[0109] The first metal trace 131 extends over a portion of the first electrode 121 and may leave space for the third metal trace 133 to extend over the first electrode 121. Figure 1 Similarly, second metal trace 132 extends over a portion of second electrode 122 and may leave space for first metal trace 131 and third metal trace 133 to extend over second electrode 122 .

[0110] The width of the first electrode 121 may be wider or narrower than the width of the first metal trace 131, for example, Figure 6a , Figure 6b and Figure 6c Similarly, the width of second electrode 122 can be wider or narrower than the width of second metal trace 132 . The width of third electrode 123 can be wider or narrower than the width of third metal trace 133 .

[0111] For example, metal track 131 may be longer or wider than 121. Example: 131 may have a width greater than 121, and 131 may extend (in length) greater than 121 to connect to the outside world (eg, a gate).

[0112] Similarly, for example, metal track 132 may be longer or wider than 122. Example: 132 may be wider than 122, 132 may extend (in length) greater than 122 to connect to the outside world (eg, a source).

[0113] The first electrode 121 may not be aligned toward the first metal trace 131, e.g. Figure 6c Similarly, the second electrode 122 may not be aligned toward the second metal trace 132 and / or the third electrode 123 may not be aligned toward the third metal trace 133, for example, as shown in FIG. Figure 6c is shown in as an example.

[0114] The shape of each of the first metal trace 131 and the second metal trace 132 over the one or more unit cells 120 corresponds to a zigzag pattern, for example, as Figure 1 The middle left image is shown as an example.

[0115] For example, the first metal trace 131 may include a portion surrounding one or more unit cells 120, such as Figure 1 As shown in the left figure of FIG. , a frame surrounds or encloses a unit cell 120 that can be used as a gate flow channel.

[0116] The shape of the third metal trace 133 over one or more unit cells 120 may correspond to a zigzag line or a straight line. Figure 1 As shown in the left picture.

[0117] One or more unit cells 120 may be arranged in a staggered pattern on the top surface 111 of the core layer 110 without forming a region of the core layer 110 or at least a sub-region thereof not occupied by the unit cells 120 between the unit cells 120. Such a configuration may be Figures 3a to 3f As shown in example.

[0118] Alternatively, one or more unit cells 120 may be aligned relative to each other so that a region of the die layer 110 or at least a sub-region thereof not occupied by the unit cells 120 is formed between the unit cells 120. Figure 8a As shown in example.

[0119] Even in a staggered pattern or layout, there may be areas of the die that are not occupied by the unit cells 120, particularly at the edges of a block, e.g. Figure 1 and Figures 3a to 3f shown.

[0120] The area of ​​the tube core layer 110 between the unit cells 120 can cover the entire area between the unit cells of the unit block, for example, Figure 1, or only cover a portion of the entire area, in which case these areas are represented as sub-areas. These sub-areas can be connected to each other and / or isolated from each other.

[0121] One or more unit cells 120 may be arranged in a periodic pattern on the top surface 111 of the die layer 110. The periodic pattern may be interrupted by one or more empty unit cells or unit cells that are not arranged in the periodic pattern. Figure 1 This configuration is not shown in FIG.

[0122] Even if the intention is to have a periodic pattern in a staggered or aligned concept, it needs to be understood that it is also possible to include interruptions of the periodic pattern: ie it is possible to replace one or several unit cells with an empty unit cell or another unit cell.

[0123] A distance may be formed between the third electrode 123 and the first electrode 121 of the unit cell 120 according to a voltage level lower than 1.2 kV and / or an ohm level lower than 500 mΩ.

[0124] The semiconductor device 100 may include, for example, a Gallium-Nitride High Electron Mobility Transistor (GaN HEMT) device.

[0125] Drain metal trace 133 may extend in a zigzag line in an area efficient but complex metallization, such as Fig. 9 as shown, or extending in a straight line with area efficient and simple metallization, e.g. Figure 3c and Figure 3f As shown, for any case of unit cell configuration, such as staggered, aligned, misaligned, etc.

[0126] For the case where there is no region between unit cells, such as Figure 3d As shown, source metal trace 132 may extend across top surface 111 of die layer 110 in a zigzag line (e.g., with a hexagonal cross section), or for the case where space (region) 611 is located between unit cells (resulting in area loss), e.g., as Figure 8a and Figure 8b shown.

[0127] The gate metal trace 131 may form a gate runner 131c, such as a frame surrounding the cell block, such as Figure 3e , Figure 3f As shown, and the zigzag connection 131 inside the gate channel 131c, for example Figure 3e , Figure 3f shown.

[0128] The gate metal trace 133 may be in a zigzag line, for example Fig. 9 As shown, or in a straight line, such as Figure 8b shown.

[0129] For the second level metallization M2, e.g., the top metallization, the metal may extend parallel, perpendicular, or at any angle toward the lower level metallization, e.g., M1, e.g., Figure 4 or Fig.12a , Figure 12b As shown. The second level metallization M2 can have a stripe shape, a wave shape or any staggered shape. This is applicable to staggered, aligned and misaligned layouts.

[0130] Semiconductor devices can have Figure 1 Hexagonal unit cell configuration shown. The layout can be organized in an aligned, staggered, or staggered fashion.

[0131] The metallization scheme may have the following features: stripe and / or zigzag metal shapes; two or more metal levels; gate metallization 131 fits the portion of the unit cell and gate metal runner shape. Any metal may extend to the inside / outside of the unit cell 120 to form a field plate. The metallization may be compatible with bonding or standard bond pad configurations on active processes.

[0132] Full metallization can be achieved in different scenarios:

[0133] For example, in a first configuration, the metallization of the source, drain and gate may be implemented on one metal level, e.g. Figure 5a M1 shown. One or more higher metal levels may be used to complete the connection.

[0134] For example, in a second configuration, the metallization of the source, drain, and gate may be performed with two metal levels (e.g., Figure 5b , Figure 5c , Figure 5d In this case, one or more higher metal levels may be used to complete the connection.

[0135] In the second configuration, different connection combinations may be implemented, such as (but not limited to) a gate connected to M1 and a source and drain in M2, or a source in M1 and a gate and drain in M2.

[0136] Another interesting configuration is to have only the source in M1 and all other terminals connected in a higher metal level. In this case, the source can be extended as a field plate and used as a design parameter to adjust the electrical performance, such as gate-drain capacitance and gate-source capacitance.

[0137] Another interesting configuration is to connect the source and drain in different metal levels: it helps to increase the current capability of the metal line.

[0138] In some configurations where the source and / or drain and / or gate extend in different metallization levels, or if the gate electrodes are connected only at the edge of the cell block (and not inside), the source and drain metal tracks may have metal extensions 132b, 133b at the edge of the cell block to connect the different metal tracks, e.g. Fig.10a , Fig.10b , Fig.11a , Fig.11b shown.

[0139] Figure 2a A schematic top view of a unit cell 120a in a closed cell configuration is provided for a first embodiment.

[0140] The unit cell 120 a includes a first electrode 121 , a second electrode 122 , and a third electrode 123 formed at the top surface 111 of the die layer 110 .

[0141] The second electrode 122 is arranged to surround the first electrode 121. Each of the first electrode 121 and the second electrode 122 is arranged to surround the third electrode 123.

[0142] In this example, the third electrode is hexagonal. The hexagon has a height 201a relative to the first direction 206. Figure 2a In the example of the vertical direction, and with respect to the second direction 205 having a width 201b, Figure 2a The hexagons are formed symmetrically about the first direction 205 and the second direction 206 along the top surface of the tube core layer 110.

[0143] The first electrode and the second electrode are also hexagonal, but unlike the third electrode, the outlines of the first electrode and the second electrode form the outer edge or frame of the hexagon, such as Figure 2a The hexagonal frame or edge of the first electrode 121 has a height 202a relative to the first direction 206 and a width 202b relative to the second direction 205. The hexagonal frame or edge of the second electrode 122 has a height 203a relative to the first direction 206 and a width 203b relative to the second direction 205. The hexagonal frames or edges of the first electrode 121 and the second electrode 122 are formed symmetrically along the top surface of the tube core layer 110 about the first direction 205 and the second direction 206.

[0144] As described above, the second electrode 122 forms a closed geometric outline around the first electrode 121. The first electrode 121 and the second electrode 122 may surround the third electrode 121 to form a closed geometric outline.

[0145] The closed geometric contour is formed symmetrically along the top surface of the tube core layer 110 about the first direction 205 and the second direction 206. The closed geometric contour may have at least one sharp angle, at least one rounded corner and / or at least one cut corner or any combination thereof. Figure 2a In the example of FIG. 1 , the closed geometrical contours of all electrodes 121 , 122 , 123 have acute angles. Figure 2a In the embodiment, each electrode 121, 122, 123 has six acute angles.

[0146] Figure 2a Also represented is a GaN-HEMT semiconductor device based on the closed unit cell configuration as described above. Figure 2a The unit cell 120a shown in FIG. 1 has a hexagonal shape, which has several advantages. In this example, the third electrode 123 (e.g. Figure 2a The inner unit cell shown in ) may represent a drain terminal.

[0147] The following variations of the disassembled unit cell 120a may also be implemented:

[0148] (1) Source (or drain) in the internal unit cell

[0149] (2) Hexagonal or circular unit cell

[0150] (3) Asymmetric hexagon (such as Figure 2b (shown)

[0151] (4) Sharp or rounded corners

[0152] (5) Metal field plates at any terminal (not shown for clarity) using any metal level

[0153] (6)C GD Can be flexibly designed according to size

[0154] Figure 2b A schematic top view of a unit cell 120b in a closed cell configuration is provided for a second embodiment.

[0155] As described above, at least one of the first electrode 121 , the second electrode 122 , and the third electrode 123 may extend in the direction 205 along the top surface of the die layer 110 .

[0156] exist Figure 2b In the embodiment, the extension is performed along the direction 205 of the top surface of the tube core layer. For example, in Figure 2b In the case of the hexagon shown in , this direction can be any of the three symmetry axes of the hexagon between two corners of the hexagon.

[0157] In this example, the third electrode 123 is in the shape of an extended hexagon. The extended hexagon has a height 201a relative to the first direction 206. Figure 2b In the example of the vertical direction, and with respect to the second direction 205 having an extended width 201b, Figure 2b The hexagons are formed symmetrically along the top surface of the core layer 110 with respect to the extending direction (eg, the second direction 205 ).

[0158] The same extension is applied to the first electrode 121 and the second electrode 122 .

[0159] Figure 2c A schematic top view of a unit cell 120c in a closed cell configuration is provided for a third embodiment.

[0160] The unit cell 120 c includes a first electrode 121 , a second electrode 122 , and a third electrode 123 formed at the top surface 111 of the die layer 110 .

[0161] The second electrode 122 is arranged to surround the first electrode 121. Each of the first electrode 121 and the second electrode 122 is arranged to surround the third electrode 123.

[0162] In this example, the third electrode 123 has a circular shape, and the first electrode 121 and the second electrode 122 are formed in a ring shape surrounding the third electrode 123 .

[0163] Figure 2d A schematic top view of a unit cell 120d in a closed cell configuration is provided for a fourth embodiment.

[0164] As described above, at least one of the first electrode 121 , the second electrode 122 , and the third electrode 123 may extend in the direction 205 along the top surface of the die layer 110 .

[0165] exist Figure 2c and Figure 2d In the example of FIG. 1 , the unit cell 120 c is circular in shape, which is extended to produce a unit cell shape 120 d representing a racetrack.

[0166] exist Figure 2c In the example of the circle shown in , the extension can be in any direction along the top surface, converting the circle into an elongated circle, for example, two semicircles connected by straight lines of equal length, for example, as shown below Figure 2d The runway shape shown in .

[0167] Figure 2e Shows Figure 2a A schematic top view of a unit cell 120 is shown for use with Figure 2fUnit cell 120f is shown for comparison.

[0168] As described above, at least one of the first electrode 121, the second electrode 122, and the third electrode 123 may extend along the top surface of the tube core layer 110 in the direction 205, resulting in Figure 2f The extended hexagon shown in .

[0169] Figure 2f A schematic top view of a unit cell 120f in a closed cell configuration is provided for a fifth embodiment.

[0170] The unit cell 120f is formed by applying Figure 2e The extension operation produces the hexagonal unit cell 120e shown.

[0171] Figure 3a A schematic top view of a unit cell 140 as a basic building block of the disclosed semiconductor device is provided for a first embodiment, the unit cell including an exemplary number of 16 unit cells 120 in a staggered cell configuration.

[0172] One or more unit cells 120 may be arranged in a staggered pattern on the top surface 111 of the core layer 110 without forming a region of the core layer 110 or at least a sub-region thereof not occupied by the unit cells 120 between the unit cells 120. Such a configuration may be Figures 3a to 3f As shown in example.

[0173] The best layout in terms of area coverage (cost efficiency) is Figure 3a The unit cells 120 are formed into a unit block 140 in a staggered manner, and the unit block 140 can be repeated as many times as necessary to ensure the desired current capability of the final product. Figure 3a The example given in contains an exemplary number of 16 unit cells.

[0174] In the following figures, for the sake of clarity, ie, to better distinguish between the unit cell and the metallization scheme, the metallization scheme may be described separately.

[0175] Figure 3b A schematic top view of a cell block 140 is shown with a through hole 321 on top of the drain contact 123 .

[0176] The shape of the through hole 321 is arbitrary.

[0177] The unit cells 120 are arranged on the top surface 111 of the die layer 110 in a staggered pattern without forming areas of the die layer 110 between the unit cells 120. The entire die area is optimally utilized.

[0178] Figure 3cA schematic top view of cell block 140 is shown, wherein drain metal track 133 extends over via 321 .

[0179] Drain metal track 133 extends over the vias of all unit cells 120 to collect drain current.

[0180] Figure 3d A schematic top view of a cell block 140 is shown, wherein a source metal line 132 extends over a source contact line 122 .

[0181] Source metal line 132 extends over the source contact line to collect source current.

[0182] Figure 3e A schematic top view of a cell block 140 is shown, in which a gate metal line 131 follows a gate terminal line 121 and a gate runner 131 c .

[0183] Figure 3e The gate metallization scheme is depicted. It consists of a gate metal line 131 following a gate terminal line and a gate runner 131c. The gate runner 131c is a gate track around the cell block 140 for collecting the gate current of the cell block 140 and bringing it to the outside.

[0184] Figure 3f A schematic top view of the metallization of the cell block 140 is shown, without the unit cells 120 .

[0185] For clarity, in Figure 3f The metallization is depicted in FIG, while the hexagonal unit cell 120 is omitted.

[0186] Complete metallization of all terminals can be achieved using only one metallization level.

[0187] Figure 4 A schematic top view of an exemplary layout of a semiconductor device 200 provided by the present invention is shown, wherein there are an exemplary number of four cell blocks 140 and a second metallization level.

[0188] The tube core layer 110 is formed by one or more unit blocks 140 arranged side by side on the top surface 111 of the tube core layer 110, such as Figure 1 Each unit block 140 includes at least one unit cell 120 among the one or more unit cells 120 .

[0189] like Figure 4 As shown, the semiconductor device 200 includes a second metal level M2 for routing current of one or more cell blocks 140. Figure 1 As shown, the second metal level M2 is arranged above the first metal level M1.

[0190] The second metal level M2 may include one or more first metal pads 211 formed to electrically contact the first electrode 121 of each unit cell 120 through corresponding vias 241 formed between the first metal trace 131 and the one or more first metal pads 211, as shown in FIG. Figure 4 as shown in .

[0191] The second metal level M2 may include one or more second metal pads 212 formed to electrically contact the second electrode 122 of each unit cell 120 through corresponding vias 242 formed between the second metal trace 132 and the one or more second metal pads 212, as shown in FIG. Figure 4 as shown in .

[0192] Second metal level M2 may include one or more third metal pads 213 formed to electrically contact third electrode 123 of each unit cell 120 through corresponding vias 243 formed between third metal trace 133 and the one or more third metal pads 213 .

[0193] It should be noted that, for the sake of clarity, the through holes 241, 242 and 243 are Figure 4 In most cases, they are not visible because they are buried under the metal tracks 213, 212 and 211 respectively.

[0194] The vias 241, 242, 243 may have any geometry that follows the metal tracks they connect to. For example, they may be discontinuous or continuous. Figure 4 The discontinuity shown at 242 is given as an example only.

[0195] The formation of a complete product, ie, the semiconductor device 200 , may be achieved by periodically repeating the unit block 140 . Figure 4 2 is an example showing a layout formed using four unit blocks 140 .

[0196] The second metallization level M2 may be needed to distribute the current to different terminals of each block (ie, cell block 140 ).

[0197] Staggered drain-source metal tracks can be used to contact each terminal alternately.

[0198] For contacting the first metal level M1 and the second level M2, vias 241, 242, 243 may be used.

[0199] For example, the shape and orientation of the metal tracks in metal level 2 (M2) may be arbitrarily selected according to the following examples.

[0200] In a first example, the metal can extend parallel, perpendicular, or at any angle toward the drain lower level metal.

[0201] In a second example, the metal may have stripes, waves, or any staggered shape.

[0202] In a third example, the metal tracks in M2 can be adapted for staggered, aligned, and misaligned layouts, for example, as described below.

[0203] from Figure 4 It can be seen that the second-level metallization M2 of the unit cell can extend over more than one unit block 140 together with each metal track; the second-level metallization M2 can ensure that the through hole of the drain (or source) covers at least part of the drain (or source) metal 1; and the second-level metallization M2 can also ensure that the through hole of the gate at least partially covers the gate metal 1 flow channel.

[0204] In summary, the metallization of the unit cell can be achieved in different ways (depending on the goals and constraints involved). Figure 5a to Figure 5d Several possible implementations and their corresponding advantages are described.

[0205] Figure 5a A schematic cross section of a semiconductor device 500 a having a first metallization level M1 is shown according to one embodiment.

[0206] As mentioned above about Figure 1 As described above, the first electrode 121 , the second electrode 122 , and the third electrode 123 are formed at the top surface 111 of the core layer 110 .

[0207] A first metal trace 131 for routing a first current of the first electrode 121 of the unit cell 120 is arranged over and formed to be in electrical contact with the first electrode 121 .

[0208] A second metal trace 132 for routing a second current of the second electrode 122 of the unit cell 120 is disposed over and formed to be in electrical contact with the second electrode 122 .

[0209] A third metal trace 133 for routing a third current of the third electrode 123 of the unit cell 120 is disposed over and formed to be in electrical contact with the third electrode 123 .

[0210] from Figure 5aAs can be seen in FIG. 1 , first metal trace 131 , second metal trace 132 , and third metal trace 133 may be formed over top surface 111 of die layer 110 through the same metal interconnect layer level ( M1 ).

[0211] A second metal level (M2) may be used to complete the connection.

[0212] The advantages of this configuration are high technology and high cost performance. However, it involves some constraints in layout.

[0213] Figure 5b A schematic cross section of a semiconductor device 500 b having a first metallization level M1 and a second metallization level M2 is shown according to one embodiment.

[0214] contrast Figure 5a , first metal trace 131 may be formed in metallization level M1 , and second metal trace 132 and third metal trace 133 may be formed over top surface 111 of die layer 110 through metallization level M2 of the same metal interconnect layer.

[0215] A third (or higher) metal level (M3) may be used to complete the connection.

[0216] This configuration is a more complex technology, resulting in higher costs. However, the advantage is a greater degree of freedom in metallization.

[0217] Figure 5c A schematic cross section of a semiconductor device 500 c having a first metallization level M1 and a second metallization level M2 is shown according to another embodiment.

[0218] contrast Figure 5a and Figure 5b , first metal trace 131 and third metal trace 133 may be formed in metallization level M2 , while second metal trace 132 and some electrically connected pads may be formed in metallization level M1 .

[0219] A third (or higher) metal level (M3) may be used to complete the connection.

[0220] This configuration is a more complex technology, resulting in higher costs. However, the advantage is that there is more freedom in metallization. The source or drain can be implemented in M1, but if the source is in M1, it is efficient to use an electrically connected field plate (FP). This configuration provides tunable capacitance Cgd (between gate and drain), Cgs (between gate and source), etc.

[0221] Figure 5dA schematic cross section of a semiconductor device 500 d having a first metallization level M1 and a second metallization level M2 is shown according to another embodiment.

[0222] contrast Figure 5a to Figure 5c , first and second metal traces 131 , 132 and some electrically connected field plates may be formed in metallization level M1 , while third metal traces 133 may be formed in metallization level M2 .

[0223] In the case of active-no-bonding, the source and gate (or drain and gate) may be implemented in the metallization level M1 and the third terminal in the metallization level M2.

[0224] The advantage of this configuration is that the current capability of the metal line is increased.

[0225] As mentioned above about Figure 1 The advantage of the staggered cell configuration of the unit cells described to Figure 5 is that full metallization can be achieved in only two metal levels, providing cost advantages and technical simplicity. This configuration also provides the best compromise between area efficiency (cost) and simplicity to refine the metallization.

[0226] Figure 6a Shown for use with Figure 6b and Figure 6c For comparison Figure 5a Schematic cross section of a semiconductor device 500a is shown in FIG.

[0227] The width of first electrode 121 may be wider or narrower than the width of first metal trace 131. Similarly, the width of second electrode 122 may be wider or narrower than the width of second metal trace 132. The width of third electrode 123 may be wider or narrower than the width of third metal trace 133.

[0228] exist Figure 6b In the example, the widths of first electrode 121 and second electrode 122 are narrower than the widths of first metal trace 131 and second metal trace 132 , and the width of third electrode 123 is wider than the width of third metal trace 133 .

[0229] exist Figure 6c In the example of FIG. 1 , the widths of first electrode 121 , second electrode 122 , and third electrode 123 are narrower than the widths of first metal trace 131 , second metal trace 132 , and third metal trace 133 .

[0230] For example, metal track or trace 131 may be longer or wider than 121. For example, the width of 131 may be greater than the width of 121, and 131 may extend (in length) greater than 121 to connect to the outside world (eg, a gate).

[0231] Similarly, for example, metal track or trace 132 can be longer or wider than 122. For example, the width of 132 can be greater than the width of 122, and 132 can extend (in length) greater than 122 to connect to the outside world (eg, a source).

[0232] exist Figure 6c , the first trace 131 may not be aligned with respect to the first electrode 121 , while the second trace 132 is aligned with the second electrode 122 , and the third trace 133 is aligned with the third electrode 123 .

[0233] Figure 7a Shown for use with Figure 7b For comparison Figure 5b Schematic cross section of a semiconductor device 500 b is shown in FIG.

[0234] Figure 7a The through holes 141, 142, 143 shown in FIG. 1 can be implemented as a metallization level (eg, M2) and a corresponding electrode (eg, Figure 7a Direct contact between 133 and 123) as shown in FIG.

[0235] However, it should be understood that this is only a simplification. A person skilled in the art will understand that, for example, 133 may be connected to 123 via a through hole 143a in contact with M1, and M1 may be in contact with 123 via a through hole 143b. Figure 7b The same situation can also be applied to 142 (although Figure 7b ), and any components separated by more than 1 level of metallization.

[0236] Figure 8a A schematic top view of a cell block 140 including an exemplary number of 16 unit cells 120 in an aligned cell configuration is provided for the second embodiment.

[0237] As the above reference Figure 1 As an alternative to the staggered unit cell configuration described in FIG. 5 , different configurations may also be applied, such as an aligned unit cell configuration.

[0238] exist Figure 8a and Figure 8b In the second embodiment shown, the unit cells are distributed and aligned.

[0239] The unit cells 120 are aligned relative to each other. Figure 8a As shown, the other edges of the hexagonal outlines of the upper four unit cells 120 are located on one line, and the lower edges of the hexagonal outlines of the upper four unit cells 120 are located on another line, as shown in FIG. Figure 8a shown.

[0240] The same positioning applies to the other unit cells 120 .

[0241] Due to this aligned configuration, unused or wasted areas are created between the unit cells 120 .

[0242] Figure 8b A schematic top view of an exemplary metallization of a cell block 140 in metal level M1 is shown, without showing unit cells 120 .

[0243] The second metallization level (M2) can be similar to the above staggered configuration. Figure 1 The same strategy as described in Figure 5 is implemented.

[0244] For Figure 8a and Figure 8b The alignment configuration shown can achieve the following advantages.

[0245] The aligned unit cell configuration greatly simplifies metallization since the drain contact can be connected only with horizontal and / or vertical metal tracks.

[0246] However, this aligned configuration results in an area loss between the unit cells 120. In order to reduce this area loss, a slight misalignment of the unit cells 120 may be applied. The resulting misalignment will result in a staggered unit cell configuration, which is the optimal solution in terms of area utilization.

[0247] Fig. 9 A schematic top view of another exemplary metallization of a unit block 140 in a metal level M1 provided in the third embodiment is shown, without showing the unit cell 120 .

[0248] This configuration is the above Figure 1 An alternative to the staggered configuration described in relation to FIG. 5 .

[0249] In this metallization scheme, the guideline to maintain best results is to connect all drain contacts without creating discontinuities in the source and gate metal lines.

[0250] This scheme is Fig. 9 , where a so-called “herringbone configuration” is applied to the drain metal track 133 .

[0251] This herringbone configuration maintains the cost-effectiveness advantage due to the staggered configuration of the unit cells (similar to the staggered configuration described above).

[0252] It should be understood that alternative implementations may also be designed. However, any deviation from the above embodiments will result in increased costs, technology, and design complexity.

[0253] For example, the principle of keeping metal tracks free of discontinuities could be overridden. This would result in additional complexity required to connect all unit cells and require additional metallization levels.

[0254] Fig.10a , Fig.10b , Fig.11a and Fig.11b An exemplary embodiment of the metallization of cell block 140 in metal level M1 is shown, without showing unit cells 120 .

[0255] In some cases where the source and / or drain and / or gate extend in different metallization levels, or if the gate electrodes are connected only at the edge of the cell block (and not inside), the source and drain metal tracks may have metal extensions 132b, 133b at the edge of the cell block 140 to connect the different metal tracks, e.g. Fig.10a , Fig.10b , Fig.11a , Fig.11b shown.

[0256] exist Fig.10a , Fig.10b In the embodiment, the metal extensions 132 b and 133 b are located at two sides of the unit block and only cover a portion of the unit block 140 .

[0257] exist Fig.11a , Fig.11b In the embodiment, the metal extensions 132b and 133b are used for the source electrode only on one side of the cell block and for the drain electrode on the other side, presenting an interdigitated concept (fork shape).

[0258] For higher metallization levels, the metal can run parallel, perpendicular, or at any angle toward the lower level metal. The higher level metallization can have stripes, waves, or any staggered shape. This works for staggered, aligned, and misaligned layouts.

[0259] Fig.12a and Figure 12b An exemplary layout of semiconductor devices 300 a , 300 b is shown with an exemplary number of six cell blocks 140 and a second metallization level.

[0260] For the second level metallization M2, e.g., the top metallization, the metal may extend parallel, perpendicular, or at any angle toward the lower level metal, e.g., M1, e.g., Fig.12a , Figure 12b The second level metallization M2 can have a stripe shape, a wave shape or any staggered shape. This is applicable to the staggered, aligned and misaligned layouts described above.

[0261] Fig.13A schematic diagram of a method 800 for manufacturing a semiconductor device provided by the present invention.

[0262] The method 800 may be suitable for manufacturing the Figure 1 to Figure 1 2 is a semiconductor device 100 described in detail.

[0263] The method 800 includes forming 801 a tube core layer 110, wherein the tube core layer 110 includes a top surface 111 and a bottom surface 112 opposite to the top surface 111, for example, as described above with reference to Figure 1 described.

[0264] The method 800 includes forming 802 one or more unit cells 120 in the tube core layer 110, wherein the one or more unit cells 120 are distributed side by side on the top surface 111 of the tube core layer 110, as described above with respect to Figure 1 shown.

[0265] The method 800 includes: forming 803 a first electrode 121, a second electrode 122, and a third electrode 123 on a top surface 111 of a tube core layer 110 in each unit cell 120, wherein the second electrode 122 is arranged to surround the first electrode 121, and each of the first electrode 121 and the second electrode 122 is arranged to surround the third electrode 123, for example, as described above with respect to Figure 1 described.

[0266] The method 800 includes forming 804 a first metal trace 131 for routing a first current of a first electrode 121 of one or more unit cells 120, the first metal trace 131 being arranged above the first electrode 121 and formed to be in electrical contact with the first electrode 121, for example, as described above with respect to Figure 1 described.

[0267] Method 800 includes forming 805 a second metal trace 132 for routing a second current to a second electrode 122 of one or more unit cells 120, the second metal trace 132 being disposed over and formed to be in electrical contact with the second electrode 122, e.g., as described above with respect to Figure 1 described.

[0268] The method 800 includes forming 806 a third metal trace 133 for routing a third current of a third electrode 123 of one or more unit cells 120, the third metal trace 133 being arranged above the third electrode 123 and formed to be in electrical contact with the third electrode 123, wherein the first metal trace 131, the second metal trace 132, and the third metal trace 133 are formed above the top surface 111 of the die layer 110 through the same metal interconnect layer level (M1), for example, as described above with reference to Figure 1 described.

[0269] For example, first metal trace 131 , second metal trace 132 , and third metal trace 133 may be formed on first metal level M1 or on other metal levels M2 , M3 , etc. Interconnection of different metal levels may also be achieved.

[0270] The disclosed technical solution can be applied to GaN HEMTs with horizontal or semi-vertical current flow. The target voltage level is below 1.2kV, but it is not limited to these voltage levels. Higher voltage levels can also be applied.

[0271] Applications using the semiconductor device described in the present invention may be used for buck-boost converters in telecommunications, servers, and the like.

[0272] The technical solution provided by the present invention has the following advantages:

[0273] Full metallization is achieved with only two metal levels, which has a positive impact on the price and simplicity of the technology, however, a third metallization level can be added to increase the degree of freedom.

[0274] Compatible with active bonding schemes for area / cost benefits and with advanced packaging techniques (also compatible with standard bond pad layout configurations), with the following advantages: reduced constraints on metallization due to small pitches; area / cost improvements; and parasitic reduction.

[0275] Furthermore, the present invention provides a unique concept of layout and metallization configuration based on closed unit cells as outlined above.

[0276] Although specific features or aspects of the present invention may have been disclosed in conjunction with only one of several implementations, such features or aspects may be combined with one or more features or aspects in other implementations, as long as it is necessary or advantageous for any given or specific application. Moreover, to a certain extent, the terms "including", "having", "having" or other variations of these words are used in the detailed specification or claims, and such terms are similar to the term "comprising" and are both intended to mean inclusion. Similarly, the terms "exemplarily" and "for example" are only represented as examples, rather than the best or optimal. The terms "coupled" and "connected" and their derivatives may be used. It should be understood that these terms can be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical contact or electrical contact, or they are not in direct contact with each other.

[0277] Although specific aspects have been illustrated and described herein, it will be appreciated by those skilled in the art that various alternative and / or equivalent implementations may be made to the specific aspects shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific aspects discussed herein.

[0278] Although elements in the following claims are recited in a specific order using corresponding labels, these elements are not necessarily limited to being implemented in that specific order unless the claim recitation otherwise implies a specific order for implementing some or all of these elements.

[0279] Through the above enlightenment, it is obvious to those skilled in the art that many alternative products, modifications and variations are available. Of course, it is easy for those skilled in the art to realize that there are many other applications of the present invention in addition to the applications described herein. Although the present invention has been described with reference to one or more specific embodiments, it will be appreciated by those skilled in the art that many changes may be made to the present invention without departing from the scope of the present invention. Therefore, it should be understood that the present invention may be practiced in a manner different from that specifically described herein, as long as it is within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device (100), It is characterized in that include: A tube core layer (110) comprising a top surface (111) and a bottom surface (112) opposite to the top surface (111); The tube core layer (110) forms one or more unit cells (120), and the one or more unit cells (120) are distributed side by side on the top surface (111) of the tube core layer (110), and each unit cell (120) includes a first electrode (121), a second electrode (122), and a third electrode (123) formed on the top surface (111) of the tube core layer (110); wherein the second electrode (122) is arranged to surround the first electrode (121); wherein each of the first electrode (121) and the second electrode (122) is arranged to surround the third electrode (123); a first metal trace (131) for routing a first current of the first electrode (121) of the one or more unit cells (120), the first metal trace (131) being arranged above the first electrode (121) and formed to be in electrical contact with the first electrode (121); a second metal trace (132) for routing a second current of the second electrode (122) of the one or more unit cells (120), the second metal trace (132) being arranged above the second electrode (122) and formed to be in electrical contact with the second electrode (122); a third metal trace (133) for routing a third current of the third electrode (123) of the one or more unit cells (120), the third metal trace (133) being arranged above the third electrode (123) and formed to be in electrical contact with the third electrode (123), The first metal trace (131), the second metal trace (132) and the third metal trace (133) are formed above the top surface (111) of the core layer (110) through the same metal interconnect layer level (M1).

2. The semiconductor device (100) according to claim 1, It is characterized in that The second electrode (122) forms a closed geometric outline around the first electrode (121).

3. The semiconductor device (100) according to claim 2, It is characterized in that At least one of the first electrode (121), the second electrode (122), and the third electrode (123) extends in a direction (205) along the top surface of the tube core layer (110).

4. The semiconductor device (100) according to claim 2 or 3, It is characterized in that The closed geometric contour is symmetrical about one or more directions (205, 206) along the top surface of the tube core layer (110); The closed geometric contour has at least one sharp corner, at least one rounded corner and / or at least one cut corner or any combination thereof.

5. The semiconductor device (100) according to any one of claims 2 to 4, It is characterized in that The closed geometric outline is a hexagon, an octagon, a triangle, a square, a rectangle or a circle.

6. The semiconductor device (100) according to any one of the preceding claims, It is characterized in that The first metal trace (131) is formed to electrically contact the first electrode (121) of each unit cell (120) through a corresponding first through hole (141), and the corresponding first through hole (141) is formed on top of the first electrode (121); The second metal trace (132) is formed to electrically contact the second electrode (122) of each unit cell (120) through a corresponding second through hole (142), and the corresponding second through hole (142) is formed on top of the second electrode (122); The third metal trace (133) is formed to electrically contact the third electrode (123) of each unit cell (120) through a corresponding third via (143) formed on top of the third electrode (123).

7. The semiconductor device (100) according to any one of the preceding claims, It is characterized in that The first metal trace (131) extends over a portion of the first electrode (121) and leaves space for the third metal trace (133) to extend over the first electrode (121); and / or The second metal trace (132) extends over a portion of the second electrode (122) and leaves space for the first metal trace (131) and the third metal trace (133) to extend over the second electrode (122).

8. The semiconductor device (100) according to any one of the preceding claims, It is characterized in that The width of the first electrode (121) is wider or narrower than the width of the first metal trace (131); The width of the second electrode (122) is wider or narrower than the width of the second metal trace (132); and / or The width of the third electrode (123) is wider or narrower than the width of the third metal trace (133).

9. The semiconductor device (100) according to any one of the preceding claims, It is characterized in that The first electrode (121) is not aligned toward the first metal trace (131); The second electrode (122) is not aligned toward the second metal trace (132); and / or The third electrode (123) is not aligned toward the third metal trace (133).

10. The semiconductor device (100) according to any one of the preceding claims, It is characterized in that The shape of each of the first metal trace (131) and the second metal trace (132) over the one or more unit cells (120) corresponds to a zigzag pattern.

11. The semiconductor device (100) according to any one of the preceding claims, It is characterized in that The first metal trace (131) includes a portion surrounding the one or more unit cells (120).

12. The semiconductor device (100) according to any one of the preceding claims, It is characterized in that The shape of the third metal trace (133) over the one or more unit cells (120) corresponds to a zigzag line or a straight line.

13. The semiconductor device (100) according to any one of the preceding claims, It is characterized in that The one or more unit cells (120) are distributed on the top surface (111) of the tube core layer (110) in a staggered pattern without forming a region of the tube core layer (110) or a sub-region thereof at least not occupied by the unit cells (120) between the unit cells (120); or The one or more unit cells (120) are aligned relative to each other so that a region of the core layer (110) or at least a sub-region thereof not occupied by the unit cells (120) is formed between the unit cells (120).

14. The semiconductor device (100) according to any one of the preceding claims, It is characterized in that The one or more unit cells (120) are distributed on the top surface (111) of the tube core layer (110) in a periodic pattern, wherein the periodic pattern is interrupted by one or more empty unit cells or unit cells not arranged in the periodic pattern.

15. The semiconductor device (100) according to any one of the preceding claims, It is characterized in that A distance is formed between the second electrode (123) and the first electrode (121) of the unit cell (120) according to a voltage level lower than 1.2 kV and / or an ohm level lower than 500 mΩ.

16. The semiconductor device (100) according to any one of the preceding claims, It is characterized in that Including Gallium-Nitride High Electron Mobility Transistor (GaN HEMT) devices.

17. The semiconductor device (100) according to any one of the preceding claims, It is characterized in that The tube core layer (110) forms one or more unit blocks (140), and the one or more unit blocks (140) are distributed side by side on the top surface (111) of the tube core layer (110), wherein each unit block (140) includes at least one unit cell (120) of the one or more unit cells (120); The semiconductor device (100) comprises: A second metal level (M2) for routing current of the one or more cell blocks (140), the second metal level (M2) being located above the first metal level (M1).

18. The semiconductor device (100) according to claim 17, It is characterized in that The second metal level (M2) includes one or more first metal pads (211), the one or more first metal pads (211) being formed to electrically contact the first electrode (121) of each unit cell (120) through a corresponding via (241), the corresponding via (241) being formed between the first metal trace (131) and the one or more first metal pads (211); and / or The second metal level (M2) includes one or more second metal pads (212), the one or more second metal pads (212) being formed to electrically contact the second electrode (122) of each unit cell (120) through a corresponding via (242), the corresponding via (242) being formed between the second metal trace (132) and the one or more second metal pads (212); and / or The second metal level (M2) includes one or more third metal pads (213), which are formed to electrically contact the third electrode (123) of each unit cell (120) through corresponding vias (243), and the corresponding vias (243) are formed between the third metal trace (133) and the one or more third metal pads (213).

19. A method (800) for manufacturing a semiconductor device (100), It is characterized in that The method comprises: forming (801) a tube core layer (110), wherein the tube core layer (110) includes a top surface (111) and a bottom surface (112) opposite to the top surface (111); forming (802) one or more unit cells (120) in the tube core layer (110), wherein the one or more unit cells (120) are distributed side by side on the top surface (111) of the tube core layer (110); forming (803) a first electrode (121), a second electrode (122) and a third electrode (123) on the top surface (111) of the tube core layer (110) in each unit cell (120), wherein the second electrode (122) is arranged to surround the first electrode (121), and each of the first electrode (121) and the second electrode (122) is arranged to surround the third electrode (123); forming (804) a first metal trace (131) for routing a first current of the first electrode (121) of the one or more unit cells (120), the first metal trace (131) being arranged above the first electrode (121) and formed to be in electrical contact with the first electrode (121); forming (805) a second metal trace (132) for routing a second current of the second electrode (122) of the one or more unit cells (120), the second metal trace (132) being disposed over the second electrode (122) and formed to be in electrical contact with the second electrode (122); forming (806) a third metal trace (133) for routing a third current of the third electrode (123) of the one or more unit cells (120), the third metal trace (133) being disposed over the third electrode (123) and formed to be in electrical contact with the third electrode (123), Wherein, the first metal trace (131), the second metal trace (132) and the third metal trace (133) are formed above through the same metal interconnect layer level (M1).

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