Frequency adjusting device and method, integrated circuit device and board card

Abstract

The invention relates to a frequency adjusting device and method, an integrated circuit device and a board card. The board card comprises a storage device, an interface device, a control device and an artificial intelligence chip. Wherein the artificial intelligence chip is respectively connected with the storage device, the control device and the interface device; the storage device is used for storing data; the interface device is used for realizing data transmission between the artificial intelligence chip and external equipment; and the control device is used for monitoring the state of the artificial intelligence chip. The board card can be used for executing artificial intelligence operation.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular, to a frequency adjustment device, method, integrated circuit device, and board card. Background Art

[0002] With the continuous progress of technologies in the field of artificial intelligence and the increasing requirements for computing performance by people, the operating frequencies of various artificial intelligence processors are getting higher and higher. While providing higher computing power and processing efficiency, it also brings higher power consumption and heat generation. To solve this problem, frequency adjustment and power consumption management technologies for processors have emerged. Among them, frequency adjustment technology refers to controlling the performance and power consumption of a processor by changing its operating frequency. Due to the complex internal hardware structure of the processor, the tasks to be executed can be decomposed into a considerable number of various complex mathematical operations or logical operations, and the amount of data to be processed by the tasks is also extremely large. How to reduce the power consumption of the processor through a reasonable frequency adjustment technology while ensuring the efficient completion of tasks has always been an urgent problem to be solved in the field of artificial intelligence technology. Summary of the Invention

[0003] To at least partially solve the technical problems mentioned in the background art, the solution of the present invention provides a frequency adjustment device, an integrated circuit device, and a board card.

[0004] In one aspect, the present invention provides a frequency adjustment device, including: a monitoring circuit, configured to obtain a status value of a monitored circuit in a processor and send the status value to a frequency modulation circuit; the frequency modulation circuit, configured to, when the status value is greater than a threshold, mask N of M pulse signals of the clock frequency of the monitored circuit, where N is less than M.

[0005] In one aspect, the status value is used to represent at least one of the number of instructions to be processed, the number of arithmetic operations, the number of handshake signals, the number of data flips, the voltage monitoring value, the current monitoring value, the temperature value, the type of data to be processed, and the power consumption value in the monitored circuit.

[0006] In one aspect, the instruction to be processed is at least one instruction among multiplication, multiply-accumulate, or convolution operation instructions.

[0007] In one aspect, the frequency modulation circuit sequentially masks the pulse signals of multiple monitored circuits according to a monitoring period, or the frequency modulation circuit staggers the masking of the pulse signals of multiple monitored circuits within one monitoring period.

[0008] In one aspect, multiple ones of the thresholds respectively correspond to multiple masking signals. The frequency modulation circuit is configured to determine a masking signal according to a comparison result between the state value and the multiple thresholds, and mask a monitored circuit pulse signal corresponding to the state value according to the masking signal. Among the multiple thresholds, for a threshold indicating a higher load of the monitored circuit, the larger the N value given in the corresponding masking signal.

[0009] In one aspect, the masking signal for masking the monitored circuit pulse signal is executed immediately, or executed when the monitored circuit is idle.

[0010] In one aspect, the frequency modulation circuit is further configured to restore a pulse signal of the monitored circuit clock frequency when the state value is less than or equal to the threshold.

[0011] In one aspect, the frequency modulation circuit is further configured to calculate a fluctuation condition among multiple ones of the state values, and mask the pulse signal of the monitored circuit according to the fluctuation condition.

[0012] In one aspect, when the fluctuation condition is a difference value, and when multiple ones of the difference values are all positive, the frequency modulation circuit masks the pulse signal of the monitored circuit clock frequency, or when multiple ones of the difference values are all negative, the frequency modulation circuit restores the pulse signal of the monitored circuit clock frequency.

[0013] In one aspect, when multiple ones of the difference values are all positive, and at least one of the difference values exceeds an adjustment value, the frequency modulation circuit masks the pulse signal of the monitored circuit clock frequency.

[0014] In one aspect, the present invention provides a frequency adjustment method, including: obtaining a state value of a monitored circuit in a processor; when the state value is greater than a threshold, masking N of M pulse signals of the monitored circuit clock frequency, where N is less than M.

[0015] In one aspect, the state value is used to represent at least one of the number of instructions to be processed, the number of arithmetic operations, the number of handshake signals, the number of data flips, a voltage monitoring value, a current monitoring value, a temperature value, a data type to be processed, and a power consumption value in the monitored circuit.

[0016] In one aspect, the instruction to be processed is at least one instruction among multiplication, multiply-accumulate, or convolution operation instructions.

[0017] In one aspect, multiple ones of the monitored circuit pulse signals are masked in sequence according to a monitoring period, or multiple monitored circuit pulse signals are masked staggeredly within one monitoring period.

[0018] In one aspect, multiple ones of the thresholds respectively correspond to multiple masking signals. A masking signal is determined based on a comparison result between the status value and the multiple thresholds, and a monitored circuit pulse signal corresponding to the status value is masked according to the masking signal. Among the multiple thresholds, for a threshold indicating a higher load of the monitored circuit, the larger the N value given in the corresponding masking signal.

[0019] In one aspect, the masking signal for masking the monitored circuit pulse signal is executed immediately or when the monitored circuit is idle.

[0020] In one aspect, when the status value is less than or equal to the threshold, the pulse signal of the monitored circuit clock frequency is restored.

[0021] In one aspect, the fluctuation condition among multiple ones of the status values is calculated, and the pulse signal of the monitored circuit is masked according to the difference value.

[0022] In one aspect, when the fluctuation condition is a difference value and all the multiple difference values are positive, the pulse signal of the monitored circuit clock frequency is masked, or when all the multiple difference values are negative, the pulse signal of the monitored circuit clock frequency is restored.

[0023] In one aspect, when all the multiple difference values are positive and at least one of the difference values exceeds an adjustment value, the pulse signal of the monitored circuit clock frequency is masked.

[0024] In one aspect, the present invention provides an integrated circuit device including the device according to any one of the above.

[0025] In one aspect, the present invention provides a board card including the integrated circuit device according to the above.

[0026] In one aspect, the present invention provides a computer program product, and when the computer program is executed by a processor, the steps of the method according to any one of the above are implemented.

[0027] In one aspect, the present invention provides a computer device including a memory, a processor, and a computer program stored on the memory, and the processor executes the computer program to implement the steps of the method according to any one of the above.

[0028] The frequency adjustment device provided by the embodiment of the present invention obtains the state value of the monitored circuit in the processor through the monitoring circuit, and sends the state value to the frequency modulation circuit. When the state value is greater than the threshold, the frequency modulation circuit shields N of the M pulse signals of the clock frequency of the monitored circuit, where N is less than M. By shielding the pulse signals of the clock frequency of the monitored circuit, the power consumption of the monitored circuit can be reduced, and by using the combination of the values of M and N, the purpose of precisely controlling the power consumption of the monitored circuit can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention.

[0030] Figure 1 is a structural diagram of a board card showing an embodiment according to the present invention;

[0031] Figure 2 is a structural diagram of a combined processing device showing an embodiment according to the present invention;

[0032] Figure 3 is a schematic diagram showing the clock frequency pulse signal;

[0033] Figure 4 is a schematic diagram showing a frequency adjustment device according to an embodiment of the present invention;

[0034] Figure 5 is a schematic diagram showing a shielding pulse signal according to an embodiment of the present invention;

[0035] Figure 6 is a schematic diagram showing a frequency adjustment device applied to a master-slave architecture according to an embodiment of the present invention;

[0036] Figure 7 is a flowchart of a frequency adjustment method provided by another embodiment of the present invention.

[0037] Through the above-mentioned accompanying drawings, specific embodiments of the present invention have been shown, and there will be more detailed descriptions hereinafter. These drawings and text descriptions are not intended to limit the scope of the inventive concept in any way, but to illustrate the concept of the present invention to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0039] The following introduces the hardware environment where the frequency adjustment device provided by the present invention is located through embodiments.

[0040] In an embodiment of the present invention, Figure 1 is a structural diagram of a board card according to an embodiment of the present invention. The frequency adjustment device in this embodiment can be set in the board card, specifically in the chip in the board card. As Figure 1 shown, the board card 10 includes a chip 101, which is a System on Chip (SoC), or a system-on-chip, integrated with one or more combined processing devices. The combined processing device is an artificial intelligence computing unit used to support various deep learning and machine learning algorithms to meet the intelligent processing requirements in complex scenarios in fields such as computer vision, speech, natural language processing, and data mining. In particular, deep learning technology is widely used in the field of cloud intelligence. A significant feature of cloud intelligence applications is a large amount of input data, which places high requirements on the storage capacity and computing capacity of the platform. The board card 10 in this embodiment is applicable to cloud intelligence applications and has a large off-chip storage, on-chip storage, and a large amount of computing power.

[0041] The chip 101 is connected to an external device 103 through an external interface device 102. The external device 103 is, for example, a server, a computer, a camera, a display, a mouse, a keyboard, a network card, or a wifi interface, etc. The data to be processed can be transmitted from the external device 103 to the chip 101 through the external interface device 102. The calculation result of the chip 101 can be transmitted back to the external device 103 via the external interface device 102. According to different application scenarios, the external interface device 102 can have different interface forms, such as a PCIe interface, etc.

[0042] The board card 10 further includes a storage device 104 for storing data, which includes one or more storage units 105. The storage device 104 is connected to the control device 106 and the chip 101 through a bus for data transmission. The control device 106 in the board card 10 is configured to regulate the state of the chip 101. For this purpose, in one application scenario, the control device 106 can include a Micro Controller Unit (MCU).

[0043] Figure 2It is a structural diagram showing the combined processing device in chip 101 of this embodiment. As Figure 2 shown in the figure, the combined processing device 20 includes a computing device 201, an interface device 202, a processing device 203, and a DRAM 204.

[0044] The computing device 201 is configured to execute operations specified by the user, mainly implemented as a single-core intelligent processor or a multi-core intelligent processor, for performing calculations of deep learning or machine learning. It can interact with the processing device 203 through the interface device 202 to jointly complete the operations specified by the user.

[0045] The interface device 202 is used to transfer data and control instructions between the computing device 201 and the processing device 203. For example, the computing device 201 can obtain input data from the processing device 203 via the interface device 202 and write it into the storage device on the chip of the computing device 201. Further, the computing device 201 can obtain control instructions from the processing device 203 via the interface device 202 and write them into the control cache on the chip of the computing device 201. Alternatively or optionally, the interface device 202 can also read the data in the storage device on the chip of the computing device 201 and transfer it to the processing device 203.

[0046] The processing device 203, as a general-purpose processing device, performs basic controls including but not limited to data transfer, starting and / or stopping of the computing device 201. Depending on different implementation manners, the processing device 203 can be a central processing unit (CPU), a graphics processing unit (GPU), or one or more types of processors such as other general-purpose and / or special-purpose processors, including but not limited to a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and the number thereof can be determined according to actual needs. As mentioned above, only for the computing device 201 of this disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when considering the integration of the computing device 201 and the processing device 203 together, the two are regarded as forming a heterogeneous multi-core structure. The device provided by the present invention can be arranged in the processing device 203 and / or can be arranged in the computing device 201.

[0047] The DRAM 204 is used to store data to be processed. It is a DDR memory, usually with a size of 16G or larger, and is used to save data of the computing device 201 and / or the processing device 203.

[0048] In the clock or synchronization related technologies of a processor, a signal continuously emitted at a certain voltage amplitude and a certain time interval is called a pulse signal. The number of pulses generated within a unit time (such as 1 second) is called the clock frequency. The clock frequency is a measurement term that describes the number of pulses of a periodic cyclic signal (including pulse signals) appearing within a unit time. The standard measurement unit of frequency is Hz (Hertz). The processor operates at a specific clock frequency, and the clock frequency is used to control the working speed and sequence of the processor (or chip), and synchronize the working states of its internal components. For example, the computing device, interface device, and storage device DRAM inside the processor all need to work in coordination according to the rhythm of the clock frequency. The clock frequency is also an important indicator reflecting the processing speed of the processor. A pulse signal is similar to the human heartbeat. For a square pulse, the process of the pulse amplitude rising from 0 to the maximum value is called the rising edge, and vice versa is called the falling edge. A clock signal in the clock frequency usually refers to a pulse signal. Figure 3 is a schematic diagram showing the clock frequency pulse signal. The number of pulse signals within a unit time can intuitively represent the frequency level of the clock frequency. For example, Figure 3 as shown, the frequency of clock frequency 1 is higher than that of clock frequency 2 and lower than that of clock frequency 3. When the clock frequency is high, the working frequency of the processor is high and the power consumption is large. On the contrary, when the clock frequency is low, the working frequency of the processor is low and the power consumption is also low.

[0049] In the prior art, a clock management chip can be used to achieve dynamic adjustment of the clock frequency. For example, the clock management chip may include a clock management module that can dynamically change the output frequency, phase shift, duty cycle, etc. of the clock. In the prior art, the clock frequency can be changed by adjusting parameters through software, or the clock frequency in the circuit can be adjusted by hardware or a combination of software and hardware. For example, integer frequency modulation and fractional frequency modulation implemented using a phase-locked loop are two common frequency adjustment methods. Integer frequency modulation means that there is an integer multiple relationship between the output frequency and the input frequency of the phase-locked loop, while fractional frequency modulation means that there is a non-integer multiple relationship between the output frequency and the input frequency of the phase-locked loop. Fractional frequency modulation has a more extensive application in the frequency adjustment of artificial intelligence processors because the frequency adjustment is relatively more precise than integer frequency modulation. However, in the existing fractional frequency modulation control schemes, usually detection indicators such as temperature and circuit load are monitored, and frequency control is performed when it is found that the processor load is too high to reduce the power consumption of the processor, and there are relatively large defects in timeliness and fineness.

[0050] Figure 4 is a schematic diagram showing a frequency adjustment device according to an embodiment of the present invention. For example,Figure 4 As shown in Figure 4 , in an embodiment of the present invention, a frequency adjustment device is provided, including:

[0051] A monitoring circuit 100, configured to obtain a status value of a monitored circuit in a processor and send the status value to a frequency modulation circuit 200;

[0052] The frequency modulation circuit 200 is configured to shield N of M pulse signals of the clock frequency of the monitored circuit when the status value is greater than a threshold, where N is less than M.

[0053] In an embodiment of the present invention, the provided frequency adjustment device is composed of a monitoring circuit and a frequency modulation circuit. The monitoring circuit is configured to obtain the status value of the monitored circuit in the processor. Among them, the monitored circuit can be any circuit inside the processor. For example, it can be the most basic various components that make up the processor, such as an adder; it can also be a logic circuit, a control circuit, an arithmetic circuit, or a data transmission circuit composed of multiple components for performing any function. For example, the arithmetic circuit with the most power consumption.

[0054] The status value of the monitored circuit can be one or more. The status value can be the status value during the operation of the monitored circuit, such as real-time status values such as temperature value, current value, or voltage value. The real-time status value can represent the real-time load or power consumption of the monitored circuit and can be used for real-time frequency adjustment of the monitored circuit. The status value can also be a status value that can be predicted or known before the task runs for the monitored circuit. For example, the number of command lines, instruction categories, or data volume related to the task that the monitored circuit is about to run, etc. The pre-status value can reflect the load or power consumption of the monitored circuit to a certain extent during operation. Using the pre-status value to control the frequency of the monitored circuit can perform power control in advance before the task runs and avoid excessive power consumption of the monitored circuit. Further, the corresponding task in the pre-status value can be the entire task to be processed by the processor, such as a certain network model to be run by the processor, or it can be a sub-task divided according to preset conditions, such as an arithmetic task of a certain layer in the network model, or it can also be a task when preset conditions are met, such as a task within a certain monitoring period, a task to be executed by a hardware circuit within a certain set range, etc.

[0055] The monitoring circuit in this embodiment can be configured accordingly according to the status value to be monitored, and can be implemented in a way of software cooperating with hardware or hardware. For example, when the status value is the current value, the monitoring circuit is a current detection circuit, and when the status value is the temperature value, the monitoring circuit is a temperature detection circuit. The present invention does not limit the specific implementation manner of the monitoring circuit. After the monitoring circuit obtains the status value of the monitored circuit, it is sent to the frequency modulation circuit.

[0056] In this embodiment, the monitoring circuit can also be used to send the execution status and / or execution result of the shielding pulse signal, so as to improve the overall working efficiency of the frequency adjustment device. For example, shielding successful, shielding not executed, shielding ended, etc.

[0057] The frequency modulation circuit in the embodiment of the present invention is used to compare the received status value with a preset threshold. When the status value is greater than the threshold, the frequency modulation circuit shields N of the M pulse signals of the monitored circuit clock frequency, where N is less than M. Optionally, the frequency modulation circuit can be a filter. The present invention does not limit the specific implementation manner of the frequency modulation circuit, and any software and hardware implementation manner capable of shielding pulse signals can be used. Among them, the threshold can be set according to empirical values or obtained by training an artificial intelligence network model.

[0058] When the status value is greater than the threshold, it indicates that the power consumption value of the monitored circuit is too high and power control is required. It can be understood that the above-mentioned too high power consumption value of the monitored circuit includes the real-time power consumption of the monitored circuit being too high and the pre-power consumption of the monitored circuit being too high. For example, when the real-time status value of the monitored circuit is greater than the threshold, it means that the real-time value of the power consumption of the monitored circuit (i.e., the real-time power consumption value) is too high. Another example is that when the pre-status value of the monitored circuit is greater than the threshold, it means that the power consumption value to be generated by the monitored circuit (i.e., the pre-power consumption value) is too high. When the power consumption value of the monitored circuit is too high, the frequency modulation circuit adjusts the clock frequency of the monitored circuit, shields N of the M pulse signals, where N is less than M, and the monitored circuit does not work when the pulse signal is shielded. By reasonably setting the values of M and N, the purpose of reducing the power consumption of the monitored circuit can be achieved.

[0059] In the embodiment of the present invention, the value of M represents the step size of the pulse signals to be shielded, and the value of N represents the number of shielded pulse signals. When N is greater than 1, the N shielded pulse signals can be evenly distributed among the M pulse signals. Figure 5 is a schematic diagram showing a kind of shielding pulse signal according to an embodiment of the present invention, as Figure 5 shown. For example, when M is 64 and N is 1, it means that 1 out of every 64 pulse signals is shielded, that is, taking 64 pulse signals as a step size, and 1 pulse signal is shielded within each step size; when M is 64 and N is 2, it means that 2 out of every 64 pulse signals are shielded, and the 2 shielded pulse signals are evenly distributed in 64. For example, the 1st and 32nd of the 64 pulse signals can be shielded. As Figure 5 shown, when the pulse signal is shielded, the clock frequency output by the clock circuit does not need to be adjusted. The frequency modulation circuit realizes the adjustment of the pulse signals of the monitored circuit by shielding the pulse signals. When the pulse signal is shielded, the monitored circuit does not work, achieving the purpose of power consumption control for it.

[0060] In an embodiment of the present invention, the frequency adjustment device can be disposed inside or outside the processor. Limited by various factors such as circuit processing delay, for example, the data transfer delay of obtaining the status value, the frequency adjustment efficiency is higher when the frequency adjustment device is disposed inside the processor. The monitoring circuit can be set to one or more according to the number of monitored circuits or monitoring requirements, and multiple monitoring circuits can be respectively used to monitor the status values of different monitored circuits. The frequency modulation circuit can be configured correspondingly according to the setting of the circuit (such as the clock circuit) that sends pulse signals in actual applications, and can be set to one or more, as long as it can shield the pulse signals of the monitored circuit according to the requirements.

[0061] The frequency adjustment device provided in this embodiment obtains the status value of the monitored circuit in the processor through the monitoring circuit and sends the status value to the frequency modulation circuit. When the status value is greater than the threshold, the frequency modulation circuit shields N of the M pulse signals of the clock frequency of the monitored circuit, where N is less than M. By shielding the pulse signals of the clock frequency of the monitored circuit, the power consumption of the monitored circuit can be reduced, and by using the combination of the M value and the N value, the purpose of precisely controlling the power consumption of the monitored circuit can be achieved.

[0062] In an embodiment of the present invention, the status value is used to represent at least one of the number of instructions to be processed, the number of operations, the number of handshake signals, the number of data flips, the voltage monitoring value, the current monitoring value, the temperature value, the type of data to be processed, and the power consumption value in the monitored circuit.

[0063] In this embodiment, the status value can be real-time status values such as the voltage monitoring value, the current monitoring value, the temperature value, and the power consumption value of the monitored circuit, or can be pre-status values such as the number of instructions to be processed, the number of operations, the number of handshake signals, the number of data flips, and the type of data to be processed of the monitored circuit. The status value can also be a combination of one or more of the above values.

[0064] Among the status values, physical circuit operating status values such as voltage monitoring value, current monitoring value, temperature value, and power consumption value can directly represent the power consumption value of the monitored circuit and can be used separately or in combination. The instruction to be processed can be any one of instructions at various levels such as software instructions, hardware instructions, or micro-instructions inside the processor. A large number of instructions to be processed indicates that the monitored circuit needs to execute more instructions and consume a high power consumption value. The number of operations can be the number of logical operations and / or the number of mathematical operations. A large number of operations indicates that the monitored circuit needs to perform a large number of operations and consume a high power consumption value. The number of handshake signals is an interactive signal used for clock synchronization or status alignment inside the monitored circuit or between the internal and external circuits of the monitored circuit. A large number of handshake signals indicates that the monitored circuit needs to process complex tasks, has a large amount of calculations, occupies more transmission resources or processing resources, and has a large amount of data to be processed. Therefore, the monitored circuit needs to consume a high power consumption value. The number of data flips can be the number of flips between "0" and "1" in the data when the data to be processed in the monitored circuit is updated. If the number of data flips is large, it means that the data to be processed by the monitored circuit is complex and requires a large power consumption value. Among the data types to be processed in the status value, data types with higher precision or longer bit widths will cause the monitored circuit to consume more power during operations.

[0065] For the above status values, corresponding thresholds can be set respectively. For example, when the status values are voltage monitoring value, current monitoring value, temperature value, and power consumption value, the thresholds can be voltage value, current value, temperature value, and power consumption value; when the status values are the number of instructions to be processed, the number of operations, the number of handshake signals, and the number of data flips, the thresholds can be the number; when the status value is the data type to be processed, different values can be set for different data types to be processed according to the precision of the data type after sorting, and the thresholds can be set as values. The present invention does not limit the representation method of the thresholds.

[0066] The status values provided in this embodiment can be used to reflect the power consumption of the monitored circuit, facilitating the frequency adjustment device to timely adjust the pulse signal of the clock frequency of the monitored circuit to reduce power consumption.

[0067] In an embodiment of the present invention, the instruction to be processed is at least one of multiplication, multiply-accumulate, or convolution operation instructions.

[0068] In the calculations in the field of artificial intelligence, multiplication and multiply-accumulate operations account for more than 90% of the operations. The multiply-accumulate operation refers to a series of operations where pairs of operands are multiplied and then the results of the multiplications are summed up. When the convolution operation runs at the bottom layer of the processor, it will be decomposed into multiply-accumulate operations and then executed. When the instruction to be processed by the monitored circuit is a multiplication, multiply-accumulate, or convolution operation instruction, it usually means that the monitored circuit has entered the core stage of the operation, and a large amount of data will be processed and a large number of instructions will be executed. Therefore, when the monitoring circuit monitors that the instruction to be processed is at least one of the multiplication, multiply-accumulate, or convolution operation instructions, the monitoring circuit counts the number of instructions to be processed and sends the counting result to the frequency modulation circuit in the form of a status value. The frequency modulation circuit compares it with the corresponding threshold (the threshold of the number of instructions). When the number of instructions to be processed is greater than the threshold, the frequency modulation circuit shields the pulse signal of the monitored circuit to avoid the situation of excessive load when the monitored circuit executes the instructions, so as to control the power consumption of the monitored circuit.

[0069] In this embodiment, the monitoring circuit monitors at least one of the multiplication, multiply-accumulate, or convolution operation instructions in the instruction to be processed. When the monitored status value is greater than the threshold, it indicates that the monitored circuit is about to enter the state of high-load operation. The frequency modulation circuit shields the pulse signal of the monitored circuit, and can control the power consumption of the monitored circuit more accurately with the minimum monitoring cost.

[0070] In an embodiment of the present invention, when there are multiple monitored circuits, one or more monitoring circuits can be set, and one monitoring circuit can monitor one or more monitored circuits. Multiple monitoring circuits can send status values to the frequency modulation circuit separately, or can be unified and sent after being summarized according to a preset rule. The frequency modulation circuit performs subsequent processing after receiving one or more summarized status values. The present invention does not make any limitations in this regard.

[0071] In an embodiment of the present invention, the monitoring circuit hierarchically monitors the status values of multiple monitored circuits, and the monitoring circuits at each level are used to summarize the status values of the lower-level monitored circuits.

[0072] In this embodiment, when there are multiple monitoring circuits, different levels can be set, and the monitoring circuits at each level can summarize the status values of the lower-level monitored circuits. Summarizing the status values of multiple monitored circuits step by step can improve the processing efficiency. For example, there are usually multiple arithmetic circuits in a processor. The multiple arithmetic circuits form a network structure, a tree structure, etc. A monitoring circuit can be set for each arithmetic circuit separately. For the arithmetic circuits with a network structure, the monitoring circuits can be classified row by row or column by column, and the status values are summarized row by row or column by column. Finally, the preset monitoring circuit summarizes and sends them to the frequency modulation circuit. For the arithmetic circuits with a tree structure, a monitoring circuit can also be set for each arithmetic circuit separately. The status values of the lower-level monitored circuits are summarized level by level according to the levels of the tree structure and sent to the upper-level monitoring circuit, and the uppermost monitoring circuit sends the final summarized value to the frequency modulation circuit.

[0073] Figure 6 is a schematic diagram showing a frequency adjustment device applied to a master-slave architecture according to an embodiment of the present invention, as Figure 6 shown, in an embodiment of the present invention, the arithmetic circuits in the processor are of a master-slave architecture. Among them, the master arithmetic circuit parses the received instructions, and after parsing the instructions into micro-instructions, sends them to the slave arithmetic circuits. The slave arithmetic circuits execute corresponding operations according to the micro-instructions to obtain intermediate results. After multiple intermediate results are sent to the master arithmetic circuit, the master arithmetic circuit processes them to obtain the final operation result of the instruction. As Figure 6 shown, the arithmetic circuit is of a master-slave architecture, where the slave arithmetic circuit includes 4 circuit groups, as Figure 6 shown in the circuit groups 1 to 4 in Figure 6 Each group includes 4 basic arithmetic circuits. As Figure 6 shown, circuit group 1 includes basic arithmetic circuit 11, basic arithmetic circuit 12, basic arithmetic circuit 13, and basic arithmetic circuit 14, etc. The basic arithmetic circuits in this embodiment are monitored circuits, and a first monitoring circuit is set for each basic arithmetic circuit. As Figure 6 shown, monitoring circuit 11 (the first monitoring circuit) is set to monitor the status value of basic arithmetic circuit 11, monitoring circuit 12 (the first monitoring circuit) is set to monitor the status value of basic arithmetic circuit 12, etc. A second monitoring circuit is set for each circuit group to summarize the status values of the 4 basic arithmetic circuits in the group. As Figure 6 shown, monitoring circuit 1 (the second monitoring circuit) is used to summarize the status value of circuit group 1, monitoring circuit 2 (the second monitoring circuit) is used to summarize the status value of circuit group 2, etc. The four second monitoring circuits summarize the status values to the third monitoring circuit, such as Figure 6As shown, the frequency modulation circuit is provided in the main operation circuit. The frequency modulation circuit determines whether the status value of each monitored circuit is greater than the threshold according to the received aggregated status value, and determines whether to shield the pulse signal of the basic operation circuit according to the determination result.

[0074] In an embodiment of the present invention, the frequency modulation circuit shields the pulse signals of multiple monitored circuits in sequence according to the monitoring period, or the frequency modulation circuit shields the pulse signals of multiple monitored circuits staggeredly within one monitoring period.

[0075] In this embodiment, when shielding the pulse signals of multiple monitored circuits, the simultaneous change of multiple pulse signals may cause SI (signal integrity) problems such as overshoot and glitch phenomena, resulting in reduced processor efficiency or device damage.

[0076] The frequency modulation circuit can shield the pulse signals of multiple monitored circuits in sequence according to the monitoring period. The monitoring period includes a time period or a frequency period set according to certain conditions, etc. When it is necessary to shield the pulse signals of multiple monitored circuits, multiple monitored circuits can be grouped, and one group of monitored circuits is shielded in sequence in different monitoring periods, or each monitored circuit is directly shielded in sequence in different monitoring periods. For example, there are 24 pulse signals in one monitoring period, and a total of 16 pulse signals of monitored circuits need to be shielded, and each monitored circuit needs to be shielded 4 pulse signals. The frequency modulation circuit can take 4 monitored circuits as a group. The frequency modulation circuit shields the 1st to 4th pulse signals of the first group of monitored circuits in monitoring period 1, and shields the 1st to 4th pulse signals of the second group of monitored circuits in monitoring period 2, and so on until the shielding is completed. In this embodiment, the grouping of the monitored circuits can be divided according to the physical structure or the logical structure, or grouped as needed.

[0077] The frequency modulation circuit can also shield the pulse signals of multiple monitored circuits staggeredly within one monitoring period. For example, there are 36 pulse signals in one monitoring period, and a total of 16 pulse signals of monitored circuits need to be shielded, and each monitored circuit needs to be shielded 2 pulse signals. The frequency modulation circuit can shield the 1st to 2nd pulse signals of the 1st monitored circuit, shield the 3rd to 4th pulse signals of the 2nd monitored circuit, shield the 5th to 6th pulse signals of the 3rd monitored circuit within one monitoring period, and so on until the pulse signals of 16 monitored circuits are shielded. The frequency modulation circuit can also group multiple monitored circuits and shield the pulse signals according to different monitoring periods between groups, and within the group, shield them in the above-mentioned staggered manner.

[0078] In this embodiment, to avoid the SI problem caused by simultaneous adjustment of multiple pulse signals, the frequency modulation circuit adopts a method of sequentially shielding with different monitoring periods or staggered shielding within one monitoring period, so as to avoid simultaneous adjustment of the pulse signals of multiple monitored circuits, and improve the stability and security of the processor operation.

[0079] In an embodiment of the present invention, multiple different thresholds may be set for a certain state value of the monitored circuit, and the multiple thresholds respectively correspond to multiple shielding signals. The frequency modulation circuit is configured to determine a shielding signal according to the comparison results of the state value with the multiple thresholds, and shield the pulse signal of the monitored circuit corresponding to the state value according to the shielding signal. Among them, for the threshold indicating a higher load of the monitored circuit among the multiple thresholds, the larger the N value given in the corresponding shielding signal.

[0080] For example, 6 thresholds of the number of multiply-accumulate instructions are set. The 6 thresholds can correspond to the high and low loads in order of magnitude, and the 6 thresholds respectively correspond to 6 shielding signals. After the state value of the monitored circuit 1 (assumed to be A multiply-accumulate instructions) is compared with the 6 thresholds, it is determined that the state value of the monitored circuit 1 is greater than threshold 1 and less than threshold 2. The shielding signal 1 corresponding to threshold 1 is to shield 2 out of 32 pulse signals. After the state value of the monitored circuit 2 (assumed to be B multiply-accumulate instructions, B > A) is compared with the 6 thresholds, it is determined that the state value of the monitored circuit 2 is greater than threshold 3 and less than threshold 4. The shielding signal 3 corresponding to threshold 3 is to shield 8 out of 32 pulse signals. Therefore, the frequency modulation circuit shields 2 out of 32 pulse signals of the monitored circuit 1 according to the shielding signal 1, and shields 8 out of 32 pulse signals of the monitored circuit 2 according to the shielding signal 3, completing the frequency adjustment of two monitored circuits with different loads. Multiple thresholds can be set as needed according to the state value; the correspondence between the thresholds and the shielding signals can be set according to empirical values, set according to the requirements of power control, or obtained through neural network training, and the present invention does not make any limitations.

[0081] In this embodiment, the multiple set thresholds correspond to different shielding signals, and each shielding signal is used to shield different numbers of pulse signals of the monitored circuit. This embodiment can perform more targeted frequency adjustment according to the actual load level and more precisely control the power consumption.

[0082] In an embodiment of the present invention, the shielding signal for shielding the pulse signal of the monitored circuit is executed immediately or executed when the monitored circuit is idle.

[0083] In this embodiment, the shielding signal may be issued when the frequency modulation circuit determines that the clock frequency of the monitored circuit needs to be shielded, and it is determined by the frequency modulation circuit whether to execute during the busy or idle period of the monitored circuit. Alternatively, after the frequency modulation circuit sends it to the monitored circuit, it is determined by the monitored circuit whether to execute during the busy or idle period. The present invention does not limit this.

[0084] In this embodiment, after the shielding signal is issued, it can be immediately executed by the frequency modulation circuit or the monitored circuit. For example, when it is monitored that the number of multiply-accumulate instructions of the monitored circuit exceeds the threshold, the frequency modulation circuit sends a shielding signal. At this time, regardless of whether the instructions that the monitored circuit needs to execute have been completed or not, the shielding signal can be inserted into the instruction queue and immediately executed. The immediate execution of the shielding signal enables the frequency adjustment device to perform real-time frequency adjustment, making power control more timely and efficient.

[0085] In this embodiment, according to whether the monitored circuit is running or whether it is performing operations (including arithmetic operations, data transfer operations, or control operations, etc.), the state of the monitored circuit can be divided into a busy period and an idle period. The shielding signal can also be waited for the monitored circuit to be idle and then executed by the frequency modulation circuit or the monitored circuit after it is issued. For example, when the monitored circuit is an arithmetic circuit, it is idle when waiting for arithmetic data transmission or loading, and it is busy when performing arithmetic operations after the arithmetic data is transmitted in place. The frequency modulation circuit can view the instruction queue or determine the state of the monitored circuit through other means, and execute the shielding signal when the monitored circuit is idle. At this time, there is a time delay in the execution of the shielding signal. To avoid too long a time delay, the frequency modulation circuit can set a maximum time delay and immediately execute the shielding signal when the maximum time delay condition is met. The execution of the shielding signal during the idle period can also avoid SI problems and improve the stability and security of the circuit operation.

[0086] In an embodiment of the present invention, the frequency modulation circuit is further configured to restore the pulse signal of the clock frequency of the monitored circuit when the state value is less than or equal to the threshold.

[0087] In this embodiment, after the frequency modulation circuit sends a shielding signal to adjust the frequency of the pulse signal of the monitored circuit, the monitoring circuit can continuously send the monitored state value to the frequency modulation circuit. The frequency modulation circuit compares the state value with the threshold and obtains a comparison result. When the comparison result is that the state value is less than or equal to the threshold, it indicates that the load or power consumption of the monitored circuit has decreased. The frequency modulation circuit can send a shielding release signal to restore the pulse signal of the clock frequency of the monitored circuit, improving the working efficiency of the monitored circuit.

[0088] In an embodiment of the present invention, the frequency modulation circuit is further configured to calculate the fluctuation situation between multiple state values and shield the pulse signal of the monitored circuit according to the fluctuation situation.

[0089] If the state value fluctuates greatly, the frequency modulation circuit will frequently send shielding signals and unshielding signals, resulting in frequent changes in the pulse signal of the monitored circuit, unstable circuit operation, and reduced work efficiency. For example, when the state value of the monitored circuit in the 1st to Nth monitoring cycles is lower than the threshold, the state value in the N+1th monitoring cycle is greater than the threshold, and the state value in the N+2th monitoring cycle falls back to less than the threshold. If the frequency modulation circuit immediately adjusts the pulse signal of the monitored circuit after the N+1th monitoring cycle, the pulse signal of the monitored circuit needs to be restored immediately after the N+2th monitoring cycle, resulting in frequent changes in the pulse signal of the monitored circuit, unstable circuit operation, and reduced safety.

[0090] In this embodiment, the monitoring circuit continuously obtains the state value of the monitored circuit, and the frequency modulation circuit does not only adjust the pulse signal of the monitored circuit according to one state value, but adjusts the pulse signal of the monitored circuit according to changes in multiple state values.

[0091] The fluctuation conditions in this embodiment include various calculated values ​​that can be used to reflect the change of the state value, such as the difference and variance between multiple state values, but the present invention does not limit this.

[0092] In this embodiment, the fluctuation situation may include a difference. The frequency modulation circuit calculates the difference between multiple state values, and shields the pulse signal of the monitored circuit according to the difference. As described above, when the state values ​​of the monitored circuit in the 1st to Nth monitoring cycles are all lower than the threshold, the state value in the N+1th monitoring cycle is greater than the threshold, and the state value in the N+2th monitoring cycle falls back to less than the threshold, and the state values ​​in the N+Mth monitoring cycle thereafter are all less than the threshold (M is greater than 2). The frequency modulation circuit calculates the difference 1 between the state values ​​in the 2nd and 1st monitoring cycles, the difference 2 between the state values ​​in the 3rd and 2nd monitoring cycles, the difference 3 between the state values ​​in the 4th and 3rd monitoring cycles, and so on until the difference between the state values ​​in the N+Mth and N+M-1th monitoring cycles is calculated. The frequency modulation circuit determines whether to adjust the pulse signal of the monitored circuit according to the changes in the difference 1, the difference 2, etc. When the difference 1 is a positive number and the difference 2 is a negative number, the frequency modulation circuit does not adjust the pulse signal of the monitored circuit. That is, the frequency modulation circuit no longer adjusts the pulse signal of the monitored circuit according to the change of multiple state values, but according to the change of multiple state values. For example, when the difference 1, the difference 2 and other multiple differences are all positive numbers, it means that the load of the monitored circuit continues to increase. At this time, the frequency modulation circuit shields the pulse signal of the clock frequency of the monitored circuit.

[0093] In addition to calculating the difference between the calculated status value and the previous status value, the frequency modulation circuit can also calculate the differences between the status value and multiple previous consecutive or non-consecutive status values. As described above, the frequency modulation circuit can also calculate the difference 1' between the status values in the 5th and 1st monitoring cycles, the difference 2' between the 5th and 2nd monitoring cycles, the difference 3' between the 5th and 3rd monitoring cycles... and adjust the pulse signal of the monitored circuit according to the changes in the differences 1', 2', 3'. The frequency modulation circuit can also calculate the differences between the Nth status value and multiple previous regularly or randomly arranged status values. The present invention does not limit the calculation method of the differences between the status values.

[0094] In this embodiment, a mutation in the status value of the monitored circuit can only increase the value of one difference, while multiple differences can reflect whether the load of the monitored circuit is continuously increasing. When the load is continuously increasing, the pulse signal of its operation is adjusted. Instead of determining whether to block the pulse signal of the monitored circuit based on one difference, the frequency modulation circuit determines it based on multiple differences, which can avoid frequent changes in the pulse signal caused by frequent fluctuations or mutations in the status value of the monitored circuit, and improve the working efficiency and safety of the monitored circuit.

[0095] In an embodiment of the present invention, when the fluctuation condition is a difference and all of the multiple differences are positive, the frequency modulation circuit blocks the pulse signal of the clock frequency of the monitored circuit, or when all of the multiple differences are negative, the frequency modulation circuit resumes the pulse signal of the clock frequency of the monitored circuit.

[0096] In this embodiment, the above-mentioned multiple differences can be obtained in the form of a time sliding window. For example, to determine whether all 5 differences are positive, after calculating 5 differences, namely difference 1 to difference 5, based on the status values in the 1st to 6th monitoring cycles, subsequently, according to difference 2 to difference 6, difference 3 to difference 7... that is, taking 5 monitoring cycles as a time sliding window, 5 differences are obtained in sequence. The above-mentioned multiple differences can also be obtained in non-overlapping time periods in sequence. For example, according to difference 1 to difference 5, difference 6 to difference 10, difference 11 to difference 15... that is, taking 5 monitoring cycles as a non-overlapping time period, 5 differences are obtained in sequence. The above-mentioned multiple differences can also be obtained according to a preset rule. For example, they can be obtained in a regular manner such as difference 1, difference 3, difference 5, or in a randomly selected manner such as difference 1, difference 4, difference 5. The present invention does not limit this.

[0097] In this embodiment, when multiple differences are all positive, it indicates that the load of the monitored circuit is continuously increasing. When multiple said differences are all negative, it indicates that the load of the monitored circuit is continuously decreasing. The frequency modulation circuit shields or restores the pulse signal of the clock frequency of the monitored circuit according to the continuous change of the differences. Among them, the number of multiple differences can be set according to experience. Since the main purpose of the frequency adjustment device is to adjust and control the average load or average power consumption of the monitored circuit, therefore, the fewer the number of differences to be considered, the higher the real-time performance of the frequency modulation circuit for regulation, and the more the number of differences to be considered, the higher the accuracy of the frequency modulation circuit for regulation.

[0098] In an embodiment of the present invention, when multiple said differences are all positive and at least one of said differences exceeds an adjustment value, the frequency modulation circuit shields the pulse signal of the clock frequency of the monitored circuit. For example, it is necessary to consider five differences at the same time. When the five differences are all positive but each difference is a very small value near 0, it indicates that the load of the monitored circuit changes little in each monitoring period, and there is no need to adjust its pulse signal to reduce power consumption; while when any one or more of the differences exceed the adjustment value (a preset value), it indicates that the load of the monitored circuit has a large increase, and the frequency modulation circuit needs to shield the pulse signal of the clock frequency of the monitored circuit to reduce power consumption. Thus, when multiple differences are all positive and exceed a certain value, the frequency modulation circuit shields the pulse signal of the clock frequency of the monitored circuit, which can make the control accuracy of the frequency modulation circuit higher.

[0099] In an embodiment of the present invention, there is provided an integrated circuit device including the device described in any one of the above.

[0100] In an embodiment of the present invention, there is provided a board card including the above integrated circuit device.

[0101] Figure 7 It is a flowchart of a frequency adjustment method provided in still another embodiment of the present invention. As Figure 7 shown, in an embodiment of the present invention, there is provided a frequency adjustment method, including:

[0102] Step 100: Obtain the state value of the monitored circuit in the processor;

[0103] Step 200: When the state value is greater than a threshold value, shield N of the M pulse signals of the clock frequency of the monitored circuit, where N is less than M.

[0104] In an embodiment of the present invention, the state value is used to represent at least one of the number of instructions to be processed, the number of operations, the number of handshake signals, the number of data flips, the voltage monitoring value, the current monitoring value, the temperature value, the type of data to be processed, and the power consumption value in the monitored circuit.

[0105] In one embodiment of the present invention, the instruction to be processed is at least one of multiplication, multiply-accumulation, or convolution operation instructions.

[0106] In one embodiment of the present invention, the pulse signals of multiple monitored circuits are sequentially masked according to the monitoring period, or the pulse signals of multiple monitored circuits are masked staggeredly within one monitoring period.

[0107] In one embodiment of the present invention, multiple thresholds respectively correspond to multiple masking signals. The masking signal is determined according to the comparison result between the state value and the multiple thresholds, and the pulse signal of the monitored circuit corresponding to the state value is masked according to the masking signal. Among the multiple thresholds, the threshold representing the higher load of the monitored circuit has a larger N value given in its corresponding masking signal.

[0108] In one embodiment of the present invention, the masking signal for masking the pulse signal of the monitored circuit is executed immediately, or executed when the monitored circuit is idle.

[0109] In one embodiment of the present invention, when the state value is less than or equal to the threshold, the pulse signal of the clock frequency of the monitored circuit is restored.

[0110] In one embodiment of the present invention, the difference between multiple state values is calculated, and the pulse signal of the monitored circuit is masked according to the difference.

[0111] In one embodiment of the present invention, when multiple differences are all positive, the pulse signal of the clock frequency of the monitored circuit is masked, or when multiple differences are all negative, the pulse signal of the clock frequency of the monitored circuit is restored.

[0112] In one embodiment of the present invention, when multiple differences are all positive and at least one difference exceeds the adjustment value, the pulse signal of the clock frequency of the monitored circuit is masked.

[0113] In one embodiment of the present invention, a computer program product, when the computer program is executed by a processor, implements the steps of the method described in any one of the above.

[0114] In one embodiment of the present invention, a computer device includes a memory, a processor, and a computer program stored on the memory. The processor executes the computer program to implement the steps of the method described in any one of the above.

[0115] It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should be aware that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0116] It further needs to be noted that although the steps in the flowchart are displayed in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other sequences. Moreover, at least a part of the steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0117] It should be understood that the above device embodiments are only illustrative, and the devices of the present invention can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units, modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0118] In addition, unless otherwise specified, in each embodiment of the present invention, the functional units / modules can be integrated in one unit / module, or each unit / module can exist physically alone, or two or more units / modules can be integrated together. The above integrated unit / module can be implemented in the form of hardware or in the form of a software program module.

[0119] When the integrated unit / module is implemented in the form of hardware, the hardware can be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes but is not limited to transistors, memristors, etc. Unless otherwise specified, the artificial intelligence processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, the storage unit can be any suitable magnetic storage medium or magneto-optical storage medium, such as a resistive random access memory (RRAM), a dynamic random access memory (DRAM), a static random access memory (SRAM), an enhanced dynamic random access memory (EDRAM), a high-bandwidth memory (HBM), a hybrid memory cube (HMC), etc.

[0120] When the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned memory includes: USB flash drives, read-only memories (ROMs), random access memories (RAMs), external hard drives, magnetic disks, or optical discs, etc., which are various media that can store program codes.

[0121] In the above embodiments, the descriptions of the various embodiments have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

Claims

1. A frequency adjustment device, comprising: a monitoring circuit, configured to obtain a status value of a monitored circuit in a processor and send the status value to a frequency modulation circuit; the frequency modulation circuit, configured to shield N of M pulse signals of the clock frequency of the monitored circuit when the status value is greater than a threshold, where N is less than M.

2. The device according to claim 1, wherein, the status value is used to represent at least one of the number of instructions to be processed, the number of operations, the number of handshake signals, the number of data flips, the voltage monitoring value, the current monitoring value, the temperature value, the type of data to be processed, and the power consumption value in the monitored circuit.

3. The device according to claim 2, wherein the instruction to be processed is at least one of a multiplication, multiply-accumulate, or convolution operation instruction.

4. The device according to claim 1, wherein the frequency modulation circuit sequentially shields the pulse signals of multiple monitored circuits according to a monitoring period, or the frequency modulation circuit staggers the shielding of the pulse signals of multiple monitored circuits within one monitoring period.

5. The device according to claim 1, wherein multiple thresholds respectively correspond to multiple shielding signals, and the frequency modulation circuit is configured to determine a shielding signal according to a comparison result between the status value and the multiple thresholds, and shield the pulse signal of the monitored circuit corresponding to the status value according to the shielding signal, wherein, for the threshold among the multiple thresholds that represents a higher load of the monitored circuit, the N value given in the corresponding shielding signal is larger.

6. The device according to claim 1, the shielding signal for shielding the pulse signal of the monitored circuit is immediately executed or executed when the monitored circuit is idle.

7. The device according to claim 1, the frequency modulation circuit is further configured to restore the pulse signal of the clock frequency of the monitored circuit when the status value is less than or equal to the threshold.

8. The device according to claim 1, the frequency modulation circuit is further configured to calculate the fluctuation situation between multiple status values and shield the pulse signal of the monitored circuit according to the fluctuation situation.

9. The device according to claim 8, when the fluctuation situation is a difference value, and when multiple difference values are all positive, the frequency modulation circuit shields the pulse signal of the clock frequency of the monitored circuit, or when multiple difference values are all negative, the frequency modulation circuit restores the pulse signal of the clock frequency of the monitored circuit.

10. The device according to claim 9, when multiple difference values are all positive and at least one difference value exceeds an adjustment value, the frequency modulation circuit shields the pulse signal of the clock frequency of the monitored circuit.

11. A frequency adjustment method, comprising: obtaining a status value of a monitored circuit in a processor; when the status value is greater than a threshold, shielding N of M pulse signals of the clock frequency of the monitored circuit, where N is less than M.

12. The method according to claim 11, wherein, the status value is used to represent at least one of the number of instructions to be processed, the number of operations, the number of handshake signals, the number of data flips, the voltage monitoring value, the current monitoring value, the temperature value, the type of data to be processed, and the power consumption value in the monitored circuit.

13. The method according to claim 12, wherein the instruction to be processed is at least one of a multiplication instruction, a multiply-accumulate instruction, or a convolution operation instruction.

14. The method according to claim 11, wherein the pulse signals of multiple monitored circuits are sequentially masked according to a monitoring period, or the pulse signals of multiple monitored circuits are masked staggeredly within one monitoring period.

15. The method according to claim 11, wherein multiple thresholds respectively correspond to multiple masking signals, a masking signal is determined according to a comparison result between the state value and the multiple thresholds, and the pulse signal of the monitored circuit corresponding to the state value is masked according to the masking signal. wherein for the threshold among the multiple thresholds that represents a higher load of the monitored circuit, the larger the N value given in the corresponding masking signal.

16. The method according to claim 11, wherein the masking signal for masking the pulse signal of the monitored circuit is immediately executed, or executed when the monitored circuit is idle.

17. The method according to claim 11 further comprises: When the state value is less than or equal to the threshold, the pulse signal of the clock frequency of the monitored circuit is restored.

18. The method according to claim 11, calculating the fluctuation condition among multiple state values, and masking the pulse signal of the monitored circuit according to the fluctuation condition.

19. The method according to claim 18, when the fluctuation condition is a difference value and all the multiple difference values are positive, masking the pulse signal of the clock frequency of the monitored circuit, or when all the multiple difference values are negative, restoring the pulse signal of the clock frequency of the monitored circuit.

20. The method according to claim 19, when all the multiple difference values are positive and at least one of the difference values exceeds an adjustment value, masking the pulse signal of the clock frequency of the monitored circuit.

21. An integrated circuit device, comprising the device according to any one of claims 1 to 10.

22. A board card, comprising the integrated circuit device according to claim 21.

23. A computer program product, wherein when the computer program is executed by a processor, the steps of the method according to any one of claims 11 to 20 are implemented.

24. A computer device, comprising a memory, a processor, and a computer program stored on the memory, wherein the processor executes the computer program to implement the steps of the method according to any one of claims 11 to 20.

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