Descriptor scheduling method of flash memory controller, flash memory controller and storage medium

Abstract

The embodiment of the invention provides a descriptor scheduling method of a flash memory controller, the flash memory controller and a storage medium, and belongs to the technical field of memories. The method comprises the following steps: generating task scheduling codes in one-to-one correspondence with initial descriptors according to a power consumption index, a performance index and each initial descriptor; combining the task scheduling codes with the corresponding initial descriptors to obtain cache descriptors, and storing the cache descriptors in a preset descriptor queue; in the task scheduling period, traversing each cache descriptor in the descriptor queue, and comparing the task scheduling code in the traversed cache descriptor with the task scheduling code of each execution descriptor in a preset task scheduling queue; and when a comparison processing result shows that the traversed cache descriptor and the execution descriptor in the task scheduling queue can be processed in parallel, pushing the cache descriptor and the execution descriptor into the task scheduling queue. The embodiment of the invention can improve the operation efficiency of the flash memory while giving consideration to the power consumption index and the performance index of the flash memory.

Description

Technical Field

[0001] This application relates to the technical field of memory, and in particular, to a descriptor scheduling method for a flash controller, a flash controller, and a storage medium. Background Art

[0002] In the technical field of memory, after a command is sent to an operation unit in NAND, NAND will have an RB time, and no operation can be performed on the same operation unit (object) during this RB time. If waiting for the RB time blindly, a lot of time will be wasted. Therefore, in related technologies, operations on NAND are packaged into a descriptor and distributed and scheduled by a flash controller. For example, when the flash controller determines that an LUN of NAND is in the RB state, the flash controller can send a command to another LUN and periodically check whether the RB state of each LUN ends, so as to make full use of the RB time. However, in practical applications, there are problems that multiple issued commands need to be executed in a certain order or a high concurrency is adopted, resulting in poor power consumption indicators and / or performance indicators of NAND. Therefore, in related technologies, it is difficult to balance the power consumption indicators, performance indicators, and operation efficiency of descriptors of NAND. Summary of the Invention

[0003] The main purpose of the embodiments of this application is to propose a descriptor scheduling method for a flash controller, a flash controller, and a storage medium, which can improve the operation efficiency of NAND while balancing the power consumption indicators and performance indicators of NAND.

[0004] To achieve the above object, a first aspect of the embodiments of this application proposes a descriptor scheduling method for a flash controller, the method including: obtaining a plurality of initial descriptors to be processed, and power consumption indicators and performance indicators of a flash memory connected to the flash controller; generating task scheduling codes corresponding one by one to the initial descriptors according to the power consumption indicators, the performance indicators, and each of the initial descriptors; combining the task scheduling codes and the corresponding initial descriptors to obtain cache descriptors corresponding one by one to the initial descriptors and storing them in a preset descriptor queue; during a task scheduling period, traversing each cache descriptor in the descriptor queue and respectively comparing and processing the task scheduling code in the traversed cache descriptor with the task scheduling codes of each execution descriptor in a preset task scheduling queue; when the result of the comparison and processing indicates that the traversed cache descriptor and the execution descriptors in the task scheduling queue can all be processed in parallel, taking out the traversed cache descriptor from the descriptor queue and pushing it into the task scheduling queue.

[0005] To achieve the above object, a second aspect of the embodiments of the present application provides a flash memory controller, including a reading module, a caching module, a scheduling module, and a parsing module. The reading module is configured to obtain a plurality of initial descriptors to be processed, as well as the power consumption index and performance index of the flash memory connected to the flash memory controller; the caching module is configured to generate a task scheduling code corresponding to each of the initial descriptors according to the power consumption index, the performance index, and each of the initial descriptors, and combine the task scheduling code and the corresponding initial descriptor to obtain a cache descriptor corresponding to each of the initial descriptors and store it in a preset descriptor queue; the scheduling module is configured to, within a task scheduling cycle, traverse each cache descriptor in the descriptor queue and respectively compare the task scheduling code in the traversed cache descriptor with the task scheduling codes of each execution descriptor in a preset task scheduling queue; the parsing module is configured to, when the result of the comparison processing indicates that the traversed cache descriptor and the execution descriptor in the task scheduling queue can be processed in parallel, take out the traversed cache descriptor from the descriptor queue and push it into the task scheduling queue.

[0006] To achieve the above object, a third aspect of the embodiments of the present application provides a flash memory controller, the flash memory controller includes a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it implements the descriptor scheduling method of the flash memory controller described in the first aspect above.

[0007] To achieve the above object, a fourth aspect of the embodiments of the present application provides a computer-readable storage medium, the storage medium stores a computer program, and when the computer program is executed by a processor, it implements the descriptor scheduling method of the flash memory controller described in any one of the first aspect.

[0008] The descriptor scheduling method, flash memory controller, and storage medium provided by the present application generate corresponding task scheduling codes for each initial descriptor to be processed, and based on the task scheduling codes of each initial descriptor to be processed and the task scheduling codes of the execution descriptors, determine whether the initial descriptors to be processed and the execution descriptors can be processed concurrently. The concurrent judgment efficiency is higher. At the same time, by generating task scheduling codes based on the power consumption index, performance index, and each initial descriptor itself, the concurrent amount of NAND and the scheduling order of each initial descriptor can be dynamically controlled. Therefore, the embodiments of the present application can improve the operation efficiency of NAND while taking into account the power consumption index and performance index of NAND. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of the modules of the flash memory controller provided by the embodiments of the present application; Figure 2It is a partial structural schematic diagram of a terminal device to which the flash memory controller provided by an embodiment of the present application is applied; Figure 3 It is a schematic flowchart of a descriptor scheduling method for a flash memory controller provided by an embodiment of the present application; Figure 4 It is a schematic scheduling flowchart of an embodiment of the descriptor scheduling method for a flash memory controller provided by an embodiment of the present application; Figure 5a It is a schematic scheduling timing diagram without scheduling in an embodiment of the descriptor scheduling method for a flash memory controller provided by an embodiment of the present application; Figure 5b It is a schematic scheduling timing diagram for CE-level scheduling in an embodiment of the descriptor scheduling method for a flash memory controller provided by an embodiment of the present application; Figure 5c It is a schematic scheduling timing diagram for hybrid scheduling in an embodiment of the descriptor scheduling method for a flash memory controller provided by an embodiment of the present application; Figure 6 It is a schematic structural diagram of the hardware structure corresponding to the descriptor scheduling method for a flash memory controller provided by an embodiment of the present application. Detailed implementation manners

[0010] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0011] It should be noted that although functional module division is performed in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order from the module division in the device or the order in the flowchart. Terms such as "first" and "second" in the specification, claims and the above drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence.

[0012] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0013] First, several nouns involved in the present application are analyzed: RB time, that is, the busy time of the device, is the abbreviation of "Read / Busy".

[0014] PLANE, that is, the grouping layer, is composed of hundreds or even thousands of Blocks. Each PLANE has a separate cache queue for managing commands with different priorities. The design of PLANE enables the flash memory to fully utilize the advantages of parallelism and achieve a twofold performance increase.

[0015] LUN, that is, Logical Unit Number, is simply referred to as the logical unit number; A LUN is the smallest independent unit in the flash memory that can execute commands and report its own status, and can also be called a Die. A LUN can have one or more PLANEs.

[0016] CE, that is, Chip Enable, is simply referred to as the chip enable; CE is the enable signal that controls the flash memory chip. Each Target is controlled by a CE pin, and multiple LUNs on one Target share a CE signal.

[0017] In the field of memory technology, after a command is sent to an operation unit in NAND, NAND will have a RB time, and the same operation unit cannot be operated on during this RB time. If waiting for the RB time passively will waste a lot of time. Therefore, in the related art, operations on NAND are packaged into a descriptor and distributed and scheduled by a flash controller. For example, when the flash controller determines that a LUN of NAND is in the RB state, the flash controller can send a command to another LUN and periodically check whether the RB state of each LUN ends, so as to make full use of the RB time. However, in practical applications, since the commands issued within a period of time can be operations on different LUNs or operations on different PLANEs, there are multiple operations that need to be executed in a certain order or multiple operations are executed in parallel at the same time, resulting in a high concurrency, which makes the power consumption index and / or performance index of NAND poor, such as a decrease in read / write performance or an increase in power consumption. Exemplarily, for 6 operations with execution sequence requirements, they are operation 1 (read CE0 LUN0 PLANE0), operation 2 (read CE0 LUN0 PLANE 1), operation 3 (set feature, configure the warmup cycle of CE0 LUN0 to 3), operation 4 (read CE0 LUN1 PLANE 2), operation 5 (read CE0 LUN0 PLANE 2), and operation 6 (read CE0 LUN0 PLANE 3) in sequence; when operations 1 to 6 are all configured in a descriptor chain, when operation 1 is executed, operations 2 to 6 can all be executed in parallel. As a result, in actual operation, operations 1, 2, 4, 5, and 6 are executed in parallel, and finally operation 3 is executed. However, the execution of operation 3 will affect the content to be read by operations 5 and 6; therefore, if the order of concurrent processing is not restricted, the actual operation result will be different from the expectation. Similarly, if there is no scheduling at all, each operation will be executed serially, but NAND can actually support concurrent operations at the PLANE level. Therefore, this method does not fully utilize the performance of the flash memory, resulting in low operation efficiency of NAND. Similarly, in some other embodiments, even if multiple operations can be executed in parallel at the same time, when the concurrency is high, the power consumption is higher, the temperature is also higher, and the read / write speed will also decrease accordingly. Therefore, it is difficult for the prior art to schedule descriptors to take into account the power consumption index, performance index of NAND and the operation efficiency of descriptors. Based on this, the present application proposes a descriptor scheduling method, a flash controller and a storage medium for a flash controller, which can improve the operation efficiency of NAND while taking into account the power consumption index and performance index of NAND.

[0018] The descriptor scheduling method, flash controller and storage medium for a flash controller provided by the embodiments of the present application are specifically described through the following embodiments. First, the descriptor scheduling method for the flash controller in the embodiments of the present application is described.

[0019] The flash memory controller of the present application can be used in many general-purpose or special-purpose computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and so on. The initial descriptor scheduling method of the present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0020] Refer to the following Figure 1 As shown, the flash memory controller provided by an embodiment of the present application includes: A reading module 100, configured to obtain a plurality of initial descriptors to be processed, as well as power consumption metrics and performance metrics of the flash memory connected to the flash memory controller; A caching module 200, configured to generate task scheduling codes corresponding to the initial descriptors one by one according to the power consumption metrics, performance metrics, and each initial descriptor; and combine the task scheduling codes and the corresponding initial descriptors to obtain cache descriptors corresponding to the initial descriptors one by one and store them in a preset descriptor queue; A scheduling module 300, configured to, within a task scheduling period, traverse each cache descriptor in the descriptor queue and perform comparison processing on the task scheduling codes in the traversed cache descriptors and the task scheduling codes of each execution descriptor in a preset task scheduling queue respectively; An analysis module 400, configured to, when the result of the comparison processing indicates that the traversed cache descriptor and the execution descriptor in the task scheduling queue can both be processed in parallel, take out the traversed cache descriptor from the descriptor queue and push it into the task scheduling queue.

[0021] The initial descriptors to be processed are received from the processor of the terminal; each initial descriptor corresponds to a read / write operation command for one of the flash memories connected to the flash memory controller, the performance metric characterizes the read / write speed of the flash memory; the power consumption metric characterizes the power consumption of the flash memory, where, in some embodiments, the read / write speed can be obtained from the performance monitoring metrics of NAND, and the power consumption can be characterized by temperature.

[0022] The task scheduling encoding is used to record the scheduling method of the descriptors and the operation object parameters under the scheduling method (the operation object parameters such as LUN information, CE information, PLANE information, etc., to indicate which object is being operated on). The scheduling method characterizes the scheduling types supported by the flash memory (i.e., NAND in the following text). In some embodiments, the scheduling methods include three types: CE-level scheduling, hybrid scheduling, and serial scheduling.

[0023] Since the task scheduling encoding is generated based on performance metrics, power consumption metrics, and the content of each initial descriptor itself, the task scheduling encoding can take into account the execution order requirements between the initial descriptors, and can also take into account the performance and power consumption of the flash memory.

[0024] Each execution descriptor stored in the task scheduling queue is a descriptor that can be executed in parallel. The scheduling period is the period when the flash memory controller calls the available descriptors for execution. Therefore, by selecting, in each scheduling period, descriptors that can be processed in parallel with the currently executing execution descriptor, multiple descriptors can be executed in parallel, thereby making full use of the inherent performance of the NAND.

[0025] When the result of the comparison process indicates that there is an execution descriptor in the task scheduling queue that needs to be processed serially with the traversed cache descriptor, the traversal of the descriptor queue is stopped, and scheduling is performed again after the execution descriptor in the task scheduling queue has completed execution.

[0026] When the task scheduling queue is empty, the first cache descriptor taken out from the descriptor queue is directly put into the task scheduling queue.

[0027] Exemplarily, referring to Figure 2 as shown, referring to Figure 2 the terminal device shown, a descriptor reader, a flash memory controller, and a NAND are provided on the terminal device. Among them, the flash memory controller is provided with a descriptor queue, a task scheduler, a task parser, and a task scheduling queue. The processor of the terminal device converts the operation command for the NAND into an initial descriptor and stores it in the descriptor reader. The processor of the flash memory controller sequentially reads multiple initial descriptors to be processed from the descriptor reader, and generates a task scheduling encoding corresponding to each initial descriptor according to the performance, power consumption of the NAND, and the multiple initial descriptors read out. The task scheduling encoding and the corresponding initial descriptor are combined to obtain a cache descriptor and stored in the descriptor queue. The task scheduler sequentially reads the cache descriptor from the descriptor queue in each scheduler, and compares the task scheduling encoding in the cache descriptor read each time with the task scheduling encoding of the execution descriptor in the task scheduling queue, so as to determine whether to execute the currently read cache descriptor in parallel. The task parser controls the NAND to execute based on the execution descriptor in the task scheduling queue.

[0028] The following is a reference to Figure 3 As shown, according to the descriptor scheduling method of the flash memory controller provided by the embodiments of the present application, the method includes: Step S100: Obtain a plurality of initial descriptors to be processed, as well as the power consumption index and performance index of the flash memory connected to the flash memory controller; Step S200: Generate task scheduling codes corresponding one-to-one to the initial descriptors according to the power consumption index, performance index, and each initial descriptor; Step S300: Combine the task scheduling code and the corresponding initial descriptor to obtain a cache descriptor corresponding one-to-one to the initial descriptor and save it in a preset descriptor queue; Step S400: During the task scheduling period, traverse each cache descriptor in the descriptor queue and compare the task scheduling code in the traversed cache descriptor with the task scheduling codes of each execution descriptor in the preset task scheduling queue respectively; Step S500: When the result of the comparison process indicates that the traversed cache descriptor and the execution descriptor in the task scheduling queue can be processed in parallel, take out the traversed cache descriptor from the descriptor queue and push it into the task scheduling queue.

[0029] Therefore, by generating a corresponding task scheduling code for each initial descriptor to be processed, and based on the task scheduling code of each initial descriptor to be processed and the task scheduling code of the execution descriptor, it is determined whether the initial descriptor to be processed and the execution descriptor can be processed concurrently, and the concurrent judgment efficiency is higher. At the same time, by generating the task scheduling code based on the power consumption index, performance index, and each initial descriptor itself, the concurrent amount of NAND and the scheduling order of each initial descriptor can be dynamically controlled. Therefore, the embodiments of the present application can improve the operation efficiency of NAND while taking into account the power consumption index and performance index of NAND.

[0030] When the result of the comparison process indicates that the traversed cache descriptor and the execution descriptor cannot be processed in parallel, the traversal of the descriptor queue will be stopped during the current scheduling period.

[0031] It can be understood that the power consumption index and performance index can be used to determine the maximum concurrent amount allowed for the parallel processing of NAND, and the execution parameters carried in the initial descriptor limit the execution order that should be satisfied between any two initial descriptors. Therefore, the task scheduling code determined based on the power consumption index, performance index, and initial descriptor can improve the operation efficiency of NAND while taking into account the power consumption index and performance index of NAND.

[0032] In some embodiments, the task scheduling encoding consists of four parts, namely the operation level field, the CE field, the LUN field, and the PLANE field. Taking the task scheduling encoding as a 9-bit encoding as an example, where each bit of the task scheduling encoding is bit[0]~bit[8], bit[0] is the operation level field, indicating the scheduling type of the operation in NAND. For example, when bit[0]=1 and the remaining bits are not all 0 or all 1, it indicates that the scheduling method is hybrid scheduling; when bit[0]=0 and the remaining bits are not all 0 or all 1, it indicates that the operation is CE scheduling. Bit[2:1] is the CE field, indicating the CE number of the operation, that is, which CE will issue this operation. The numbering starts from 0. Bit[4:3] is the LUN field, indicating the LUN number of the operation, that is, which LUN will issue this operation. The numbering starts from 0. Bit[8:5] is the PLANE field, indicating the PLANE number of the operation, that is, which PLANE is the object of this operation. When the scheduling method is CE scheduling, this field is filled with 0. When the scheduling method is hybrid scheduling, the numbering starts from 0. When the scheduling method is serial scheduling, all bits are set to all 0 or 1. At this time, it is possible to quickly determine whether the initial descriptor is allowed to be executed in parallel by comparing the content filled in the task scheduling encoding of the initial descriptor with the content in the task scheduling code of the executed descriptor. Exemplarily, for example, four read operations are respectively operation 1 (read CE0 LUN0 PLANE 0), operation 2 (read CE0 LUN0 PLANE 1), operation 3 (read CE0 LUN0 PLANE 2), and operation 4 (read CE0 LUN0 PLANE 3). When the task scheduling encodings are respectively configured as 2B’000000000, 2B’000100000, 2B’001000000, 2B’001100000, at this time the four read operations are parallel, but the power consumption is relatively high. When the task scheduling encodings are respectively configured as 2B’000000000, 2B’000000000, 2B’000000000, 2B’000000000, then when operation 1 is executed, operations 2~4 will wait; when operation 2 is executed, operations 3~4 will wait, so that the four operations are executed serially. When the task scheduling encodings are respectively configured as 2B’000000000, 2B’000000000, 2B’001000000, 2B’001100000, the first three operations are executed serially, but when the third operation is executed, the third and fourth operations can be executed in parallel.

[0033] It can be understood that according to the power consumption index, performance index, and each initial descriptor, task scheduling encodings corresponding one-to-one to the initial descriptors are generated, including: Determine the available concurrent scheduling quantity according to the power consumption index, performance index, and the hardware parameters of the flash memory connected to the flash memory controller; Determine the first scheduling type of each initial descriptor according to the schedulable available concurrency; Extract the CE information, LUN information, and PLANE information from each initial descriptor; Generate a task scheduling code corresponding one-to-one with the initial descriptor according to the first scheduling type, the corresponding CE information, LUN information, and PLANE information.

[0034] The hardware parameters can be the model, or the maximum power consumption, the minimum read / write speed, etc. configured. Based on the power consumption index, performance index, and hardware parameters, the schedulable available concurrency that can be called can be determined. Based on the descriptor queue, the number of descriptors scheduled in parallel within the scheduled period where the cache descriptor to be generated is located (i.e., the parallel scheduling occupancy) can be determined. Therefore, based on the schedulable available concurrency and the parallel scheduling occupancy corresponding to the cache descriptor to be generated, the schedulable available concurrency can be determined. In some embodiments, a variable can be set to record the parallel scheduling occupancy, and the parallel scheduling occupancy is updated each time a cache descriptor is stored in the descriptor queue, so that the parallel scheduling occupancy can represent the number of descriptors scheduled in parallel within the scheduled period where the cache descriptor to be generated is located.

[0035] The schedulable available concurrency represents the number of descriptors that NAND can execute in parallel at the current moment.

[0036] The CE information indicates the CE number for which the descriptor operates and which CE will issue it. The LUN information indicates the LUN number for which the descriptor operates and which LUN will issue it; the PLANE information indicates the PLANE number for which the descriptor operates and indicates which PLANE is the object of the operation.

[0037] When the schedulable available concurrency is 0 (i.e., concurrent scheduling is not supported), the task scheduling code of the current cache descriptor is set to all 0s or all 1s. At this time, the first scheduling type is serial scheduling. Among them, when there is a CE-level scheduling among the cache descriptors to be executed before the current cache descriptor, each character of the task scheduling code is set to the value corresponding to the CE-level scheduling (for example, if the CE-level operation is represented by 0, it is set to all 0s). When there is only a PLANE-level operation among the cache descriptors to be executed before, each character of the task scheduling code can be set to the value corresponding to the PLANE-level operation (for example, if the PLANE-level operation is represented by 1, it is set to all 1s). After this cache descriptor is cached in the descriptor queue, the corresponding parallel scheduling occupancy is updated to the initial value and recalculated.

[0038] The embodiments of the present application do not limit how to determine the first scheduling type. For example, if the descriptor is a LUN-level operation, the first scheduling type may be CE-level scheduling or serial scheduling, where serial scheduling means that the available concurrency for scheduling is 0. If the initial descriptor is a PLANE-level operation, the first scheduling type may be any one of CE-level scheduling, serial scheduling, and hybrid scheduling. When the available concurrency for scheduling is non-0, CE-level scheduling, hybrid scheduling, or serial scheduling can be selected according to the service priority of the initial descriptor, NAND hardware resources, performance, and the execution order requirements with respect to the prior descriptor. For example, if the current initial descriptor is a set command and there is a sequence with the cache descriptors that have been determined to allow parallel execution within the same scheduling period, the first scheduling type is set to serial scheduling. When there is no sequence requirement and the current hardware resources can satisfy adding a CE-level concurrent scheduling, the first scheduling type can be set to CE-level scheduling. If the current hardware resources do not satisfy adding a CE-level concurrent scheduling, the first scheduling type can be set to hybrid scheduling. Those skilled in the art can selectively set according to the actual situation. The scheduling combination type in the task scheduling queue can be identified by setting a scheduling type identifier, making the determination of the first scheduling type simpler.

[0039] It can be understood that, according to the first scheduling type, the corresponding CE information, LUN information, and PLANE information, task scheduling codes corresponding one-to-one to the initial descriptors are generated, including: When the first scheduling type is CE-level scheduling, the operation level field of the initial scheduling code of the corresponding initial descriptor is set to the first value, and the fields corresponding to the first scheduling type, CE information, and LUN information in the initial scheduling code are filled respectively to obtain the task scheduling codes corresponding one-to-one to the initial descriptors; When the first scheduling type is hybrid scheduling, the operation level field of the initial scheduling code of the corresponding initial descriptor is set to the second value, and the fields corresponding to the corresponding first scheduling type, CE information, LUN information, and PLANE information in the initial scheduling code of the initial descriptor are filled respectively to obtain the task scheduling codes corresponding one-to-one to the initial descriptors; When the first scheduling type is serial scheduling, all bits of the initial scheduling code of the corresponding initial descriptor are set to 0 or 1.

[0040] By setting the hybrid scheduling method, LUN-level operations and PLANE-level operations can be scheduled simultaneously in the current task scheduling queue, so that the PLANE-level operations supported by NAND can be fully utilized and the equal RB time can be fully utilized.

[0041] The serial scheduling indicates that the cache descriptor needs to wait for the completion of the execution of the previous cache descriptor before it can be executed. Whether it is set to all 0s or all 1s can be determined according to the type of operation executed in the task scheduling queue. It can also be set directly, and the embodiments of the present application do not limit this.

[0042] It can be understood that according to the power consumption index, performance index, and hardware parameters of the flash memory connected to the flash memory controller, the available concurrent amount for scheduling is determined, including: According to the hardware parameters, determine the read / write performance index curve and the power consumption index curve; According to the read / write performance index and the read / write performance index curve, determine the first remaining concurrent amount; According to the power consumption index and the power consumption index curve, determine the second remaining concurrent amount; According to the first remaining concurrent amount and the second remaining concurrent amount, determine the available concurrent amount for scheduling.

[0043] It can be understood that according to the available concurrent amount for scheduling, the first scheduling type of each initial descriptor is determined, including: According to the data of each description field in each initial descriptor, determine the supported second scheduling type; According to the second scheduling type, determine the scheduling quantity corresponding to the second scheduling type one by one; Allocate the scheduling types of each initial descriptor according to the scheduling quantity and the available concurrent amount for scheduling, and determine the first scheduling type of each initial descriptor.

[0044] In some embodiments, the first remaining concurrent amount and the second remaining concurrent amount can be weighted and calculated to obtain the available concurrent amount for scheduling. At this time, by jointly judging through two dimensions, the accuracy of the available concurrent amount for scheduling can be improved.

[0045] In some embodiments, the power consumption can be determined through the temperature monitoring module. At this time, the power consumption index curve corresponds to the temperature index curve. The read / write performance index curve and the power consumption index curve can be determined through simulation data. The read / write performance index curve represents the relationship between the read / write performance and the concurrent amount, and the power consumption index curve represents the relationship between the power consumption and the concurrent amount.

[0046] It can be understood that the task scheduling code in the traversed cache descriptor is compared with the task scheduling codes of each execution descriptor in the preset task scheduling queue respectively, including: Take the first execution descriptor in the task scheduling queue as the initial descriptor to be compared; Perform an exclusive OR operation on the task scheduling code in the traversed cache descriptor and the task scheduling code of the initial descriptor to be compared to obtain the decision scheduling code; When each field of the decision scheduling code represents an operation on a different operation object, the next un-traversed execution descriptor in the task scheduling queue is used as the initial descriptor to be compared, and the process jumps to the step of performing an exclusive OR operation on the task scheduling code in the cache descriptor to be traversed and the task scheduling code of the initial descriptor to be compared; When each field of the decision scheduling code represents an operation on the same operation object, stop comparing the task scheduling code in the cache descriptor to be traversed with the task scheduling codes of each execution descriptor in the preset task scheduling queue.

[0047] Exemplarily, taking the operation object including LUN-level operation object and PLANE-level operation object as an example, referring to Figure 4 as shown, the following steps are for each initial descriptor to be compared: S1. Obtain the task scheduling code of the execution descriptor that has not participated in the comparison in the task scheduling queue; S2. Perform an exclusive OR operation on the task scheduling code of the initial descriptor to be compared and the task scheduling code of the retrieved execution descriptor, and obtain the decision scheduling code after the exclusive OR operation.

[0048] S3. Determine whether bit[0] of the task scheduling code after the exclusive OR operation is 0. If not, jump to S4; if yes, jump to S5. Among them, if bit[0] of the task scheduling code after the exclusive OR operation is 1, it indicates that the command corresponding to the initial descriptor to be compared is a command of a different level from the currently executed execution descriptor. If bit[0] of the task scheduling code after the exclusive OR operation is 0, it indicates that the command corresponding to the initial descriptor to be compared and the currently executed execution descriptor are commands of the same level.

[0049] S4. Determine whether the CE field related information, that is, bit[4:1], is 0. If bit[4:1] is 0, it indicates an operation on the same CE / LUN, then the current initial descriptor is not executed, and the comparison process of this initial descriptor to be compared exits. If bit[4:1] is not 0, it indicates an operation on different CE / LUNs, that is, different operation objects, then the current initial descriptor can be executed; and jump to S6.

[0050] S5. Determine whether the PLANE related information, that is, bit[8:1], is 0. If bit[8:1] is 0, the current initial descriptor cannot be executed, and the comparison process of this initial descriptor to be compared exits. If bit[8:1] is 1, that is, different operation objects, then the current initial descriptor can be executed, and jump to S6.

[0051] S6: Determine whether there are uncompared execution descriptors in the task scheduling queue. If so, jump to S6; otherwise, put the initial descriptor to be compared into the task scheduling queue. That is, the comparison results between the initial descriptor to be compared and each execution descriptor in the execution queue must be that they can be executed in parallel in order to execute in parallel.

[0052] After the initial descriptor to be compared is pushed into the task scheduling queue, the next initial descriptor to be compared is taken out from the descriptor queue until the initial descriptor to be compared does not meet the conditions for parallel execution or the scheduling period ends.

[0053] It can be understood that the operations of the same operation are determined through the following steps: When the value of the operation level field of the decision scheduling code is 1, determine whether it is an operation on the same operation object according to the CE field and the LUN field of the decision scheduling code; When the value of the operation level field of the decision scheduling code is 0, determine whether it is an operation on the same operation object according to the fields other than the operation level field in the decision scheduling code.

[0054] Exemplarily, taking the example that there are two cache descriptors in the descriptor queue and two execution descriptors in the task scheduling queue, where the execution descriptors in the task scheduling queue are shown in Table 1 below:

[0055] Table 1 The task number of the first initial descriptor is 0, which is a PLANE-level operation on CE0, LUN0, and PLNAE1. The task number of the second initial descriptor is 1, which is a LUN-level operation on CE0 and LUN0. The task scheduling number of the first initial descriptor is: 000000001. Assume that the task scheduling code of the second initial descriptor is 000000000. Then, referring to Figure 2 and Figure 4 as shown, the task scheduler first performs an exclusive OR operation on 000000001 and the task scheduling code of the first descriptor in the task scheduling queue (that is, 000000010), and gets 000000011. bit[0]=1, indicating that the two descriptors are operations of different levels. Then, looking at bit[4:1]= 1, it indicates that the operation objects are not the same CE\LUN, and the comparison passes; then perform an exclusive OR operation on 000000001 and the task scheduling code of the second execution descriptor in the task scheduling queue. The exclusive OR result is 000100000. bit[0]=0, indicating that the two descriptors are operations of the same level. Then compare bit[8:1]=00010000, indicating that they are different operation objects, and it also passes. Therefore, the cache descriptor corresponding to the initial descriptor 000000001 can be pushed into the task parser to start execution. At this time, the task scheduling queue is shown in Table 2 below:

[0056] Table 2 Then the task scheduler fetches the task scheduling code of the current second initial descriptor: 000000000 and compares it with the execution descriptors in the task scheduling queue respectively. First, XOR it with the first task scheduling code to get: 000000010. Since bit[0]=0, it indicates that the two initial descriptors are operations of the same level. Then compare bit[8:1]=00000001, indicating that they are different operation objects, and the comparison passes. Then XOR 000000000 with the second execution descriptor in the task scheduling queue to get: 000100001. Since bit[0]=1, it indicates that the two initial descriptors are operations of different levels. Then look at bit[4:1]=0, indicating that the operation objects are the same object, and the comparison fails. The initial descriptor corresponding to 000000000 needs to continue to wait in the descriptor queue.

[0057] Exemplarily, referring to Figures 5a to 5c , assume there are three initial descriptors, namely CE1 LUN0 PLANE0, CE0 LUN0 PLANE1, and CE0 LUN0 PLANE0.

[0058] As Figure 5a shown, when the task scheduling codes generated by the three initial descriptors are all 0 or all 1, that is, there is no scheduling, at this time, the three initial descriptors are executed serially.

[0059] As Figure 5b shown, when the task scheduling codes generated by the three initial descriptors are all CE-level scheduling, at this time, only CE1 LUN0 PLANE0 and CE0 LUN0 PLANE1 are executed in parallel, and CE0 LUN0 PLANE0 needs to wait for CE0 LUN0 PLANE1 to complete the execution.

[0060] As Figure 5c shown, when the scheduling types of CE1 LUN0 PLANE0 and CE0 LUN0 PLANE1 are CE-level scheduling and CE0 LUN0 PLANE0 is mixed scheduling, at this time, CE1 LUN0 PLANE0, CE0 LUN0 PLANE1, and CE0 LUN0 PLANE0 can be executed in parallel.

[0061] The embodiment of the present application also provides a flash memory controller. The flash memory controller includes a memory and a processor. The memory stores a computer program. When the processor executes the computer program, it implements the descriptor scheduling method of the above flash memory controller. The flash memory controller can be any intelligent terminal including a tablet computer, an in-vehicle computer, etc.

[0062] Please refer to Figure 6 , Figure 6 which schematically shows the hardware structure of a flash memory controller according to another embodiment. The flash memory controller includes: A processor 601, which can be implemented by using a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, etc., and is used to execute relevant programs to implement the technical solutions provided by the embodiments of the present application; A memory 602, which can be a NAND flash. The relevant program codes are stored in the memory 602, and the processor 601 is used to call and execute the descriptor scheduling method of the flash memory controller according to the embodiments of the present application; An input / output interface 603, which is used to implement information input and output; A communication interface 604, which is used to implement communication interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or through wireless means (such as mobile network, WIFI, Bluetooth, etc.); A bus 605, which transmits information between various components of the device (such as the processor 601, the memory 602, the input / output interface 603, and the communication interface 604); Among them, the processor 601, the memory 602, the input / output interface 603, and the communication interface 604 are communicatively connected to each other inside the device through the bus 605.

[0063] The embodiments of the present application also provide a computer-readable storage medium. The computer-readable storage medium is a computer-readable storage medium. This storage medium stores a computer program, and when the computer program is executed by a processor, it implements the above-mentioned descriptor scheduling method of the flash memory controller.

[0064] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory can include high-speed random access memory, and can also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory optionally includes a memory remotely provided relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above-mentioned network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0065] The embodiments described in the embodiments of the present application are to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art will know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0066] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than those shown in the figures, or combine certain steps, or different steps.

[0067] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0068] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and their appropriate combinations.

[0069] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0070] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (one) of the following" or its similar expressions refer to any combination of these items, including any combination of single items (ones) or plural items (ones). For example, at least one (one) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0071] In several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the above division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be in electrical, mechanical or other forms.

[0072] The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0073] In addition, each functional unit in various embodiments of this application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0074] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes multiple instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present application. The foregoing storage medium includes: various media that can store programs, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0075] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings, which do not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall fall within the scope of the rights of the embodiments of the present application.

Claims

1. A descriptor scheduling method for a flash memory controller, characterized in that: The method comprises: Acquire a plurality of initial descriptors to be processed and a power consumption index and a performance index of a flash memory connected to the flash memory controller; Generate a task scheduling code corresponding to each of the initial descriptors according to the power consumption indicator, the performance indicator and each of the initial descriptors; Combining the task scheduling code with the corresponding initial descriptor to obtain a cache descriptor corresponding to the initial descriptor one by one and saving the cache descriptor in a preset descriptor queue; In a task scheduling cycle, traverse each cache descriptor in the descriptor queue and compare the task scheduling code in the traversed cache descriptor with the task scheduling code of each execution descriptor in the preset task scheduling queue; When the comparison result indicates that the traversed cache descriptor and the execution descriptor in the task scheduling queue can be processed in parallel, the traversed cache descriptor is taken out from the descriptor queue and pushed into the task scheduling queue.

2. The descriptor scheduling method of the flash memory controller according to claim 1, characterized in that: The step of generating a task scheduling code corresponding to each of the initial descriptors according to the power consumption indicator, the performance indicator and each of the initial descriptors includes: Determine the available concurrency for scheduling according to the power consumption indicator, the performance indicator and the hardware parameters of the flash memory; Determining a first scheduling type for each of the initial descriptors according to the available concurrency for scheduling; Extracting chip enable CE information, logical unit number LUN information and packet layer PLANE information from each of the initial descriptors; A task scheduling code corresponding to the initial descriptor is generated according to the first scheduling type, the corresponding CE information, the LUN information and the PLANE information.

3. The descriptor scheduling method of the flash memory controller according to claim 2, characterized in that: The step of generating a task scheduling code corresponding to the initial descriptor in a one-to-one manner according to the first scheduling type, the corresponding CE information, the LUN information, and the PLANE information includes: When the first scheduling type is CE-level scheduling, the operation level field of the initial scheduling code of the corresponding initial descriptor is set to a first value, and the fields corresponding to the CE information and the LUN information in the initial scheduling code are filled respectively to obtain a task scheduling code corresponding to the initial descriptor one by one; When the first scheduling type is hybrid scheduling, the operation level field of the initial scheduling code of the corresponding initial descriptor is set to a second value, and the fields corresponding to the CE information, the LUN information and the PLANE information in the initial scheduling code are filled respectively to obtain a task scheduling code corresponding to the initial descriptor one by one; When the first scheduling type is serial scheduling, each bit of the initial scheduling code of the corresponding initial descriptor is set to 0 or 1.

4. The descriptor scheduling method of the flash memory controller according to claim 3, characterized in that: The determining, according to the power consumption indicator, the performance indicator, and the hardware parameter of the flash memory connected to the flash memory controller, the available concurrency for scheduling includes: Determine a read / write performance index curve and a power consumption index curve according to the hardware parameters; Determining a first remaining concurrency according to the read / write performance indicator and the read / write performance indicator curve; Determining a second remaining concurrency according to the power consumption indicator and the power consumption indicator curve; The available concurrency for scheduling is determined according to the first remaining concurrency and the second remaining concurrency.

5. The descriptor scheduling method of the flash memory controller according to claim 4, characterized in that: The determining, according to the available concurrency of the scheduling, the first scheduling type of each of the initial descriptors comprises: Determining a supported second scheduling type according to data of each description field in each of the initial descriptors; According to the second scheduling type, determining a scheduling quantity corresponding to the second scheduling type one by one; Allocate a scheduling type for each of the initial descriptors according to the scheduling quantity and the scheduling available concurrency, and determine a first scheduling type for each of the initial descriptors.

6. The descriptor scheduling method of the flash memory controller according to claim 1, characterized in that: The task scheduling code in the traversed cache descriptor is compared with the task scheduling code of each execution descriptor in the preset task scheduling queue, including: Using the first execution descriptor in the task scheduling queue as the initial descriptor to be compared; Performing XOR processing on the task scheduling code in the traversed cache descriptor and the task scheduling code of the initial descriptor to be compared to obtain a decision scheduling code; When the fields of the decision scheduling code all represent operations that are not the same operation object, the next execution descriptor in the task scheduling queue that has not been traversed is used as the initial descriptor to be compared, and the step of performing XOR processing on the task scheduling code in the traversed cache descriptor and the task scheduling code of the initial descriptor to be compared is jumped to; When the fields of the decision scheduling code represent operations on the same operation object, the comparison process of the task scheduling code in the traversed cache descriptor and the task scheduling codes of each execution descriptor in the preset task scheduling queue is stopped.

7. The descriptor scheduling method of the flash memory controller according to claim 6, characterized in that: The operation of the same operation object is determined by the following steps: When the value of the operation level field of the decision scheduling code is 1, determining whether the operations are for the same operation object according to the CE field and the LUN field of the decision scheduling code; When the value of the operation level field of the decision scheduling code is 0, it is determined whether the operations are of the same operation object according to the fields other than the operation level field in the decision scheduling code.

8. A flash memory controller, characterized in that: include: A reading module, used for acquiring a plurality of initial descriptors to be processed and a power consumption index and a performance index of a flash memory connected to the flash memory controller; A cache module, used for generating a task scheduling code corresponding to each initial descriptor according to the power consumption index, the performance index and each initial descriptor; and combining the task scheduling code and the corresponding initial descriptor to obtain a cache descriptor corresponding to the initial descriptor one by one and save the cache descriptor in a preset descriptor queue; A scheduling module, used for traversing each cache descriptor in the descriptor queue within a task scheduling cycle and comparing the task scheduling code in the traversed cache descriptor with the task scheduling code of each execution descriptor in the preset task scheduling queue; The parsing module is used to take out the traversed cache descriptor from the descriptor queue and push it into the task scheduling queue when the comparison processing result indicates that the traversed cache descriptor and the execution descriptor in the task scheduling queue can be processed in parallel.

9. A flash memory controller, characterized in that: The flash memory controller includes a memory and a processor, the memory stores a computer program, and the processor implements the descriptor scheduling method of the flash memory controller according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the descriptor scheduling method of the flash memory controller according to any one of claims 1 to 7 is implemented.

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