A method and device for processing instruction address misalignment exception

Abstract

The present invention discloses a method and device for processing an instruction fetch address misalignment exception. The method of the present invention splits an unconditional jump instruction into a first operation of calculating a link address and writing the result into a destination register, and a second operation of calculating a branch target address and completing the jump, and executes them in an integer calculation unit and a branch unit respectively. The conditional branch instruction only includes the first operation of calculating a branch target address and determining whether to jump, which is executed in the branch unit. The branch unit only implements one calculation module and does not set a result write bus. A completion field and a misalignment field are set in the ROB, and these two fields are updated when the operation is dispatched and executed. After the operation is executed, the first operation checks the misalignment field of its corresponding item in the ROB to determine whether to report an instruction fetch address misalignment exception. The present invention aims to provide a method for processing an instruction fetch address misalignment exception with low area overhead for an out-of-order superscalar processor of the RISC‑V architecture.

Description

Technical Field

[0001] The present invention relates to an out-of-order superscalar processor design technology in the field of processor design, and in particular to a method and device for processing an instruction fetch address misalignment exception. Background Art

[0002] In the open instruction set architecture (RISC-V), instructions come in two lengths: 32 bits and 16 bits. If the processor doesn't implement compressed instruction extensions (C extensions), the instruction length is fixed at 32 bits, occupying 4 bytes. The instruction fetch address must be 4-byte aligned. If not, an instruction fetch address misalignment exception will be generated. The RISC-V architecture stipulates that the instruction fetch address misalignment exception is reported at the instruction that causes the instruction fetch address misalignment, and the instruction that causes the instruction fetch address misalignment cannot modify the processor's architectural state.

[0003] Control transfer instructions in the RISC-V instruction set are divided into two categories: unconditional jumps and conditional branches. Both can cause misalignment of the instruction fetch address. Unconditional jump instructions act as a jump link, saving the link address (i.e., the address of the instruction following the unconditional jump instruction) in the destination register and then modifying the instruction fetch address to the target address. Therefore, unconditional jump instructions require calculation of both the link address and the target address. Conditional branch instructions compare the values ​​of two source registers to see if they meet a certain condition, such as equality. If so, the instruction fetch address is modified to the target address; otherwise, instructions are fetched sequentially. Conditional branch instructions only require calculation of the target address and do not have a destination register.

[0004] When designing RISC-V architecture processors, existing techniques typically implement a branch unit to execute control transfer instructions. When executing an unconditional jump instruction, the instruction is sent to the branch unit as an operation, which simultaneously performs both link address updates and branch jumps. If the target address is misaligned, the instruction neither uses the link address to update the destination register nor jumps. This approach requires the branch unit to implement two computation modules: one to calculate the link address and one to calculate the branch target address. A write bus for the result is also required to write back the link address, which adds an additional write port to the integer register file and an additional bypass source to the integer data bypass network, both of which increase processor area overhead. Of the control transfer instructions executed by the branch unit, only unconditional jump instructions have a link function; conditional branch instructions do not require link address calculation and write to the destination register. Therefore, the computation module and result write bus added to the branch unit are not used by the conditional branch. Existing branch unit designs are not conducive to processor area optimization. Summary of the Invention

[0005] The technical problem to be solved by the present invention is as follows: In view of the above-mentioned problems in the prior art, a method and device for processing instruction fetch address misalignment exceptions are provided. The present invention aims to provide a method for processing instruction fetch address misalignment exceptions with low area overhead for out-of-order superscalar processors of RISC-V architecture.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A method for handling an instruction fetch address misalignment exception includes the following steps:

[0008] 1) Take out the control transfer instruction;

[0009] 2) If the control transfer instruction is an unconditional jump instruction, the unconditional jump instruction is split into a first operation of calculating the link address and writing the result to the destination register, and a second operation of calculating the branch target address and completing the jump; if the control transfer instruction is a conditional branch instruction, the conditional branch instruction is regarded as the first operation;

[0010] 3) Decode and rename the operations of control transfer instructions;

[0011] 4) Dispatching the operations of the control transfer instruction to the functional units and allocating entries in the re-order buffer: If the control transfer instruction is an unconditional jump instruction, the first operation is dispatched to the integer calculation unit, the second operation is dispatched to the branch unit, and two consecutive entries are allocated in the re-order buffer for the first operation and the second operation, each entry is set with an unaligned field and a completed field, wherein the unaligned field is used to record whether the instruction fetch address is unaligned, and the completed field is used to record whether the operation is completed; If the control transfer instruction is a conditional branch instruction, the conditional branch instruction is dispatched to the branch unit, and an entry is allocated in the re-order buffer for the first operation, which also sets an unaligned field for recording whether the instruction fetch address is unaligned and a completed field for recording whether the operation is completed; When the operation of the control transfer instruction is executed, its allocated entry in the re-order buffer is updated; Finally, after the operation is executed, the first operation checks the value of its unaligned field in the re-order buffer to decide whether to report an instruction fetch address unaligned exception.

[0012] Optionally, the value of the unaligned field is 1 or 0, 1 indicates that the instruction fetch address is unaligned, 0 indicates that the instruction fetch address is aligned, and the initial value when it is assigned is 0; the value of the completed field is 1 or 0, 1 indicates that the operation has been completed, 0 indicates that the operation has not been completed, and the initial value when it is assigned is 0.

[0013] Optionally, updating the item allocated in the re-order buffer when the operation of the control transfer instruction is executed includes: when the control transfer instruction is an unconditional jump instruction, calculating the link address when the first operation of the unconditional jump instruction executed by the integer calculation unit is executed, and writing the result into the intermediate result register, and not immediately updating the architecture state after the first operation is executed. After the first operation is executed, the completion field in the item allocated in the re-order buffer is set to 1, indicating that the operation has been completed, and the misalignment field remains unchanged.

[0014] Optionally, updating the item allocated to the control transfer instruction in the re-order buffer when the operation is executed includes: when the control transfer instruction is an unconditional jump instruction, calculating the target address when the second operation of the unconditional jump instruction executed by the branch component is executed, determining whether the target address is 4-byte aligned, and updating the information of the corresponding item of the second operation and its previous item in the re-order buffer according to the result of whether the target address is 4-byte aligned: setting the completion field of the corresponding item of the second operation in the re-order buffer to 1, indicating that the operation is completed, and updating the unaligned field of the previous item of the second operation in the re-order buffer: if the target address is not 4-byte aligned, then setting the unaligned field to 1, otherwise setting it to 0, and keeping the unaligned field of the corresponding item of the second operation in the re-order buffer unchanged.

[0015] Optionally, updating the item allocated in the re-order buffer when the operation of the control transfer instruction is executed includes: when the control transfer instruction is a conditional branch instruction, calculating the target address when the first operation of the conditional branch instruction executed by the branch component is executed, and judging whether the subsequent instruction fetch address is 4-byte aligned in combination with the jump direction; if it is not 4-byte aligned, setting the unaligned field of the corresponding item in the re-order buffer to 1, otherwise setting it to 0; and at the same time, setting the completed field of the corresponding item in the re-order buffer to 1, indicating that the operation has been completed.

[0016] Optionally, the first operation checks the value of the misaligned field in the reorder buffer to determine whether to report an instruction fetch address misalignment exception, including: the first operation checks the value of the misaligned field of the corresponding item in the reorder buffer to determine whether to report an instruction fetch address misalignment exception; if the value of the misaligned field is 1, indicating that the control transfer instruction causes the instruction fetch address misalignment, then the instruction fetch address misalignment exception is reported at the operation, and all subsequent operations starting from the operation will not be submitted, thereby ensuring that the control transfer instruction that causes the instruction fetch address misalignment exception will not modify the architecture state; if the value of the misaligned field is 0, then the operations corresponding to the control transfer instruction can be submitted normally, if the control transfer instruction is a conditional branch instruction, the instructions are fetched sequentially or jumped to the target address, if the control transfer instruction is an unconditional jump instruction, the value of the destination register is updated and the jump to the target address is made.

[0017] Optionally, the control transfer instruction refers to a control transfer instruction in the RISC-V instruction set.

[0018] In addition, the present invention also provides an electronic device, comprising a processor and a memory connected to each other, wherein the processor is programmed or configured to execute the method for processing an instruction fetch address misalignment exception.

[0019] In addition, the present invention also provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the method for processing the instruction fetch address misalignment exception through a processor.

[0020] In addition, the present invention also provides a computer program product, including a computer program or instruction, wherein the computer program or instruction is programmed or configured to execute the method for handling instruction fetch address misalignment exception through a processor.

[0021] Compared with the prior art, the present invention primarily achieves the following beneficial effects: The present invention splits an unconditional jump instruction into a first operation, calculating a link address and writing the result to a destination register, and a second operation, calculating a branch target address and completing the jump. The first operation is executed in the integer calculation unit, while the second operation is executed in the branch unit. A conditional branch instruction only includes the first operation, which calculates the branch target address and determines whether to jump, and is executed in the branch unit. A completion field, used to record whether the operation is complete, and an unaligned field, used to record whether the instruction fetch address is misaligned, are provided in the reorder buffer. These two fields are updated when the operation is dispatched and executed. After the operation is completed, the first operation checks the unaligned field of its corresponding entry in the reorder buffer to determine whether to report an instruction fetch address misalignment exception. The calculation of the link address and writing the result to the destination register for the unconditional jump instruction is performed by the integer calculation unit, eliminating the need for additional calculation and writeback logic. The branch unit only needs to implement a single calculation module and does not require a result write bus, thus reducing area overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the basic process of the method of the embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0024] like Figure 1 As shown, the method for handling the instruction fetch address misalignment exception in this embodiment includes the following steps:

[0025] 1) Take out the control transfer instruction;

[0026] 2) If the control transfer instruction is an unconditional jump instruction, the unconditional jump instruction is split into a first operation of calculating the link address and writing the result to the destination register, and a second operation of calculating the branch target address and completing the jump; if the control transfer instruction is a conditional branch instruction, the conditional branch instruction is regarded as the first operation;

[0027] 3) Decode and rename the operations of control transfer instructions;

[0028] 4) Dispatching the operations of the control transfer instruction to the functional units and allocating entries in the reorder buffer (ROB, a structure used to implement sequential instruction submission in out-of-order superscalar processors): If the control transfer instruction is an unconditional jump instruction, the first operation is dispatched to the integer calculation unit and the second operation is dispatched to the branch unit. Two consecutive entries are allocated in the reorder buffer for the first and second operations, each with an unaligned field and a completed field. The unaligned field is used to record whether the instruction fetch address is unaligned, and the completed field is used to record whether the operation is completed. If the control transfer instruction is a conditional branch instruction, the conditional branch instruction is dispatched to the branch unit, and an entry is allocated in the reorder buffer for the first operation. The entry also has an unaligned field to record whether the instruction fetch address is unaligned and a completed field to record whether the operation is completed. The entry allocated to the control transfer instruction in the reorder buffer is updated when the operation is executed. Finally, after the operation is completed, the first operation checks the value of its unaligned field in the reorder buffer to determine whether to report an instruction fetch address unaligned exception.

[0029] To handle instruction address misalignment exceptions, two types of fields are set in the reorder buffer in this embodiment: one field indicates whether the operation has been completed, which is named the completion field; the other field indicates whether the instruction address is misaligned during the operation, which is named the misalignment field. In this embodiment, the misalignment field has a value of 1 or 0, with 1 indicating that the instruction address is misaligned and 0 indicating that the instruction address is aligned, and the initial value when it is assigned is 0; the completion field has a value of 1 or 0, with 1 indicating that the operation has been completed and 0 indicating that the operation has not been completed and the initial value when it is assigned is 0. When the operation of a control transfer instruction is dispatched into the reorder buffer, the completion field and misalignment field of the corresponding item are both set to 0. Other fields are also set in the reorder buffer, but they are not related to the present invention and are not described here.

[0030] The execution unit executes the operation of the control transfer instruction and updates the completion field and the misalignment field of the corresponding entry in the reorder buffer according to the execution status. When the operation of the control transfer instruction is executed, the entry allocated in the reorder buffer is updated including:

[0031] When the control transfer instruction is an unconditional jump instruction, the link address is calculated when the first operation of the unconditional jump instruction executed by the integer calculation unit is executed, and the result is written to the intermediate result register. Because it is not yet certain whether the unconditional jump instruction corresponding to the operation will cause an instruction fetch address misalignment exception, the architecture status is not updated immediately after the first operation is executed. After the first operation is executed, the completion field in the item allocated to it in the reorder buffer is set to 1, indicating that the operation has been completed, and the misalignment field remains unchanged.

[0032] When the control transfer instruction is an unconditional jump instruction, the target address is calculated when the second operation of the unconditional jump instruction executed by the branch component is executed to determine whether the target address is 4-byte aligned. Since the unconditional jump instruction will always jump, the determination of whether the target address is 4-byte aligned is performed directly. Then, based on the result of whether the target address is 4-byte aligned, the information of the entry corresponding to the second operation and its previous entry in the reorder buffer is updated: the completion field of the entry corresponding to the second operation in the reorder buffer is set to 1, indicating that the operation is completed, and the misalignment field of the previous entry in the reorder buffer of the second operation is updated: if the target address is not 4-byte aligned, the misalignment field is set to 1, otherwise it is set to 0, and the misalignment field of the entry corresponding to the second operation in the reorder buffer remains unchanged. Even if the target address is not 4-byte aligned, the misalignment field of the entry corresponding to the second operation in the reorder buffer does not need to be updated; in fact, the misalignment field is not used.

[0033] When the control transfer instruction is a conditional branch instruction, the target address is calculated when the first operation of the conditional branch instruction executed by the branch component is executed, and combined with the jump direction, it is determined whether the subsequent instruction fetch address is 4-byte aligned. If it is not 4-byte aligned, the unaligned field of the corresponding item in the reorder buffer is set to 1, otherwise it is set to 0. At the same time, the completion field of the corresponding item in the reorder buffer of the operation is set to 1, indicating that the operation has been completed.

[0034] After all operations corresponding to the control transfer instruction are executed, its first operation checks the value of the misaligned field of the corresponding item in the reorder buffer to determine whether to report an instruction fetch address misalignment exception. Specifically, in this embodiment, the first operation checks the value of the misaligned field in the reorder buffer to determine whether to report an instruction fetch address misalignment exception, including: the first operation checks the value of the misaligned field of the corresponding item in the reorder buffer to determine whether to report an instruction fetch address misalignment exception. If the value of the misaligned field is 1, indicating that the control transfer instruction caused the instruction fetch address misalignment, then the instruction fetch address misalignment exception is reported at this operation, and all subsequent operations starting from this operation will not be submitted, thereby ensuring that the control transfer instruction that caused the instruction fetch address misalignment exception does not modify the architecture state; if the value of the misaligned field is 0, then the operations corresponding to the control transfer instruction can all be submitted normally. If the control transfer instruction is a conditional branch instruction, the instructions are sequentially fetched or jumped to the target address. If the control transfer instruction is an unconditional jump instruction, the value of the destination register is updated and the jump to the target address is performed.

[0035] The method of this embodiment is applicable to various types of out-of-order superscalar processors. As an optional implementation method, this embodiment targets a RISC-V processor, and the control transfer instruction refers to the control transfer instruction in the RISC-V instruction set.

[0036] In summary, the method for handling an instruction fetch address misalignment exception in this embodiment splits an unconditional jump instruction into a first operation, which calculates the link address and writes the result to the destination register, and a second operation, which calculates the branch target address and completes the jump. The first operation is performed in the integer calculation unit, without additional calculation and write-back logic, and the second operation is performed in the branch unit. A conditional branch instruction only includes the first operation, which calculates the branch target address and determines whether to jump. This operation is performed in the branch unit, which implements only one calculation module and does not have a result write bus. A completion field is provided in the reorder buffer to record whether the operation is completed, and an alignment field is provided to indicate whether the instruction fetch address is misaligned. These two fields are updated when the operation is dispatched and executed. After the operation is executed, the first operation checks the alignment field of its corresponding entry in the reorder buffer to determine whether to report an instruction fetch address misalignment exception. Because the calculation of the link address and writing the result to the destination register for the unconditional jump instruction is performed by the integer calculation unit, no additional calculation and write-back logic is required. The branch unit only needs to implement one calculation module and does not need a result write bus. Therefore, the method in this embodiment can reduce processor area overhead.

[0037] In addition, this embodiment further provides an electronic device, including a processor and a memory connected to each other, wherein the processor is programmed or configured to execute the method for handling instruction fetch address misalignment exception.

[0038] In addition, this embodiment further provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the method for handling instruction fetch address misalignment exception through a processor.

[0039] In addition, this embodiment also provides a computer program product, including a computer program or instructions, which is programmed or configured to execute the method for handling instruction fetch address misalignment exception through a processor.

[0040] Those skilled in the art should understand that the technical solution provided by the present invention may be in the form of a method, a system, or a computer program product. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions described in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including the instruction device, which implements the function specified in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0041] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for handling an instruction fetch address misalignment exception, characterized in that: The steps include: 1) Take out the control transfer instruction; 2) If the control transfer instruction is an unconditional jump instruction, the unconditional jump instruction is split into a first operation of calculating a link address and writing the result to a destination register, and a second operation of calculating a branch target address and completing the jump; if the control transfer instruction is a conditional branch instruction, the conditional branch instruction is considered the third operation; the link address is the address of the instruction following the unconditional jump instruction; 3) Decode and rename the operations of control transfer instructions; 4) Dispatching the operations of the control transfer instruction to the functional units and allocating entries in the reorder buffer: If the control transfer instruction is an unconditional jump instruction, dispatching the first operation to the integer calculation unit and the second operation to the branch unit, and allocating two consecutive entries in the reorder buffer for the first operation and the second operation, each entry having an unaligned field and a completed field, wherein the unaligned field is used to record whether the instruction fetch address is unaligned, and the completed field is used to record whether the operation is completed; If the control transfer instruction is a conditional branch instruction, dispatching the conditional branch instruction to the branch unit, and allocating an entry in the reorder buffer for the third operation, the entry also having an unaligned field for recording whether the instruction fetch address is unaligned and a completed field for recording whether the operation is completed; When the operation of the control transfer instruction is executed, updating its allocated entry in the reorder buffer; Finally, after the operation is executed, the first operation or the third operation checks the value of its unaligned field in the reorder buffer to determine whether to report an instruction fetch address unaligned exception; The updating of the entry allocated to the control transfer instruction in the reorder buffer when the operation of the control transfer instruction is executed includes: when the control transfer instruction is an unconditional jump instruction, calculating a target address when a second operation of the unconditional jump instruction executed by the branch component is executed, determining whether the target address is 4-byte aligned, and updating information of the entry corresponding to the second operation and its previous entry in the reorder buffer based on the result of whether the target address is 4-byte aligned: setting a completion field of the entry corresponding to the second operation in the reorder buffer to 1 to indicate that the second operation is completed, and updating an unaligned field of the previous entry in the reorder buffer of the second operation: if the target address is not 4-byte aligned, setting the unaligned field of the previous entry in the reorder buffer of the second operation to 1, otherwise setting it to 0, and keeping the unaligned field of the entry corresponding to the second operation in the reorder buffer unchanged.

2. The method for handling instruction fetch address misalignment exception according to claim 1, wherein: The value of the unaligned field is 1 or 0, 1 indicates that the instruction address is not aligned, 0 indicates that the instruction address is aligned, and the initial value when it is assigned is 0; the value of the completed field is 1 or 0, 1 indicates that the operation has been completed, 0 indicates that the operation has not been completed, and the initial value when it is assigned is 0.

3. The method for handling instruction fetch address misalignment exception according to claim 1, wherein: The updating of the entry allocated in the re-order buffer when the operation of the control transfer instruction is executed includes: when the control transfer instruction is an unconditional jump instruction, calculating a link address when a first operation of the unconditional jump instruction executed by the integer calculation unit is executed, and writing the result to a destination register; after the first operation is completed, the architecture state is not updated immediately; after the first operation is completed, the completion field of the entry allocated in the re-order buffer is set to 1 to indicate that the first operation has been completed, and the misalignment field remains unchanged.

4. The method for handling instruction fetch address misalignment exception according to claim 1, wherein: The updating of the entry allocated to the control transfer instruction in the reorder buffer when the operation of the control transfer instruction is executed includes: when the control transfer instruction is a conditional branch instruction, calculating a target address when the third operation executed by the branch component is executed, and determining whether a subsequent instruction fetch address is 4-byte aligned in combination with the jump direction; if not, setting an unaligned field of the corresponding entry in the reorder buffer to 1, otherwise setting it to 0; and simultaneously setting a completed field of the corresponding entry in the reorder buffer for the third operation to 1, indicating that the third operation has been completed.

5. The method for handling instruction fetch address misalignment exception according to claim 1, wherein: The first operation or the third operation checks the value of the misaligned field in the reorder buffer to determine whether to report an instruction fetch address misalignment exception, including: if the value of the misaligned field is 1, indicating that the control transfer instruction causes the instruction fetch address to be misaligned, then the instruction fetch address misalignment exception is reported at the operation corresponding to the misaligned field, and all subsequent operations starting from the operation corresponding to the unaligned field will not be submitted, thereby ensuring that the control transfer instruction that causes the instruction fetch address misalignment exception will not modify the architecture state; if the value of the misaligned field is 0, then the operations corresponding to the control transfer instruction can be submitted normally, if the control transfer instruction is a conditional branch instruction, the instructions are fetched sequentially or jumped to the target address, if the control transfer instruction is an unconditional jump instruction, the value of the destination register is updated and the jump to the target address is made.

6. The method for handling instruction fetch address misalignment exception according to claim 1, wherein: The control transfer instruction refers to the control transfer instruction in the RISC-V instruction set.

7. An electronic device comprising a processor and a memory connected to each other, characterized in that: The processor is programmed or configured to execute the method for handling instruction fetch address misalignment exception according to any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute, through a processor, the method for handling instruction fetch address misalignment exceptions as recited in any one of claims 1 to 6.

9. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute, through a processor, the method for handling instruction fetch address misalignment exceptions as recited in any one of claims 1 to 6.

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