Chip test platform and system based on FPGA

Abstract

The invention relates to an FPGA (Field Programmable Gate Array)-based chip test platform and system, and the test platform is characterized in that the test platform comprises a first instruction execution module which is configured to decode a first instruction from an upper computer; and the second instruction execution module is configured to read and analyze a second instruction, and the type of the second instruction corresponds to different operations in the chip testing process. According to the chip testing platform based on the FPGA, the second instruction can be cached in the FPGA in advance, part of operation originally carried out in an upper computer is transferred to the FPGA to be carried out, the clock frequency of the FPGA is high, unnecessary structures such as bus transmission do not exist, and therefore time delay in the testing process is reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and particularly to a chip test platform and system based on FPGA. Background Art

[0002] Under the background of the rapid development of contemporary electronic technology, the demand for hardware testing has shown an unprecedented growth trend. With the continuous progress of technology, the complexity and integration of integrated circuits have increased sharply, which has put forward more stringent requirements for testing technology.

[0003] Programmable hardware architectures, such as FPGA, have brought unprecedented flexibility and customization capabilities to the testing field. It can dynamically adjust the test plan according to the requirements of specific devices and functional modules, thus significantly improving the test coverage and efficiency.

[0004] In the existing platforms for testing chips using FPGA, operations such as data parsing and instruction conversion are usually completed in the host computer. There are some bus transmission structures in the host computer that are not required for testing chips, and the clock cycle of the host computer is relatively long, which results in a large amount of delay during the testing process. When testing some chips with relatively high speeds, the chip sends data at a faster speed, while the host computer reads data at a slower speed, and the host computer may miss some important information sent by the chip, so it cannot accurately determine whether the chip under test is working properly. Summary of the Invention

[0005] In view of the technical problems existing in the prior art, this application proposes a chip test platform based on FPGA, which is characterized by including: a first instruction execution module configured to decode a first instruction from a host computer, where the type of the first instruction at least includes a storage instruction and an execution instruction. When the first instruction is a storage instruction, the content of the first instruction includes a second instruction and the corresponding address for storing it, and the first instruction execution module is configured to perform a storage operation on the second instruction based on the address; and a second instruction execution module coupled to the first instruction execution module. When the type of the first instruction is an execution instruction, the first instruction execution module is configured to send a control signal to the second instruction execution module, and the second instruction execution module is configured to read and parse the second instruction, where the type of the second instruction corresponds to different operations in the chip test process.

[0006] Particularly, the test platform proposed in this application is characterized by including a storage module configured to provide a storage space for the second instruction.

[0007] Specifically, for the test platform proposed in this application, it is characterized in that the second instruction execution module is configured to send data to the chip under test; the type of the second instruction includes a data sending instruction, and its content includes an instruction type flag; the content of the data to be sent and the data length.

[0008] Specifically, for the test platform proposed in this application, it is characterized in that the second instruction execution module is configured to read data from the chip under test; the type of the second instruction includes a data reading instruction, and its content includes an instruction type flag; the length of the data to be read.

[0009] Specifically, for the test platform proposed in this application, it is characterized in that when the second instruction execution module is also configured to test abnormal situations, while reading data from the chip under test, it sends specific data to the chip under test; in this case, the content of the second instruction also includes the data sent to the chip under test.

[0010] Specifically, for the test platform proposed in this application, it is characterized in that the second instruction execution module includes a counting module; the type of the second instruction includes a jump instruction, and its content includes an instruction type flag; a jump address; and the number of loops; when the second instruction execution module reads a jump instruction, it is configured to obtain the second instruction at the corresponding position according to the jump address and execute it, and the count value of the counting module is incremented by one until the count value of the counting module meets the number of loops in the jump instruction.

[0011] Specifically, for the test platform proposed in this application, it is characterized in that the second instruction execution module includes a timing module; the type of the second instruction includes a delay instruction, and its content includes an instruction type flag; a delay time; when the second instruction execution module reads a delay instruction, the timing module starts timing and waits until the time specified in the delay instruction is reached before reading the next second instruction.

[0012] Specifically, for the test platform proposed in this application, it is characterized in that the first instruction execution module includes a first state machine, which is configured to set the first instruction execution module in the corresponding state according to the type of the first instruction.

[0013] Specifically, for the test platform proposed in this application, it is characterized in that the second instruction execution module includes a second state machine, which is configured to set the second instruction execution module in the corresponding state according to the type of the second instruction.

[0014] Specifically, the test platform proposed in this application is characterized in that the first instruction includes a synchronization byte to represent the new first instruction. When the first instruction execution module receives the synchronization byte, the first instruction execution module and the second instruction execution module stop executing the current operations and start executing the new first instruction.

[0015] Specifically, the test platform proposed in this application further includes an interface protocol driver module, coupled to the second instruction execution module and the chip under test, configured to be controlled by the second instruction execution module, receive data from the second instruction execution module, send it to the chip under test; and read data from the chip under test and send it to the second instruction execution module.

[0016] Specifically, the test platform proposed in this application further includes a read-back cache module, coupled to the second instruction execution module, configured to cache the data read back from the chip under test in sequence.

[0017] Specifically, this application also proposes a chip test system, which is characterized by including a host computer and the above-mentioned chip test platform.

[0018] The FPGA-based chip test platform and system proposed in this application can realize pre-caching the second instruction in the FPGA and transferring some operations originally performed in the host computer to the FPGA for execution. The clock frequency of the FPGA is relatively fast, and there is no unnecessary structure such as bus transmission, so the delay in the test process is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Next, the preferred embodiments of this application will be further described in detail with reference to the drawings, where: Figure 1 is a schematic diagram of the modules of a chip test system according to an embodiment of this application; Figure 2 is a schematic diagram of the structure of the first instruction after communication coding according to an embodiment of this application; Figure 3 is a flowchart of the test platform processing the first instruction according to an embodiment of this application; Figure 4 is a schematic diagram of the states and jump methods of the first state machine according to an embodiment of this application; Figure 5 is a schematic diagram of the states and jump methods of the second state machine according to an embodiment of this application; Figure 6 is a schematic diagram of the operation steps executed by the second instruction execution module during the chip test process according to an embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Apparently, the described embodiments are some, but not all, of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts shall fall within the scope of protection of this application.

[0021] In the following detailed description, reference may be made to the various specification drawings that form a part of this application and illustrate specific embodiments of the application. In the drawings, like reference numerals generally describe substantially similar components in different figures. The various specific embodiments of this application have been described in sufficient detail below to enable those of ordinary skill in the relevant art to implement the technical solutions of this application. It should be understood that other embodiments may also be utilized or structural, logical, or electrical changes may be made to the embodiments of this application.

[0022] For technologies, methods, and devices known to those of ordinary skill in the relevant art, detailed discussion may not be provided, but where appropriate, the technologies, methods, and devices should be regarded as part of the specification. Regarding the connections between the units in the drawings, they are merely for ease of illustration and indicate that at least the units at both ends of the connection communicate with each other, and are not intended to limit that the units not connected cannot communicate. Additionally, the number of lines between two units is intended to represent at least the number of signals involved in the communication between the two units or at least the number of output terminals they have, and is not used to limit that the two units can only communicate with the signals shown in the figure.

[0023] Figure 1 is a schematic diagram of the modules of a chip testing system according to an embodiment of this application.

[0024] According to one embodiment, the chip testing system may include a host computer 10 and a testing platform 11, and a user directly tests a chip under test 12 using the testing platform 11. According to one embodiment, the host computer 10 may send a first instruction to the testing platform, and the testing platform 11 may perform operations on its interior according to the first instruction.

[0025] According to one embodiment, the host computer 10 may include a test process storage module 101 for storing all detailed process step-related information for testing the chip under test.

[0026] According to one embodiment, the host computer 10 may further include a chip register-related information storage module 102 for storing detailed information such as the length, address, and function of the chip register.

[0027] According to one embodiment, the host computer 10 may further include an instruction encoding module 103. The instruction encoding module 103 may generate a first instruction recognizable by the test platform 11 or perform first instruction encoding according to the information stored in the test process storage module 101 and the chip register related information storage module 102.

[0028] According to one embodiment, the host computer 10 may further include a communication module 104 to perform communication encoding on the first instruction generated by the instruction encoding module 103. According to one embodiment, the communication encoding may include the insertion of a synchronization byte and the insertion of an escape byte.

[0029] According to one embodiment, the communication module 104 may communicate with the test platform 11 in a serial manner. Since the serial manner is adopted, data transmission between the host computer 10 and the test platform 11 can be completed only through a serial port bus, simplifying the circuit connection of the test system.

[0030] Figure 2 It is a schematic diagram of the structure of the first instruction after communication encoding according to an embodiment of the present application.

[0031] According to one embodiment, the first instruction may include at least two types, namely a write instruction and an execution instruction. Of course, according to the needs of the user and the type of the chip under test, more types of the first instruction may be included.

[0032] According to one embodiment, the first instruction may include a write control word or an execution control word to distinguish whether the instruction type is a write instruction or an execution instruction.

[0033] According to one embodiment, when the first instruction is a write instruction, it may include the content of the second instruction. According to one embodiment, the test platform 11 may perform a detection operation on the chip under test according to the second instruction.

[0034] According to one embodiment, when the first instruction is a write instruction, its content may include the second instruction storage address information, such as the high address of the second instruction storage and the low address of the second instruction storage.

[0035] According to one embodiment, the content of the first instruction may further include a synchronization byte and an escape byte, which are two specific bytes defined in the communication encoding process. The synchronization byte is the start flag of a new first instruction. In the communication encoding process, the content of the synchronization byte and the escape byte is defined first. Then, an escape byte is inserted before each byte whose content is the same as the synchronization byte or the escape byte. Finally, a synchronization byte is added before each first instruction. The position of the escape byte is not fixed and changes according to the situation. Only one of the situations is shown in this embodiment.

[0036] According to one embodiment, the test platform 11 may include a receiving module 111, coupled to the host computer 10. The receiving module 111 receives a first instruction in the form of a serial signal from the host computer 10 and may convert it into a parallel signal. Using the parallel signal can improve the data processing efficiency of the test platform 11.

[0037] According to one embodiment, the test platform 11 may further include a first instruction execution module 112, coupled to the receiving module 111. The first instruction execution module 112 receives the parallel signal from the receiving module 111.

[0038] According to one embodiment, the first instruction execution module 112 may include a first state machine 1121. According to one embodiment, the first state machine 1121 may involve 7 states and jump in a certain manner. In different states, the first state machine 1121 can identify the first instruction, synchronize communication frames, perform byte escape, and decode the first instruction.

[0039] According to one embodiment, the test platform 11 may further include a storage module 113, coupled to the first instruction execution module 112. The storage module 113 is configured to store a second instruction.

[0040] In the existing platforms using FPGA to test chips, operations such as data parsing and instruction conversion are usually completed in the host computer. The communication delay between the host computer and the FPGA is long and not fixed, which will cause a large amount of delay during the test. The storage module 113 can store the second instruction, so as to realize caching the second instruction in the FPGA in advance and transferring some operations originally performed in the host computer to the FPGA for execution. The clock frequency of the FPGA is fast, and there is no unnecessary structure such as bus transmission, so the delay during the test is reduced.

[0041] According to one embodiment, the test platform 11 may further include a second instruction execution module 114, coupled to the first instruction execution module 112, the storage module 113, and the chip under test 12. The second instruction execution module 114 can read the second instruction from the storage module 113 and perform operations related to chip testing such as sending data and reading data.

[0042] According to one embodiment, the second instruction execution module 114 may include a second state machine 1141 and a timing module 1142. According to one embodiment, the second state machine 1141 may involve 8 states and jump in a certain manner. According to one embodiment, in a specific state, the timing module 1142 can cooperate with the second state machine 1141 to achieve state jump.

[0043] According to one embodiment, the second instruction execution module 114 may further include a data sending control module 1143, configured to send data to the chip under test 12.

[0044] According to one embodiment, the second instruction execution module 114 may further include a data reading control module 1144, configured to read data from the chip under test 12.

[0045] According to one embodiment, the second instruction execution module 114 may further include a counting module 1145. During the chip testing process, some types of instructions need to be repeatedly executed a certain number of times. The counting module 1145 may be configured to count the number of repeated executions.

[0046] According to one embodiment, the test platform 11 may further include an interface protocol driver module 115, coupled between the second instruction execution module 114 and the chip under test 12. According to one embodiment, the interface protocol driver module 115 may be controlled by the second instruction execution module 114, receive signals from the second instruction execution module 114 and send them to the chip under test 12, or receive signals from the chip under test 12 and send them to the second instruction execution module 114. According to one embodiment, the operating clock frequency of the test platform 11 is relatively high, while the operating clock frequency of the chip under test 12 is relatively low. The interface protocol driver module 115 can perform frequency division processing so that the operating clock frequency of the test platform 11 meets the required range of the chip under test 12.

[0047] According to one embodiment, the test platform 11 may further include a read-back cache module 116, coupled to the second instruction execution module 114. According to one embodiment, the read-back cache module 116 may include a first-in-first-out queue 1161, capable of caching the signals read back by the second instruction execution module 114 from the chip under test 12 in order.

[0048] According to one embodiment, the test platform 11 may further include a data sending module 117, coupled to the read-back cache module 116 and the host computer 10. According to one embodiment, the read-back cache module 116 is configured to send data to the data sending module 117 in the read-back order, and the data sending module 117 is configured to convert parallel data into serial data and send it to the host computer 10.

[0049] According to one embodiment, when the first instruction is a write instruction, the first state machine 1121 in the first instruction execution module 112 can parse the first instruction and write the second instruction to the corresponding address in the storage module 113 according to the address therein.

[0050] According to one embodiment, when the first instruction is an execution instruction, the first instruction execution module 112 may send a control signal to control the second instruction execution module 114 to obtain and execute the second instruction.

[0051] According to one embodiment, the second instruction may include various types such as sending data, reading data, waiting for transmission completion, waiting for a specific signal, configuring a specific signal, jumping, delaying, and ending.

[0052] According to one embodiment, when the type of the second instruction is sending data, its content may include an instruction type flag, the content of the data to be sent, and the length of the data to be sent.

[0053] According to one embodiment, when the type of the second instruction is reading data, its content may include an instruction type flag, the length of the data, and the content of the data. According to one embodiment, in some special cases, data needs to be sent while reading data, so the content of sending data is included in the read data instruction.

[0054] According to one embodiment, when the type of the second instruction is waiting for transmission completion, its content may include an instruction type flag.

[0055] According to one embodiment, when the type of the second instruction is waiting for a specific signal, its content may include an instruction type flag and the encoding of the signal to be waited for. The signal to be waited for is the signal in the chip under test 12.

[0056] According to one embodiment, when the type of the second instruction is configuring a specific signal, its content may include an instruction type flag, the target level of the signal to be configured, and the encoding of the signal to be configured. The signal to be configured is the signal in the second instruction execution module 114.

[0057] According to one embodiment, when the type of the second instruction is jumping, its content may include an instruction type flag, the predetermined number of jump times, and the storage address of the second instruction to which the jump is made.

[0058] According to one embodiment, when the second instruction is a delay, its content may include an instruction type flag and the number of clock cycles of the delay.

[0059] According to one embodiment, when the second instruction is an end, its content may include an instruction type flag.

[0060] Figure 3 It is a flowchart of the test platform processing the first instruction according to an embodiment of the present application.

[0061] Step 301: The test platform 11 receives the first instruction from the host computer. According to one embodiment, this step may further include converting the first instruction from a serial instruction to a parallel instruction.

[0062] Step 302: Decode the first instruction, and determine whether the first instruction is a write instruction or an execution instruction according to the control word in the first instruction.

[0063] Step 303: When the first instruction is a write instruction, store the write content in the first instruction as the second instruction based on the second instruction storage high address and the second instruction storage low address in the first instruction.

[0064] Step 304: When the first instruction is an execution instruction, the test platform 11 starts to execute the second instruction.

[0065] Figure 4 It is a schematic diagram of the state and jump mode of the first state machine according to an embodiment of the present application.

[0066] According to an embodiment, after the test platform is started, the first state machine 1121 is in the default state 401.

[0067] According to an embodiment, when the first instruction execution module 112 receives the first instruction and detects the synchronization byte, the first state machine 1121 jumps to the synchronization state 402.

[0068] According to an embodiment, when the first instruction execution module 112 receives the first instruction control word, the first state machine 1121 jumps to the first instruction recognition state 403. According to an embodiment, the first instruction control word can include two types, namely the write control word and the execution control word. In the first instruction recognition state 403, the first state machine 1121 will recognize the type of the first instruction control word.

[0069] According to an embodiment, if the first instruction control word is a write control word, it is determined that the first instruction is a write instruction, and it jumps to the state 405 of receiving the second instruction storage high address, and the first instruction execution module 112 receives the second instruction storage high address.

[0070] According to an embodiment, after receiving the second instruction storage high address, the first state machine 1121 jumps to the state 406 of receiving the second instruction storage low address, and the first instruction execution module 112 receives the second instruction storage low address.

[0071] According to an embodiment, after receiving the second instruction storage low address, the first state machine 1121 sequentially jumps to the state of receiving the 1st byte of the write content, the state of receiving the 2nd byte of the write content, the state of receiving the 3rd byte of the write content, and the state of receiving the 4th byte of the write content, and the first instruction execution module 112 sequentially receives the 1st byte to the 4th byte of the write content. According to an embodiment, the write content or the second instruction with different specifications can be determined according to user needs.

[0072] According to an embodiment, after receiving the 4th byte of the write content, the first state machine 1121 can jump to the write state 411, write the second instruction content to the specified address in the storage module 113. After the writing is completed, it jumps to the default state 401.

[0073] According to one embodiment, in the first instruction recognition state 403, if the first instruction control word is recognized as an execution control word, it is determined that the first instruction is an execution instruction, and the process jumps to the start execution state 404 of the second instruction execution module. The first state machine 1121 controls the second instruction execution module 114 to execute the second instruction, and then jumps to the default state 401.

[0074] According to one embodiment, when the first instruction execution module 112 receives an escape byte, the next byte is regarded as an ordinary byte, even if the next byte appears to be a synchronization byte or an escape byte.

[0075] According to one embodiment, the synchronization byte is a flag indicating the start of a new instruction. Therefore, regardless of the current state of the first state machine 1121, as long as a synchronization byte without an added escape byte is received, the process jumps to the synchronization state 402. The first instruction may be interrupted during transmission. In this case, the host computer 10 only needs to send a synchronization byte without an added escape byte to start sending a new first instruction from the beginning.

[0076] Figure 5 It is a schematic diagram of the states and jump methods of the second state machine according to an embodiment of the present application.

[0077] According to one embodiment, before receiving the control signal sent by the first instruction execution module 112, the second state machine 1141 is in the default state 501.

[0078] According to one embodiment, after receiving the control signal sent by the first instruction execution module 112, the second state machine 1141 jumps to the second instruction reading state 502. In this state, the second instruction execution module 114 reads an instruction from the storage module 113 and parses it. According to one embodiment, the second instruction execution module 114 can also increment the storage index address of the next second instruction to be read by 1 in advance to ensure that the next second instruction is read from a new address.

[0079] According to one embodiment, when the second instruction execution module 114 finds that the second instruction it reads is an end instruction after parsing, the second state machine 1141 jumps back to the default state 501.

[0080] According to one embodiment, when the second instruction execution module 114 finds that the second instruction it reads is a non-end instruction after parsing, the second state machine 1141 jumps to the corresponding state according to the specific instruction type.

[0081] According to one embodiment, when the second instruction is a data transmission instruction, the second state machine 1141 jumps from the second instruction reading state 502 to the data transmission state 503. In this state, the data transmission control module 1143 performs an operation of transmitting data to the interface protocol driver module 115, and after the operation is completed, the second state machine 1141 jumps back to the second instruction reading state 502.

[0082] According to one embodiment, when the second instruction is a data reading instruction, the second state machine 1141 jumps from the second instruction reading state 502 to the data reading state 504. In this state, the data reading control module 1144 reads data from the interface protocol driver module 115, and transmits the read data to the read-back cache module 116, and after the operation is completed, the second state machine 1141 jumps back to the second instruction reading state 502.

[0083] According to one embodiment, when the second instruction is to wait for a specific signal, the second state machine 1141 jumps from the second instruction reading state 502 to the wait signal state 505. In this state, the second state machine 1141 performs a waiting operation until the specific signal is valid, and after the operation is completed, it jumps back to the second instruction reading state 502.

[0084] According to one embodiment, when the second instruction is to configure a specific signal, the second state machine 1141 jumps from the second instruction reading state 502 to the configure signal state 506. In this state, the second state machine 1141 performs an operation of configuring the specific signal to a specified level, and after the operation is completed, the second state machine 1141 jumps back to the second instruction reading state 502.

[0085] According to one embodiment, when the second instruction is a jump instruction, the second state machine 1141 jumps from the second instruction reading state 502 to the second instruction address change state 507. In this state, the second state machine 1141 performs an operation of changing the second instruction storage index address to a specified address, and after the operation is completed, it jumps back to the second instruction reading state 502. During the chip testing process, some operations need to be repeated until a certain number of times is reached. The counting module 1145 is configured to count the number of repeated executions.

[0086] According to one embodiment, when the second instruction is a delay, the second state machine 1141 jumps from the second instruction reading state 502 to the delay state 508. In this state, the timing module 1142 starts counting until the count of the timing module 1142 accumulates to a specified value, and after completion, the second state machine 1141 jumps back to the second instruction reading state 502.

[0087] According to one embodiment, when the second instruction is an end, the second state machine 1141 jumps from the second instruction reading state 502 to the default state 501.

[0088] Figure 6 It is a schematic diagram of the operation steps executed by the second instruction execution module during the chip testing process according to an embodiment of the present application.

[0089] According to an embodiment, during the chip testing process, the second instructions stored in the storage module 113 are shown in Table 1.

[0090] Table 1 Address Second Instruction Address 1 Send Data 0xFF Address 2 Delay 1 Millisecond Address 3 Configure Specific Signal to be Valid Address 4 Wait for Completion Signal to be Valid Address 5 Send Data 0x44 Address 6 Read Data Address 7 Change the Storage Index Address of the Second Instruction to Address 4 until the Set Number of Repetitions is Reached Address 8 End According to an embodiment, during the chip testing process, the steps for the second state machine 1141 to execute operations are as Figure 6 shown.

[0091] Step 601: The second instruction execution module 114 receives a control signal from the first instruction execution module 112 and starts to execute the second instruction.

[0092] Step 602: The second instruction execution module 114 reads from address 1 of the storage module 113 the second instruction to send data 0xFF, and the data sending control module 1143 executes the operation of sending data 0xFF.

[0093] Step 603: The second instruction execution module 114 reads from address 2 of the storage module 113 the second instruction to delay for 1 millisecond, and the timing module 1142 executes the operation of delaying for 1 millisecond.

[0094] Step 604: The second instruction execution module 114 reads from address 3 of the storage module 113 the second instruction to configure a specific signal to be valid, and the second state machine 1141 executes the operation of configuring the specific signal to be valid.

[0095] Step 605: The second instruction execution module 114 reads from address 4 of the storage module 113 the second instruction to wait for the completion signal to be valid. The completion signal indicates that the chip has completed the conversion of data. The second state machine 1141 executes the operation of waiting for this signal to be valid.

[0096] Step 606: The second instruction execution module 114 reads from address 5 of the storage module 113 the second instruction to send data 0x44, and the data sending control module 1143 executes the operation of sending data 0x44.

[0097] Step 607: The second instruction execution module 114 reads from address 6 of the storage module 113 the second instruction to read data, and the data reading control module 1144 executes the operation of reading data.

[0098] Step 608: The second instruction execution module 114 reads the second instruction to be jumped from address 7 of the storage module 113, and the second state machine 1141 performs an operation to change the storage index address of the second instruction. According to one embodiment, during the chip testing process, steps 605 to 608 need to be repeated until a set number of repetitions is reached. Therefore, when executing step 608, if the count of the counting module 1145 has not reached the set number of repetitions, the second state machine 1141 will change the storage index address of the second instruction to address 4, that is, return to step 605.

[0099] Step 609: When the count of the counting module 1145 has reached the set number of repetitions, the second instruction execution module 114 reads the ending second instruction from address 8 of the storage module 113.

[0100] This application adopts the method of pre-caching instructions in the FPGA, transfers some operations originally completed in the host computer to the FPGA to complete, and uses each clock cycle as much as possible. Compared with the existing FPGA chip testing platform, the present invention reduces the delay, enables the chip under test to accurately enter the specified state, and completes the testing of the specified functions. The interface protocol driving module proposed in this application can perform frequency division processing, so that the working clock frequency of the testing platform meets the requirements of the chip under test.

[0101] The above embodiments are only for illustrating this application, rather than limiting this application. Those of ordinary skill in the relevant technical field can also make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of the disclosure of this application.

Claims

1. A chip testing platform based on FPGA, characterized in that: include: A first instruction execution module is configured to decode a first instruction from a host computer, wherein the type of the first instruction includes at least a storage instruction and an execution instruction, and when the first instruction is a storage instruction, the content of the first instruction includes a second instruction and a corresponding address for storing the second instruction, and the first instruction execution module is configured to perform a storage operation on the second instruction based on the address; and A second instruction execution module is coupled to the first instruction execution module. When the first instruction type is an execution instruction, the first instruction execution module is configured to send a control signal to the second instruction execution module, and the second instruction execution module is configured to read and parse the second instruction, wherein the type of the second instruction corresponds to different operations in the chip testing process.

2. The test platform according to claim 1, characterized in that: A storage module is included, configured to provide a storage space for the second instruction.

3. The test platform according to claim 1, characterized in that: The second instruction execution module is configured to send data to the chip under test; the type of the second instruction includes a data sending instruction, the content of which includes Including instruction type tag; data content and data length to be sent.

4. The test platform according to claim 1, characterized in that: The second instruction execution module is configured to read data from the chip under test; the type of the second instruction includes a data read instruction, and the content of the second instruction includes Includes instruction type tag and length of data to be read.

5. The test platform according to claim 1, characterized in that: The second instruction execution module is further configured to send specific data to the chip under test while reading data from the chip under test when testing an abnormal situation; in this case, the second instruction content also includes the data sent to the chip under test.

6. The test platform according to claim 1, characterized in that: The second instruction execution module includes a counting module; the type of the second instruction includes a jump instruction, and the content of the second instruction includes an instruction type tag; Jump address; and the number of cycles; When the second instruction execution module reads a jump instruction, it is configured to obtain the second instruction at the corresponding position according to the jump address and execute it, and the count value of the counting module is increased by one until the count value of the counting module meets the number of loops in the jump instruction.

7. The test platform according to claim 1, characterized in that: The second instruction execution module includes a timing module; the type of the second instruction includes a delay instruction, and its content includes an instruction type tag; a delay time; when the second instruction execution module reads the delay instruction, the timing module starts timing and waits until the time specified in the delay instruction is reached before reading the next second instruction.

8. The test platform according to claim 1, characterized in that: The first instruction execution module includes a first state machine configured to set the first instruction execution module in a corresponding state according to the type of the first instruction.

9. The test platform according to claim 1, characterized in that: The second instruction execution module includes a second state machine configured to set the second instruction execution module in a corresponding state according to the type of the second instruction.

10. The test platform according to claim 1, characterized in that: The first instruction includes a synchronization byte to represent the new first instruction. When the first instruction execution module receives the synchronization byte, the first instruction execution module and the second instruction execution module stop executing the current operation and start executing the new first instruction.

11. The test platform according to claim 1, characterized in that It also includes an interface protocol driver module, which is coupled to the second instruction execution module and the chip to be tested, and is configured to be controlled by the second instruction execution module, receive data from the second instruction execution module, and send it to the chip to be tested; and read data from the chip to be tested and send it to the second instruction execution module.

12. The test platform according to claim 1, characterized in that It also includes a read-back cache module, which is coupled to the second instruction execution module and is configured to cache the data read back by the chip to be tested in sequence.

13. A chip testing system, characterized in that It comprises a host computer and a chip testing platform as described in any one of claims 1 to 12.

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