A hypergraph partitioning algorithm for multiple fpga multi-constrained considering logic cell replication

Abstract

The application discloses a hypergraph partitioning algorithm, which comprises the following steps: integrating and constructing a data structure; using mtKahypar to divide a circuit netlist into N parts in the form of a hypergraph; using a Steiner tree to map circuit nodes to corresponding FPGAs; using a legalization algorithm to cancel nodes that do not meet the FPGA resource constraints and hop constraints from the current partition, store the nodes in a list data structure, and set the current partition result as an initial solution; performing linear programming mathematical modeling; using a greedy algorithm to copy nodes with maximum benefits to reduce an objective function, and then obtaining a final solution. Compared with the prior art, the application has the advantages that: by combining mtKahypar, a Steiner tree, linear programming and a greedy algorithm, the application effectively solves the problems of resource constraints and cross-FPGA connection in FPGA partitioning, and significantly improves the efficiency, accuracy and adaptability of hypergraph partitioning.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and particularly relates to a hypergraph partitioning algorithm considering logic cell replication for multiple FPGAs with multiple constraints. BACKGROUND

[0002] With the rapid expansion of integrated circuit design scale, a single FPGA (Field-Programmable Gate Array) cannot meet the simulation requirements of designs up to tens of billions of gates. In a multi-FPGA system, the design needs to be distributed on multiple FPGAs for simulation, which puts higher requirements on the quality and speed of the partitioning algorithm. Unreasonable partitioning will increase the number of cross-FPGA connections, leading to a decrease in the running frequency of the DUT (Design Under Test), and thus affecting the efficiency and accuracy of the simulation.

[0003] In the prior art, hypergraph partitioning algorithms are widely used in integrated circuit design, especially for handling high-order interaction relationships in large-scale circuits. However, these algorithms face the following challenges in the multi-FPGA scenario:

[0004] Insufficient timing optimization: The partitioning result often ignores the timing requirements of the design, limiting the simulation efficiency.

[0005] Layout and routing complexity: The difficulty of layout and routing within the FPGA increases, affecting overall performance.

[0006] Connection density problem: The increase in the number of cross-FPGA connections significantly reduces the system running frequency.

[0007] Research shows that in VLSI circuit layout design, the technology of combining vertex replication with the HP (Hypergraph Partitioning) model can effectively reduce the number of connections between networks and the wiring density. Vertex replication refers to replicating the same logic cell or gate in multiple networks to share the connection load. Introducing the logic cell replication technology in hypergraph partitioning can not only optimize cross-FPGA connections but also improve timing performance. Although replicating logic cells increases some resource overhead, by reducing cross-FPGA connections between networks, it can significantly improve the efficiency of system simulation.

[0008] The application of hardware simulation platforms in IC verification shows that their high performance and full visualization features make them key tools for handling SoC hardware and software interactions. However, existing hypergraph partitioning algorithms have not fully utilized the potential of logic cell replication, making it difficult to meet the needs of multi-FPGA systems for efficient partitioning. SUMMARY

[0009] The technical problem solved by the present application is to provide a hypergraph partitioning algorithm combined with logic unit replication in view of the deficiencies in the prior art, which significantly reduces cross-FPGA connections, improves DUT running frequency and simulation efficiency, and ensures that resource utilization and wiring complexity are within a controllable range through optimization of partitioning and replication strategies for multi-FPGA simulation scenarios in large-scale integrated circuit design.

[0010] To solve the above technical problems, the technical solution provided by the present application is a hypergraph partitioning algorithm considering logic unit replication for multiple FPGA multi-constraints, which comprises the following steps:

[0011] Step 1: Make a parser to extract the information needed for partitioning and integrate and build a data structure;

[0012] Step 2: Use mtKahypar to partition the circuit netlist into N parts as a hypergraph, where N is the number of FPGA partitions;

[0013] Step 3: Use the Steiner tree to map the circuit nodes to the corresponding FPGA;

[0014] Step 4: Use the legalization algorithm to cancel the nodes that do not meet the FPGA resource constraints and hop constraints from the current partition and store them in a list data structure, and set the current partition result as the initial solution;

[0015] Step 5: Perform linear programming mathematical modeling, one of the core innovations of the present application is to introduce a linear programming model to optimize the partitioning result, by defining the objective function and constraint conditions, the initial solution and the nodes that do not meet the constraints are jointly optimized to obtain the optimal solution. This method is significantly different from traditional hypergraph partitioning algorithms, and embodies the advantages of linear programming in multi-FPGA partitioning.

[0016] Step 6: Use the greedy algorithm to replicate the nodes with the maximum benefit to reduce the objective function, and then obtain the final solution.

[0017] Further, the making parser of step 1 extracts the information needed for partitioning, which is performed by the following steps:

[0018] A. Delete useless comments, spaces and line breaks, and arrange valid string data;

[0019] B. Lexical analysis: use symbols and characters such as parentheses, colons, semicolons, etc. as morphemes to convert the string to a lexical string;

[0020] C. Syntax analysis: according to the delimiter, use a finite state machine to extract key-value pairs in the lexical string, and store the key-value pairs in a recursive structure;

[0021] D, find value: recursively find the key containing a certain string from the above structure, and store its value in the database.

[0022] Further, step two adopts the mtkhypar algorithm for hypergraph partitioning, specifically, the following steps are used for preprocessing:

[0023] A, in order to reduce the repeated calculation of distance time and reduce the time complexity, the distance between each two nodes is calculated in advance, and a two-dimensional array structure is used to store these distances;

[0024] B, an improved algorithm based on mtKahypar is developed to quickly and accurately locate the unassigned nodes adjacent to the input node, and based on this, the node sequence meeting the constraints is efficiently selected for FPGA allocation.

[0025] Further, step three adopts the Steiner tree to map the circuit nodes to the corresponding FPGA, specifically, the following steps are used for mapping:

[0026] A, construct the minimum Steiner tree to map the circuit nodes to the corresponding FPGA to optimize the connection length between nodes and reduce the number of cross-FPGA connections;

[0027] B, optimize FPGA mapping through Steiner tree, and use legality check function to filter out illegal partition nodes.

[0028] Further, step four adopts the legalization algorithm to cancel the nodes that do not meet the FPGA resource constraints and hop constraints from the current partition, specifically, the following steps are used for legalization:

[0029] A, design legality check function to ensure that the resource consumption and maximum interconnection number of each FPGA do not exceed the limit;

[0030] B, the nodes that do not meet the constraints will be removed and stored in a list, while the partition results that meet the constraints will be used as the initial solution.

[0031] Further, step five performs linear programming mathematical modeling, specifically, the following steps are used for solving:

[0032] A, define decision variables, objective function and constraint conditions, and use solver to find the optimal solution;

[0033] B, the initial solution and nodes that do not meet the constraints are passed in for linear programming solution.

[0034] Further, step six uses the greedy algorithm to copy the nodes with maximum benefit to reduce the objective function, specifically, the following steps are used for copying:

[0035] A, construct a sparse matrix for each node to record the source node and drain node connected thereto;

[0036] B, calculate the cost function of replicating a node, based on which, sort the cost of all nodes, and sort the FPGA that contributes to the cost of the node, so that the node to be replicated first and the FPGA to which the node is replicated first can be obtained.

[0037] After adopting the above method, the present application has the following advantages: by combining mtKahypar, steiner tree, linear programming and greedy algorithm, the present application effectively solves the resource limitation and cross-FPGA connection problem in FPGA division, and significantly improves the efficiency, accuracy and adaptability of hypergraph division. BRIEF DESCRIPTION OF DRAWINGS

[0038] Fig. 1 It is a schematic diagram of a hypergraph partitioning algorithm considering logic unit replication of multiple FPGA multi-constraints;

[0039] Fig. 2 It is a step five solution schematic diagram of a hypergraph partitioning algorithm considering logic unit replication of multiple FPGA multi-constraints;

[0040] Fig. 3 It is a step six algorithm schematic diagram of a hypergraph partitioning algorithm considering logic unit replication of multiple FPGA multi-constraints. DETAILED DESCRIPTION

[0041] The present application will be further described in detail below with reference to the accompanying drawings.

[0042] In combination with the accompanying drawings Figs. 1-3 A hypergraph partitioning algorithm considering logic unit replication of multiple FPGA multi-constraints, the entire program is written based on python. First, parse the input design file, then build the circuit diagram and FPGA graph and convert to a specific format. Next, use the Mt-KaHyPar tool for preliminary division, map the design to the FPGA, then filter out illegal division nodes through the legalization step, and optimize through linear programming and greedy algorithm to find the best FPGA mapping scheme, and finally output the optimized result. Next, each step will be described in detail:

[0043] Step one: make a parser to extract the information needed for division, integrate and build a data structure, the parser extracts the information needed for division, which is extracted by the following steps:

[0044] A, delete useless comments, spaces and line breaks, and arrange valid string data;

[0045] B. Lexical analysis: Use symbols such as parentheses, colons, semicolons, and characters as morphemes to convert strings into lexical strings.

[0046] C. Syntax analysis: According to the delimiter, use a finite state machine to extract key-value pairs in the lexical string, and store them in a recursive structure.

[0047] D. Find the value: recursively find the key containing a certain string in the above structure, and store its value in the database.

[0048] In order to improve the execution efficiency of the algorithm, it is essential to write a parser that can handle multiple file inputs and convert them into appropriate data structures. The following is a description of the main data structures used in the parser:

[0049]

[0050] The general flow of the Parser is as follows:

[0051] Read the design.are file to fill in the nodes dictionary, with node names as keys and node resource lists as values. At the same time, generate node_id_map for the mapping between node ID and name.

[0052] Read the design.info file and fill in the FPGAs dictionary to store the maximum interconnection number and resource limit of the FPGA. At the same time, generate fpga_id_map to facilitate the mapping between FPGA name and ID.

[0053] Read the design.net file, parse the network information, and fill in the nets list.

[0054] Read the design.topo file to get the hop limit and fill in the topo list. Then use the Floyd-Warshall algorithm to calculate the shortest path between all FPGAs to establish hop_map.

[0055] In order to improve the efficiency of subsequent processing, the following measures are taken after file parsing is completed: First, in order to adapt to the use of Mt-KaHyPar tool, the entire circuit netlist is constructed into a hypergraph and exported in hmetis format. This helps to optimize the subsequent processing flow. Second, considering the demand of FPGA mapping, the FPGA is constructed into a graph and output in metis format. These steps are to ensure higher efficiency and performance in the FPGA mapping process.

[0056] Step two: divide the circuit netlist into N parts, where N is the number of FPGAs, and use the algorithm to divide the hypergraph, specifically using the following steps for preprocessing:

[0057] A. To reduce repeated distance calculations and lower time complexity, the distance between each pair of nodes is calculated in advance and stored using a two-dimensional array structure.

[0058] B. Quickly and accurately locate the unassigned nodes adjacent to the input node, and based on this, efficiently select the node sequence that meets the constraints for FPGA allocation.

[0059] In the implementation of an efficient hypergraph partitioning process, Mt-KaHyPar is chosen as the main tool, which is a multi-threaded hypergraph partitioner that stands out in its class with its outstanding processing speed. The reasons for choosing Mt-KaHyPar mainly include the following two points:

[0060] Fast processing capability: Mt-KaHyPar can quickly process large-scale hypergraph data, significantly reducing the time required for partitioning. This makes it ideal in scenarios where an initial partition needs to be generated quickly.

[0061] Multi-threading support: The multi-threading feature of this tool fully utilizes the multi-core processing power of modern computers, making the partitioning process more efficient.

[0062] When using Mt-KaHyPar for hypergraph partitioning, the goal of the initial partition is to quickly divide the hypergraph into M parts, where M is set according to the number of FPGAs. By dividing the hypergraph into several parts, subsequent optimization algorithms can work on smaller sub-problems, thereby improving overall optimization efficiency.

[0063] Step three: Use the Steiner tree to map the circuit nodes to the corresponding FPGAs. Specifically, the following steps are used for mapping:

[0064] A. Construct the minimum Steiner tree to map the circuit nodes to the corresponding FPGAs to optimize the connection length between nodes and reduce the number of cross-FPGA connections.

[0065] B. Optimize FPGA mapping through the Steiner tree and use a legality check function to filter out illegal partition nodes.

[0066] In FPGA mapping, the minimum Steiner tree is used for guidance. The Steiner tree is used to find the shortest tree-like structure connecting a given set of nodes. When partitioning a circuit graph onto an FPGA graph, we want the circuit nodes to be as close as possible, essentially optimizing a kind of layout so that the connection length between nodes (in the abstract sense of physical layout or logical connection) is as short as possible.

[0067] Guided by Steiner trees, directly connected nodes can be prioritized for partitioning, ensuring that their physical distance is minimized. This not only helps satisfy hop constraints, but also minimizes the number of hyperedges cut during partitioning, as hyperedges connect multiple nodes. This keeps nodes within hyperedges within the same FPGA as much as possible, reducing the number of cross-FPGA connections and minimizing cutting overhead.

[0068] Step 4: Use a validation algorithm to remove nodes that do not meet the FPGA resource constraints and hop count constraints from the current partition and store them in a list data structure. Set the current partition result as the initial solution. The validation algorithm is used to remove nodes that do not meet the FPGA resource constraints and hop count constraints from the current partition. Specifically, the validation is performed using the following steps:

[0069] A. Design a validity check function to ensure that the resource consumption and maximum number of interconnects for each FPGA do not exceed the limit;

[0070] B. Nodes that do not meet the constraints will be removed and stored in a list, while the partitioning results that meet the constraints will be used as the initial solution.

[0071] Since the problem requires the use of hard constraints, the FPGA mapping based on the minimum Steiner tree cannot guarantee global validity. Therefore, a validity check function is designed to verify the validity of the current result. For violating nodes, they are removed from the partitioned FPGA and stored in a list. Then, a relaxation operation is performed to ensure that the current partitioning result is valid. This valid result will be used as the initial partition for the linear programming solver and passed to subsequent linear programming solvers to implement soft constraints, enabling the linear programming solver to find a better solution within the time limit. The notation is explained in Table 1 below.

[0072]

[0073] The specific expression for the validity check function is as follows:

[0074] Resource constraint valid: If a certain FPGA i resource usage U i >R i Then from V i Remove nodes that exceed the available resources and add them to V. violated ;

[0075] Hop constraint: If the source node s of a certain hyperedge is assigned to the FPGA i The drain node d directly connected to it is partitioned into the FPGA. j , and h ij >h maxThe drain node is removed from the corresponding FPGA j and then added to the V violated

[0076] The legalized output result is the partition result after removing the illegal nodes. Because there are millions of cells in an actual circuit, the result is used as the initial solution of the linear programming, which aims to reduce the solution space of the linear programming and improve the solution speed.

[0077] Step five: mathematical modeling of linear programming. One of the core innovations of the present application is to introduce a linear programming model to optimize the partition result. By defining the objective function and the constraint condition, the initial solution and the nodes that do not meet the constraint are jointly optimized to obtain the optimal solution. This method is significantly different from the traditional hypergraph partitioning algorithm and embodies the advantage of linear programming in multi-FPGA segmentation. The mathematical modeling of linear programming is performed by the following steps:

[0078] A, define the decision variable, objective function and constraint condition, and use the solver to find the optimal solution;

[0079] B, the initial solution and the nodes that do not meet the constraint are transmitted into the linear programming solver.

[0080] The nodes that violate the rules are partitioned in accordance with the mathematical model by using the linear programming solver. The linear programming mathematical modeling is as follows, and the symbols are shown in Table 1:

[0081] 1. Define the decision variable:

[0082] x n,m : if node n is allocated to FPGA m, then x n,m = 1, otherwise 0.

[0083] y k,m : if the hyperedge k is cut (the source node and the drain node are not in the same FPGA), and the source node is on FPGA m, and at least one of its drain nodes is on a different FPGA, then y k,m = 1, otherwise 0.

[0084] 2. Define the objective function as the minimization of the hop of all cut edges multiplied by the weight of the edge:

[0085]

[0086] Here Z is the objective function, representing the quantity to be minimized, and wk is the weight of the hyperedge k.

[0087] 3. Define the resource constraint:

[0088] Node assignment constraint, each node can only be assigned to one FPGA:

[0089]

[0090] Here is the total number of nodes, and the total number of FPGAs. This constraint indicates that each node can only be assigned to one FPGA on the resource constraint, the resource consumption on each FPGA cannot exceed the resource limit:

[0091]

[0092] The maximum number of interconnections constraint ensures that the maximum number of interconnections of each FPGA does not exceed the limit:

[0093]

[0094] The hop constraint ensures that the source and drain of the superedge do not exceed the hop constraint

[0095] h i,j ≤h max

[0096] The linear programming solution model is as follows:

[0097]

[0098] The nodes that violate the above mathematical model are solved by using a linear programming solver to obtain an optimal solution. The specific process is as follows: first, establish a linear programming problem according to the above mathematical model. Then, the nodes that do not satisfy the constraint conditions (such as resource constraints, interconnection line constraints, etc.) are taken as variables, and are solved by a linear programming solver. The linear programming solver will find the optimal solution of the objective function under the condition of satisfying all the constraint conditions, thereby obtaining the optimal allocation scheme of the nodes.

[0099] Step six: use the greedy algorithm to copy the node with the maximum benefit to reduce the objective function, and then obtain the final solution. The greedy algorithm is used to copy the node with the maximum benefit to reduce the objective function. The specific steps are as follows:

[0100] A. Construct a sparse matrix for each node to record the connected source nodes and drain nodes;

[0101] B. Calculate the cost function of copying a node. Based on this, sort the cost of all nodes, and sort the FPGAs that contribute to the cost of the node. Therefore, the node to be copied first and the FPGA to which the node is copied first can be obtained.

[0102] After getting the better solution by using linear programming solver, in order to further optimize the objective function, consider replicating logic units. In the replication process, still need to follow the previous constraints, using greedy algorithm to achieve the maximum degree of replication.

[0103] Core idea:

[0104] For each node, a sparse matrix is constructed to record the source and drain nodes connected to it. By querying a node, you can understand which drain nodes it connects as a source node, and which source nodes it connects as a drain node, while also containing the number of hops between nodes and the weight of the edge.

[0105] Cost function:

[0106] The cost function for replicating a node is defined as:

[0107] cost = decrease_cost - increase_cost

[0108] decrease_cost calculation:

[0109] When traversing the node, if there are multiple nodes belonging to the same FPGA among the drain nodes connected as source nodes, consider them as an edge connecting these nodes.

[0110] Calculate the number of hops using the source and drain nodes and multiply by the weight, noting to avoid repeated calculation. This result is the reduced cost after replication.

[0111] If the connected drain nodes come from different FPGAs, each edge needs to be calculated separately to reduce the cost.

[0112] increase_cost calculation:

[0113] When the node is a drain node, the increase cost is the number of hops between the other nodes connected to it and itself multiplied by the weight.

[0114] Node sorting and optimization:

[0115] Based on the cost function, sort all nodes by cost, and sort the FPGAs that contribute to the cost of the node.

[0116] This way you can get the nodes to be replicated first, and the FPGAs to be replicated to first.

[0117] The greedy algorithm will replicate as many nodes as possible to reduce the objective function while meeting the constraints.

[0118] The above describes the present application and its embodiments, which are not limited. The actual structure is not limited to the above. In general, if a person skilled in the art is inspired by the above, without departing from the spirit of the present application, similar structural modes and embodiments can be designed without creativity, and all of them should belong to the protection scope of the present application.

Claims

1. A hypergraph partitioning algorithm for multiple FPGA multi-constrained consideration of logic cell replication, characterized by: It comprises the following steps: Step one: make a parser to extract the information required for partitioning, integrate and build a data structure; Step two: use mtKahypar to divide the circuit netlist into N supergraphs, where N is the number of FPGA partitions; Step three: use Steiner tree to map the circuit nodes to the corresponding FPGA; Step four: use the legalization algorithm to cancel the nodes that do not meet the FPGA resource constraints and hop constraints from the current partition, store them in a list data structure, and set the current partition result as the initial solution; Step five: perform linear programming mathematical modeling, introduce linear programming model optimization partitioning results, define objective function and constraint conditions, jointly optimize the initial solution and nodes that do not meet the constraints to obtain the optimal solution; Step six: use the greedy algorithm to copy the nodes with the maximum benefit to reduce the objective function, and then get the final solution; Step five performs linear programming mathematical modeling, which is solved by the following steps: A, define decision variables, objective function and constraint conditions, and use the solver to find the optimal solution; B, the initial solution and the nodes that do not meet the constraints are transmitted to perform linear programming solution; The linear programming solution model is as follows: Here Z is the objective function, M is the total number of FPGAs, w k is the weight of hyperedge k, R is the maximum interconnect number constraint, is the mth resource constraint of FPGA i , C is the hop constraint, which ensures that the source and drain of hyperedge do not exceed the hop constraint, C imax is the maximum external interconnect number of FPGA i , h i，j is the hop number between FPGAs i and FPGAs j , h max is the maximum hop distance constraint allowed; y k,m : 1 if super-edge k is cut and the source node is on FPGAm and at least one of its drain nodes is on a different FPGA, otherwise 0; x n,m : 1 if node n is assigned to FPGA m, else 0; The nodes that violate the rules are solved by mathematical model using linear programming solver to get better solution, the specific process is as follows: first, according to the above mathematical model to establish linear programming problem, then, the nodes that do not meet the constraint conditions, such as resource constraints, interconnection line constraints, etc., are used as variables, and the linear programming solver is used to solve, the linear programming solver will find the optimal solution of the objective function under the condition of meeting all the constraints, so as to obtain the optimal allocation scheme of the nodes.

2. The algorithm for hypergraph partitioning considering multiple FPGAs and multiple constraints and logic cell replication according to claim 1, wherein: Step one of making a parser to extract the information required for partitioning, which is extracted by the following steps: A, delete useless annotations, spaces and line breaks, and arrange valid string data; B, lexical analysis: taking parentheses, colons and semicolons as morphemes, convert string to lexical string; C, syntax analysis: according to the delimiter, use finite state machine to extract key-value pairs in lexical string, and store them in a recursive structure; D, find value: recursively find the key containing a certain string in the structure and store its value in the database.

3. The algorithm for hypergraph partitioning considering multiple FPGAs and multiple constraints and logic cell replication according to claim 1, wherein: Step two uses mtkhypar algorithm to divide supergraph, which is preprocessed by the following steps: A, calculate the distance between each two nodes and store the distance using two-dimensional array structure; B, based on the improved algorithm of mtKahypar, locate the unassigned nodes adjacent to the input nodes, and select the node sequence that meets the constraints for FPGA allocation.

4. The algorithm of claim 1, wherein the plurality of FPGAs are multi-constrained. Step three uses Steiner tree to map the circuit nodes to the corresponding FPGA, which is mapped by the following steps: A, build the minimum Steiner tree to map the circuit nodes to the corresponding FPGA; B, optimize FPGA mapping through Steiner tree and use legality check function to filter out illegal partition nodes.

5. The algorithm for hypergraph partitioning considering multiple FPGAs and multiple constraints and logic cell replication according to claim 1, wherein: Step four uses the legalization algorithm to cancel the nodes that do not meet the FPGA resource constraints and hop constraints from the current partition, which is legalized by the following steps: A, design legality check function to ensure that each FPGA resource consumption and the maximum number of interconnections does not exceed the limit; B, the node that does not meet the constraints will be removed and stored in a list, and the partition result that meets the constraints will be used as the initial solution.

6. The algorithm for hypergraph partitioning considering multiple FPGAs and multiple constraints and logic cell replication according to claim 1, wherein: Step six uses the greedy algorithm to copy the node with the maximum benefit to reduce the objective function, which is as follows: A, for each node, a sparse matrix is constructed to record the source node and drain node connected to it; B, calculate the cost function of copying a node, based on which, sort the cost of all nodes, and sort the FPGA that contributes to the cost of the node to get the priority of copying the node and the FPGA to which it is copied.

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