A method for generating a sequence of logic synthesis optimization operators

Abstract

The application belongs to the field of electronic design automation (EDA), and specifically provides a logic synthesis optimization operator sequence generation method, which effectively solves the problems of high calculation complexity, low generation efficiency and high implementation cost of other schemes; in terms of optimization effect, the global optimal solution is obtained by using an exhaustive search strategy in the previous stage, thereby improving the overall optimization quality; in terms of generation efficiency, the local fast search is performed by using a grouping exploration strategy in the later stage, thereby significantly shortening the generation time of the optimization operator sequence; in summary, the application gets rid of the dependence on large-scale labeled data and complex training process, and significantly improves the generation efficiency of the optimization operator sequence while ensuring the optimization quality.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of electronic design automation (EDA), and particularly provides a logic synthesis optimization operator sequence generation method. BACKGROUND

[0002] In integrated circuit design, logic synthesis is a key step to convert register transfer level (RTL) hardware description language into gate-level netlist, and its core goal is to generate a physical implementation scheme that meets design constraints by optimizing circuit structure, timing, area, power consumption and other parameters. Logic optimization is completed by some optimization operators. In the logic synthesis process, numerous operators form an operator sequence, which optimizes the circuit in sequence. Due to the complex interaction between different optimization operations, the permutation and combination will significantly affect the core indicators such as timing margin, area utilization and dynamic power consumption of the final circuit. With the continuous shrinking of process nodes and the rapid growth of design complexity, the traditional method based on fixed rules or single optimization strategy is difficult to meet the needs of multi-objective optimization. Therefore, how to organize optimization operators and generate high-quality optimization operator sequences has become an important problem to break through the design bottleneck and improve the competitiveness of chips.

[0003] At present, the mainstream logic synthesis optimization operator sequence generation methods can be divided into three categories: rule library method based on expert experience, heuristic search method and machine learning method emerging in recent years. Among them, the rule library method relies on the design personnel to manually write the optimization process, which has the advantage of strong interpretability, but is severely limited by the accumulation of engineers' field knowledge, and is difficult to cope with new processes or complex design scenarios. Heuristic algorithms, such as genetic algorithms, simulated annealing and other methods, automatically search by establishing a mapping model between the optimization operator sequence and the circuit quality indicators. Although it can break through the limitations of human experience, it has problems such as high computational complexity, long time consumption and insufficient generalization ability. Machine learning methods train optimization strategy prediction models through historical data, which have shown potential in some benchmark tests, but face practical problems such as the need for a large amount of labeled data, high training cost and poor model generalization. In summary, the existing logic synthesis optimization operator sequence generation methods have obvious deficiencies in one or more aspects such as optimization effect, computational complexity and generalization ability. SUMMARY

[0004] The present application aims to overcome the deficiencies of the prior art and provide a logic synthesis optimization operator sequence generation method that efficiently generates optimization operator sequences for different circuits without labeled data, effectively improving the logic synthesis optimization effect.

[0005] To achieve the above purpose, the technical scheme adopted by the present application is:

[0006] A method for generating a sequence of logic synthesis optimization operators, characterized by comprising the following steps:

[0007] A1. Generate a global sequence of m-operators;

[0008] Let the set of logic synthesis optimization operators be W = {w1, w2, ..., w...} I}, where w i Let i be the i-th logic synthesis optimization operator, 1≤i≤I, where I is the number of logic synthesis optimization operators;

[0009] Arbitrarily arrange the optimization operators in the logic synthesis optimization operator set W to generate an operator sequence of length m, denoted as the m-operator sequence, generating a total of I... m A sequence of m-operators;

[0010] A2. Select the optimal m-operator sequence;

[0011] A2-1. For each m-operator sequence, perform sequence logic optimization on the input circuit using the current operator sequence to obtain the optimized circuit and calculate the index parameters of the circuit.

[0012] A2-2. Select the sequence with the largest index parameter as the optimal m-operator sequence, and denote the optimized circuit of this sequence as the current target circuit;

[0013] A2-3. Add each optimized operator in the optimal m-operator sequence to the optimized operator sequence R in sequence order;

[0014] A3. Generate a set of local n-operator sequences;

[0015] A3-1. Arrange the optimization operators in the logic synthesis optimization operator set W in any order to generate an operator sequence of length n, denoted as the n-operator sequence. Store all the generated n-operator sequences in the operator sequence set B.

[0016] A3-2. For each optimization operator in the set of logic synthesis optimization operators W, perform the following operation on the i-th optimization operator w: i Randomly select k operator sequences from the set of operator sequences B, and modify the first optimization operator of each operator sequence to w. i The modified k operator sequences are grouped together, denoted as the i-th group of n-operator sequences, and denoted as C. i ;

[0017] A4. Select the optimal sequence of n-operators;

[0018] A4-1. For each operator sequence group: use each operator sequence in the group to respectively perform sequence logic optimization on the current target circuit to obtain the optimized circuit of the sequence, and calculate the index parameter of the circuit; calculate the average value of the index parameters of the operator sequences in the group, and record the average index parameter of the operator sequence group as the average index parameter;

[0019] A4-2. Select the operator sequence group with the largest average index parameter as the optimal operator sequence group, select the operator sequence with the largest index parameter in the group as the current optimal n-operator sequence, and update the optimized circuit of the sequence as the current target circuit;

[0020] A4-3. Append each optimization operator in the current optimal n-operator sequence to the optimization operator sequence R in sequence order;

[0021] A5. Determine whether the sequence length meets the requirements: if the length of the optimization operator sequence R is less than the set sequence length, go to step A3, otherwise, output the optimization operator sequence R.

[0022] Further, in step A2-1, the process of sequence logic optimization is:

[0023] A2-1-1. Use the first operator of the operator sequence to perform logic optimization on the current circuit to obtain the optimized circuit;

[0024] A2-1-2. In sequence order, sequentially execute the subsequent operators to perform a set of continuous logic optimization on the circuit, each operator acting on the circuit optimized by the previous operator, until all operators in the sequence are executed, to obtain the optimized circuit of the operator sequence.

[0025] Further, in step A1, the sequence length m of the global m-operator sequence is in the range of 1≤m≤5.

[0026] Further, in step A3-1, the sequence length n of the local n-operator sequence is in the range of 3≤n≤15.

[0027] Further, in step A3-2, the value range of the number k of operator sequence searches is 10≤k≤100.

[0028] Based on the above technical solutions, the beneficial effects of the present application are:

[0029] The application provides a logic synthesis optimization operator sequence generation method, effectively solves the problems of high calculation complexity, low generation efficiency and high implementation cost of other schemes, in the optimization effect aspect, the global optimal solution is obtained by using an exhaustive search strategy in the previous stage, and the overall optimization quality is improved, in the generation efficiency aspect, the local fast search is performed by using a grouping exploration strategy in the later stage, and the generation time of the optimization operator sequence is significantly shortened, and finally, the application is free from the dependence on large-scale labeled data and complex training process, the optimization quality is ensured, and the generation efficiency of the optimization operator sequence is significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A flowchart of the logic synthesis optimization operator sequence generation method in the application is shown. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and beneficial effects of the application more clear, the application is further described in detail below with reference to the drawings and examples.

[0032] The application provides a logic synthesis optimization operator sequence generation method, and the flowchart is as shown in Figure 1 The specific steps are as follows:

[0033] A1. Generate a global m-operator sequence;

[0034] There are a logic synthesis optimization operator set W={w1, w2,..., w I}, wherein w i is the i-th logic synthesis optimization operator, 1≤i≤I, and I is the number of logic synthesis optimization operators; the optimization operators in W are arranged in any manner to generate an operator sequence with a length of m, wherein the operators can be repeated, and then I m m operator sequences with a length of m are generated, that is, I m m-operator sequences are generated;

[0035] In the embodiment, there are I=6 logic synthesis optimization operators in the logic synthesis optimization operator set W, which are Rewrite, rewrite-z, refactor, refactor-z, resub-K-8 and dc2; the value range of the sequence length m is 1≤m≤5, and the value in the embodiment is 3; the 6 operators are arranged in any manner to generate an operator sequence with a length of 3, and the optimization operators can be repeated, and then I m =216 3-operator sequences are generated: rewrite→rewrite-z→refactor, refactor→dc2→rewrite,..., refactor-z→resub-K-8→dc2;

[0036] A2. Select the optimal m-operator sequence;

[0037] A2-1. For each operator sequence, perform sequential logic optimization on the input circuit using the current operator sequence to obtain the optimized circuit of the sequence, and calculate the index parameter of the circuit;

[0038] In this embodiment, the input circuit is denoted as G0, which is in the format of AIG (And-Inverter Graph) and contains 482 input ports, 257 output ports, and 28910 AND gates. The index parameter is the number of reduced AND gates. Sequential logic optimization is performed on G0 using each operator sequence to obtain the optimized circuit of the sequence, and the number of reduced AND gates of the circuit relative to G0 is calculated;

[0039] Taking the operator sequence rewrite→rewrite-z→refactor as an example, sequential logic optimization specifically includes the following steps:

[0040] A2-1-1. Perform the first operator of the operator sequence on the current circuit to obtain the optimized circuit;

[0041] In this embodiment, the first operator rewrite of the operator sequence rewrite→rewrite-z→refactor is executed to perform logic optimization on the input circuit G0 to obtain the optimized circuit G1;

[0042] A2-1-2. In sequence, sequentially execute the subsequent operators to perform a set of continuous logic optimization on the circuit, each operator acting on the circuit optimized by the previous operator, until all operators in the sequence are executed, and finally the optimized circuit of the operator sequence is obtained;

[0043] In this embodiment, in sequence, sequentially execute the subsequent operators to perform a set of continuous logic optimization on the circuit: first, execute the second operator rewrite-z of the operator sequence rewrite→rewrite-z→refactor to perform logic optimization on the circuit G1 to obtain the optimized circuit G2, and then execute the third operator refactor of the operator sequence rewrite→rewrite-z→refactor to perform logic optimization on the circuit G2 to obtain the optimized circuit G3;

[0044] A2-2. Select the sequence with the largest index parameter as the optimal m-operator sequence, and record the optimized circuit of the sequence as the current target circuit;

[0045] In the embodiment, the number of AND gates of all 216 3-operator sequences is calculated and compared, and the sequence with the largest number of AND gate reduction is found to be dc2→dc2→rewrite, which is taken as the optimal 3-operator sequence, and the circuit G after optimization of dc2→dc2→rewrite is shown in Fig. 2b. best The current target circuit is denoted as G

[0046] A2-3. Each optimization operator in the optimal m-operator sequence is added to the optimization operator sequence R in sequence order.

[0047] In the embodiment, the dc2, dc2 and rewrite operators in the optimal 3-operator sequence dc2→dc2→rewrite are added to the optimization operator sequence R in sequence order. Since R is initially empty, R is updated to dc2→dc2→rewrite after the addition.

[0048] A3. Generate a local n-operator sequence group.

[0049] A3-1. The optimization operators in the logic synthesis optimization operator set W are arranged randomly to generate an operator sequence with a length of n, denoted as an n-operator sequence, where the operators can be repeated, and all generated n-operator sequences are saved in the operator sequence set B.

[0050] In the embodiment, the sequence length n is in the range of 3≤n≤15, and the value is 9 in the embodiment. The 6 operators in the operator set W are arranged randomly to generate an operator sequence with a length of 9, such as dc2→rewrite→rewrite→resub-K-8→refactor→rewrite-z→refactor-z→rewrite→dc2. All generated 9-operator sequences are added to the set B, and the operator sequence set B is initially empty.

[0051] A3-2. For each optimization operator w i , in the logic synthesis optimization operator set W, the first optimization operator of each operator sequence in the operator sequence set B is modified to w i , and the k operator sequences after modification form a group, denoted as the ith n-operator sequence group, denoted as C i , where k is a preset number of operator sequence searches.

[0052] In the embodiment, the value range of the number k of the operator sequence is: 10≤k≤100, and the value is 20 in the embodiment. The same processing is performed on each operator in the operator set W. Taking the first operator rewrite in W as an example, 20 operator sequences are randomly selected from the set B, the first operator of each operator sequence is modified to rewrite, that is, the first operator of these operator sequences is rewrite, and the 20 operator sequences form a group, which is recorded as the first 9-operator sequence group C1. The above processing is sequentially performed on other operators in the operator set W, and finally six 9-operator sequence groups are obtained, which are C1, C2,..., and C6 in sequence.

[0053] A4. Selecting the optimal n-operator sequence;

[0054] A4-1. Performing the following processing on each operator sequence group:

[0055] A4-1-1. Using each operator sequence in the group to perform sequential logic optimization on the current target circuit to obtain the optimized circuit of the sequence, and calculating the index parameter of the circuit;

[0056] In the embodiment, for the ith operator sequence group, the jth operator sequence c i,j in the group is used to perform sequential logic optimization on the current target circuit G best , to obtain the optimized circuit of the sequence, and calculate the number z i,j of AND gate reductions of the circuit relative to the input circuit G0.

[0057] A4-1-2. Calculating the average value of the index parameters of the operator sequences in the group, which is recorded as the average index parameter of the operator sequence group;

[0058] In the embodiment, for the ith operator sequence group, the index parameters of the operator sequences in the group are z i,1 , z i,2 ,..., and z i,20 , and the average value of the 20 index parameters is calculated , which is recorded as the average index parameter of the operator sequence group;

[0059] A4-2. Selecting the operator sequence group with the largest average index parameter as the optimal operator sequence group, selecting the operator sequence with the largest index parameter in the group as the current optimal n-operator sequence, and updating the optimized circuit of the sequence to the current target circuit;

[0060] In the embodiment, the average index parameters of each operator sequence group are compared, the operator sequence group with the largest numerical value is selected as the optimal operator sequence group, specifically the second group, and the number of AND gates of each operator sequence in the second group is compared, the operator sequence with the largest number of AND gate reduction is found as resub-K-8→dc2→rewrite→resub-K-8→refactor-z→dc2→refactor→rewrite→rewrite-z, which is recorded as the current optimal 9-operator sequence, and the optimized circuit of the operator sequence is updated as the current target circuit.

[0061] A4-3. Each optimization operator in the current optimal n-operator sequence is sequentially added to the optimization operator sequence R in sequence order.

[0062] In the embodiment, the resub-K-8, dc2, rewrite, resub-K-8, refactor-z, dc2, refactor, rewrite, and rewrite-z operators in the current optimal 9-operator sequence resub-K-8→dc2→rewrite→resub-K-8→refactor-z→dc2→refactor→rewrite→rewrite-z are sequentially added to the optimization operator sequence R, and after the first iteration, R is updated as dc2→dc2→rewrite→resub-K-8→dc2→rewrite→resub-K-8→refactor-z→dc2→refactor→rewrite→rewrite-z.

[0063] A5. Determine whether the sequence length meets the requirements: if the length of the optimization operator sequence R is less than the set sequence length, go to step A3, otherwise end the entire process and output the optimization operator sequence R.

[0064] In the embodiment, the set sequence length is 120, and it is determined whether the sequence length of the current optimization operator sequence R meets the requirements: when the length of R is less than 120, go to step A3, otherwise end the entire process and output the optimization operator sequence R with a length of 120: dc2→dc2→rewrite→resub-K-8→dc2→rewrite→resub-K-8→refactor-z→dc2→refactor→rewrite→rewrite-z→……→refactor→dc2→rewrite-z→resub-K-8→refactor→rewrite→dc2→resub-K-8→rewrite-z.

[0065] As a comparative example, a sequence generation method based on reinforcement learning is used as a comparative example, and the performance of the present application and the comparative example is compared, and the generation efficiency and optimization effect are respectively measured by the generation time and the number of AND gate reduction, the present application and the comparative example use the same input circuit as the test circuit, generate an optimized operator sequence with a length of 120, and the sequence generation performance comparison results are shown in Table 1.

[0066] Table 1

[0067] Method Generation time And gate reduction number Comparative example 10 min 4 sec 8434 The invention 4 min 05 sec 9139

[0068] As can be seen from the table, compared with the reinforcement learning method, the generation time of the present application is greatly shortened, and the number of AND gate reduction indicators is also obviously improved, indicating that the present application can obtain better sequence optimization effect in a shorter time.

[0069] The above is only a specific embodiment of the present application, any feature disclosed in the specification can be replaced by other equivalent or similar purpose alternative features unless specifically described, and all features disclosed or all steps in the method or process can be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A method for generating a sequence of logic synthesis optimization operators, characterized in that, The method comprises the following steps: A1. Generating a global m-operator sequence; A set of logic synthesis optimization operators W = {w1, w2,..., w I} is provided, wherein w i is the i-th logic synthesis optimization operator, 1≤i≤I, and I is the number of logic synthesis optimization operators. The optimization operators in the logical synthesis optimization operator set W are arranged randomly to generate an operator sequence with a length of m, denoted as an m-operator sequence, and a total of I m m-operator sequences are generated; A2. Selecting an optimal m-operator sequence; A2-1. For each m-operator sequence: using the current operator sequence to perform sequential logic optimization on the input circuit to obtain an optimized circuit of the sequence, and calculating an index parameter of the circuit; A2-2. Selecting the sequence with the largest index parameter as the optimal m-operator sequence, and recording the optimized circuit of the sequence as the current target circuit; A2-3. Adding each optimization operator in the optimal m-operator sequence to the optimization operator sequence R in sequence order; A3. Generating a local n-operator sequence group; A3-1. Randomly arranging the optimization operators in the logic synthesis optimization operator set W to generate an operator sequence with a length of n, recording the n-operator sequence as an n-operator sequence, and saving all generated n-operator sequences in an operator sequence set B; A3-2. For each optimization operator in the logical synthesis optimization operator set W, do: For the i-th optimization operator w i , randomly select k operator sequences from the operator sequence set B, modify the first optimization operator of each operator sequence to w i , and form a group of the modified k operator sequences, denoted as the i-th group of n-operator sequence groups, denoted as C i ; A4. Selecting an optimal n-operator sequence; A4-1. For each operator sequence group: using each operator sequence in the group to perform sequential logic optimization on the current target circuit to obtain an optimized circuit of the sequence, and calculating an index parameter of the circuit; calculating the average value of the index parameters of the operator sequences in the group, and recording the average index parameter of the operator sequence group as an average index parameter; A4-2. Selecting the operator sequence group with the largest average index parameter as the optimal operator sequence group, selecting the operator sequence with the largest index parameter in the group as the current optimal n-operator sequence, and updating the optimized circuit of the sequence as the current target circuit; A4-3. Adding each optimization operator in the current optimal n-operator sequence to the optimization operator sequence R in sequence order; A5. Determining whether the sequence length meets the requirements: if the length of the optimization operator sequence R is less than the set sequence length, proceeding to step A3, otherwise, outputting the optimization operator sequence R.

2. The method of claim 1, wherein the generating the sequence of logic synthesis optimization operators comprises: In step A2-1, the process of sequential logic optimization is as follows: A2-1-1. Using the first operator of the operator sequence to perform logic optimization on the current circuit to obtain an optimized circuit; A2-1-2. In sequence order, sequentially performing the subsequent operators to perform a group of continuous logic optimization on the circuit, each operator acting on the circuit optimized by the previous operator, until all operators in the sequence are executed, to obtain the optimized circuit of the operator sequence.

3. The method of claim 1, wherein the generating the sequence of logic synthesis optimization operators comprises: generating a sequence of logic synthesis optimization operators based on the sequence of logic synthesis optimization operators and the sequence of logic synthesis optimization operators. In step A1, the sequence length m of the m-operator sequence ranges from 1 to 5.

4. The method of claim 1, wherein the generating the sequence of logic synthesis optimization operators comprises: generating a sequence of logic synthesis optimization operators based on the sequence of logic synthesis optimization operators and the sequence of logic synthesis optimization operators. In step A3-1, the sequence length n of the n-operator sequence ranges from 3 to 15.

5. The method of claim 1, wherein the generating the sequence of logic synthesis optimization operators comprises: generating a sequence of logic synthesis optimization operators based on the sequence of logic synthesis optimization operators and the sequence of logic synthesis optimization operators. In step A3-2, the value of the operator sequence search number k ranges from 10 to 100.

Images