Model-based chip debugging system

Abstract

The invention relates to the technical field of chip verification, in particular to a model-based chip debugging system, which is newly added with a virtual module, the virtual module only needs to realize the functions of part of hardware modules without specifically abstracting the interface definition of the hardware modules, and the hardware modules are debugged according to the target hierarchy corresponding to the target debugging information. The chip debugging model is formed through the hardware module of which the first module level is smaller than or equal to the target level and the virtual module of which the second module level is equal to the target level, so that the debugging efficiency by using the chip debugging model is improved on the premise of meeting the function accuracy of the chip debugging model, namely, the chip debugging efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip debugging, and in particular to a model-based chip debugging system. Background Art

[0002] In the scenarios of chip design and verification, Cmodel can refer to a model written in C language or C++ language. Cmodel can be used to quickly model and verify the functions and behaviors of a chip in the early stage of chip design, and can also serve as a bridge between hardware and software during the chip design process. This enables software development and debugging to be carried out based on Cmodel even before the hardware is fully implemented, thereby verifying in advance the interfaces and interaction logics between software and hardware. Moreover, by modeling the key functional modules of the chip in Cmodel, it is convenient to evaluate and compare the performances of different algorithm implementations and architecture designs, providing a basis for chip optimization.

[0003] In the prior art, the expected behaviors of all hardware modules are usually described in C language or C++ language, and it is necessary to abstract the interface definitions of each hardware module to support hardware performance verification, module-level co-simulation, etc. However, describing all hardware modules will result in poor debugging efficiency of Cmodel and is difficult to meet the high-speed requirements of software for chip debugging.

[0004] Therefore, how to improve the efficiency of chip debugging has become an urgent problem to be solved. Summary of the Invention

[0005] For the above technical problems, the technical solution adopted by the present invention is as follows: A model-based chip debugging system, the system includes: M hardware modules {a 1 , a 2 , …, a m , …, a M}, N virtual modules {b 1 , b 2 , …, b n , …, b N}, a processor, and a memory storing a computer program, where a m is the m-th hardware module, m is an integer within the range of [1, M], b n is the n-th virtual module, n is an integer within the range of [1, N], the hardware modules correspond to the first module level, the virtual modules correspond to the second module level, and when the computer program is executed by the processor, the following steps are implemented: S101, obtaining target debugging information, and determining a target level d according to the target debugging information.

[0006] S102. Form a chip debugging model with all hardware modules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d.

[0007] S103. Use the chip debugging model to debug the target debugging information.

[0008] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solution, a model-based chip debugging system provided by the present invention can achieve considerable technological progressiveness and practicality, and has wide industrial utilization value. It has at least the following beneficial effects: The present invention provides a model-based chip debugging system, and the system includes: M hardware modules {a 1 , a 2 , …, a m , …, a M}, N virtual modules {b 1 , b 2 , …, b n , …, b N}, a processor, and a memory storing a computer program. Among them, a m is the m-th hardware module, m is an integer within the range of [1, M], b n is the n-th virtual module, n is an integer within the range of [1, N]. The hardware module corresponds to the first module level, and the virtual module corresponds to the second module level. When the computer program is executed by the processor, the following steps are implemented: S101. Obtain target debugging information, and determine the target level d according to the target debugging information. S102. Form a chip debugging model with all hardware modules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d. S103. Use the chip debugging model to debug the target debugging information.

[0009] It can be seen that for the newly added virtual module, the virtual module only needs to implement the functions of some hardware modules, without specifically abstracting the interface definition of the hardware module. According to the target level corresponding to the target debugging information, a chip debugging model is formed by the hardware modules whose first module level is less than or equal to the target level and the virtual modules whose second module level is equal to the target level. Thus, on the premise of meeting the functional accuracy of the chip debugging model, the efficiency of debugging using the chip debugging model is improved, that is, the efficiency of chip debugging is improved. Description of the Drawings

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0011] Figure 1 It is a schematic flowchart of a computer program when executed by a processor in a model-based chip debugging system provided by an embodiment of the present invention. Specific embodiments

[0012] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0013] This embodiment provides a model-based chip debugging system. Refer to Figure 1 It is a schematic flowchart of a computer program when executed by a processor in a model-based chip debugging system provided by an embodiment of the present invention. The system includes: M hardware modules {a 1 a 2 …, a m …, a M}, N virtual modules {b 1 b 2 …, b n …, b N}, a processor, and a memory storing a computer program. Among them, a m is the mth hardware module, m is an integer within the range of [1, M], b n is the nth virtual module, n is an integer within the range of [1, N]. The hardware module corresponds to the first module level, and the virtual module corresponds to the second module level. When the computer program is executed by the processor, the following steps are implemented: S101, obtain target debugging information, and determine the target level d according to the target debugging information; S102, form a chip debugging model from all hardware modules with the first module level less than or equal to d and virtual modules with the second module level equal to d; S103, use the chip debugging model to debug the target debugging information.

[0014] Among them, both the hardware module and the virtual module are implemented in C language or C++ language, rather than physical modules. The hardware module corresponds to the first module level. The first module levels corresponding to different hardware modules can be different or the same. When the first module levels corresponding to different hardware modules are the same, it means that different hardware modules belong to the same module level.

[0015] The virtual module corresponds to the second module level, and the second module levels corresponding to different virtual modules are different.

[0016] The target debugging information can refer to the debugging content that the software needs to execute through the chip debugging model. Different target debugging information may correspond to different target levels. The implementer can pre-record the module levels corresponding to various types of target debugging information. After receiving the target debugging information provided by the software, determine the module level corresponding to the target debugging information as the target level.

[0017] Specifically, in this embodiment, the value ranges of the first module level, the second module level, and the target level can all be [0, K], so that the first module level or the second module level can be directly compared with the target level to determine the eligible hardware module and virtual module.

[0018] In a specific implementation manner, the virtual module with the second module level equal to d corresponds to all hardware modules with the first module level greater than d.

[0019] Among them, the functions implemented by the virtual module with the second module level equal to d are the same as the functions implemented by all hardware modules with the first module level greater than d, thus ensuring the functional accuracy of the chip debugging model.

[0020] Specifically, for a hardware module, the functional implementation of the hardware module can be included in several virtual modules.

[0021] In a specific implementation manner, the first module level and the second module level both belong to the reference level set, and the reference level set includes K + 1 reference levels, where K is a positive integer.

[0022] Among them, in this embodiment, the value range of the reference level can be [0, K]. Correspondingly, the value ranges of the first module level and the second module level can both be [0, K].

[0023] In a specific implementation manner, the M hardware modules correspond to the target chip, and the target chip includes a cache with I cache levels, where I is a positive integer; I and K satisfy the condition: K = I + 1.

[0024] Among them, the M hardware modules may refer to the implementation of the functions of each module in the target chip. The target chip may include caches with I cache levels. For example, the memory in the DPC unit, the L1 cache in the DPC unit, the L2 cache in the chip, etc. respectively correspond to different cache levels, and the cache level can characterize the complexity of accessing the corresponding cache from software.

[0025] Specifically, in this embodiment, each cache level corresponds to a reference level respectively, and the value range of the reference levels corresponding to the I cache levels is [1, I].

[0026] I and K satisfy the condition: K = I + 1, that is, among the K + 1 reference levels, the first reference level is 0, and the second reference level to the (K + 1)-th reference level are 1 to I in sequence.

[0027] In a specific implementation manner, for any hardware module, if the hardware module belongs to the functional layer in the target chip, the first module level corresponding to the hardware module is the first reference level in the reference level set; if the hardware module does not belong to the functional layer in the target chip, the cache level corresponding to the cache that the hardware module can directly access is used as the reference level corresponding to the hardware module.

[0028] Among them, the functional layer may include modules with actual functions.

[0029] Specifically, if the hardware module belongs to the functional layer, the first module level corresponding to the hardware module is the first reference level in the reference level set, that is, the reference level corresponding to the hardware module is 0; if the hardware module does not belong to the functional layer in the chip, the cache level corresponding to the cache that the hardware module can directly access is used as the reference level corresponding to the hardware module. For example, the hardware module can directly access the L2 cache. In this embodiment, the cache level of the L2 cache is 3, so the reference level corresponding to the hardware module is 3.

[0030] In a specific implementation manner, the hardware module includes several sub-modules, and the sub-modules correspond to the first module level.

[0031] Among them, any hardware module may include multiple sub-modules, and the first module levels corresponding to the respective sub-modules included in the same hardware module may be different.

[0032] In a specific implementation manner, the chip debugging model formed by all hardware modules with the first module level less than or equal to d and virtual modules with the second module level equal to d includes: A chip debugging model is formed by all sub-modules with the first module level less than or equal to d and virtual modules with the second module level equal to d, where the virtual modules with the second module level equal to d correspond to all sub-modules with the first module level greater than d.

[0033] In this embodiment, a chip debugging model is formed by all sub-modules with the first module level less than or equal to d and virtual modules with the second module level equal to d. Among them, the virtual modules with the second module level equal to d correspond to all sub-modules with the first module level greater than d, thereby improving the fine granularity of the chip debugging model formed by hardware modules and virtual modules, and further improving the efficiency of chip debugging.

[0034] In a specific implementation manner, the virtual module is implemented in C language.

[0035] Among them, the virtual module can also be implemented in C++ language.

[0036] It can be seen that in this embodiment, new virtual modules are added. The virtual modules only need to implement the functions of some hardware modules, without specifically abstracting the interface definitions of the hardware modules. According to the target level corresponding to the target debugging information, a chip debugging model is formed by hardware modules with the first module level less than or equal to the target level and virtual modules with the second module level equal to the target level. Thus, on the premise of meeting the functional accuracy of the chip debugging model, the efficiency of debugging using the chip debugging model is improved, that is, the efficiency of chip debugging is improved.

[0037] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present invention. The scope disclosed by the present invention is defined by the appended claims.

Claims

1. A model-based chip debugging system, characterized in that: The system includes: M hardware modules {a1, a2, ..., a m , …, a M }, N virtual modules {b1, b2, ..., b n , …, b N }, a processor and a memory storing a computer program, wherein a m is the mth hardware module, m is an integer in the range [1, M], b n is the nth virtual module, n is an integer in the range of [1, N], the hardware module corresponds to the first module level, the virtual module corresponds to the second module level, and when the computer program is executed by a processor, the following steps are implemented: S101, obtaining target debugging information, and determining a target level d according to the target debugging information; S102, forming a chip debugging model by all hardware modules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d; S103: Use the chip debugging model to debug the target debugging information.

2. The model-based chip debugging system according to claim 1, characterized in that: The virtual modules whose second module level is equal to d correspond to all the hardware modules whose first module level is greater than d.

3. The model-based chip debugging system according to claim 1, characterized in that: The first module level and the second module level both belong to a reference level set, and the reference level set includes K+1 reference levels, where K is a positive integer.

4. The model-based chip debugging system according to claim 3, characterized in that: The M hardware modules correspond to a target chip, and the target chip includes a cache with I cache levels, where I is a positive integer; I and K satisfy the condition: K=I+1.

5. The model-based chip debugging system according to claim 4, characterized in that: For any hardware module, if the hardware module belongs to a functional layer in the target chip, the first module level corresponding to the hardware module is the first reference level in the reference level set; If the hardware module does not belong to the functional layer in the target chip, the cache level number corresponding to the cache that the hardware module can directly access is used as the reference level corresponding to the hardware module.

6. The model-based chip debugging system according to claim 1, characterized in that: The hardware module includes several sub-modules, and the sub-modules correspond to the first module level.

7. The model-based chip debugging system according to claim 6, characterized in that: The chip debugging model is formed by all hardware modules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d, including: A chip debugging model is formed by all submodules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d, wherein the virtual modules whose second module level is equal to d correspond to all submodules whose first module level is greater than d.

8. The model-based chip debugging system according to claim 1, characterized in that: The virtual module is implemented by C language.

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