Method for extracting six-end model of NMOS device with DNW isolation structure

Abstract

The invention provides a method for extracting a six-end model of an NMOS device with a DNW isolation structure. The method comprises the following steps: designing an NMOS device structure; measuring the NMOS structure to obtain electrical test parameters; establishing an initial NMOS (N-channel Metal Oxide Semiconductor) model; performing curve fitting for the first time; judging whether curve fitting is qualified or not; if yes, establishing a mismatch model of the NMOS structure; designing DNW structures with different sizes; measuring a C-V curve and an I-V curve of the parasitic diode; establishing an initial diode model; performing secondary curve fitting; judging whether curve fitting is qualified or not; and if yes, obtaining a voltage value, current value and capacitance value mismatch model of the six-end NMOS structure with the DNW isolation structure, and verifying the voltage value, current value and capacitance value mismatch model. According to the method, the area and perimeter of the parasitic diode are extracted through the LVS to establish the initial diode model, so that the model characteristic difference caused by the layout difference is accurately reflected, and the accuracy of the device model is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a method for extracting a six-terminal model of an NMOS device with a DNW isolation structure. Background Art

[0002] There are two types of NMOS (N-Metal-Oxide-Semiconductor) devices, one with isolation and the other without isolation. Since the digital circuit part has high noise and the analog circuit part is relatively sensitive, in order to prevent the noise from interfering with the analog circuit, usually a ring of N-well is connected to the power supply around the analog circuit, and then a ring of P-substrate is grounded outside to perform isolation in turn. If the noise still has a relatively large impact during post-layout simulation and the area allows, several more rings of N-well connected to the power supply and P-substrate grounded can be set, and they can be arranged alternately.

[0003] In the traditional CMOS process, NMOS devices are formed in a P-well or substrate connected to the ground, and substrate noise caused by minority carrier injection into the substrate and well can be collected by using guard rings. However, one problem is that the capacitive coupling of noise from the well to the substrate means that more noise reaches the power supply. In digital circuits, since logic gates have relatively high noise immunity, this is usually not a problem. However, in analog designs, such as 12-bit ADC (Analog-to-Digital Converter), noise can be a serious problem. Various techniques can be used to minimize this noise, such as by keeping analog devices around the guard ring, or using separate power supplies for the substrate / well. However, the guard ring alone cannot prevent noise coupling deep in the substrate, only surface current can be prevented. Another problem is that it is impossible to isolate NMOS devices. Therefore, relatively noisy digital logic cannot be completely isolated from the more sensitive analog area.

[0004] One solution is to isolate NMOS devices by using an additional well, namely: "Deep N-well" (DNW). In this case, the deep N-well is formed by high-energy ion implantation to provide a peak impurity concentration deep enough so as not to affect the performance of NMOS devices. The connection to the deep N-well is formed by an N-well ring connected to VDD. The deep N-well has the effect of reducing noise coupling through it to the substrate and has the advantage of completely isolating NMOS devices. In mixed-signal designs, using deep N-well devices can significantly reduce noise coupling between sensitive analog areas and noisy digital areas.

[0005] Due to the wide application of isolation structures in MOS devices (especially NMOS devices), circuit design engineers need to continuously improve device structures to improve the accuracy of isolation structure models. Summary of the Invention

[0006] The object of the present invention is to provide a method for extracting a six-terminal model of an NMOS device with a DNW isolation structure, which has better isolation effect, can better reduce the influence of noise, and improves the accuracy of the device model.

[0007] To solve the above technical problems, the present invention provides a method for extracting a six-terminal model of an NMOS device with a DNW isolation structure, including the following steps: Design NMOS structures with different sizes; Measure the NMOS structures to obtain electrical test parameters; Establish an initial NMOS model according to the obtained electrical test parameters; Change the characteristic parameters of the NMOS structure to perform the first curve fitting on the electrical test parameters; Judge whether the first curve fitting is qualified. If not, modify the characteristic parameters of the NMOS structure and return to the previous step; If it is qualified, establish a mismatch model of the NMOS structure; Design DNW structures with different sizes; Measure the C-V curve and I-V curve of the parasitic diodes between the DNW and the substrate and between the DNW and the pwell; Extract the area and perimeter of the parasitic diodes through LVS to establish an initial diode model; Change the characteristic parameters of the diodes to perform the second curve fitting on the voltage value, current value and capacitance value; Judge whether the second curve fitting is qualified. If not, modify the relevant characteristic parameters of the DNW structure and return to the previous step; If it is qualified, obtain the voltage value, current value and capacitance value mismatch model of the six-terminal NMOS structure with a DNW isolation structure, and verify the mismatch model.

[0008] Optionally, the characteristic parameters of the NMOS structure include size, threshold voltage and temperature; the electrical test parameters include voltage value and current value.

[0009] Optionally, the method for judging whether the first curve fitting is qualified includes: judging the offset of the voltage value and current value of the NMOS structure obtained by measurement from the voltage value and current value obtained according to the initial NMOS model. If the offset is greater than or equal to 10%, the fitting is unqualified; if the offset is less than 10%, the fitting is qualified.

[0010] Optionally, the relevant characteristic parameters of the diodes include size, threshold voltage and temperature.

[0011] Optionally, the initial diode model is: *pwell to dnw d1 is connected to dnw, with d_5_pwdnw_2t area = area_pwdnw and pj = pj_pwdnw *dnw to psub d2 connects psub to dnw, with d_5_dnpwpsub_2t area = area_dnwpsub and pj = pj_dnwpsub; Among them, area_pwdnw represents the total area of the pwell, pj_pwdnw represents the total perimeter of the pwell, area_dnwpsub represents the total area of the dnwell, pj_dnwpsub represents the total perimeter of the dnwell, dnw is the deep n-well, pwell is the p-well, dnwell is the deep n-well surrounding the p-well, and psub is the p-substrate.

[0012] Optionally, the method for determining whether the second curve fitting is qualified includes: determining the offsets of the voltage value, current value, and capacitance value of the diode obtained by measurement from the voltage value, current value, and capacitance value obtained according to the initial diode model. If the offset is greater than or equal to 10%, the fitting is unqualified; if the difference is less than 10%, the fitting is qualified.

[0013] Optionally, the method for verifying the mismatch model includes: Obtaining the first mismatch rate through simulation according to the voltage value, current value, and capacitance value mismatch model of the six-terminal NMOS structure with a DNW isolation structure; obtaining the second mismatch rate of the voltage value, current value, and capacitance value of the six-terminal NMOS structure with a DNW isolation structure through measurement; Modifying the parameters related to the NMOS structure and the parameters related to the size of the NMOS device isolation structure according to the difference between the second mismatch rate and the first mismatch rate.

[0014] Optionally, the method for extracting the area and perimeter of the parasitic diode through LVS includes: extracting the X / Y direction distances from the pwell to the active region through LVS; the method for extracting the X / Y direction distances from the pwell to the active region through LVS includes: Finding the vertical side A1 of the active region; Finding the horizontal side A2 of the active region; Calculating the horizontal distance between the vertical side of the pwell and the vertical side A1 of the active region, and assigning it to the A1 side; Calculating the vertical distance between the horizontal side of the pwell and the horizontal side A2 of the active region, and assigning it to the A2 side; Statistically analyze the horizontal distance vectors X1n / X2n, assign them to the GATE auxiliary layer A3, and obtain the horizontal distance parameters from the pwell to the vertical edges A1 of each section of the active region; Statistically analyze the vertical distance vectors Y1n / Y2n, assign them to the GATE auxiliary layer A4, and obtain the vertical distance parameters from the pwell to the horizontal edges A2 of each section of the active region; Assign the calculated horizontal and vertical distance vector values to the GATE auxiliary layer A5 (X1n / X2n / Y1n / Y2n); Calculate the weighted average values (X1 / X2 / Y1 / Y2).

[0015] Optionally, the method for extracting the area and perimeter of parasitic diodes through LVS further includes: extracting the X / Y direction distances from the DNW to the active region through LVS; the method for extracting the X / Y direction distances from the DNW to the active region through LVS is the same as the method for extracting the X / Y direction distances from the pwell to the active region through LVS.

[0016] Optionally, the voltage value, current value, and capacitance value mismatch model of the six-terminal NMOS structure with a DNW isolation structure includes: .subckt m_n5_iso_6t_ckt d g s b dnw psub w=10e-6 l=0.5e-6 nf=1 mr=1dtemp=0 sa=1.238E-6 sb=1.238E-6 sd=4.66e-7 sca=0 scb=0 scc=0 mismod=1 .param + X1 = 15 + X2 = 15 + Y1 = 6 + Y2 = 6 + Xdn1 = 4 + Xdn2 = 4 + Ydn1 = 4 + Ydn2 = 4 + wf = ‘w / nf‘ + Lpwell = ‘(nf-1)*sd+l*nf+sa+sb+X1+X2’ + Wpwell = ‘wf+Y1+Y2’ + Ldnwell = ‘(nf-1)*sd+l*nf+sa+sb+X1+X2+Xdn1+Xdn2’ + Wdnwell = ‘wf+Y1+Y2+Ydn1+Ydn2‘ + area_pwdnw = ’Lpwell*Wpwell’ + pj_pwdnw = '(Lpwell+Wpwell)*2‘ + area_dnwpsub = 'Ldnwell*Wdnwell' + pj_dnwpsub = '(Ldnwell+Wdnwell)*2' *pwell to dnw d1 b dnw d_5_pwdnw_2t area=area_pwdnw pj=pj_pwdnw *dnw to psub d2 psub dnw d_5_dnpwpsub_2t area=area_dnwpsub pj=pj_dnwpsub .ends m_n5_iso_6t_ckt Among them, l represents the length of the gate, nf represents the number of gates, sd represents the distance between the gates, wf represents the width of the active region, sa represents the distance between the edge of the right active region and the gate, sb represents the distance between the edge of the left active region and the gate, X1 and X2 represent the X-direction distance from pwell to the active region, Y1 and Y2 represent the Y-direction distance from pwell to the active region, Xdn1 and Xdn2 represent the X-direction distance from pwell to psub, Ydn1 and Ydn2 represent the Y-direction distance from pwell to psub, Lpwell represents the total length of pwell, Wpwell represents the total width of pwell, Ldnwell represents the total length of dnwell, Wdnwell represents the total width of dnwell, area_pwdnw represents the total area of pwell, pj_pwdnw represents the total perimeter of pwell, area_dnwpsub represents the total area of dnwell, pj_dnwpsub represents the total perimeter of dnwell, dnw is the deep n-well, pwell is the p-well, dnwell is the deep n-well surrounding the p-well, and psub is the p-substrate.

[0017] Compared with the prior art, in the method for extracting the six-terminal model of the NMOS device with a DNW isolation structure provided by the present invention, the area and perimeter of the parasitic diode are extracted through LVS to establish an initial diode model. Utilizing the advantage of the LVS tool itself in accurately extracting the characteristic dimensions of the parasitic diode, the actual object dimensions in the layout are fed back for model calculation. The extracted values are consistent with the actual layout dimensions, so that the actual dimensions in the layout can be used as input items for model calculation, thereby accurately reflecting the differences in model characteristics caused by layout differences and improving the accuracy of the device model. In addition, due to the addition of two parasitic diodes between the DNW and the pwell and between the DNW and the Psub, the six-terminal model of the NMOS device can better and more accurately reflect the device characteristics of the NMOS after adding DNW isolation. Description of the Drawings

[0018] Figure 1 is the design layout of the NMOS with a DNW isolation structure.

[0019] Figure 2 is the flowchart of the method for extracting the six-terminal model of the NMOS device with a DNW isolation structure provided in an embodiment of the present invention. Detailed Embodiments

[0020] To make the objectives, advantages, and features of the present invention clearer, the following further describes the present invention in detail with reference to the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and not drawn to scale, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structures. In particular, the emphasis that each drawing needs to show is different, and sometimes different scales are used.

[0021] As used in the present invention, the singular forms "a", "an", and "the" include plural objects unless the context clearly indicates otherwise. As used in the present invention, the term "or" is generally used in the sense of including "and / or" unless the context clearly indicates otherwise. As used in the present invention, the term "several" is generally used in the sense of including "at least one" unless the context clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in the sense of including "two or more" unless the context clearly indicates otherwise. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", and "third" may explicitly or implicitly include one or at least two of such features unless the context clearly indicates otherwise.

[0022] The NMOS with DNW isolation structure adds a parasitic diode on the basis of the NMOS device without the isolation structure. Figure 1 The following is the design layout of the NMOS with DNW isolation structure. Please refer to Figure 1 As shown, the first parasitic diode is from pwell (p-well) to dnwell (abbreviated as dnw or DNW, deep n-well), and the second parasitic diode is from dnwell to psub (p-substrate). It mainly plays a role in isolating noise and generally has no impact on the performance of the main device. When modeling the NMOS device with DNW isolation structure, on the NMOS model without DNW, just attach the DNW parasitic diode, that is: write the area (area) and perimeter (pj) of the first diode as relevant formulas related to wf, l, sa, sb, nf, ds, and the distance from pwell to the AA package, and write the area (area) and perimeter (pj) of the second diode as relevant formulas related to pwell area pj and the distance from dnwell to the pwell package.

[0023] Exemplarily, please refer to Figure 1 As shown, pwell is the p-well, dnwell is the deep n-well surrounding the p-well (which can also be abbreviated as DNW), psub is the p-substrate, l represents the length of the gate, nf represents the number of gates, sd represents the distance between the gates, and multiple dummy gates are also provided on both sides of the gate. Figure 1 There are 5 gates shown in it, and 3 dummy gates are provided on each side of the gate. Of course, it is not limited to this. wf represents the width of the active area (AA), X1 and X2 represent the X-direction distance from pwell to the active area, Y1 and Y2 represent the Y-direction distance from pwell to the active area, Xdn1 and Xdn2 represent the X-direction distance from pwell to psub, and Ydn1 and Ydn2 represent the Y-direction distance from pwell to psub.

[0024] In the parasitic diode pwell_dnw between pwell and dnwell, the total length Lpwell of pwell is: (nf - 1)*sd + l*nf + sa + sb + X1 + X2, the total width Wpwell of pwell is: wf + Y1 + Y2, the total area area_pwdnw of pwell is: Lpwell * Wpwell, and the total perimeter pj_pwdnw of pwell is: (Lpwell + Wpwell)*2.

[0025] In the parasitic diode dnw_psub between dnwell and psub, the total length Ldnwell of dnwell is: (nf - 1)*sd + l*nf + sa + sb + X1 + X2 + Xdn1 + Xdn2, the total width Wdnwell of dnwell is: wf + Y1 + Y2 + Ydn1 + Ydn2, the total area area_dnwpsub of dnwell is: Ldnwell * Wdnwell, and the total perimeter pj_dnwpsub of dnwell is: (Ldnwell + Wdnwell) * 2.

[0026] For the above two parasitic diodes, the present invention provides a method for extracting a six-terminal model of an NMOS device with a DNW isolation structure. Figure 2 It is a flowchart of a method for extracting a six-terminal model of an NMOS device with a DNW isolation structure provided in an embodiment of the present invention. Please refer to Figure 2 As shown, the method for extracting a six-terminal model of an NMOS device with a DNW isolation structure provided in this embodiment includes the following steps: Design NMOS structures with different sizes; Measure the NMOS structures to obtain electrical test parameters; Establish an initial NMOS model according to the electrical test parameters; Change the characteristic parameters of the NMOS structure to perform the first curve fitting on the electrical test parameters; Judge whether the first curve fitting is qualified. If not, modify the characteristic parameters of the NMOS structure and return to the previous step; If it is qualified, establish a mismatch model of the NMOS structure; Design DNW structures with different sizes; Measure the C-V curves and I-V curves of the parasitic diodes between DNW and Psub and between DNW and pwell; Extract the area and perimeter of the parasitic diodes through LVS to establish an initial diode model; Change the characteristic parameters of the diodes to perform the second curve fitting on the voltage values, current values, and capacitance values; Judge whether the second curve fitting is qualified. If not, modify the relevant characteristic parameters of the DNW structure and return to the previous step; If it is qualified, obtain the voltage value, current value, and capacitance value mismatch models of the six-terminal NMOS structure with a DNW isolation structure, and verify the mismatch models.

[0027] In this embodiment, first, NMOS structures with different sizes are designed, and then the electrical parameters of the NMOS structures are measured, that is, the electrical test parameters of the NMOS structures with all the sizes designed in the previous step are obtained. In this embodiment, the electrical parameters of the NMOS structures are measured under different sizes, threshold voltages or temperatures, and the electrical test parameters include but are not limited to voltage values and current values. Then, an initial NMOS model is established according to the electrical test parameters.

[0028] Then, the characteristic parameters of the NMOS structure are changed to perform the first curve fitting on the electrical test parameters. In this embodiment, the characteristic parameters of the NMOS structure include size, threshold voltage and temperature, that is, the size, threshold voltage and temperature of the NMOS structure are changed to perform the first curve fitting on the voltage value and the current value. Then, it is judged whether the first curve fitting is qualified, that is, it is judged whether the above fitting is qualified. If it is not qualified, the characteristic parameters of the NMOS structure are modified, and the previous step is returned, that is, the step of "changing the characteristic parameters of the NMOS structure to perform curve fitting on the electrical test parameters to obtain the first fitting curve" is returned. If it is qualified, a mismatch model of the NMOS structure is established, for example, a voltage-current mismatch model of the NMOS structure is established. In one embodiment, the method for judging whether the second curve fitting is qualified includes: judging the offset between the voltage value and the current value of the NMOS structure obtained by measurement and the voltage value and the current value obtained according to the initial NMOS model. If the offset is greater than or equal to 10%, the fitting is unqualified. If the offset is less than 10%, the fitting is qualified. In this embodiment, the voltage value and the current value of the initial NMOS model are obtained through simulation.

[0029] Next, DNW structures with different sizes (i.e., the above-mentioned dnwell) are designed, and the C-V curves and I-V curves of the parasitic diodes between the DNW and the Psub and between the DNW and the pwell are measured.

[0030] Then, the area and perimeter of the parasitic diode are extracted through LVS (Layout Versus Schematics) to establish an initial diode model. In this embodiment, the method for extracting the area and perimeter of the parasitic diode through LVS includes: extracting the X / Y direction distance from the pwell to the active region through LVS; the method for extracting the X / Y direction distance from the pwell to the active region through LVS includes: Find the vertical side A1 of the GATE active region: ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient = COINCIDENT EDGEntgate_no_mis; Find the horizontal side A2 of the GATE active region: nsdntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient=NOT COINCIDENTEDGE ntgate_no_mis; Calculate the horizontal distance between the vertical edge of pwell and the vertical edge A1 of the active region, and assign it to the A1 edge: nsdntgate_no_mis__pwell__enc__TVF_tmp_1.side_enclosure.dfmspace = DFMSPACE ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient pwell <= 10 BY ENC BYLAYER pwell COUNT == 0; Calculate the vertical distance between the horizontal edge of pwell and the horizontal edge A2 of the active region, and assign it to the A2 edge: ntgate_no_mis__pwell__enc__TVF_tmp_1.end_enclosure.dfmspace = DFMSPACE ntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient pwell <= 10 BY ENC BYLAYER pwell COUNT == 0; Statistical horizontal distance vectors X1n / X2n, assign them to the GATE auxiliary layer A3, and obtain the distance parameters in the horizontal direction from pwell to the vertical edges A1 of each section of the active region: ntgate_no_mis__pwell__enc__TVF_tmp_1.side = DFM PROPERTY ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient ntgate_no_mis__pwell__enc__TVF_tmp_1.side_enclosure.dfmspace OVERLAP ABUT ALSO MULTI [PER=RANGE_XXY( SORT_MERGE_XXY( CONCAT( VECTOR(ECMIN(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_enclosure.dfmspace), ECMAX(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_enclosure.dfmspace),EW(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_enclosure.dfmspace)+0), VECTOR(ECMIN(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient),ECMAX(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient),10))), VECTOR(ECMIN(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient),ECMAX(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient)) )]; Statistically analyze the vertical distance vectors Y1n / Y2n, assign them to the GATE auxiliary layer A4, and obtain the vertical distance parameters from pwell to the horizontal sides A2 of each active region segment: ntgate_no_mis__pwell__enc__TVF_tmp_1.end=DFM PROPERTY ntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient ntgate_no_mis__pwell__enc__TVF_tmp_1.end_enclosure.dfmspace OVERLAP ABUT ALSO MULTI [ PAR = RANGE_XXY( SORT_MERGE_XXY(CONCAT(VECTOR(ECMIN(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_enclosure.dfmspace), ECMAX(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_enclosure.dfmspace), EW(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_enclosure.dfmspace)+0), VECTOR(ECMIN(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient).ECMAX(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient), 10))), VECTOR(ECMIN(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient), ECMAX(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient)) ]; Assign the calculated horizontal and vertical distance vector values to the GATE auxiliary layer A5 (X1n / X2n / Y1n / Y2n): nsgate15_wpe = DFM PROPERTY ntgate_no_mis ntgate_no_mis__pwell__enc__TVF_tmp_1.side ntgate_no_mis__pwell__enc__TVF_tmp_1.end OVERLAP ABUT ALSO [PER_1 = VPROPERTY( ntgate_no_mis__pwell__enc__TVF_tmp_1.side, PER,1 ) ] [PER_2 = VPROPERTY( ntgate_no_mis__pwell__enc__TVF_tmp_1.side, PER, 2) ] [PAR_1 = VPROPERTY( ntgate_no_mis__pwell__enc__TVF_tmp_1.end, PAR, 1) ] [ PAR_2 = VPROPERTY( ntgate_no_mis__pwell__enc__TVF_tmp_1.end, PAR, 2) ] Calculate the weighted average (X2 / X2 / Y1 / Y2): proc calc_sca_dfm { PER_1 PER_2 PAR_1 PAR_2 W L UNITS} { set scale 1.0 set side_1 [ device::dfm_vec_measurements $PER_1 ] set side_2 [ device::dfm_vec_measurements $PER_2 ] set sides [ concat $side_1 $side_2 ] set end_1 [ device::dfm_vec_measurements $PAR_1 ] set end_2 [ device::dfm_vec_measurements $PAR_2 ] set sum [ expr { [ calc_sca_dfm__getsum $sides [$L] [$UNITS] ] + [calc_sca_dfm__getsum $end_1 [$W] [$UNITS] ] + [ calc_sca_dfm__getsum $end_2[$W] [$UNITS] ]} ] return [ expr { $sum / ( [$W] * $scale * [$L] * $scale* 1e12 )} ]}。

[0031] In this embodiment, the method for extracting the area and perimeter of parasitic diodes through LVS further includes: extracting the X / Y direction distances from DNW to the active region through LVS. The same method as above can be used to calculate the X / Y direction distances Xdn1+X1, Xdn2+X2, Ydn1+Y1, and Ydn2+Y2 from DNW to the active region, so as to obtain the areas and perimeters of the parasitic diodes between DNW and Psub and between DNW and pwell.

[0032] In this embodiment, the initial diode model is: *pwell to dnw d1 b dnw d_5_pwdnw_2t area=area_pwdnw pj=pj_pwdnw *dnw to psub d2 psub dnw d_5_dnpwpsub_2t area=area_dnwpsub pj=pj_dnwpsub。

[0033] Then, change the characteristic parameters of the diode to perform a second curve fitting on the voltage value, current value, and capacitance value. In this embodiment, the characteristic parameters of the diode include size, threshold voltage, and temperature. Then, determine whether the second curve fitting is qualified. If it is not qualified, modify the relevant characteristic parameters of the DNW structure and return to the previous step, that is, return to the step of "changing the characteristic parameters of the diode to perform curve fitting on the voltage value, current value, and capacitance value to obtain the second fitting curve". Among them, the method for determining whether the second curve fitting is qualified includes: determining the offset of the voltage value, current value, and capacitance value of the diode obtained by measurement from the voltage value, current value, and capacitance value obtained according to the initial diode model. If the offset is greater than or equal to 10%, the fitting is unqualified; if the difference is less than 10%, the fitting is qualified. In this embodiment, the voltage value, current value, and capacitance value of the initial diode model are obtained through simulation.

[0034] If it is qualified, obtain the voltage value, current value, and capacitance value mismatch model of the six-terminal NMOS structure with the DNW isolation structure, and verify the mismatch model. In this embodiment, the method for verifying the mismatch model includes: obtaining the first mismatch rate through simulation according to the voltage value, current value, and capacitance value mismatch model of the six-terminal NMOS structure with the DNW isolation structure; obtaining the second mismatch rate of the voltage value, current value, and capacitance value of the six-terminal NMOS structure with the DNW isolation structure through measurement; modifying the parameters related to the NMOS structure and the parameters related to the size of the NMOS device isolation structure according to the difference between the second mismatch rate and the first mismatch rate.

[0035] The present invention extracts the area and perimeter of the parasitic diode through LVS to establish an initial diode model, and utilizes the advantage of the LVS tool itself in accurately extracting the characteristic dimensions of the parasitic diode to feedback the actual object dimensions in the layout for model calculation. The extracted values are consistent with the actual dimensions of the layout, so that the actual dimensions in the layout can be used as input items for model calculation, thereby accurately reflecting the model characteristic differences brought about by layout differences and improving the accuracy of the device model.

[0036] In this embodiment, the voltage value, current value, and capacitance value mismatch model of the six-terminal NMOS structure with the DNW isolation structure (i.e., the six-terminal model of the NMOS device with the DNW isolation structure) includes: .subckt m_n5_iso_6t_ckt d g s b dnw psub w=10e-6 l=0.5e-6 nf=1 mr=1 dtemp=0 sa=1.238E-6 sb=1.238E-6 sd=4.66e-7 sca=0 scb=0 scc=0 mismod=1 .param + X1 = 15 + X2 = 15 + Y1 = 6 + Y2 = 6 + Xdn1 = 4 + Xdn2 = 4 + Ydn1 = 4 + Ydn2 = 4 + wf = ‘w / nf‘ + Lpwell = ‘(nf-1)*sd+l*nf+sa+sb+X1+X2’ + Wpwell = ‘wf+Y1+Y2’ + Ldnwell = ‘(nf-1)*sd+l*nf+sa+sb+X1+X2+Xdn1+Xdn2’ + Wdnwell = ‘wf+Y1+Y2+Ydn1+Ydn2‘ + area_pwdnw = ’Lpwell*Wpwell’ + pj_pwdnw = '(Lpwell+Wpwell)*2‘ + area_dnwpsub = 'Ldnwell*Wdnwell' + pj_dnwpsub = '(Ldnwell+Wdnwell)*2' *pwell to dnw d1 b dnw d_5_pwdnw_2t area=area_pwdnw pj=pj_pwdnw *dnw to psub d2 psub dnw d_5_dnpwpsub_2t area=area_dnwpsub pj=pj_dnwpsub .ends m_n5_iso_6t_ckt Wherein, l represents the length of the gate, nf represents the number of gates, sd represents the distance between the gates, wf represents the width of the active region, sa represents the distance between the edge of the right active region and the gate, sb represents the distance between the edge of the left active region and the gate, X1 and X2 represent the X-direction distance from the pwell to the active region, Y1 and Y2 represent the Y-direction distance from the pwell to the active region, Xdn1 and Xdn2 represent the X-direction distance from the pwell to the psub, Ydn1 and Ydn2 represent the Y-direction distance from the pwell to the psub, Lpwell represents the total length of the pwell, Wpwell represents the total width of the pwell, Ldnwell represents the total length of the dnwell, Wdnwell represents the total width of the dnwell, area_pwdnw represents the total area of the pwell, pj_pwdnw represents the total perimeter of the pwell, area_dnwpsub represents the total area of the dnwell, pj_dnwpsub represents the total perimeter of the dnwell, dnw is the deep n-well, pwell is the p-well, dnwell is the deep n-well surrounding the p-well, and psub is the p-substrate.

[0037] In this embodiment, a six-terminal model of the DNW and psub is added to the six-terminal model of the NMOS device with a DNW isolation structure, and the isolation effect is better, which can better reduce the influence of noise. At the same time, due to the addition of two parasitic diodes between the DNW and the pwell and between the DNW and the Psub, the six-terminal model of the NMOS device can better and more accurately reflect the device characteristics of the NMOS after adding DNW isolation, improving the accuracy of the device model.

[0038] In summary, in the extraction method of the six-terminal model of the NMOS device with a DNW isolation structure provided by the present invention, the area and perimeter of the parasitic diode are extracted by LVS to establish an initial diode model. Utilizing the advantage of the LVS tool itself in accurately extracting the characteristic dimensions of the parasitic diode, the actual object dimensions in the layout are fed back for model calculation, and the extracted values are consistent with the actual dimensions of the layout. In this way, the actual dimensions in the layout can be used as input items for model calculation, thereby accurately reflecting the model characteristic differences brought about by the layout differences and improving the accuracy of the device model. In addition, due to the addition of two parasitic diodes between the DNW and the pwell and between the DNW and the Psub, the six-terminal model of the NMOS device can better and more accurately reflect the device characteristics of the NMOS after adding DNW isolation.

[0039] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.

Claims

1. A method for extracting a six-terminal model of an NMOS device with a DNW isolation structure, characterized in that: The following steps are involved: Design NMOS structures of different sizes; Measure NMOS structure to obtain electrical test parameters; Establishing an initial NMOS model according to the electrical test parameters; Changing the characteristic parameters of the NMOS structure to perform the first curve fitting on the electrical test parameters; Determine whether the first curve fitting is qualified. If not, modify the characteristic parameters of the NMOS structure and return to the previous step. If qualified, a mismatch model of the NMOS structure is established; Design DNW structures of different sizes; Measure the CV curve and IV curve of the parasitic diode between DNW and Psub and between DNW and pwell; The initial diode model is established by extracting the area and perimeter of the parasitic diode through LVS; Changing the characteristic parameters of the diode to perform a second curve fitting on the voltage value, current value and capacitance value; Determine whether the second curve fitting is qualified. If not, modify the characteristic parameters of the DNW structure and return to the previous step; If qualified, a mismatch model of voltage, current and capacitance values ​​of the six-terminal NMOS structure with a DNW isolation structure is obtained, and the mismatch model is verified.

2. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, characterized in that: The characteristic parameters of the NMOS structure include size, threshold voltage and temperature; the electrical test parameters include voltage value and current value.

3. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 2, characterized in that: The method for judging whether the first curve fitting is qualified includes: judging the offset between the voltage value and the current value of the NMOS structure obtained by measurement and the voltage value and the current value obtained according to the initial NMOS model; if the offset is greater than or equal to 10%, the fitting is unqualified; if the offset is less than 10%, the fitting is qualified.

4. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, characterized in that: The characteristic parameters of a diode include size, threshold voltage and temperature.

5. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, characterized in that: The initial diode model is: *pwell to dnw d1 b dnw d_5_pwdnw_2t area=area_pwdnw pj=pj_pwdnw *dnw to psub d2 psub dnw d_5_dnpwpsub_2t area=area_dnwpsub pj=pj_dnwpsub; Among them, area_pwdnw represents the total area of ​​pwell, pj_pwdnw represents the total perimeter of pwell, area_dnwpsub represents the total area of ​​dnwell, pj_dnwpsub represents the total perimeter of dnwell, dnw is a deep n-well, pwell is a p-well, dnwell is a deep n-well surrounding the p-well, and psub is a p-substrate.

6. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, characterized in that: The method for judging whether the second curve fitting is qualified includes: judging the offset between the voltage value, current value and capacitance value of the diode obtained by measurement and the voltage value, current value and capacitance value obtained according to the initial diode model; if the offset is greater than or equal to 10%, the fitting is unqualified; if the difference is less than 10%, the fitting is qualified.

7. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, characterized in that: The method for validating the model includes: A first mismatch rate is obtained by simulation according to a mismatch model of voltage value, current value and capacitance value of a six-terminal NMOS structure with a DNW isolation structure; and a second mismatch rate of voltage value, current value and capacitance value of a six-terminal NMOS structure with a DNW isolation structure is obtained by measurement; Parameters related to the NMOS structure and parameters related to the size of the NMOS device isolation structure are modified according to the difference between the second mismatch rate and the first mismatch rate.

8. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, characterized in that: The method of extracting the area and perimeter of the parasitic diode by LVS includes: extracting the distance from the pwell to the active area in the X / Y direction by LVS; The method of extracting the distance from the pwell to the active area in the X / Y direction by LVS includes: Find the vertical edge A1 of the GATE active area; Find the horizontal edge A2 of the GATE active area; Calculate the horizontal distance between the vertical edge of pwell and the vertical edge A1 of the active area, and assign it to the A1 edge; Calculate the vertical distance between the horizontal edge of pwell and the horizontal edge A2 of the active area, and assign it to the A2 edge; Count the horizontal distance vectors X1n / X2n, assign them to the GATE auxiliary layer A3, and obtain the horizontal distance parameters from the pwell to the vertical edges A1 of each active area; Count the vertical distance vectors Y1n / Y2n, assign them to the GATE auxiliary layer A4, and obtain the vertical distance parameters from pwell to the horizontal edges A2 of each active area; Assign the calculated horizontal and vertical distance vector values ​​to the GATE auxiliary layer A5 (X1n / X2n / Y1n / Y2n); Calculates the weighted average (X1 / X2 / Y1 / Y2).

9. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 8, characterized in that: The method of extracting the area and perimeter of the parasitic diode through LVS also includes: extracting the distance from DNW to the active area in the X / Y direction through LVS; the method of extracting the distance from DNW to the active area in the X / Y direction through LVS is the same as the method of extracting the distance from pwell to the active area in the X / Y direction through LVS.

10. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, characterized in that: The voltage, current and capacitance mismatch models of the six-terminal NMOS structure with DNW isolation structure include: .subckt m_n5_iso_6t_ckt dgsb dnw psub w=10e-6 l=0.5e-6 nf=1 mr=1 dtemp=0 sa=1.238E-6 sb=1.238E-6 sd=4.66e-7 sca=0 scb=0 scc=0 mismod=1 .param + X1 = 15 + X2 = 15 + Y1 = 6 + Y2 = 6 + Xdn1 = 4 + Xdn2 = 4 + Ydn1 = 4 + Ydn2 = 4 + wf = 'w / nf' + Lpwell = '(nf-1)*sd+l*nf+sa+sb+X1+X2' + Wpwell = 'wf+Y1+Y2' + Ldnwell = '(nf-1)*sd+l*nf+sa+sb+X1+X2+Xdn1+Xdn2' + Wdnwell = 'wf+Y1+Y2+Ydn1+Ydn2' + area_pwdnw = 'Lpwell*Wpwell' + pj_pwdnw = '(Lpwell+Wpwell)*2' + area_dnwpsub = 'Ldnwell*Wdnwell' + pj_dnwpsub = '(Ldnwell+Wdnwell)*2' *pwell to dnw d1 b dnw d_5_pwdnw_2t area=area_pwdnw pj=pj_pwdnw *dnw to psub d2 psub dnw d_5_dnpwpsub_2t area=area_dnwpsub pj=pj_dnwpsub .ends m_n5_iso_6t_ckt Where l represents the length of the gate, nf represents the number of gates, sd represents the distance between the gates, wf represents the width of the active area, sa represents the distance from the right edge of the active area to the gate, sb represents the distance from the left edge of the active area to the gate, X1 and X2 represent the distance from the pwell to the active area in the X direction, Y1 and Y2 represent the distance from the pwell to the active area in the Y direction, Xdn1 and Xdn2 It represents the distance from pwell to psub in the X direction, Ydn1 and Ydn2 represent the distance from pwell to psub in the Y direction, Lpwell represents the total length of pwell, Wpwell represents the total width of pwell, Ldnwell represents the total length of dnwell, Wdnwell represents the total width of dnwell, area_pwdnw represents the total area of ​​pwell, pj_pwdnw represents the total perimeter of pwell, area_dnwpsub represents the total area of ​​dnwell, pj_dnwpsub represents the total perimeter of dnwell, dnw is a deep n-well, pwell is a p-well, dnwell is a deep n-well surrounding the p-well, and psub is a p-substrate.

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