Clock driving chip, crimping memory module and information processing system

Abstract

The invention provides a clock driving chip of a crimping memory module, the crimping memory module and an information processing system. The crimping memory module comprises N channels, each channel comprises two sub-channels, the clock driving chip comprises 2N phase locking control circuits, the output end of each phase locking control circuit is correspondingly connected with each sub-channel and is used for outputting clock signals to the sub-channels, and N is a positive integer greater than or equal to 2; the input end of the control word state machine is used for receiving clock control signals, the output end of the control word state machine is connected with the 2N phase locking control circuits, and the control word state machine is used for adjusting the output frequency of the phase locking control circuits according to the clock control signals and enabling or forbidding the phase locking control circuits to output corresponding clock signals; the phase locking control circuit comprises a phase-locked loop. According to the embodiment of the invention, the chip volume of the crimping memory module can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and more particularly, to a clock driver chip for a press-fit memory module, a press-fit memory module applying the clock driver chip, and an information processing system including the press-fit memory module. Background Art

[0002] A Compress Attached Memory Module (CAMM) is a high-density memory module. The core technology is to directly connect memory chips to the motherboard by means of press-fitting, so as to achieve higher storage density and performance. Since the press-fit memory module is different from a conventional memory, relevant circuits need to be redesigned.

[0003] Currently, the clock scheme of a Compress Attached Memory Module (CAMM) is to re-drive the clock control signal from the CPU direction to improve the signal integrity of the clock. A memory chip usually includes two channels, each channel includes two sub-channels, and each sub-channel needs to be configured with an independent clock signal, that is, at least four independent clock signals need to be provided. In the conventional design concept, as the number of clock signals increases, the number of corresponding circuits will also increase exponentially, which poses a challenge to the design volume of the press-fit memory module.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present disclosure is to provide a clock driver chip for a press-fit memory module, a press-fit memory module applying the clock driver chip, and an information processing system including the press-fit memory module, which are used to reduce the volume of the press-fit memory module.

[0006] According to a first aspect of the present disclosure, there is provided a clock driver chip for a press-fit memory module. The press-fit memory module includes N channels, and each channel includes two sub-channels. The clock driver chip is characterized in that it includes: 2N phase-locked control circuits, the output end of each phase-locked control circuit is correspondingly connected to each sub-channel for outputting a clock signal to the sub-channel, where N is a positive integer greater than or equal to 2; a control word state machine, the input end is used to receive a clock control signal, and the output end is connected to the 2N phase-locked control circuits. The control word state machine is used to adjust the output frequency of the phase-locked control circuit according to the clock control signal, and enable or disable the phase-locked control circuit to output the corresponding clock signal; wherein, the phase-locked control circuit includes a phase-locked loop.

[0007] In an exemplary embodiment of the present disclosure, the phase-locked control circuit includes: an input buffer for receiving a first initial clock signal and a second initial clock signal corresponding to a sub-channel corresponding to the phase-locked control circuit; a phase-locked loop (PLL) whose input terminal is connected to the output terminal of the input buffer, and whose control terminal is used to receive a PLL control signal from a control word state machine and a reset signal from an external circuit; a multiplexer having a first input terminal, a second input terminal, an output terminal, and a control terminal, where the first input terminal of the multiplexer is connected to the output terminal of the PLL, the second input terminal of the multiplexer is connected to the output terminal of the input buffer, and the control terminal of the multiplexer is used to receive a PLL mode setting signal; a clock tree whose input terminal is connected to the output terminal of the multiplexer, and whose output terminal is used to output a first clock signal and a second clock signal; an output driver having a first input terminal, a second input terminal, an output terminal, and a control terminal, where the first input terminal of the output driver is used to receive the first clock signal, the second input terminal of the output driver is used to receive the second clock signal, and the control terminal of the output driver is used to receive a clock output enable signal from the control word state machine.

[0008] In an exemplary embodiment of the present disclosure, the clock control signal includes a serial clock signal and a serial data signal.

[0009] In an exemplary embodiment of the present disclosure, the frequencies of the clock signals output by each phase-locked control circuit are not exactly the same.

[0010] In an exemplary embodiment of the present disclosure, it further includes N power modules, each power module is controlled to be enabled or disabled through an independent switching element, and each power module is connected to two phase-locked control circuits corresponding to the same channel.

[0011] In an exemplary embodiment of the present disclosure, the power module includes a switching element, the first end of the switching element is connected to a preset power supply, the second end of the switching element is used to supply power to two phase-locked control circuits corresponding to the same channel, and the control end of the switching element is connected to a controller.

[0012] In an exemplary embodiment of the present disclosure, N = 2, or N = 3, or N = 4, or N = 8.

[0013] According to a second aspect of the present disclosure, there is provided a crimped memory module, including a plurality of memory chips disposed on a substrate and a clock driver chip according to any one of the above embodiments, where the clock driver chip is used to provide 2N clock signals for N channels of the memory chips, and each channel includes 2 sub-channels.

[0014] In an exemplary embodiment of the present disclosure, a plurality of memory chips include a first group of memory chips disposed on a first surface of a substrate, and a second group of memory chips disposed on a second surface of the substrate. The first group of memory chips includes T memory chips, and the second group of memory chips includes M memory chips, where T≥1 and M≥1.

[0015] In an exemplary embodiment of the present disclosure, a plurality of memory chips include a third group of memory chips connected to the substrate through a connection structure, and a fourth group of memory chips disposed on the third group of memory chips. The third group of memory chips includes P memory chips, and the fourth group of memory chips includes Q memory chips, where P≥1 and Q≥1.

[0016] According to a third aspect of the present disclosure, there is provided an information processing system disposed on a main board, including a press-fit memory module and a control chip according to any one of the above embodiments.

[0017] The clock driver chip according to the embodiment of the present disclosure can provide 2N groups of independent clock signals to the press-fit memory module within a limited circuit layout area by using a control word state machine to control 2N phase-locked control circuits, thereby reducing the volume and cost of the press-fit memory module.

[0018] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0020] Figure 1 is a schematic structural diagram of a clock driver chip in an exemplary embodiment of the present disclosure.

[0021] Figure 2 is a schematic diagram of a phase-locked control circuit in an embodiment of the present disclosure.

[0022] Figure 3 is a schematic connection diagram of a control word state machine and a phase-locked control circuit in an embodiment of the present disclosure.

[0023] Figure 4 is a schematic power connection diagram of a phase-locked control circuit in an embodiment of the present disclosure.

[0024] Figure 5 is a schematic diagram of a press-fit memory module in an exemplary embodiment of the present disclosure.

[0025] Figure 6 It is a schematic diagram of a storage chip of a press-fit memory module in an embodiment of the present disclosure.

[0026] Figure 7 It is a schematic diagram of a storage chip of a press-fit memory module in another embodiment of the present disclosure.

[0027] Figures 8A - 8C It is a schematic diagram of the layout of the storage chip in an embodiment of the present disclosure.

[0028] Figures 9A - 9C It is a schematic diagram of an information processing system in an embodiment of the present disclosure. Detailed implementation manners

[0029] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. The features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will realize that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be used. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0030] In addition, the accompanying drawings are only schematic illustrations of the present disclosure, and the same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0031] The example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0032] Figure 1 It is a schematic diagram of the structure of a clock driver chip in an exemplary embodiment of the present disclosure.

[0033] Refer to Figure 1 , the clock driver chip 100 is applied to a press-fit memory module, the press-fit memory module includes N channels 10, each channel includes two sub-channels 101, and the clock driver chip 100 may include:

[0034] 2N phase-locked control circuits 1, the output terminal of each phase-locked control circuit 1 is correspondingly connected to each sub-channel 101, and is used to output clock signals CLKAi / CLKBi to the sub-channel 101. N is a positive integer greater than or equal to 2, i is the serial number of the channel corresponding to the phase-locked control circuit 1, A\B is the number of the sub-channel 101 in the channel i, and 1≤i≤N;

[0035] A control word state machine 2, the input terminal is used to receive a clock control signal CON, and the output terminal is connected to 2N phase-locked control circuits 1. The control word state machine 2 is used to adjust the output frequency of the phase-locked control circuit 1 according to the clock control signal CON, and enable or disable the phase-locked control circuit 1 to output the corresponding clock signal CLKAi / CLKBi; wherein, the phase-locked control circuit 1 includes a phase-locked loop (PLL, Phase-Locked Loop).

[0036] A clock driver chip, also known as CKD (Clock Driver), is mainly responsible for buffering clock signals between the controller and the memory. In the embodiment of the present disclosure, the memory is a press-fit memory module.

[0037] The clock control signal CON comes from the CPU direction, and is used to perform clock frequency setting, clock enable setting, data read / write control, address selection control, etc. on the clock driver chip 100, so as to finely adjust the working mode and performance of the clock driver chip 100. Among them, the clock frequency setting is mainly used to set the frequency of the clock signals output by the clock driver chip 100 to each sub-channel to adapt to different application requirements; the clock enable setting can be used to control whether to output clock signals to a certain or certain sub-channels, that is, to set to enable or disable the phase-locked control circuit 1 corresponding to a certain or certain sub-channels to output the corresponding clock signals CLKAi / CLKBi; the data read / write instruction is mainly used to manage the data transmission between the clock driver chip 100 and the controller, including operations such as reading data and writing data; the address selection instruction is used to specify the channel and sub-channel to be operated (to locate the corresponding phase-locked control circuit 1) to ensure the correct transmission of data.

[0038] In the embodiments of the present disclosure, the clock driver chip 100 can perform internal control word access, that is, receive a clock control signal CON through the control word state machine 2. The internal control word access function enables the master device to configure the functions and behaviors of the slave device through specific control words. For example, the controller can set the operating mode of the clock driver chip 100, such as a high-performance mode or a low-power mode, by sending different control words. In addition, the controller can also perform fine-tuning and optimization on the clock driver chip 100 through internal control word access, such as setting the clock frequencies of each clock signal, clock enable setting, data read / write control, address selection control, etc. as described above. The setting of the control word state machine 2 can improve the flexibility and adjustability of the system and enhance the overall performance of the clock driver chip 100.

[0039] In one embodiment, the clock driver chip 100 supports the I2C bus to achieve asynchronous control, and the clock control signal CON may include a serial clock signal (SCL) and a serial data signal (SDA).

[0040] The serial clock signal (SCL) and the serial data signal (SDA) are two core signal lines on the I2C bus. The master device (controller / CPU) uses these two signals to complete the control and data communication of the slave device (clock driver chip 100). Specifically, the main function of the SCL signal is to synchronize data transmission, that is, when transmitting data, each data bit is transmitted on the edge of the SCL signal to make the data transmission more accurate and efficient. The SDA signal is mainly used for data transmission. When the master device needs to transmit data to the slave device, the master device writes the data to be transmitted into the SDA line and transmits it on the edge of the SCL signal. Using the I2C bus to transmit the SCL signal and the SDA signal can greatly improve the efficiency and accuracy of data transmission, enabling the controller to more accurately set the clock frequencies of each clock signal, clock enable setting, data read / write control, address selection control of the clock driver chip 100.

[0041] In some other embodiments, the clock driving chip 100 also supports I3C sideband access. At this time, the clock control signal CON can reach the clock driving chip 100 through I3C bus sideband access. The I3C sideband access technology is mainly used for low-speed communication between the master device and the slave device. Compared with the traditional I2C interface, I3C has some advantages. First, although I2C only requires two lines for communication, it often needs to add an additional interrupt signal line, while I3C does not. Second, different from the situation where I2C does not support multi-master and multi-slave, I3C supports a multi-master and multi-slave topology. In addition, I3C also supports two-way communication. When the clock driving chip 100 uses the I3C sideband access technology to receive the clock control signal CON, the clock control signal CON can also have more control functions. The embodiments of the present disclosure do not limit all the control functions of the clock control signal CON, and those skilled in the art can set them according to the control requirements by themselves.

[0042] In addition, in an exemplary embodiment of the present disclosure, the frequencies of the clock signals output by each phase-locked control circuit 1 are not exactly the same. Correspondingly, the phase-locked loop (PLL) circuits in each phase-locked control circuit 1 are independently controlled. The phase-locked loop circuit is a feedback control circuit that uses an externally input reference signal to control the frequency and phase of the oscillation signal inside the loop. The phase-locked loop circuit mainly includes three parts: a phase detector (PD), a loop filter (LF), and a voltage-controlled oscillator (VCO). The main function of the phase detector is to detect the phase difference between the input signal and the output signal, and convert the detected phase difference signal into a voltage signal for output. This voltage signal is filtered by a low-pass filter to form the control voltage of the voltage-controlled oscillator, so as to implement control over the frequency of the oscillator output signal. When the phase-locked loop starts to work, since there is a phase difference between the two signals input to the phase detector, the phase detector will output an error voltage to change the oscillation frequency of the voltage-controlled oscillator to make it consistent with the reference signal (capture process). When the phase-locked loop is locked, if the input signal or the frequency of the voltage-controlled oscillator changes due to certain reasons, the loop can quickly adjust itself through its own feedback, so that the output frequency and phase of the VCO are locked on the reference signal parameters again (tracking process). Each phase-locked loop circuit can have a separate input signal and is controlled by the control word state machine 2 to independently output clock signals with different frequencies.

[0043] It can be understood that both the clock signals CLKAi / CLKBi can include two sub-clock signals. For specific details, please refer to Figure 2 the embodiments shown.

[0044] In an exemplary embodiment of the present disclosure, the clock driver chip 100 is applied to a press-fit memory module, where N = 2, or N = 3, or N = 4, or N = 8.

[0045] In DDR technology, the number of channels of a press-fit memory module depends on the specific memory type and configuration. For DDR4 memory, each 64-bit wide (excluding ECC) physical layer is called a channel, which is usually connected to a 64-bit memory controller. Therefore, the most common is a dual-channel configuration, where the CPU usually has two memory controllers, each connected to a 64-bit physical layer. Additionally, there may be more memory channels, such as 3 channels and 4 channels.

[0046] For the new DDR5 memory, since the 64-bit physical layer is split into two 32-bit physical layers, the number of channels doubles. However, there are two 32-bit sub-channels on each DIMM (Dual-Inline-Memory-Modules), so although the number of channels doubles, the number of memory strips does not increase. For example, a dual-channel configuration requires 2 memory strips, and a quad-channel configuration requires 4 memory strips.

[0047] In one embodiment, the clock driver chip 100 is applied to a press-fit memory module of DDR5, where N = 2. DDR5 can be provided with two independent data channels to separately access the memory chips on the left and right (or front and back) sides, thereby improving the data access efficiency and reducing the access latency without changing the total bandwidth. In this case, the clock driver chip 100 includes four phase-locked control circuits 1, and all four phase-locked control circuits 1 are controlled by a control word state machine 2.

[0048] In another embodiment, N = 3. The three-channel is a special design, but it can also be implemented in a highly integrated press-fit memory module. Corresponding to the three-channel design, the clock driver chip 100 includes six phase-locked control circuits 1, and all six phase-locked control circuits 1 are controlled by a control word state machine 2.

[0049] In yet another embodiment, N = 4. For the CPUs on some servers, they can support true four-channel for special applications such as high-performance computing and big data processing, so the press-fit memory module can achieve four channels. Correspondingly, the clock driver chip 100 includes eight phase-locked control circuits 1, and all eight phase-locked control circuits 1 are controlled by a control word state machine 2.

[0050] In yet another embodiment, N = 8. In some cases, the CPU can support a truly eight-channel for special applications such as high-performance computing and big data processing. Therefore, the crimped memory module can be made eight-channel. Correspondingly, the clock driver chip 100 includes sixteen phase-locked control circuits 1, and the sixteen phase-locked control circuits 1 are all controlled by a control word state machine 2.

[0051] Through the architecture provided by the embodiments of the present disclosure, the clock driver chip 100 can control 2N phase-locked control circuits 1 through a control word state machine 2. Using one clock driver chip 100 can provide corresponding independent clock signals for the multi-channel crimped memory module design, thereby greatly reducing the design volume of the crimped memory module.

[0052] Figure 2 It is a schematic diagram of the phase-locked control circuit in an embodiment of the present disclosure.

[0053] Reference Figure 2 , in an exemplary embodiment of the present disclosure, the phase-locked control circuit 1 includes:

[0054] An input buffer 11 that receives a first initial clock signal DCKt and a second initial clock signal DCKc corresponding to a sub-channel corresponding to the phase-locked control circuit 1;

[0055] A phase-locked loop 12, whose input terminal is connected to the output terminal of the input buffer 11, and the control terminal is used to receive a PLL control signal PLLCON from the control word state machine 2 and a reset signal Reset from an external circuit;

[0056] A multiplexer 13 having a first input terminal, a second input terminal, an output terminal, and a control terminal. The first input terminal of the multiplexer 13 is connected to the output terminal of the phase-locked loop 12, the second input terminal of the multiplexer 13 is connected to the output terminal of the input buffer 11, and the control terminal of the multiplexer 13 is used to receive a PLL mode setting signal PLLMODE;

[0057] A clock tree 14 (Clock Tree), whose input terminal is connected to the output terminal of the multiplexer 13, and the output terminal is used to output a first clock signal QCKt and a second clock signal QCKc;

[0058] An output driver 15 having a first input terminal, a second input terminal, an output terminal, and a control terminal. The first input terminal of the output driver 15 is used to receive the first clock signal QCKt, the second input terminal of the output driver 15 is used to receive the second clock signal QCKc, and the control terminal of the output driver 15 is used to receive a clock output enable signal En from the control word state machine 2.

[0059] Among them, the input buffer 11 is used to temporarily store the first initial clock signal DCKt and the second initial clock signal DCKc transmitted by an external device, so that the processor can obtain and process these data more efficiently. In addition, the input buffer can also be regarded as a bandwidth limiter, which can control the speed of the data stream to ensure the stability and accuracy of data processing.

[0060] The phase-locked loop 12 is used to output an intermediate clock signal with a corresponding frequency based on the control of the control word state machine 2. The specific structure has been described above and will not be elaborated here.

[0061] The multiplexer 13 is used to select and output either the intermediate clock signal output by the phase-locked loop 12 or the first initial clock signal DCKt and the second initial clock signal DCKc buffered by the input buffer 11 based on the control of the control word state machine 2.

[0062] The clock tree 14 is used to drive and distribute clock signals. Through specific wiring and distribution strategies, the clock signal output by the multiplexer 13 is transmitted to each component or module in the system that requires clock signal drive. In the embodiment of the present disclosure, the clock tree 14 is mainly used to distribute one clock signal output by the multiplexer 13 into two clock signals for output.

[0063] The output driver 15 is mainly used to convert the high-frequency signal generated by the voltage-controlled oscillator into a low-frequency signal suitable for driving the subsequent circuit. The voltage-controlled oscillator generates an oscillation frequency according to the control voltage, and then this high-frequency signal is converted by the output driver. The output driver converts the high-frequency, low-current signal of the oscillator into a low-frequency, high-current signal for use by the subsequent circuit. This can not only meet the working requirements of the subsequent circuit but also help reduce interference between circuits.

[0064] The first clock signal QCKt and the second clock signal QCKc combine to form the clock signal CLKAi output by the phase-locked control circuit 1, or the first clock signal QCKt and the second clock signal QCKc combine to form the clock signal CLKBi output by the phase-locked control circuit 1.

[0065] Figure 3 It is a schematic connection diagram of the control word state machine and the phase-locked control circuit in an embodiment of the present disclosure.

[0066] Reference Figure 3 When the phase-locked control circuit 1 is as Figure 2When in the structure shown, a control word state machine 2 can correspondingly control the phase-locked loops 12, strobes 13, and output drivers 15 of multiple phase-locked control circuits 1. For the convenience of representation, the arrows between different phase-locked loops 12 are used to indicate that these phase-locked loops are all directly connected to the control word state machine 2. Similarly, the arrows between different strobes 13 and the arrows between different output drivers 15 are all used to indicate that they are all directly connected to the control word state machine 2. The arrow corresponding to the reset signal Reset indicates that the reset signal Reset is input to each phase-locked loop 12.

[0067] The first initial clock signal DCKt and the second initial clock signal DCKc corresponding to different phase-locked control circuits 1 are different (not shown).

[0068] Figure 2 and Figure 3 The phase-locked control circuit 1 of the illustrated embodiment has an independent structure, and multiple identical phase-locked control circuits 1 can be arranged in parallel, so as to provide a clear architecture. When the number of clock signals needs to be increased subsequently, the number of phase-locked control circuits 1 can be increased without major modifications.

[0069] In addition, by providing only a pair of initial clock signals for each phase-locked control circuit 1, the input ports of the clock driver chip 100 can be saved, the wiring can be simplified, and the volume of the crimped memory module can be further reduced.

[0070] In addition to providing two independent clock signals for each channel, in an embodiment of the present disclosure, independent power supplies are also provided for the clock signals of each channel.

[0071] Figure 4 is a schematic diagram of the power connection of the phase-locked control circuit in an embodiment of the present disclosure.

[0072] Reference Figure 4 , in an embodiment of the present disclosure, the clock driver chip 100 further includes N power modules 3. Each power module 3 is controlled to be enabled or disabled through an independent switching element Ki, and each power module 3 is connected to two phase-locked control circuits 1 corresponding to the same channel i.

[0073] In Figure 4In the illustrated embodiment, the power supply module 3 includes a switching element Ki. The first end of the switching element Ki is connected to a preset power supply VCLKi. The second end of the switching element Ki is used to supply power to two phase-locked control circuits 1 corresponding to the same channel i. The control end of the switching element Ki is connected to a controller. The preset power supplies corresponding to different channels can be the same or different. The types of the switching element Ki include, but are not limited to, transistors, IGBTs, etc. In other embodiments, the power supply module 3 may also have other designs, which can be determined by those skilled in the art according to the actual situation, and the present disclosure does not limit this.

[0074] By configuring an independent power supply module 3 for the two phase-locked control circuits 1 corresponding to each channel, the electric energy resources can be effectively utilized, and the efficiency and reliability of the entire system can be improved.

[0075] When only one or several channels need to work, the controller can control the state of the switching element Ki to turn off the power supply modules 3 corresponding to other channels. In this way, the phase-locked control circuits 1 of other channels will no longer be powered, and thus enter the sleep state, reducing unnecessary energy consumption. At the same time, since each channel has an independent power supply module 3, even if one channel fails, it will not affect the normal operation of other channels.

[0076] In addition, by configuring an independent power supply module 3 for the two phase-locked control circuits 1 corresponding to each channel, flexible power distribution can also be achieved. According to the actual requirements, the working state of the power supply module 3 of each channel can be adjusted to meet the power consumption requirements of different channels. For example, in a scenario where high-power output is required, more power supply modules 3 can be allocated to the corresponding channels to provide sufficient power support. In the case of low power consumption requirements, the number of power supply modules 3 can be reduced to lower the overall power consumption.

[0077] In summary, by configuring an independent power supply module 3 for the two phase-locked control circuits 1 corresponding to each channel, the clock driver chip 100 can achieve efficient energy utilization and flexible power distribution. This design can not only save power consumption and improve the overall efficiency of the system, but also provide better reliability and maintainability.

[0078] In summary, the clock driver chip 100 provided by the embodiments of the present disclosure supports a multi-channel press-fit memory module, can provide multiple independent clock signals that meet the quantity requirements for the press-fit memory module through one clock driver chip 100, and can perform separate power control on the clock signals corresponding to each channel, having obvious cost advantages and power consumption advantages.

[0079] The present disclosure also provides a press-fit memory module applying the above clock driver chip 100.

[0080] Figure 5 It is a schematic diagram of a press-fit memory module in an exemplary embodiment of the present disclosure.

[0081] Reference Figure 5 , in an embodiment of the present disclosure, the press-fit memory module 500 includes a plurality of memory chips 51 disposed on a substrate 50 and a clock driving chip 100 as described in any one of the above embodiments. The clock driving chip 100 is configured to provide 2N clock signals for N channels of the memory chips, and each channel includes 2 sub-channels.

[0082] In an exemplary embodiment of the present disclosure, the memory chips include DDR5 chips.

[0083] By using one clock driving chip 100 to provide clock signals for a plurality of memory chips 51 in the press-fit memory module 500, the design volume of the press-fit memory module can be greatly saved.

[0084] Figure 6 It is a schematic diagram of the memory chips of the press-fit memory module in an embodiment of the present disclosure.

[0085] Reference Figure 6 , in an embodiment, the plurality of memory chips 51 include a first group of memory chips 51A disposed on the first surface of the substrate 50 and a second group of memory chips 51B disposed on the second surface of the substrate 50. The first group of memory chips 51A includes T memory chips, and the second group of memory chips 51B includes M memory chips, where T≥1 and M≥1. M can be equal to T or not equal to T.

[0086] The first group of memory chips 51A includes T memory chips, and these memory chips can be different types of memories, such as static random access memory (SRAM), dynamic random access memory (DRAM), or flash memory, etc. Configuring different memories can be used to store various data and instructions to meet different system requirements. In a more common application scenario, the T memory chips are all the same type of memory, such as DDR5, to improve storage density.

[0087] The second group of memory chips 51B also includes M memory chips. Similar to the first group of memory chips 51A, these memory chips can also be different types of memories or the same type of memory.

[0088] By disposing the two groups of memory chips on different surfaces of the substrate 50 respectively, higher storage capacity and faster data access speed can be achieved. It should be noted that both T and M are integers greater than or equal to 1. This means that at least one memory chip is disposed on the first surface or the second surface of the substrate 50. This design flexibility enables the system to be configured and optimized according to actual requirements.

[0089] In summary, by separately disposing multiple memory chips 51 on the first surface and the second surface of the substrate 50, higher memory density and performance can be achieved to meet the requirements of different application scenarios.

[0090] In Figure 6 the illustrated embodiment, the clock driver chip 100 can be disposed on the first surface or the second surface of the substrate 50.

[0091] Figure 7 is a schematic diagram of the memory chips of a crimped memory module in another embodiment of the present disclosure.

[0092] Referring to Figure 7 , in one embodiment, the multiple memory chips 51 include a third group of memory chips 51C connected to the substrate 50 through a connection structure, and a fourth group of memory chips 51D disposed on the third group of memory chips 51C. The third group of memory chips 51C includes P memory chips, and the fourth group of memory chips 51D includes Q memory chips, where P≥1 and Q≥1. P may be equal to Q or not equal to Q.

[0093] The third group of memory chips 51C is connected to the substrate 50 through a specific connection structure. The connection structure can ensure a stable connection between each memory chip 51 in the third group of memory chips 51C and the substrate 50, thereby ensuring the data transmission efficiency and stability. The connection structure includes, but is not limited to, a connection structure formed by techniques such as compression connection technology (such as a compression connector). The third group of memory chips 51C and the fourth group of memory chips 51D can also be connected through a compression connector. In addition, the entire component may also be encapsulated and protected to enhance its stability and durability. The present disclosure does not limit the specific form of the connection structure.

[0094] The memory chips 51 in the third group of memory chips 51C can be of the same type of memory or different types of memory, and are selected according to actual needs.

[0095] Above the third group of memory chips 51C, a fourth group of memory chips 51D is also crimped. The fourth group of memory chips 51D can include either a layer of memory chips 51 parallel to the substrate 50 or multiple layers of memory chips 51 parallel to the substrate 50, as Figure 7 shown. The multiple layers of memory chips 51 can be crimped by means of a pre-set compression connector or the like.

[0096] The third group of memory chips 51C and the fourth group of memory chips 51D can be disposed on the first surface or the second surface of the substrate 50.

[0097] With such a design, more memory chips can be integrated on a single substrate, thereby improving the capacity and performance of the storage device. At the same time, by using different connection structures and crimping methods, the layout and connection of the memory chips can be flexibly adjusted to meet different application requirements.

[0098] In Figure 7 the illustrated embodiment, the clock driver chip 100 can be disposed on the same surface of the substrate 50 as the third group of memory chips 51C and the fourth group of memory chips 51D to facilitate other connections on the other surface of the substrate 50; in addition, the clock driver chip 100 can also be disposed on different surfaces of the substrate 50 from the third group of memory chips 51C and the fourth group of memory chips 51D to reduce the area occupation of the substrate 50.

[0099] In yet another embodiment of the present disclosure, the memory chip layout manners shown in Figure 6 and Figure 7 can be combined to achieve a higher density memory layout.

[0100] Figures 8A - 8C is a schematic diagram of the memory chip layout in an embodiment of the present disclosure.

[0101] Referring to Figures 8A - 8C , in an exemplary embodiment of the present disclosure, the first group of memory chips 51A includes the third group of memory chips 51C and the fourth group of memory chips 51D, T = P + Q, and / or, the second group of memory chips 51B includes the third group of memory chips 51C and the fourth group of memory chips 51D, M = P + Q.

[0102] In Figure 8A , the first group of memory chips 51A includes the third group of memory chips 51C and the fourth group of memory chips 51D, T = P + Q. The first group of memory chips 51A is disposed on the first surface of the substrate 50, the second group of memory chips 51A is disposed on the second surface of the substrate 50, and the clock driver chip 100 is disposed on the first surface or the second surface of the substrate 50.

[0103] In Figure 8B , the second group of memory chips 51A includes the third group of memory chips 51C and the fourth group of memory chips 51D, M = P + Q. The first group of memory chips 51A is disposed on the first surface of the substrate 50, the second group of memory chips 51A is disposed on the second surface of the substrate 50, and the clock driver chip 100 is disposed on the first surface or the second surface of the substrate 50.

[0104] In Figure 8C, the first group of memory chips 51A includes the third group of memory chips 51C and the fourth group of memory chips 51D, the second group of memory chips 51A includes the third group of memory chips 51C and the fourth group of memory chips 51D, T = P1 + Q1, M = P2 + Q2, where P1 is the number of memory chips 51 in the third group of memory chips 51C in the first group of memory chips 51A, Q1 is the number of memory chips 51 in the fourth group of memory chips 51D in the first group of memory chips 51A, P2 is the number of memory chips 51 in the third group of memory chips 51C in the second group of memory chips 51B, and Q2 is the number of memory chips 51 in the fourth group of memory chips 51D in the second group of memory chips 51A. P1 may be equal to P2 or not equal to P2; Q1 may be equal to Q2 or not equal to Q2; M may be equal to T or not equal to T. The first group of memory chips 51A is disposed on the first surface of the substrate 50, the second group of memory chips 51A is disposed on the second surface of the substrate 50, and the clock driver chip 100 is disposed on the first surface or the second surface of the substrate 50.

[0105] By combining the two layout methods, the storage density of the press-fit memory module can be greatly increased, and the volume of the press-fit memory module with the same storage capacity can be further reduced.

[0106] According to the third aspect of the present disclosure, an information processing system applying the above-mentioned press-fit memory module is provided.

[0107] Figures 9A - 9C It is a schematic diagram of the information processing system in the embodiment of the present disclosure.

[0108] Reference Figures 9A - 9C , in the embodiment of the present disclosure, the information processing system 900 is disposed on the main board 90, and includes a press-fit memory module 500 and a control chip 91 as described in any of the above embodiments. The main board may be a PCB board (Printed Circuit Board), and the control chip includes, but is not limited to, various controllers such as a CPU and a GPU.

[0109] In Figure 9A , the control chip 91 and the press-fit memory module 500 are disposed on the same surface of the main board 90, and this design can simplify the wiring.

[0110] In Figure 9B , the control chip 91 and the press-fit memory module 500 are disposed on different surfaces of the main board 90. At the same time, the control chip 91 and the press-fit memory module 500 have an overlapping part in the direction perpendicular to the main board 90, and this design can reduce the overall volume of the information processing system 900.

[0111] In Figure 9C, the control chip 91 and the press-fit memory module 500 are disposed on different surfaces of the main board 90. At the same time, the projections of the control chip 91 and the press-fit memory module 500 in the direction perpendicular to the main board 90 do not have overlapping parts. This design can minimize the overall volume of the information processing system 900 while minimizing the amount of signal trace crossings on the main board 90 and improving the signal quality.

[0112] It should be noted that although several modules or units of the devices for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of the two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0113] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and examples are only to be considered as exemplary, and the true scope and concept of the present disclosure are pointed out by the claims.

Claims

1. A clock driver chip for a press-fit memory module, the press-fit memory module including N channels, each of the channels including two sub-channels, characterized in that, the clock driver chip includes: 2N phase-locked control circuits, the output end of each phase-locked control circuit is correspondingly connected to each sub-channel for outputting a clock signal to the sub-channel, and N is a positive integer greater than or equal to 2; a control word state machine, the input end is used for receiving a clock control signal, and the output end is connected to the 2N phase-locked control circuits. The control word state machine is used for adjusting the output frequency of the phase-locked control circuits according to the clock control signal, and enabling or disabling the phase-locked control circuits to output corresponding clock signals; wherein, the phase-locked control circuit includes a phase-locked loop.

2. The clock driver chip according to claim 1, characterized in that, the phase-locked control circuit includes: an input buffer for receiving a first initial clock signal and a second initial clock signal corresponding to the sub-channel corresponding to the phase-locked control circuit; a phase-locked loop, the input end is connected to the output end of the input buffer, and the control end is used for receiving a PLL control signal from the control word state machine and a reset signal from an external circuit; a multiplexer having a first input end, a second input end, an output end and a control end. The first input end of the multiplexer is connected to the output end of the phase-locked loop, the second input end of the multiplexer is connected to the output end of the input buffer, and the control end of the multiplexer is used for receiving a PLL mode setting signal from the control word state machine; a clock tree, the input end is connected to the output end of the multiplexer, and the output end is used for outputting a first clock signal and a second clock signal; an output driver having a first input end, a second input end, an output end and a control end. The first input end of the output driver is used for receiving the first clock signal, the second input end of the output driver is used for receiving the second clock signal, and the control end of the output driver is used for receiving a clock output enable signal from the control word state machine.

3. The clock driver chip according to claim 1, characterized in that, the clock control signal includes a serial clock signal and a serial data signal.

4. The clock driver chip according to claim 1, characterized in that, the frequencies of the clock signals output by each phase-locked control circuit are not completely the same.

5. The clock driver chip according to claim 1, characterized in that, it further includes N power modules, each power module is controlled to be enabled or turned off through an independent switching element, and each power module is connected to two phase-locked control circuits corresponding to the same channel.

6. The clock driver chip according to claim 5, characterized in that, the power module includes a switching element, the first end of the switching element is connected to a preset power supply, the second end of the switching element is used for supplying power to two phase-locked control circuits corresponding to the same channel, and the control end of the switching element is connected to a controller.

7. The clock driver chip according to claim 1, characterized in that, N = 2, or, N = 3, or, N = 4, or, N = 8.

8. A press-fit memory module, characterized in that it includes a plurality of memory chips disposed on a substrate and a clock driver chip as described in any one of claims 1-7, and the clock driver chip is configured to provide 2N clock signals for N channels of the memory chips, and each of the channels includes 2 sub-channels.

9. The press-fit memory module according to claim 8, characterized in that the plurality of memory chips include a first group of memory chips disposed on a first surface of the substrate and a second group of memory chips disposed on a second surface of the substrate, the first group of memory chips includes T memory chips, and the second group of memory chips includes M memory chips, where T ≥ 1 and M ≥ 1.

10. The press-fit memory module according to claim 8, characterized in that the plurality of memory chips include a third group of memory chips connected to the substrate through a connection structure and a fourth group of memory chips disposed on the third group of memory chips, the third group of memory chips includes P memory chips, and the fourth group of memory chips includes Q memory chips, where P ≥ 1 and Q ≥ 1.

11. An information processing system disposed on a main board, comprising a press-fit memory module as described in any one of claims 8-10 and a control chip.

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