Display module and display device

Abstract

Embodiments of the present application provide a display module and a display device, and relate to the technical field of display, which are used for reducing the frame width of the corner of the display panel. The non-display area of the display panel includes a first non-display area, a second non-display area and a third non-display area; the first non-display area and the display area are arranged along a first direction, and the second non-display area and the display area are arranged along a second direction; the third non-display area is located between the first non-display area and the second non-display area, and the third non-display area is arranged corresponding to the corner of the display area; the display area includes a plurality of first pixel rows and a plurality of second pixel rows, and the second pixel row is located on one side of the first pixel row close to the second non-display area; the first non-display area includes a gate drive circuit, and the first pixel row is electrically connected to the gate drive circuit through a first gate drive signal line; the non-display area includes a driving chip, and the second pixel row is electrically connected to the driving chip through a second gate drive signal line.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display module and display device. Background Technology

[0002] With the continuous development of science and technology, more and more display devices are being widely used in people's daily lives and work, becoming indispensable tools for people today. Moreover, with the continuous development of display technology, consumers have increasingly higher requirements for the appearance and size of display screens.

[0003] Currently, display panels suffer from large bezel widths, especially for irregularly shaped display panels that are not rectangular, making it difficult to compress the bezel width. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a display module and display device for reducing the width of the third non-display area and improving the visual effect of the display module.

[0005] On one hand, embodiments of the present invention provide a display module, including a display panel, including a display area and a non-display area, the non-display area including a first non-display area, a second non-display area and a third non-display area; the first non-display area and the display area are arranged along a first direction, the second non-display area and the display area are arranged along a second direction, the first direction and the second direction intersect; the third non-display area is located between the first non-display area and the second non-display area, and the third non-display area is set at the corner of the display area;

[0006] The display area includes multiple first pixel rows and multiple second pixel rows, which are arranged along a second direction; the second pixel rows are located on the side of the first pixel rows that is closer to the second non-display area.

[0007] The first non-display area includes a gate driving circuit, and the first pixel row is electrically connected to the gate driving circuit through a first gate driving signal line.

[0008] The non-display area includes a driver chip, and the second pixel row is electrically connected to the driver chip through a second gate drive signal line.

[0009] On the other hand, embodiments of the present invention provide a display device including the display panel described above.

[0010] The display module and display device provided in the embodiments of the present invention can reduce or even eliminate the need for gate driving circuits in the third non-display area of ​​the display panel by having the second pixel electrically connected to the driving chip. This is beneficial for reducing the width of the third non-display area of ​​the display panel and narrowing the width difference between the third non-display area and the second non-display area. For example, the width of the third non-display area can be made equal to the width of the second non-display area, thereby improving the visual effect of the display panel. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a display module provided in an embodiment of the present invention;

[0013] Figure 2 for Figure 1 An enlarged schematic diagram of region A1 in the middle;

[0014] Figure 3 A circuit diagram of a sub-pixel provided in an embodiment of the present invention;

[0015] Figure 4 A circuit diagram of another sub-pixel provided in an embodiment of the present invention;

[0016] Figure 5 for Figure 1 An enlarged schematic diagram of region A1 in the middle;

[0017] Figure 6 A cross-sectional schematic diagram of a display module in which the bent portion is in a bent state, provided in an embodiment of the present invention;

[0018] Figure 7 for Figure 1 The diagram shown is a top view of the display module with its bent section in a bent state.

[0019] Figure 8 A cross-sectional schematic diagram of another display module provided in an embodiment of the present invention, in which the bent portion is in a bent state;

[0020] Figure 9 for Figure 1 Another enlarged schematic diagram of region A1 in the diagram;

[0021] Figure 10 This is a cross-sectional schematic diagram of the display area of ​​a display panel provided in an embodiment of the present invention;

[0022] Figure 11 A cross-sectional schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention;

[0023] Figure 12 This is a cross-sectional schematic diagram of the non-display area of ​​a display panel provided in an embodiment of the present invention;

[0024] Figure 13 for Figure 1 Another enlarged schematic diagram of the central region A1;

[0025] Figure 14 for Figure 1 Another enlarged schematic diagram of the central region A1;

[0026] Figure 15 for Figure 1 Another enlarged schematic diagram of the central region A1;

[0027] Figure 16 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0028] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0030] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0031] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0032] It should be understood that although the terms "first," "second," etc., may be used to describe pixel rows in embodiments of the present invention, these pixel rows should not be limited to these terms. These terms are only used to distinguish the different pixel rows from one another. For example, without departing from the scope of embodiments of the present invention, a first pixel row may also be referred to as a second pixel row, and similarly, a second pixel row may also be referred to as a first pixel row.

[0033] This invention provides a display module, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a display module provided in an embodiment of the present invention. The display module 100 includes a display panel 10 and a driver chip 20. The driver chip 20 can be used to provide various display signals to the display panel 10.

[0034] For example, such as Figure 1 As shown, the display panel 10 includes a display area AA and a non-display area NA. The display area AA includes multiple sub-pixels ( Figure 1 (Not shown). The non-display area AA does not include subpixels.

[0035] Optionally, in an embodiment of the invention, the shape of the display area AA includes a polygon with rounded corners. Figure 1 The display area AA, including a rounded rectangle, is used as an example. Figure 1 As shown, the display area AA includes a first edge E1 extending along a first direction h11 and a second edge E2 extending along a second direction h12. The first edge E1 and the second edge E2 are connected by a third edge E3, which includes a curve. That is, the third edge E3 corresponds to a corner of the display area AA, where the corner connects two edges in the display area AA with different extending directions. The curve of the third edge E3 can make the display effect of the display area AA more aesthetically pleasing and improve the visual effect of the display panel.

[0036] Combination Figure 1 and Figure 2 As shown, Figure 2 for Figure 1 An enlarged schematic diagram of the central region A1 shows that the display area AA includes multiple first pixel rows 11 and multiple second pixel rows 12. The first pixel rows 11 include multiple sub-pixels 1 arranged along a first direction h11; the second pixel rows 12 include multiple sub-pixels 1 arranged along the first direction h11.

[0037] like Figure 2As shown, the first pixel row 11 and the second pixel row 12 are arranged along the second direction h12; along the second direction h12, the second pixel row 12 is located on the side of the first pixel row 11 closer to the second non-display area NA2; for example, the first pixel row 11 includes m1 sub-pixels 1 arranged along the first direction h11, and the second pixel row 12 includes m2 sub-pixels 1 arranged along the first direction h11, where m1 and m2 are both integers greater than 2. The first direction h11 and the second direction h12 intersect. In this embodiment of the invention, m2 < m1. Figure 2 As shown, along the direction from the display area AA to the second non-display area NA2, the edge sub-pixels in the second pixel row 12 are recessed inward relative to the edge sub-pixels in the first pixel row 11, moving closer to the interior of the display area AA. Based on this arrangement, the second pixel row 12, with a smaller number of sub-pixels, can define a third edge E3 with the aforementioned curved shape, thereby optimizing the visual effect of the display panel. Figure 2 As shown, at the position of the third edge E3 near the display area AA, multiple sub-pixels 1 can be arranged in a stepped manner so that the edge of the display area AA presents a visual effect of having a curved edge in a macroscopic visual sense.

[0038] For example, the display panel may include a plurality of second pixel rows 12. The number of sub-pixels in different second pixel rows 12 may be the same or different. This embodiment of the invention does not limit this. Figure 2 The display panel 10 includes three second pixel rows 12, and the number of the three second pixel rows 12 is different from each other.

[0039] For example, such as Figure 2 As shown, the display area AA also includes a first gate signal line 13 and a second gate signal line 14 extending along the first direction h11. The first gate signal line 13 is electrically connected to the first pixel row 11 to provide a gate driving signal to the first pixel row 11, and the second gate signal line 14 is electrically connected to the second pixel row 12 to provide a gate driving signal to the second pixel row 12.

[0040] In embodiments of the present invention, such as Figure 1 and Figure 2 As shown, the non-display area NA includes a first non-display area NA1, a second non-display area NA2, and a third non-display area NA3; the first non-display area NA1 and the display area AA are arranged along a first direction h11, the second non-display area NA2 and the display area AA are arranged along a second direction h12, and the third non-display area NA3 is located between the first non-display area NA1 and the second non-display area NA2, and the third non-display area NA3 is positioned at the corner of the display area AA. In this embodiment of the invention, the corner of the display area AA is rounded. Figure 1As shown, the first non-display area NA1 is located on the side of the first edge E1 away from the display area AA. The second non-display area NA2 is located on the side of the second edge E2 away from the display area AA. The third non-display area NA is located on the side of the third edge E3 away from the display area AA.

[0041] Optional, such as Figure 1 and Figure 2 As shown, the edge of the third non-display area NA3 away from the display area AA includes an arc, and the edge of the third non-display area NA3 close to the display area AA is also an arc. The arc setting can optimize the visual effect of the display panel 10.

[0042] For example, such as Figure 2 As shown, the first non-display area NA1 includes a gate driving circuit 15, which provides a gate driving signal to the first pixel row 11. Figure 2 As shown, the display area AA may include multiple first pixel rows 11; correspondingly, the gate driving circuit 15 includes multiple cascaded gate driving units 150, which are electrically connected to the first pixel rows 11. When the display panel 10 is in operation, the multiple gate driving units 150 provide gate driving signals step by step to turn on the multiple first pixel rows 11 sequentially.

[0043] In embodiments of the present invention, such as Figure 2 As shown, the second pixel row 12 is electrically connected to the driver chip 20. The gate drive signal required for the operation of the second pixel row 12 is not provided by the aforementioned gate drive circuit 15, but by the driver chip 20.

[0044] When the display panel 10 is operating, the gate driving circuit 15 and the driving chip 20 respectively provide the gate driving signals required for the operation of the first pixel row 11 and the second pixel row 12. Optionally, the gate driving signal provided by the driving chip 20 can be located after the gate driving signal provided by the last stage gate driving unit 150 in the gate driving circuit 15. Here, the gate driving signal refers to the signal provided to the gates of at least some of the transistors in the first pixel row 11 and the second pixel row 12. The characteristics of the gate driving signal can be determined according to the specific structure of the sub-pixel 1.

[0045] For example, combining Figure 3 As shown, Figure 3This is a circuit diagram of a sub-pixel provided in an embodiment of the present invention. The sub-pixel 1 includes a pixel driving circuit 101 and a light-emitting element 102 electrically connected. The pixel driving circuit 101 includes a switching transistor T11, a driving transistor T12, and a storage capacitor C1. The gate of the switching transistor T11 is electrically connected to the scan signal terminal S, and the first terminal of the switching transistor T11 is electrically connected to the data voltage terminal Data. The second terminal of the switching transistor T11 is electrically connected to the gate of the driving transistor T12. The first terminal of the driving transistor T12 is electrically connected to the second power supply voltage terminal PVDD. The second terminal of the driving transistor T12 is electrically connected to the light-emitting element 102. The light-emitting element 102 is also electrically connected to the first power supply voltage terminal PVEE. The two plates of the storage capacitor C1 are respectively electrically connected to the second power supply voltage terminal PVDD and the gate of the driving transistor T12.

[0046] The pixel driving circuit 101 is designed as follows: Figure 3 When the "2T1C" structure shown includes two transistors and a storage capacitor, the gate drive signal mentioned above includes... Figure 3 The scan signal received by the scan signal terminal S shown. Figure 2 As shown, the gate driving circuit 15 includes a scan driving circuit, which can provide, for example, Figure 3 The scan signal received by the scan signal terminal S shown.

[0047] Or, such as Figure 4 As shown, Figure 4 The present invention provides a circuit diagram of another sub-pixel, wherein the pixel driving circuit 101 includes a storage capacitor Cst, a driving transistor M11, a first reset module 111, a data writing module 112, a threshold compensation module 113, a light emission control module 114, and a second reset module 115.

[0048] The storage capacitor Cst has two plates electrically connected to the second power supply voltage terminal PVDD and the gate of the driving transistor M11, respectively. The first reset module 111, in response to the first scan signal, resets the potential of the gate of the driving transistor M11 during the reset period. The data writing module 112, in response to the second scan signal, writes a data voltage to the first electrode of the driving transistor M11 during the data writing and threshold compensation period. The threshold compensation module 113 compensates for the threshold voltage of the driving transistor M11 during the data writing and threshold compensation period. The second reset module 115, in response to the first scan signal, resets the electrodes of the light-emitting element 102 during the reset period. The light-emitting control module 114, in response to the aforementioned light-emitting control signal, controls the light-emitting element 102 to light up during the light-emitting period.

[0049] Optional, such as Figure 4As shown, the first reset module 111 includes a first reset transistor M12, whose gate is electrically connected to the first scan signal terminal S1, and whose first and second terminals are electrically connected to the reset signal terminal Vref and the gate of the driving transistor M11, respectively. The data writing module 112 includes a data writing transistor M13, whose gate is electrically connected to the second scan signal terminal S2, and whose first and second terminals are electrically connected to the data signal terminal Data and the first terminal of the driving transistor M11, respectively. The threshold compensation module 113 includes a threshold compensation transistor M14, whose gate is electrically connected to the second scan signal terminal S2, whose first terminal is electrically connected to the second terminal of the driving transistor M11, and whose second terminal is electrically connected to the gate of the driving transistor M11. The light emission control module 114 includes a first light emission control transistor M15 and a second light emission control transistor M16, both of whose gates are electrically connected to the light emission control signal terminal E. The first terminal of the first light emission control transistor M15 is electrically connected to the second power supply voltage terminal PVDD, and its second terminal is electrically connected to the first terminal of the driving transistor M11. The first terminal of the second light emission control transistor M16 is electrically connected to the second terminal of the driving transistor M11, and its second terminal is electrically connected to the first electrode of the light-emitting element 102. The second reset module 115 includes a second reset transistor M17, whose gate is electrically connected to the first scan signal terminal S1, its first electrode is electrically connected to the reset signal terminal Vref, and its second electrode is electrically connected to the first electrode of the light-emitting element 102. The second electrode of the light-emitting element 102 is electrically connected to the first power supply voltage terminal PVEE.

[0050] The pixel driving circuit 101 is designed as follows: Figure 4 When the "7T1C" structure shown has seven transistors and one storage capacitor, the gate drive signal includes, as follows: Figure 4 The pixel driving circuit 101 shown may receive any one or more of the following: the first scan signal received by the first scan signal terminal S1, the second scan signal received by the second scan signal terminal S2, and the light emission control signal received by the light emission control signal terminal E.

[0051] Correspondingly, such as Figure 5 As shown, Figure 5 This is a schematic diagram of another display module provided in an embodiment of the present invention. The first gate signal line 13 includes a first scan signal line S1_1, a second scan signal line S2_1, and a light emission control signal line E_1; the second gate signal line 14 includes a first scan signal line S1_2, a second scan signal line S2_2, and a light emission control signal line E_2; the first scan signal line S1_1 and the first scan signal line S1_2 transmit... Figure 4 The first scan signal received by the first scan signal terminal S1, and the second scan signal line S2_1 and the second scan signal line S2_2 transmit the signal. Figure 4 The second scan signal received by the second scan signal terminal S2, as shown, is transmitted via the light emission control signal line E_1 and the light emission control signal line E_2. Figure 4 The light-emitting control signal received by terminal E shown.

[0052] For example, such as Figure 5 As shown, the gate driving circuit 15 includes a scan driving circuit 151 and a light-emitting driving circuit 152. The scan driving circuit 151 includes multiple cascaded scan driving units 1510, and the light-emitting driving circuit 152 includes multiple cascaded light-emitting driving units 1520. The gate driving unit 150 includes a scan driving unit 1510 and / or a light-emitting driving unit 1520.

[0053] For example, the scan driving unit 1510 can be electrically connected to the second scan signal line S2_1 connected to the current second pixel row 12 and the first scan signal line S1_1 electrically connected to the next second pixel row 12 to provide a first scan signal and a second scan signal to the first pixel row 11; the light emission driving unit 1520 is electrically connected to the light emission control signal line E_1 to provide a light emission control signal to the first pixel row 11.

[0054] like Figure 5 As shown, the driver chip 20 is electrically connected to the second pixel row 12, which means that the driver chip 20 is electrically connected to the first scan signal line S1_2, the second scan signal line S2_2 and the light emission control signal line E_2 respectively.

[0055] The display module provided in this embodiment of the invention can reduce or even eliminate the need for setting gate driving units 150 in the third non-display area NA3 by having the second pixel row 12 receive gate driving signals through the driving chip 20. This is beneficial for reducing the bezel width of the third non-display area NA3 and narrowing the width difference between the third non-display area NA3 and the second non-display area NA2. For example, the width of the third non-display area NA3 can be made equal to the width of the second non-display area NA2 to improve the visual effect of the display panel.

[0056] It should be noted that when the edge of the third non-display area NA3 is set as an arc, the width direction of the third non-display area NA3 at a certain position is perpendicular to the tangent of the edge at the corresponding position.

[0057] It should be understood that Figure 3 and Figure 4 The pixel driving circuit 101 shown is merely an illustration. In this embodiment of the invention, a greater number of transistors can be incorporated into the pixel driving circuit 101 according to different design requirements; this embodiment does not impose any limitations on this. Of course, the display panel may also include a liquid crystal display panel, and this embodiment does not limit the type of display panel.

[0058] In addition, it should be noted that Figure 5The positional relationship between the scanning driving circuit 151 and the light-emitting driving circuit 152 shown is merely illustrative. Embodiments of the present invention can adjust their positions according to different design requirements. For example, along the first direction h11, embodiments of the present invention can position the scanning driving circuit 151 and the light-emitting driving circuit 152 on opposite sides of the display area AA. Embodiments of the present invention do not limit this. Figure 5 The illustration of a light-emitting driving unit 1520 electrically connected to a first pixel row 11 is merely schematic. In other possible implementations, a light-emitting driving unit 1520 may be electrically connected to two or more first pixel rows 11 to drive two or more first pixel rows 11 using a light-emitting driving unit 1520. This embodiment of the invention does not limit this.

[0059] For example, the number n of the second pixel rows 12 satisfies: 3 ≤ n ≤ 10. Based on this setting, on the one hand, it can avoid setting too many second pixel rows 12 electrically connected to the driver chip 20, avoiding the driver chip 20 providing gate drive signals to too many pixel rows, and reducing the design complexity of the driver chip 20; on the other hand, it can also avoid setting too few second pixel rows 12 electrically connected to the driver chip 20, avoiding setting too many pixel rows to provide gate drive signals through the gate drive circuit 15, thereby avoiding the gate drive circuit 15 including too many gate drive units 150, and avoiding the gate drive units 150 occupying the space of the third non-display area NA3, resulting in an increase in the width of the third non-display area NA3.

[0060] For example, in combination Figure 1 , Figure 2 , Figure 5 and Figure 6 As shown, Figure 6 This is a cross-sectional schematic diagram of a display module provided in an embodiment of the present invention, showing the bent portion of the module in a bent state. The display module 100 also includes a bent portion 30, which can switch between an unfolded state and a bent state.

[0061] When the bent portion 30 is in the unfolded state, such as Figure 1 , Figure 2 and Figure 5 As shown, the bending portion 30 is located on the side of the driver chip 20 near the display area AA. Specifically, the bending portion 30 may be located on the side of the driver chip 20 near the second non-display area NA2.

[0062] For example, such as Figure 1As shown, when the shape of the display area AA is set to a rounded rectangle, the display panel 10 may include at least two first non-display areas NA1 and at least two second non-display areas NA2. The two first non-display areas NA1 are disposed opposite each other on both sides of the display area AA along a first direction h11, and the two second non-display areas NA2 are disposed opposite each other on both sides of the display area AA along a second direction h12. Correspondingly, the display panel may include at least four of the aforementioned third non-display areas NA3. Figure 1 As shown, the bent portion 30 can be set to correspond to one of the second non-display areas NA2, that is, the driver chip 20 can be located on the side of one of the second non-display areas NA2 that is away from the display area AA.

[0063] When the bent portion 30 is in a bent state, optional features include: Figure 6 and Figure 7 As shown, Figure 7 for Figure 1 The diagram shows a top view of the display module 100 with the bending portion 30 in a bent state. The driver chip 20 can be bent to the side of the display panel 10 away from the light-emitting side via the bending portion 30. The bending portion 30 avoids the driver chip 20 occupying space on the light-emitting side of the display panel 10, which helps to further reduce the width of the bezel of the display panel 10 and increase the screen-to-body ratio of the display panel 10.

[0064] For example, the above-described bending portion 30 may include various forms.

[0065] For example, such as Figure 6 As shown, in this embodiment of the invention, a flexible circuit board 40 can be provided in the display module 100, and the flexible circuit board 40 includes the aforementioned bent portion 30. For example... Figure 6 As shown, the driver chip 20 is bonded to the flexible circuit board 40, and the second non-display area NA2 of the display panel 10 includes a bonding area BA, which includes multiple bonding terminals. The flexible circuit board 40 is electrically connected to the bonding terminals.

[0066] like Figure 6 As shown, the driver chip 20 is mounted on the flexible circuit board 40, that is, the flexible circuit board 40 serves as the carrier of the driver chip 20; and the driver chip 20 is electrically connected to the flexible circuit board 40. The flexible circuit board 40 on which the driver chip 20 is mounted can be called a chip-on-film (COF). After the COF is bonded to the display panel 10, this embodiment of the invention can bend the flexible circuit board 40 to bend the driver chip 20 to the side of the display panel 10 away from the light-emitting surface, thereby improving the screen-to-body ratio of the display panel 10.

[0067] Alternatively, in another feasible way, such as Figure 8 As shown, Figure 8 This is a cross-sectional schematic diagram of another display module provided in an embodiment of the present invention with the bent portion in a bent state. The display panel 10 includes a substrate 51, a driving function layer 52 located on one side of the substrate 51, and a display function layer 53. The driving function layer 52 includes the aforementioned pixel driving circuit, and the display function layer 53 includes the aforementioned light-emitting element.

[0068] In this embodiment of the invention, the substrate 51 includes a flexible material. Exemplary flexible materials include polymeric resins such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0069] like Figure 8 As shown, in addition to the aforementioned display area AA and non-display area NA, the substrate 51 also includes a bending area WA, which is located between the driver chip 20 and the display area AA. Specifically, the bending area BA can be located between the driver chip 20 and at least one of the aforementioned second non-display areas NA2, and the bending portion 30 includes the substrate 51 located in the bending area BA. In this embodiment of the invention, the substrate 51 located in the bending area BA can be bent to bend the driver chip 20 to the side of the display panel 10 away from the light-emitting side, thereby increasing the screen-to-body ratio of the display panel 10.

[0070] For example, such as Figure 2 and Figure 5 As shown, the display panel 10 also includes a first gate drive signal line 111 and a second gate drive signal line 17. The first gate drive signal line 111 is electrically connected to the gate drive circuit 2 and the first pixel row 11. The second gate drive signal line 17 is electrically connected to the second pixel row 12 and the driver chip 20. The first gate drive signal line 111 is used to provide the gate drive signal provided by the gate drive circuit 2 to the first pixel row 11. The second gate drive signal line 17 is used to provide the gate drive signal provided by the driver chip 20 to the second pixel row 12.

[0071] like Figure 2 and Figure 5 As shown, at least a portion of the first gate drive signal line 111 is located in the first non-display area NA1, and the first gate drive signal line 111 and the first gate signal line 13 are electrically connected. The second gate drive signal line 17 and the second gate signal line 14 are electrically connected.

[0072] For example, such as Figure 9 As shown, Figure 9 for Figure 1Another enlarged schematic diagram of region A1 shows that at least a portion of the second gate drive signal line 17 is located in the display area AA. Compared to the method of partially placing the second gate drive signal line 17 in the third non-display area NA3, this arrangement can further reduce the number of traces and devices in the third non-display area NA3, which is beneficial for further reducing the width of the third non-display area NA3.

[0073] When setting the second gate drive signal line 17, for example, as follows: Figure 9 As shown, in this embodiment of the invention, the second gate drive signal line 17 may include a first sub-gate drive signal line 171, a second sub-gate drive signal line 172, and a third sub-gate drive signal line 173 electrically connected, wherein at least a portion of the first sub-gate drive signal line 171 is located in the display area AA. At least a portion of the second sub-gate drive signal line 172 is located in the second non-display area NA2. At least a portion of the third sub-gate drive signal line 173 is located in the third non-display area NA3.

[0074] Optional, such as Figure 9 As shown, in this embodiment of the invention, the first sub-gate drive signal line 171 can be extended along the second direction h12. Combined with... Figure 10 As shown, Figure 10 This is a cross-sectional schematic diagram of the display area of ​​a display panel provided in an embodiment of the present invention. The first sub-gate driving signal line 171 and the second gate signal line 14 can be disposed in different layers, and the two are electrically connected through a via K1 located in the insulating layer between them.

[0075] For example, such as Figure 10 As shown, Figure 10 This is a cross-sectional schematic diagram of the display area of ​​a display panel provided in an embodiment of the present invention. The display panel 10 includes a substrate 51, a driving functional layer 52 located on one side of the substrate 51, and a display functional layer 53. The display functional layer 53 is located on the side of the driving functional layer 52 away from the substrate 51.

[0076] The driving functional layer 52 includes a first insulating layer IS1, a semiconductor layer SE, a second insulating layer IS2, a first metal layer M1, a third insulating layer IS3, a second metal layer M2, a fourth insulating layer IS4, a third metal layer M3, a passivation layer PV, and a planarization layer PLN, which are sequentially stacked along a direction h2 away from the substrate 51. The semiconductor layer SE includes the channels of at least a portion of the transistors in the pixel driving circuit 101 described above. Figure 10 Only one transistor T01 electrically connected to the light-emitting element 102 is shown as an illustration.

[0077] The first metal layer M1 includes the gates of at least some of the transistors in the pixel driving circuit 101, the first electrode C11 of the storage capacitor C in the pixel driving circuit 101, and the first gate signal line and the second gate signal line 14. The second metal layer M2 includes the second electrode C12 of the storage capacitor C in the pixel driving circuit 101. The third metal layer M3 includes the first and second electrodes of at least some of the transistors in the pixel driving circuit 101. The display function layer 53 includes a pixel definition layer 531, a first electrode layer 1021, a second electrode layer 1022, and a light-emitting layer 1020. The pixel definition layer 531 includes a pixel opening 5310, and the light-emitting layer 1020 is at least partially located within the pixel opening 5310.

[0078] Figure 10 The first sub-gate drive signal line 171 is located in the third metal layer M3 and the second gate signal line 14 is located in the first metal layer M1 as an illustration. The two are electrically connected through a through hole K1 that passes through the fourth insulating layer IS4 and the third insulating layer IS3.

[0079] In this embodiment of the invention, the extension of the first sub-gate drive signal line 171 is offset from the aforementioned third non-display area NA3. For example, as shown... Figure 9 As shown, the extension of the first sub-gate drive signal line 171 passes through the aforementioned second non-display area NA2. This arrangement helps to further reduce the width of the third non-display area NA3.

[0080] For example, such as Figure 9 As shown, the display area AA also includes multiple data lines 16, including a first data line 161. The extension of the first data line 161 passes through the third non-display area NA3. The display panel 10 also includes a data connection line 162 electrically connected to the first data line 161. The first data line 161 is electrically connected to the driver chip 20 through the data connection line 162. In this embodiment of the invention, at least a portion of the data connection line 162 is located in the display area AA. This arrangement avoids the data connection line 162 passing through the third non-display area NA3, further reducing the number of traces in the third non-display area NA3 and thus facilitating a further reduction in the width of the third non-display area NA3.

[0081] For example, such as Figure 9 As shown, the data connection line 162 includes a first sub-data connection line 1621 extending along a first direction h11 and a second sub-data connection line 1622 extending along a second direction h12; the first sub-data connection line 1621 and the second sub-data connection line 1622 are electrically connected, and both are at least partially located in the display area AA. The first sub-data connection line 1621 and the first data line 161 are electrically connected in a cross configuration.

[0082] like Figure 9As shown, data connection line 162 also includes a third sub-data connection line 1623, at least a portion of which is located in the second non-display area NA2. The second sub-data connection line 1622 and the third sub-data connection line 1623 are electrically connected.

[0083] For example, in this embodiment of the invention, at least two of the first sub-gate driving signal line 171, the second sub-data connection line 1622, and the data line 15 are disposed on the same layer. For instance, this embodiment of the invention may have the first sub-gate driving signal line 171 and the second sub-data connection line 1622 disposed on the same layer, or the first sub-gate driving signal line 171 and the data line 15 disposed on the same layer; or the second sub-data connection line 1622 and the data line 15 disposed on the same layer, or all three of them (the first sub-gate driving signal line 171, the second sub-data connection line 1622, and the data line 15) disposed on the same layer. Based on this arrangement, the number of film layers in the display panel can be reduced, which is beneficial for reducing the thickness of the display panel 10. For example, as... Figure 11 As shown, Figure 11 This is a cross-sectional schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention. In this embodiment of the present invention, the first sub-gate drive signal line 171, the second sub-data connection line 1622 and the data line 16 can be disposed on the same layer of the third metal layer M3.

[0084] It should be noted that, Figure 10 and Figure 11 The film structure shown is only an illustration. In this embodiment of the invention, a fourth metal layer can be provided in the driving functional layer 52 on the side of the third metal layer M3 away from the substrate 51 as needed, and at least two of the first sub-gate driving signal line 171, the second sub-data connection line 1622 and the data line 15 can be provided in the fourth metal layer. Based on this arrangement, the structure in the third metal layer M3 can be reduced and the wiring difficulty can be reduced.

[0085] In another possible implementation, for example, such as Figure 2 and Figure 5 As shown, in embodiments of the present invention, at least a portion of the second gate drive signal line 17 may be located in the non-display area NA. For example, in embodiments of the present invention, at least a portion of the second gate drive signal line 17 may be located in the third non-display area NA3.

[0086] like Figure 2 and Figure 5 As shown, the end of the second gate signal line 14 extends to the third non-display area NA3 and is electrically connected to the second gate drive signal line 17. This arrangement avoids placing the second gate drive signal line 17 in the display area AA, thus reducing the wiring difficulty of the display area AA.

[0087] Optional, such as Figure 2 and Figure 5 As shown, the second gate drive signal line 17 includes a first sub-connection line 174, a second sub-connection line 175, and a third sub-connection line 176 that are electrically connected. The extending directions of the first sub-connection line 174, the second sub-connection line 175, and the third sub-connection line 176 intersect. At least a portion of the first sub-connection line 174 is located in the third non-display area NA3, at least a portion of the second sub-connection line 175 is located in the second non-display area NA2, and at least a portion of the third sub-connection line 176 is located in the bend portion 30.

[0088] In this embodiment of the invention, the angle between the extension direction of the first sub-connecting line 174 at at least a portion of its position and the second direction h12 is less than or equal to 45°. Based on this arrangement, the length of the component of the first sub-connecting line 174 in the first direction h11 can be reduced. When the display panel 10 includes multiple first sub-connecting lines 174, it is beneficial to reduce the total area occupied by the multiple first sub-connecting lines 174 in the first direction h11, thereby reducing the width of the third non-display area NA3 in the first direction h111.

[0089] It should be noted that the first sub-connecting line 174 mentioned above can be a straight line or a curve. When the first sub-connecting line 174 is set as a curve, the extension direction of the first sub-connecting line 174 at a certain position refers to the extension direction of the tangent of the first sub-connecting line 324 at that position.

[0090] For example, in embodiments of the present invention, two adjacent second gate drive signal lines 17 can be located in different film layers. For instance, two adjacent second gate drive signal lines 17 can be alternately located in any two of the aforementioned first metal layer, second metal layer, and third metal layer. Figure 12 As shown, Figure 12 This is a cross-sectional schematic diagram of the non-display area of ​​a display panel provided in an embodiment of the present invention, wherein one of two adjacent second gate drive signal lines 17 is located in the first metal layer M1 and the other is located in the third metal layer M3. Based on this arrangement, the distance between two adjacent second gate drive signal lines 17 can be reduced, which is beneficial for further compressing the width of the non-display area NA where the second gate drive signal lines 17 are located. For example, the two adjacent second gate drive signal lines 17 can be arranged to at least partially overlap in the direction h2 perpendicular to the plane of the substrate 51.

[0091] For example, two adjacent second gate drive signal lines 17 located in different film layers include at least one of the following three cases: two adjacent first sub-connection lines 174 located in different film layers, two adjacent second sub-connection lines 175 located in different film layers, and two adjacent second sub-connection lines 175 located in different film layers.

[0092] For example, such as Figure 13 and Figure 14 As shown, Figure 13 and Figure 14 for Figure 1 Two other enlarged schematic diagrams of the central area A1 show that the third non-display area NA3 includes an electrostatic discharge (ESD) protection circuit 181. The ESD protection circuit 181 improves the anti-static capability of the display panel 10, preventing electrostatic damage to the electronic structures in the display area AA.

[0093] For example, such as Figure 13 As shown, in embodiments of the present invention, at least a portion of the second gate drive signal line 17 can be located in the display area AA. Alternatively, as... Figure 14 As shown, in this embodiment of the invention, at least a portion of the second gate drive signal line 17 can be located in the third non-display area NA3.

[0094] like Figure 14 As shown, when at least a portion of the second gate drive signal line 17 is located in the third non-display area NA3, in this embodiment of the invention, at least a portion of the electrostatic discharge (ESD) protection circuit 181 can be located on the side of the second gate drive signal line 17 away from the display area AA. That is, the ESD protection circuit 181 is located outside the second gate drive signal line 17. Based on this arrangement, the ESD protection circuit 181 can be used to protect the second gate drive signal line 17 from electrostatic discharge.

[0095] For example, such as Figure 13 and Figure 14 As shown, the display panel 10 also includes a gate drive input signal line 153, which is electrically connected to the gate drive unit 150. The gate drive input signal line 153 is used to transmit drive signals that drive the gate drive unit 150 to operate. For example, the drive signals include one or more of a first level signal VGH, a second level signal VGL, a first clock signal CK, and a second clock signal XCK.

[0096] In embodiments of the present invention, such as Figure 13 and Figure 14 As shown, the electrostatic discharge (ESD) protection circuit 181 is electrically connected to the driver chip 20 and the gate drive input signal line 153. The drive signal required for the operation of the gate drive unit 150 is received from the driver chip 20 through the ESD protection circuit 181. Based on this configuration, the drive signal required for the operation of the gate drive unit 150 can be processed by the ESD protection circuit 181 before being input to each stage of the gate drive unit 150, thereby reducing the risk of the corresponding gate drive input signal line 153 being damaged by electrostatic discharge and improving the reliability of the gate drive input signal line 153.

[0097] For example, such as Figure 13 and Figure 14 As shown, the third non-display area NA3 also includes a first electrostatic discharge (ESD) protection connection line 1821, which is electrically connected to the driver chip 20 and the ESD protection circuit 181. Optionally, the signal transmitted by the first ESD protection connection line 1821 is the aforementioned drive signal. Figure 13 and Figure 14 The diagram illustrates the following: four first electrostatic discharge (ESD) protection lines 1821 connect the electrostatic discharge (ESD) protection circuit 181 and the driver chip 20, respectively transmitting the first level signal VGH, the second level signal VGL, the first clock signal CK, and the second clock signal XCK. Similarly, four second ESD protection lines 1822 connect the gate drive unit 1520 and the ESD protection circuit 181, respectively transmitting the first level signal VGH, the second level signal VGL, the first clock signal CK, and the second clock signal XCK.

[0098] Optional, such as Figure 14 As shown, at least a portion of the second gate drive signal line 17 is located in the third non-display area NA3; as Figure 14 As shown, the third non-display area NA3 includes the aforementioned first sub-connection line 174.

[0099] When setting up the routing in the third non-display area NA3, for example, as follows: Figure 14 As shown, in this embodiment of the invention, at least a portion of the first electrostatic discharge (ESD) protection connection line 1821 can be located on the side of the second gate drive signal line 17 away from the display area AA. That is, the first ESD protection connection line 1821 is positioned outside the second gate drive signal line 17. This arrangement protects the second gate drive signal line 17 from ESD damage, improving its stability and ensuring accurate display on the display panel 10.

[0100] For example, such as Figure 15 As shown, Figure 15 for Figure 1 Another enlarged schematic diagram of the central area A1 shows that the third non-display area NA3 also includes a first power connection line 19, which is electrically connected to the first pixel row 11 and the second pixel row 12 in the display area AA; the first power connection line 19 can provide power to the first pixel row 11 and the second pixel row 12 as follows: Figure 3 or Figure 4 The first power supply voltage PVEE is shown.

[0101] like Figure 15 As shown, the first power connection line 19 is located on the side of the electrostatic discharge protection circuit 181 away from the display area AA. For example, as... Figure 15As shown, the width of the first power connection line 19 is greater than the width of the second gate drive signal line 17, thereby reducing the resistance of the first power connection line 19 and reducing the voltage drop of the first power supply voltage PVEE during transmission. The first power connection line 19 transmits a constant signal and has a larger line width. Compared with the second gate drive signal line 17, the first power connection line 19 has stronger resistance to electrostatic discharge (ESD). In this embodiment of the invention, by placing the first power connection line 19 on the side of the ESD protection circuit 181 away from the display area AA, the first power connection line 19 can be used to protect the second gate drive signal line 17 from ESD damage, which is beneficial to further improve the stability of the second gate drive signal line 17, thereby ensuring the accurate display of the display panel 10.

[0102] This invention also provides a display device, such as... Figure 16 As shown, Figure 16 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the display module 100 described above. The specific structure of the display module 100 has been described in detail in the above embodiments and will not be repeated here. Of course, Figure 16 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader, in-vehicle display screen or television.

[0103] The display device provided in this embodiment of the invention can reduce or even eliminate the need for a gate driving unit 150 in the third non-display area NA3 by electrically connecting the second pixel row 12 in the display panel to the driving chip 20. This is beneficial for reducing the bezel width of the third non-display area NA3 and narrowing the width difference between the third non-display area NA3 and the second non-display area NA2. For example, the width of the third non-display area NA3 can be made equal to the width of the second non-display area NA2, thereby improving the visual effect of the display panel.

[0104] It should be understood that, without conflict, the above embodiments and features described in the embodiments of the present invention can be combined with each other.

[0105] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A display module, characterized by The display panel comprises a display area and a non-display area, the non-display area comprises a first non-display area, a second non-display area and a third non-display area; the first non-display area and the display area are arranged along a first direction, the second non-display area and the display area are arranged along a second direction, the first direction and the second direction intersect; the third non-display area is located between the first non-display area and the second non-display area, and the third non-display area is arranged corresponding to a corner of the display area; The display area comprises a plurality of first pixel rows and a plurality of second pixel rows, the first pixel rows and the second pixel rows are arranged along the second direction; the second pixel rows are located on one side of the first pixel rows close to the second non-display area; The first non-display area comprises a gate drive circuit, and the first pixel rows are electrically connected to the first gate drive circuit through a first gate drive signal line; The non-display area comprises a driving chip, and the second pixel rows are electrically connected to the driving chip through a second gate drive signal line; The display panel further comprises a bending part, and the bending part is located on one side of the driving chip close to the display area; The driving chip is bent to one side of the display panel away from the light-emitting side through the bending part.

2. The display module according to claim 1, wherein At least part of the second gate drive signal line is located in the display area.

3. The display module according to claim 2, wherein The display area further comprises a plurality of data lines, and the plurality of data lines comprise a first data line, an extension line of the first data line passes through the third non-display area, The display panel further comprises a data connection line electrically connected to the first data line, and at least part of the data connection line is located in the display area. The data connection line comprises a first sub-data connection line extending along the first direction and a second sub-data connection line extending along the second direction; 4. The display module of claim 3, wherein, The second gate drive signal line comprises a first sub-gate drive signal line located at least partially in the display area, an extension line of the first sub-gate drive signal line is offset from the third non-display area, and the first sub-gate drive signal line and the second sub-data connection line are arranged on the same layer.

5. The display module according to claim 1, wherein At least part of the second gate drive signal line is located in the non-display area.

6. The display module according to claim 5, wherein The second gate drive signal line comprises a first sub-connection line, a second sub-connection line and a third sub-connection line electrically connected, and the extension directions of the first sub-connection line, the second sub-connection line and the third sub-connection line intersect; The third non-display area comprises at least part of the first sub-connection line, The included angle between the extension direction of the first sub-connection line and the second direction is less than or equal to 45°.

7. The display module according to claim 5, wherein Two adjacent second gate drive signal lines are located in different film layers.

8. The display module according to claim 1, wherein The third non-display area comprises an electrostatic protection circuit. ​ 9.The display module of claim 8, wherein at least part of the second gate driving signal line is located in the third non-display area. At least part of the electrostatic protection circuit is located on a side of the second gate driving signal line away from the display area. 10.The display module of claim 8, wherein the first gate driving circuit comprises a plurality of cascaded gate driving units, the display panel further comprises a gate driving input signal line, the gate driving input signal line and the gate driving units are electrically connected, and the electrostatic protection circuit is electrically connected with the driving chip and the gate driving input signal line. 11.The display module of claim 10, wherein the third non-display area further comprises a first electrostatic protection connection line, the first electrostatic protection connection line is electrically connected with the driving chip and the electrostatic protection circuit. 12.The display module of claim 11, wherein at least part of the second gate driving signal line is located in the third non-display area, and at least part of the first electrostatic protection connection line is located on a side of the second gate driving signal line away from the display area. 13.The display module of claim 8, wherein the third non-display area comprises a first power supply connection line, the first power supply connection line is electrically connected with the first pixel row and the second pixel row, and the first power supply connection line is located on a side of the electrostatic protection circuit away from the display area. 14.The display module of claim 1, wherein the number n of the second pixel rows satisfies 3≤n≤10. 15.The display module of claim 1, wherein the edge of the third non-display area away from the display area comprises an arc line. The display module of any one of claims 1-15. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 16. A display device comprising: ​

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