Operation method of memory system and memory system

Abstract

The invention provides an operation method of a memory system, which comprises the following steps of: accumulating individual operation times of a plurality of memory blocks in a memory to generate a plurality of accumulated values respectively corresponding to the plurality of memory blocks; judging a difference value between two accumulated values corresponding to a relatively large number of accumulated operations and a relatively small number of accumulated operations in the plurality of accumulated values; and when the difference value is equal to a preset value, carrying out refreshing operation on the longer idle storage block corresponding to the smaller accumulated operation times. Through the method and the system disclosed by the invention, the drift influence caused by bias voltage can be reduced, the problem of data reading errors caused by bias voltage drift can be reduced, and longer power-on data maintenance time can be supported.

Description

Technical Field

[0001] This application generally relates to the field of electronic devices, and particularly to an operation method and a storage system for a storage system. Background Art

[0002] Memory is the foundation of information technology. As a candidate for the next-generation non-volatile semiconductor memory, Phase Change Random Access Memory (PCM) has received extensive attention due to its advantages such as high-speed reading, high erasable and writable times, non-volatility, small component size, low power consumption, strong vibration resistance, and radiation resistance, especially 3D PCM. Therefore, with the increase in storage capacity and the development of PCM technology, using PCM as the storage unit of a large-capacity storage system has also become a trend.

[0003] However, how to prevent the stored data in PCM from being affected by the read and write operations of adjacent storage units is an important issue, so there is a need to propose an operation method that can solve these problems. Summary of the Invention

[0004] The purpose of this application is to provide an operation method and a storage system for a storage system, which are used to solve the problem of data drift caused by read and write bias voltages of storage units.

[0005] In a first aspect, this application provides an operation method for a storage system, and the operation method includes:

[0006] Accumulating the individual operation times of multiple storage blocks in a memory to generate multiple accumulated values respectively corresponding to the multiple storage blocks;

[0007] Judging the difference between two of the multiple accumulated values corresponding to the larger accumulated operation times and the smaller accumulated operation times; and

[0008] When the difference is equal to a preset value, performing a refresh operation on the relatively long-idle storage block corresponding to the smaller accumulated operation times.

[0009] Optionally, the method further includes: forming a stack table for storing the multiple accumulated values respectively corresponding to the multiple storage blocks.

[0010] Optionally, the method further includes: after performing the refresh operation on the relatively long-idle storage block, repeating the accumulation and the judgment to determine a second storage block corresponding to the smaller accumulated operation times that meets the preset value as the relatively long-idle storage block, and performing the refresh operation on the relatively long-idle storage block.

[0011] Optionally, the method further includes: after performing the refresh operation on the long-idle storage block, updating the cumulative value corresponding to the long-idle storage block to the cumulative value corresponding to the larger cumulative operation count as the cumulative value after refresh.

[0012] Optionally, the method further includes: after performing the refresh operation on the long-idle storage block, removing the long-idle storage block from the determination until the refresh status of the multiple storage blocks meets a predetermined condition, and then including it in the determination again.

[0013] Optionally, the method further includes:

[0014] setting initial values of the multiple cumulative values respectively corresponding to the multiple storage blocks; and,

[0015] when the multiple storage blocks include N storage blocks and N - 1 of the storage blocks are refreshed, resetting the cumulative values respectively corresponding to all the storage blocks to the initial values.

[0016] Optionally, the method further includes: setting the initial value of the cumulative value to 0, and when each operation is performed, incrementing by 1 the cumulative value of the storage block corresponding to the operation, and the operation includes one of a write operation and a read operation.

[0017] Optionally, the method further includes: setting the initial value of the cumulative value to be greater than or equal to the preset value, and when each operation is performed, decrementing by 1 the cumulative value of the storage block corresponding to the operation, and the operation includes one of a write operation and a read operation.

[0018] Optionally, the method further includes: setting the storage block as an individual storage stack, storage plane, block storage array, page storage array, or storage matrix composed of N * M storage units in the memory, and N and M are positive integers greater than 1, and N is equal to or not equal to M.

[0019] Optionally, the operation method further includes: setting the multiple storage blocks to be located on the same bit line or word line.

[0020] In a second aspect, the present application provides a storage system, the storage system includes:

[0021] a memory having multiple storage blocks;

[0022] a controller connected to the memory for controlling the memory, and the controller is configured to perform the following actions:

[0023] accumulating the individual operation counts of multiple storage blocks in a cumulative memory to generate multiple cumulative values respectively corresponding to the multiple storage blocks;

[0024] determining the difference between two of the cumulative values corresponding to the larger and smaller cumulative operation counts among the multiple cumulative values; and

[0025] when the difference is equal to a preset value, performing a refresh operation on the relatively long-idle storage block corresponding to the smaller cumulative operation count.

[0026] Optionally, the controller further includes a system memory for storing a stack table, and the stack table is used to store the multiple cumulative values respectively corresponding to the multiple storage blocks.

[0027] Optionally, the controller is further configured to: after performing the refresh operation on the relatively long-idle storage block, repeat the accumulation and the determination to determine a second storage block corresponding to a smaller cumulative operation count that meets the preset value as the relatively long-idle storage block, and perform the refresh operation on the relatively long-idle storage block.

[0028] Optionally, the controller is further configured to: after performing the refresh operation on the relatively long-idle storage block, update the cumulative value corresponding to the relatively long-idle storage block to the cumulative value corresponding to the larger cumulative operation count as the cumulative value after refresh.

[0029] Optionally, the controller is further configured to: after performing the refresh operation on the relatively long-idle storage block, exclude the relatively long-idle storage block from the determination until the refresh status of the multiple storage blocks meets a predetermined condition and then include it in the determination again.

[0030] Optionally, the memory controller is further configured to: set the initial values of the multiple cumulative values respectively corresponding to the multiple storage blocks; and when there are N storage blocks among the multiple storage blocks and N - 1 of the storage blocks are refreshed, reset the cumulative values respectively corresponding to all the storage blocks to the initial values.

[0031] Optionally, the controller is further configured to: set the initial value of the cumulative value to 0, and when each operation is performed, increment the cumulative value of the corresponding storage block of the operation by 1, and the operation includes one of a write operation and a read operation.

[0032] Optionally, the controller is further configured to: set the initial value of the cumulative value to be greater than or equal to the preset value, and each time an operation is performed, decrement the cumulative value of the corresponding storage block of the operation by 1, and the operation includes one of a write operation and a read operation.

[0033] Optionally, the storage block is an individual storage stack, storage plane, block storage array, page storage array, or storage matrix composed of N*M storage cells in the memory, and N and M are positive integers greater than 1, and N is equal to or not equal to M.

[0034] Optionally, the multiple storage blocks are located on the same bit line or word line.

[0035] Through the operation method of the storage system and the storage system provided by the present application, the influence of bias drift on the system storage block can be effectively reduced, the read error caused by excessive drift due to bias can be prevented, and the power-on data retention time can be improved.

[0036] The operation method of the storage system and the storage system provided by the present application can further reduce the difference in the maximum write times of the storage blocks on the same word line (WL) or bit line (BL) through the configuration of the storage blocks and in cooperation with the wear leveling operation. Description of the Drawings

[0037] The following will, by way of detailed description of the specific embodiments of the present application in conjunction with the drawings, make the technical solutions and other beneficial effects of the present application obvious.

[0038] Figure 1 is a functional block diagram of a storage system according to some embodiments of the present application.

[0039] Figure 2 is a functional block diagram of the peripheral circuit of a memory according to some embodiments of the present application.

[0040] Figure 3a is a circuit schematic diagram of a storage array of a memory according to some embodiments of the present application.

[0041] Figure 3b is a structural diagram of a phase change memory cell according to some embodiments of the present application.

[0042] Figure 4 is a distribution diagram of threshold voltage drift of a memory cell according to some embodiments of the present application.

[0043] Figure 5 is a step schematic diagram of an operation method of a storage system according to some embodiments of the present application.

[0044] Figure 6 It is a schematic diagram of a storage block in a memory provided according to some embodiments of the present application.

[0045] Figure 7 It is a schematic diagram of a storage block under secondary addressing in a memory provided according to some embodiments of the present application.

[0046] Figure 8 It is a schematic diagram of a stack provided according to some embodiments of the present application.

[0047] Figure 9 It is a further step schematic diagram of an operation method of a storage system provided according to some embodiments of the present application. Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0049] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component without departing from the scope of the present application.

[0050] It should be understood that when a component is said to be "on" another component or "connected" to another component, it can be directly on another component or connected to another component, or there may also be inserted components. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0051] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer can extend over the entire underlying or overlying structure, or can have a scope smaller than the scope of the underlying or overlying structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically, and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above, and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers, contact layers, and one or more dielectric layers.

[0052] It should be noted that the diagrams provided in the embodiments of the present application only illustrate the basic concept of the present application in a schematic manner. Although only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation, the types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0053] In this article, directions are represented by Cartesian coordinates. With the substrate as a reference, the "Z" direction represents the first direction, which is perpendicular to the substrate; the "X" direction represents the second direction parallel to the substrate; and the "Y" direction represents the third direction parallel to the substrate and perpendicular to the X direction.

[0054] First, please refer to Figure 1 , Figure 1 which is a functional schematic block diagram of a storage system provided according to some embodiments of the present application.

[0055] As Figure 1 shown, a storage system 1 provided according to some embodiments of the present application includes a controller 100 and a memory 200; the controller 100 is electrically connected to the memory 200 and is used to control the memory 200. The memory 200 further controls the storage array 10 in the memory through the peripheral circuit 20 in the memory 200, and various operations can be performed on each storage unit (not shown) in the storage array.

[0056] In some embodiments, the storage system 1 can be implemented as, for example, a memory module, a high-end SSD, a high-bandwidth memory (HBM), a universal flash storage (UFS) device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of SD, mini SD, and micro SD, a storage device of the personal computer memory card international association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card, or a memory stick, etc.

[0057] As Figure 2 shown, the memory 200 mainly includes a storage array 10 and a peripheral circuit 20 that connects to and controls the storage array 10. The peripheral circuit 20 generally includes at least a row decoder 210, a word line voltage generator 211, a word line driver 212, a column decoder 220, a bit line driver 222, a bit line voltage generator 221, a reference current / voltage generator 261, a sense amplifier comparator 260, and a logic control module 230 that is connected to the foregoing devices and is used to receive operation instructions to control the foregoing devices.

[0058] The row decoder 210 receives a row address signal from the bus 290, decodes the row address signal, and selects an addressed word line.

[0059] The word line driver 212 is connected to a plurality of word lines WL<0:m>, a word line voltage generator 211, and the row decoder 210. The word line driver 212 receives a row address selection signal and a word line drive voltage, and outputs the word line drive voltage to the plurality of word lines WL according to the row address selection signal. <m>At least one row of memory cells connected to at least one word line WL.

[0060] The bit line driver 222, the bit line voltage generator 221, and the column decoder 220 belong to the column driving circuit and are connected as Figure 2 shown. The bit line voltage generator 221 and the column decoder 220 are connected to the logic control module 230 to receive the control of the logic control module 230.

[0061] The column decoder 220 receives the column address signal and decodes the column address signal to select the addressed bit line to which the operation target memory cell is connected. The bit line voltage generator 221 generates the voltage required for each selected bit line BL and outputs the set voltage to each corresponding selected bit line BL.

[0062] The bit line driver 222 is connected to a plurality of bit lines BL, the bit line voltage generator 221, and the column decoder 220. The bit line driver 222 receives the bit line voltage and the column address selection signal, and outputs the set bit line voltage to the plurality of bit lines BL according to the column address selection signal <n>At least one column of memory cells connected to at least one bit line BL.

[0063] The peripheral circuit 20 further includes a sense amplifier comparator 260, a reference current / voltage generator 261, a data latch 270, etc. The sense amplifier comparator 260 is connected to the reference current / voltage generator 261 and multiple bit lines BL<0:n> and is connected to the data latch 270. The sense amplifier comparator 260 is used to compare with the reference value generated by the reference current / voltage generator 261 after receiving the read data when reading data, determine the data stored in the selected memory cell, and then store the data in the data latch 270. Together with the data read from other bit lines, it passes through the input / output interface 280 and is output to the data bus 290 for output.

[0064] Based on the structural design of the peripheral circuit 20 of the above memory, the operations of the memory can include an erase operation, a read operation, a program operation, or a set and reset operation. Moreover, when performing the foregoing various operations, the controller 100 will receive logical address information according to an L2P (logical address to physical address) mapping table, and according to the L2P mapping table, send out the physical address. After receiving the physical address, the peripheral circuit 20 will select appropriate word lines WL and bit lines BL through the row decoder 210 and the column decoder 220, and address the memory cells in the memory array 10, and then bias the selected word lines WL and bit lines BL through the word line driver 212 and the bit line driver 222, so as to perform various operations on the selected memory cells. Moreover, when addressing, in some embodiments, the logical addresses are arranged in the order of the word line WL and the bit line BL addresses. For example, Figure 3a As shown in a memory array, it will first address on a WL, traverse different BLs, and then switch to the next WL for addressing.

[0065] It can be understood that although the memory 200 and the controller 100 are collectively referred to as a storage system here, in some embodiments, the controller 100 can also be integrated with the memory 200 on one chip. Therefore, the so-called storage system here can actually be a memory, not limited to the naming of the so-called system.

[0066] Please continue to refer to Figure 3a , Figure 3a FIG. is a circuit diagram showing an example of the memory array 10 as a memory according to some embodiments of the present application. The memory array 10 includes a plurality of memory cells 11 arranged in a multi-row and multi-column array, and word lines WL and bit lines BL respectively connected to the plurality of memory cells 11 in multiple rows and columns. Each row of memory cells includes a plurality of memory cells 11 arranged along the row direction X. Each column of memory cells includes a plurality of memory cells 11 arranged along the column direction (i.e., the second direction Y). Figure 3a Only the memory cells of three rows WLn-1 to WLn+1 and three columns BLn-1 to BLn+1 are schematically shown, where n represents any positive integer greater than 2. In fact, the number of rows and columns of memory cells in the memory depends on its storage capacity.

[0067] It should be understood that the memory cells in the memory array can be memory cells of various types of structures, such as floating gate memory cells, nitride layer structure (ONO) memory cells, resistive memory cells (RRAM), phase change structure memory cells (PCM / PCRAM / SOM), etc. The present application does not limit this, however, the present application is particularly applicable to phase change structure memory cells. Therefore, the phase change structure memory cell PCM will be taken as an example for illustration below, but it should be understood that it is not limited thereto.

[0068] Figure 3a The illustrated memory cell is a phase change memory cell 11. The phase change memory cell 11 includes a bidirectional threshold switch ((Ovonic Threshold Switch, OTS) 111 and a phase change memory cell (PCM cell) 112 connected in series between the word line WL and the bit line BL. The bidirectional threshold switch ((Ovonic Threshold Switch, OTS) 111 and the phase change memory cell (PCM cell) 112 are both composed of phase change materials. However, in some technologies, since the phase change memory cell 112 is used as the threshold setting for data storage, in this embodiment, the two phase change materials in the memory cell 11 are respectively called the bidirectional threshold switch (OTS) 111 and the phase change memory cell (PCM storage cell) 112.

[0069] Figure 3b It is a schematic structural diagram of the memory cell provided by some embodiments of the present application. As Figure 3b shown, the structure of the phase change memory cell provided by some embodiments of the present application includes: a top electrode 11a and a bottom electrode 11b respectively connected to the word line WL and the bit line BL, and a phase change memory cell 112, an intermediate electrode 11c, and a bidirectional threshold switch (OTS) 111 located between the top electrode 11a and the bottom electrode 11b. It should be understood that in some embodiments, the intermediate electrode 11c may not be provided. Therefore, the present application is not limited to the structure disclosed herein.

[0070] The phase change memory cell 112 includes one or more phase change materials such as those based on germanium-antimony-tellurium (Ge-Sb-Te, GST), and one example thereof can be Ge2Sb2Te5. The phase change materials that are currently used more often are chalcogenides (represented by Intel) and synthetic materials containing germanium, antimony, and tellurium (GST), such as Ge2Sb2Te5. The phase change material can have a large resistivity contrast between different phases (e.g., crystalline phase and amorphous phase). For example, the phase change material can exhibit a relatively low resistivity in the crystalline phase but a relatively high resistivity in the amorphous phase, and the resistivity of the phase change material in the amorphous phase can be hundreds to thousands of times higher than that in the crystalline phase.

[0071] When the phase change material is heated, it can switch between different phases to achieve the writing of information (data) (including setting and resetting). In this embodiment, the electrodes 11a and 11c can heat the phase change memory cell 112 via the OTS 111 to change the phase of the heated region 112f in the phase change cell 112, thereby reducing the resistance of the phase change memory cell 112 (setting). The top electrode 11a and the bottom electrode 11b are oppositely arranged, and their positions can be interchanged and cooperate with the outer bit line BL and word line WL to overlap, thereby forming a 3D phase change memory.

[0072] In some embodiments, the OTS device is composed of a phase change material such as Ge-Te-As-Si. At this time, the threshold voltage Vth of the OTS 111 will be controlled by the polarity of the applied voltage and change. More specifically, the threshold voltage change ΔVth occurs with the change of the applied voltage polarity. Using this ΔVth, even without the phase change cell 112, setting and resetting can still be achieved, and the OTS device is independently used as a binary storage device. Therefore, in this example, the OTS 111 is called a SOM memory cell (selector only memory) or an SSM memory cell (self-selecting memory).

[0073] Therefore, it can be understood that the phase change memory (PCM) described in this application includes various deformed PCMs, such as the Xpoint type PCM, and the selector only memory SOM (selector only memory) or SSM (self-selecting memory) composed of the foregoing OTS, etc., and includes various phase change memories arranged in two dimensions (2D) and three dimensions (3D), as well as PCMs with single-pole or multi-level storage.

[0074] Furthermore, in further research of the present application, it is understood that when performing read and write operations on a certain cell, for example Figure 3a for the storage unit 11(S), a relatively high voltage bias, such as Vhh and Vll, will be applied to the corresponding WLn (word line) and BLn (bit line); for the unselected WLn+1 / n-1 and BLn+1 / n-1, a zero bias or a low bias, such as Vuw and Vub, will be maintained to ensure the non-conducting state.

[0075] Also, by way of example, for instance, when selecting to perform a write operation on Figure 3a the storage unit 11(s), a write voltage Vwrite will be applied to the corresponding BLn (bit line), and a zero bias V0 will be applied to the WLn (bit line); for the unselected adjacent storage units 11(a) and 11(b), a low bias, such as Vwrite / 2, will be applied to the corresponding word line and bit line WLn+1 / n-1 and BLn+1 / n-1. For other unselected cells on the same WLn and BLn as the selected storage unit 11(s), although they will not be selected to conduct or be written, there will also be a certain bias across the storage unit 11, and these storage units 11 will have the problem of bias shift (biasshit). That is, the threshold voltage shift caused by the operating bias on the same bit line and word line to other storage units.

[0076] Figure 4 It shows the Vth distributions of set and reset when the bias drift effect of the threshold voltage (Vth) occurs in the research of the present application. Among them, the curve on the left of Vread represents the Vth distribution of set, the curve on the right of Vread represents the Vth distribution in the reset state, and the solid line B0 represents the case without bias drift. As the number of operations on the same word line WLn or bit line BL increases, the corresponding Vth distributions of set and reset states will drift as shown by the dashed lines B1 and B2. The bias offset and the number of operations (i.e., the compressive stress stress) are strongly correlated. The more the number of operations, the greater the influence of the offset drift. Due to the existence of bias drift, the RWM (read window margin) that can accurately distinguish the set and reset states is greatly reduced, that is, it is easy to cause reading errors.

[0077] Moreover, in some embodiments of three-dimensional phase change memories, in the case of a 2k WL x 4k BL x 2 stack architecture, due to the existence of a certain bias voltage on the same word line / bit line (WL / BL), for the memory cells on the same word line WL, it will affect 4k memory cells above and below respectively, while for the operation on the same bit line BL, it will affect 2k memory cells, resulting in threshold voltage shift and causing problems with power on retention.

[0078] In some embodiments, for the problems of bias drift and power on retention, there are those who adopt methods such as read retry or ECC (error correction), but the increase in the number of read retries will sacrifice the performance of the system and there is room for improvement.

[0079] Therefore, according to some embodiments of the present application, as Figure 5 shown, the present application further provides an operation method for a storage system, including:

[0080] Step S1: Accumulate the individual operation times of multiple storage blocks in the memory, and generate multiple accumulated values respectively corresponding to the multiple storage blocks;

[0081] Step S2: Judge the difference between the two accumulated values corresponding to the larger accumulated operation times and the smaller accumulated operation times among the multiple accumulated values; and

[0082] Step S3: When the difference is equal to a preset value, perform a refresh operation on the relatively long-idle storage block corresponding to the smaller accumulated operation times.

[0083] Specifically, as Figure 6 shown, in a storage array 10 of a memory, it includes multiple storage blocks 10b, and each storage block 10b has a corresponding block address. Each storage block 10b may include a plurality of the aforementioned memory cells 11. The number of storage blocks 10b in the storage array 10 may be n*n, and the serial numbers may be ROW1-1, ROW1-2,..., ROW1-n,..., ROWn-1,..., ROWn-n.

[0084] In some embodiments, the storage block 10b is set as a matrix composed of N*M memory cells in the memory, and N and M are positive integers greater than 1, and N is equal to or not equal to M. Specifically, as Figure 7 shown, Figure 7 Particularly, it shows a schematic diagram of a storage block under secondary addressing in a memory provided according to some embodiments of the present application. N and M can both be 64, that is, 4096 storage units form a storage block 10b. And 4096 storage blocks 10b form a storage array 10. In Figure 7 In the illustrated example, the storage block 10b can be selected by the high bits in the address, that is, ROW0 to ROW4096, and the storage unit can be selected by the low bits in the address, that is, ADD0 to ADD4096, so as to achieve secondary addressing, and the management of refreshing is performed through the storage block 10b, that is, ROW to ROW4096.

[0085] However, it can be understood that the division of the illustrated storage block 10b is not limited to the foregoing example. In some embodiments, the storage block 10b can also be set to be divided in units of individual storage stacks, storage planes, block storage arrays, or page storage arrays in the memory.

[0086] Further, in some embodiments, the multiple storage blocks 10b for which cumulative values are compared are set such that multiple storage blocks 10b on the same bit line or word line are grouped together, and the cumulative values of each storage block within a group are compared. Since each read / write operation affects the storage units on the same bit line or word line, through such a configuration, comparison can be performed individually for the storage blocks on the same word line or bit line, and when the number of write operations received by the storage blocks on the same word line or bit line differs too much, immediate refreshing remedies can be taken to prevent data from being scrambled.

[0087] Specifically, as Figure 7 shown, the cumulative values can be compared between the storage block numbers ROW0 to ROW63 as a range, and then the cumulative values can be compared between the storage block numbers ROW64 to ROW127 as a range.

[0088] In some embodiments, the method further includes forming a stack table for storing the multiple cumulative values respectively corresponding to the multiple storage blocks.

[0089] Specifically, as Figure 8 As shown, the stack table 300 stores a plurality of cumulative values respectively corresponding to the plurality of storage blocks 10b. Moreover, the initial value of each of the plurality of storage blocks 10b at the beginning can be 0 or, for example, 2000. For each operation, the cumulative value of the corresponding storage block of the operation is incremented by 1 (with 0 as the initial value) or decremented by 1 (with, for example, 2000 as the initial value), that is, the count value can count up or down. That is, when the initial value is set to 0, for each operation, the cumulative value of the corresponding storage block of the operation is incremented by 1. When the initial value is set to be greater than or equal to the preset value, for each operation, the cumulative value of the corresponding storage block of the operation is decremented by 1, and the operation includes one of a write operation and a read operation.

[0090] In Figure 8 the example shown, the sorting is not performed according to the cumulative value, but according to the storage block number. However, in some embodiments, it is possible to sort the stack table according to the magnitude of the cumulative value.

[0091] As Figure 5 described in the foregoing steps S2 and S3 shown, when the difference between the cumulative values corresponding to the cumulative operation times with more and less cumulative operation times among the plurality of cumulative values is equal to the preset value, the storage block corresponding to the less cumulative operation times is set as the relatively long-idle storage block, and a refresh operation is performed on the relatively long-idle storage block.

[0092] Specifically, taking the example shown in Figure 8 as an example, if the preset value is set to 2000, then in the stack table, there is a cumulative value of 2000 times for the storage block ROW1-1 and a cumulative value of 0 times for the storage block ROWn-n. That is, when the difference is equal to the preset value 2000, the condition described in step S3 is met, and an action of performing a refresh operation on the storage block ROWn-n, which is called the relatively long-idle storage block corresponding to the less cumulative operation times (0), is performed. The refresh operation can use various feasible methods in the prior art, and will not be elaborated here.

[0093] Also, in some embodiments, as shown in Figure 9 it is optional that the method further includes:

[0094] After performing the refresh operation on the relatively long-idle storage block, return to steps S1 and S2, and repeat the accumulation and judgment for each storage block 10b to determine the second storage block corresponding to the less cumulative operation times that meets the preset value as the relatively long-idle storage block, and perform the refresh operation on the relatively long-idle storage block.

[0095] Specifically, for example, after refreshing the relatively long-idle storage block ROWn-n, the cumulative value of the storage block ROW1-1 with a relatively large number of cumulative operation times reaches 2010. In addition to the aforementioned old relatively long-idle storage block ROWn-n, the cumulative value of the second storage block with a relatively small number of cumulative operation times, such as ROWn-1, reaches 10. That is, a second storage block ROWn-1 corresponding to a relatively small number of cumulative operation times that meets the preset value of 2000 appears, and it is used as the new relatively long-idle storage block, and then the refresh operation is performed on the new relatively long-idle storage block ROWn-1.

[0096] It should be noted here that since steps S1 - S3 are repeated steps, for the convenience of description here, whether it is an old relatively long-idle storage block or a new relatively long-idle storage block, it is all called a relatively long-idle storage block. However, it should be understood that the relatively long-idle storage block will have new and old distinctions according to different steps. But in a loop of steps S1 - S3 that has not returned to step S1, the relatively long-idle storage block referred to will be the same relatively long-idle storage block. Also, the meaning of the aforementioned sentence "in addition to the aforementioned old relatively long-idle storage block" is because in some embodiments, after the old relatively long-idle storage block ROWn-n is refreshed, the judgment of the cumulative value of the old relatively long-idle storage block ROWn-n can be excluded. As for the exclusion method, there are many possibilities, which are further described as follows.

[0097] In some embodiments, as Figure 9 shown, after step S3 of the method, it may optionally include:

[0098] Step S31a: After performing the refresh operation on the relatively long-idle storage block, update the cumulative value corresponding to the relatively long-idle storage block to the cumulative value corresponding to the relatively large number of cumulative operation times as the cumulative value after refresh.

[0099] Specifically, as in the example described above, after the storage block of the relatively long-idle storage block ROWn-n with the relatively small number of cumulative operation times (0) is refreshed, the cumulative value of the relatively long-idle storage block ROWn-n is set to 2000, that is, the cumulative value of the relatively large number of cumulative operation times. In this way, even if the relatively long-idle storage block ROWn-n is not excluded from the comparison object of the cumulative value, because the cumulative value of the relatively long-idle storage block ROWn-n is set to 2000, the difference from the cumulative value of the relatively large number of cumulative operation times of 2000 will be the smallest, becoming 0, and it will be the storage block with the smallest difference compared to other storage blocks 10b, and it will not fall into the refresh process soon and will not be regarded as an object to be refreshed.

[0100] Moreover, regarding the disposal method of the relatively long-idle storage block ROWn-n after being refreshed, in addition to the exceptions shown in the previous step S31a, in some embodiments, the operation method may alternatively include:

[0101] Step S31b: After performing the refresh operation on the relatively long-idle storage block, exclude the relatively long-idle storage block from the accumulation and judgment steps S1 and S2 until the refresh status of the multiple storage blocks meets a predetermined condition, and then it is included in the accumulation and judgment steps again.

[0102] Specifically, in some embodiments, it is not necessary to modify the accumulated value corresponding to the relatively long-idle storage block ROWn-n to 2000 as described in the previous step S31a, but directly exclude the relatively long-idle storage block ROWn-n from the next accumulated value comparison object.

[0103] As for when to include the relatively long-idle storage block ROWn-n in the accumulated value comparison object again, it can be determined according to a predetermined condition. For example, this so-called predetermined condition can be a predetermined condition that until half of the multiple storage blocks have been refreshed, it is included in the judgment again. Or for another example, this so-called predetermined condition can be that when the multiple storage blocks include N storage blocks, after N-1 storage blocks have been refreshed, it is included in the judgment again; that is, except for the storage block with more accumulated operation times, all other storage blocks have been refreshed.

[0104] In some embodiments, after the operation mode of step 31b, when the relatively long-idle storage block ROWn-n or all storage blocks are to be included in the judgment again, as Figure 9 shown, it may further include:

[0105] Step S32: Reset the accumulated value corresponding to the relatively long-idle storage block or all the storage blocks to the initial value.

[0106] Specifically, for example, reset the accumulated value of the relatively long-idle storage block ROWn-n or the accumulated values of all storage blocks to the initial value of 0 or 2000.

[0107] It can be understood that although the above examples are for the disposal of the relatively long-idle storage block after being refreshed in one round, the same disposal method can also be applied to the second round, the third round, the fourth round... to the N-1th round of refreshing. That is, after each storage block is refreshed, it can choose to update the accumulated value or be excluded from the objects of accumulation and comparison.

[0108] Also, it can be understood that when the cumulative value is an upward count of +1, it is easy to understand that the cumulative value is the upward count value itself. However, when the cumulative value is a downward count of -1, the cumulative operation count here does not equal the downward count value itself, but rather the difference between the downward count value and the initial value. For example, when the initial value is 2000 or a larger value and a downward count is performed, when the downward count value reaches 500, the so-called cumulative operation count here refers to the 1500 times obtained from 2000 - 500, rather than the value of 500. In this way, when making a comparison and judgment of the multiple cumulative values, the statement "judging the difference between the two cumulative values corresponding to the larger and smaller cumulative operation counts among the multiple cumulative values" can be applied to the scenario of upward or downward counting.

[0109] Next, taking downward counting as an example, an embodiment of updating the cumulative value will be described. For example, if the initial value is 2000 and the preset value is 1000, when the downward count value with the smaller cumulative operation count reaches 1500 and there are 500 cumulative operation counts, and if the downward count value with the larger cumulative operation count has reached 500 and there are 1500 cumulative operation counts, the difference between the cumulative values corresponding to the larger and smaller cumulative operation counts reaches the preset value of 1000. At this time, a refresh operation is performed on the storage block where the downward count value reaches 1500 and has the smaller cumulative operation count, and the downward count value of the older idle storage block with the smaller cumulative operation count is set to 500, which is the same as the downward count value of 500 corresponding to the larger cumulative operation count, so it will not be refreshed soon.

[0110] Also, in some embodiments, it can be understood that the refreshed cumulative value is not limited to being set to the cumulative value corresponding to the larger cumulative operation count, and can also be any appropriate value, such as the smaller cumulative value. Also, it can be understood that for the approach of excluding the compared storage blocks that have been refreshed, it can also be that after a certain number of storage blocks have been refreshed, that is, not necessarily the previously mentioned N - 1, but for example N / 2, all the cumulative values of the storage blocks can be returned to the initial value, and all the storage blocks can be re - included in the next round of comparison.

[0111] Through the operation method of the storage system provided by the present application described above, it can effectively reduce the influence of bias drift on the system storage blocks, prevent read errors caused by excessive threshold voltage drift of the storage cells due to bias, and improve the power - on data retention time.

[0112] The operation method of the storage system provided by this application can further reduce the difference in the maximum write counts of the storage blocks on the same word line (WL) or bit line (BL) through the configuration of the storage blocks and in cooperation with wear leveling operations.

[0113] According to the operation method of the storage system provided by some of the foregoing embodiments, some embodiments of this application further correspondingly provide a storage system, including:

[0114] A memory, including a storage array composed of a plurality of storage units; and

[0115] A controller, electrically connected to the memory, for controlling the memory, and the controller is configured to perform the following actions:

[0116] Accumulate the individual operation counts of a plurality of storage blocks in the memory to generate a plurality of cumulative values respectively corresponding to the plurality of storage blocks;

[0117] Judge the difference between two of the cumulative values corresponding to the larger cumulative operation count and the smaller cumulative operation count among the plurality of cumulative values; and

[0118] When the difference is equal to a preset value, perform a refresh operation on the relatively long-idle storage block corresponding to the smaller cumulative operation count.

[0119] Specifically, as shown in Figure 1 the structure, in the controller 100, the foregoing configuration can be completed through various modules, and the actions of accumulation, judgment, and refresh can be completed.

[0120] In some embodiments, the controller further includes a system memory for storing a stack table, and the stack table is used to store the plurality of cumulative values respectively corresponding to the plurality of storage blocks.

[0121] In some embodiments, the controller is further configured to: after performing the refresh operation on the relatively long-idle storage block, repeat the accumulation and the judgment to determine a second storage block corresponding to the smaller cumulative operation count that meets the preset value as the relatively long-idle storage block, and perform the refresh operation on the relatively long-idle storage block.

[0122] In some embodiments, the controller is further configured to: after performing the refresh operation on the relatively long-idle storage block, update the cumulative value corresponding to the relatively long-idle storage block to the cumulative value corresponding to the larger cumulative operation count as the cumulative value after refresh.

[0123] In some embodiments, the controller is further configured to: after performing the refresh operation on the long-idle storage block, exclude the long-idle storage block from the determination until the refresh status of the multiple storage blocks meets a predetermined condition, and then include it in the determination again.

[0124] In some embodiments, the memory controller is further configured to: set initial values of the multiple cumulative values respectively corresponding to the multiple storage blocks; and when the multiple storage blocks include N storage blocks and N - 1 of the storage blocks are refreshed, reset the cumulative values respectively corresponding to all the storage blocks to the initial values.

[0125] In some embodiments, the controller is further configured to: set the initial value of the cumulative value to 0, and when each operation is performed, increment by 1 the cumulative value of the storage block corresponding to the operation, and the operation includes one of a write operation and a read operation.

[0126] In some embodiments, the controller is further configured to: set the initial value of the cumulative value to be greater than or equal to the preset value, and when each operation is performed, decrement by 1 the cumulative value of the storage block corresponding to the operation, and the operation includes one of a write operation and a read operation.

[0127] In some embodiments, the storage block is an individual storage stack, storage plane, block storage array, page storage array, or storage matrix composed of N * M storage cells in the memory, and N and M are positive integers greater than 1, and N is equal to or not equal to M.

[0128] In some embodiments, the multiple storage blocks are located on the same bit line or word line.

[0129] The operations of these configurations have been described in the corresponding operation methods described above, and can be implemented in conjunction with the software and firmware of the controller, so they will not be repeated here. For specific content, please refer to the above description.

[0130] Through the storage system disclosed in the present application, the beneficial effects corresponding to the various operation methods and configurations described above can also be achieved, that is, not only can the influence of bias drift be reduced, which helps to reduce the problem of bias drift, and thus longer power-on data retention time can be supported.

[0131] The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.< / n> < / m>

Claims

1. A method for operating a storage system, characterized in that: The operation method comprises: Accumulating the number of individual operations of a plurality of storage blocks in the memory to generate a plurality of accumulated values ​​respectively corresponding to the plurality of storage blocks; Determine a difference between two of the accumulated values ​​corresponding to a larger accumulated operation number and a smaller accumulated operation number among the plurality of accumulated values; and When the difference is equal to a preset value, a refresh operation is performed on the longer idle storage block corresponding to the smaller cumulative operation times.

2. The operating method according to claim 1, characterized in that: The method further comprises: A stack table is formed to store the plurality of accumulated values ​​respectively corresponding to the plurality of storage blocks.

3. The operating method according to claim 1, characterized in that: The method further comprises: After the refresh operation is performed on the longer idle storage block, the accumulation and the judgment are repeated to determine a second storage block that meets the preset value and corresponds to a smaller number of accumulated operations as the longer idle storage block, and the refresh operation is performed on the longer idle storage block.

4. The operating method according to claim 1, characterized in that: The method further comprises: After the refresh operation is performed on the longer idle storage block, the accumulated value corresponding to the longer idle storage block is updated to an accumulated value corresponding to the larger accumulated operation times as a refreshed accumulated value.

5. The operating method according to claim 1, characterized in that: The method further comprises: After the refresh operation is performed on the longer idle storage blocks, the longer idle storage blocks are excluded from the judgment until the refresh status of the plurality of storage blocks meets a predetermined condition, and then they are included in the judgment again.

6. The operating method according to claim 2, characterized in that: The method further comprises: Setting initial values ​​of the plurality of accumulated values ​​respectively corresponding to the plurality of storage blocks; and When the plurality of storage blocks include N storage blocks, and N-1 storage blocks are refreshed, the accumulated values ​​corresponding to all the storage blocks are reset to the initial values.

7. The operating method according to claim 2, characterized in that: The method further comprises: The initial value of the accumulated value is set to 0, and each time the operation is performed, the accumulated value of the storage block corresponding to the operation is increased by 1, and the operation includes one of a write operation and a read operation.

8. The operating method according to claim 2, characterized in that: The method further comprises: The initial value of the accumulated value is set to be greater than or equal to the preset value. Each time the operation is performed, the accumulated value of the storage block corresponding to the operation is -1, and the operation includes one of a write operation and a read operation.

9. The operating method according to claim 1, characterized in that: The method further comprises: The storage block is set as an individual storage stack, storage plane, block storage array, page storage array, or a storage matrix composed of N*M storage units in the memory, and N and M are positive integers greater than 1, and N is equal to or not equal to M.

10. The operating method according to claim 1, characterized in that: The operation method further includes: The plurality of memory blocks are set to be located on the same bit line or word line.

11. A storage system, characterized in that: The storage system comprises: a memory having a plurality of memory blocks; and A controller is connected to the memory and is used to control the memory, and the controller is configured to perform the following actions: Accumulating the number of individual operations of a plurality of storage blocks in the memory to generate a plurality of accumulated values ​​respectively corresponding to the plurality of storage blocks; Determine a difference between two of the accumulated values ​​corresponding to a larger accumulated operation number and a smaller accumulated operation number among the plurality of accumulated values; and When the difference is equal to a preset value, a refresh operation is performed on the longer idle storage block corresponding to the smaller cumulative operation times.

12. The storage system according to claim 11, wherein: The controller further includes a system memory for storing a stack table, wherein the stack table is used to store the plurality of accumulated values ​​respectively corresponding to the plurality of storage blocks.

13. The storage system according to claim 11, wherein: The controller is also configured to: After the refresh operation is performed on the longer idle storage block, the accumulation and the judgment are repeated to determine a second storage block that meets the preset value and corresponds to a smaller number of accumulated operations as the longer idle storage block, and the refresh operation is performed on the longer idle storage block.

14. The storage system according to claim 11, wherein: The controller is also configured to: After the refresh operation is performed on the longer idle storage block, the accumulated value corresponding to the longer idle storage block is updated to an accumulated value corresponding to the larger accumulated operation times as a refreshed accumulated value.

15. The storage system according to claim 11, wherein: The controller is also configured to: After the refresh operation is performed on the longer idle storage blocks, the longer idle storage blocks are excluded from the judgment until the refresh status of the plurality of storage blocks meets a predetermined condition, and then they are included in the judgment again.

16. The storage system according to claim 13, wherein: The memory controller is also configured as: Setting initial values ​​of the plurality of accumulated values ​​respectively corresponding to the plurality of storage blocks; as well as When the plurality of storage blocks include N storage blocks, and N-1 storage blocks are refreshed, the accumulated values ​​corresponding to all the storage blocks are reset to the initial values.

17. The storage system according to claim 13, wherein: The controller is also configured to: The initial value of the accumulated value is set to 0, and each time the operation is performed, the accumulated value of the storage block corresponding to the operation is increased by 1, and the operation includes one of a write operation and a read operation.

18. The storage system according to claim 11, wherein: The controller is also configured to: The initial value of the accumulated value is set to be greater than or equal to the preset value. Each time the operation is performed, the accumulated value of the storage block corresponding to the operation is -1, and the operation includes one of a write operation and a read operation.

19. The storage system according to claim 11, wherein: The storage block is an individual storage stack, storage plane, block storage array, page storage array, or a storage matrix composed of N*M storage units in the memory, and N and M are positive integers greater than 1, and N is equal to or not equal to M.

20. The storage system according to claim 11, wherein: The plurality of memory blocks are located on the same bit line or word line.

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