Semiconductor device

Abstract

A semiconductor device includes a semiconductor chip in which a plurality of circuit blocks are formed. The plurality of circuit blocks includes a plurality of logic circuits. Each logic circuit of the plurality of logic circuits includes an inverter circuit. After pre-charging by the trigger signal, the inverter circuit outputs a signal according to a result of a logical operation of the first signal and the second signal.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2023-206855, filed on December 7, 2023, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device, such as a semiconductor device equipped with an exclusive OR circuit (hereinafter also referred to as an XOR circuit). Background Art

[0004] Semiconductor devices are becoming increasingly highly integrated. As the degree of integration increases, the probability of soft errors occurring due to radiation such as alpha rays becomes higher. For example, when a semiconductor device is equipped with a memory, there is a concern that the data stored in the memory may be changed (destroyed) by soft errors, resulting in a reduction in the reliability of the stored data.

[0005] The disclosed technologies are listed below.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2006-14156

[0007] In order to improve the reliability of stored data, a semiconductor device having an ECC (error correction code) circuit is provided in practice. In this case, the ECC circuit can detect the destruction of stored data and further correct the destroyed data, thereby improving the reliability of the stored data. Summary of the Invention

[0008] The ECC circuit is composed of many XOR circuits. An example of an XOR circuit is shown in Patent Document 1 Figure 7 . In Patent Document 1, a two-input XOR circuit (for example Figure 7 the logic unit 20 therein) is composed of two parallel-connected P-channel series circuits between the output terminal (node N0) and the power supply voltage (VCC), and two parallel-connected N-channel series circuits between the output terminal (N0) and the ground voltage (GND).

[0009] In this text, each of the two P-channel series circuits consists of two P-channel field effect transistors (hereinafter referred to as PMOSFETs or P-type MOS transistors), where an input signal is supplied to the gate electrode and the source-drain paths are connected in series. Similarly, each of the two N-channel series circuits consists of two N-channel field effect transistors (hereinafter referred to as NMOSFETs or N-type MOS transistors), where an input signal is supplied to the gate electrode and the source-drain paths are connected in series. In this specification, when P-type MOS transistors and N-type MOS transistors are commonly referred to, they are simply called MOSFETs or MOS transistors.

[0010] In the case where the logical values of the two inputs of the XOR circuit match, one of the two N-channel series circuits becomes conductive, while in the case of a mismatch, one of the two P-channel series circuits becomes conductive. Thus, the exclusive logical sum of the two inputs is achieved.

[0011] However, in order to implement a two-input XOR circuit, 8 MOS transistors are required. In addition, as shown in Patent Document 1 Figure 7 two inverter circuits are required to generate the inputs of the XOR circuit (20). Since one inverter circuit can be implemented with, for example, two MOS transistors, an additional 4 MOS transistors are required. Therefore, in order to implement a two-input XOR circuit, 12 MOS transistors are required, which presents the problem of an increased occupied area of the ECC circuit.

[0012] A brief overview of the representative embodiments disclosed in this application is as follows.

[0013] That is, a semiconductor device according to an embodiment includes a semiconductor chip on which a plurality of circuit blocks are formed.

[0014] In this text, the plurality of circuit blocks are provided with a memory, a first input circuit for outputting a signal, a plurality of logic circuits, a first processing circuit for processing the signal from the first input circuit, and a first output circuit for supplying the output of the first processing circuit to the memory.

[0015] In addition, each of the plurality of logic circuits includes a first terminal, a second terminal, and a first gate terminal for controlling conduction between the first terminal and the second terminal, wherein a first signal from the first input circuit is supplied to the first terminal, and a second signal from the first input circuit is supplied to the first gate terminal of the first NMOS transistor, and the second NMOS transistor includes a third terminal, a fourth terminal, and a second gate terminal for controlling conduction between the third terminal and the fourth terminal, wherein the second signal is supplied to the third terminal, and the first signal is supplied to the second gate terminal, and the output driver includes an input terminal connected to the second terminal of the first NMOS transistor and the fourth terminal of the second NMOS transistor, and the first PMOS transistor is connected between the input terminal of the output driver and a predetermined voltage, and it pre-charges the input terminal of the output driver with a voltage based on the predetermined voltage in response to a first trigger signal supplied to the gate terminal, and the output driver outputs a signal according to the result of the logical operation of the first signal and the second signal after being pre-charged by the first trigger signal.

[0016] Through the description and the drawings of this specification, other objects and novel features will become apparent.

[0017] According to one embodiment, a semiconductor device that can suppress an increase in occupied area can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a block diagram showing the configuration of a semiconductor device according to the first embodiment.

[0019] Figure 2 is a block diagram showing an example of an encoder according to the first embodiment.

[0020] Figure 3 is a block diagram showing an example of a decoder and a correction circuit according to the first embodiment.

[0021] Figure 4 is a block diagram showing an example of an ECC circuit according to the first embodiment.

[0022] Figure 5 is a circuit diagram showing the configuration of a cell logic circuit according to the first embodiment.

[0023] Figure 6 is a timing diagram for explaining the operation of the cell logic circuit according to the first embodiment.

[0024] Figure 7 is a circuit diagram showing an example of an input circuit and a processing circuit according to the first embodiment.

[0025] Figure 8is a circuit diagram showing a configuration example of a cell output circuit according to the first embodiment.

[0026] Figure 9 is a timing chart for explaining the operation of an encoder according to the first embodiment.

[0027] Figure 10 is a block diagram showing an example of an ECC circuit according to the first embodiment.

[0028] Figure 11 is a timing chart for explaining the operation of a decoder according to the first embodiment.

[0029] Figure 12A and 12B is a diagram for explaining a cell logic circuit according to a second modification example of the first embodiment.

[0030] Figure 13 is a block diagram showing the configuration of a parallel multiplier according to the second embodiment.

[0031] Figure 14A and 14B is a block diagram showing the configuration of an adder circuit according to the second embodiment.

[0032] Figure 15 is a block diagram showing an example of an ECC circuit according to the third embodiment.

[0033] Figure 16 is a circuit diagram showing the configuration of a cell logic circuit according to the third embodiment.

[0034] Figure 17 is a diagram for explaining the effect of an ECC circuit according to the first embodiment.

[0035] Figure 18 is a diagram for explaining the effect of an ECC circuit according to the first embodiment. Detailed Description

[0036] Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that this disclosure is merely an example, and those skilled in the art can easily conceive appropriate changes while maintaining the spirit of the present invention, which naturally includes within the scope of the present invention.

[0037] In addition, in this specification and the drawings, the same reference numerals are assigned to the same elements as those previously described with respect to the drawings presented, and the detailed description thereof may be appropriately omitted.

[0038] (First Embodiment) <Configuration of Semiconductor Device>

[0039] Figure 1is a block diagram showing the configuration of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment includes a single semiconductor chip formed by a well-known semiconductor manufacturing technique, on which a plurality of circuit blocks are formed. In Figure 1 , the CHP indicated by the dashed line represents the semiconductor chip on which a plurality of circuit blocks are formed. Although various circuit blocks are formed as a plurality of circuit blocks on the semiconductor chip CHP, in Figure 1 , only the circuit blocks necessary for explanation are depicted to avoid complicating the drawings.

[0040] In Figure 1 , CBT represents a memory equipped with an ECC circuit. Additionally, CBP represents a front-end circuit that supplies a signal (data Din) to the memory CBT, and CBA represents a back-end circuit that receives a signal (data Dout) from the memory CBT. The front-end circuit CBP is composed of a processor, for example, and the data Din generated by the processor is supplied to and written into the memory CBT. The data Dout read from the memory CBT is supplied to a back-end circuit such as a peripheral circuit CBA, for example, where the data Dout is processed.

[0041] The memory CBT, which is not particularly limited, includes a single memory RM and an ECC circuit EC. The single memory RM according to the first embodiment includes two storage areas DBA and RBA. The storage area DBA is a data bit area in which the data Din generated by the front-end circuit CBP is written. The storage area RBA is a code bit area in which a code (error correction code) generated by the ECC circuit EC described later is written.

[0042] For example, during the read operation and write operation of the memory RM, the front-end circuit CBP generates an address signal to access the memory RM. The generated address signal accesses a predetermined area (address area specified by the address signal) in each of the two storage areas DBA and RBA. During writing, the data Din is written into the predetermined area of the storage area DBA, and the code R generated by the ECC circuit EC is written into the predetermined area of the storage area RBA.

[0043] During a read operation, data (bits) stored in a predetermined area of the storage area DBA are read out as data Din_E and supplied to the ECC circuit EC. Also, during a read operation, data (codes) stored in a predetermined area of the storage area RBA are read out as code R and supplied to the ECC circuit EC. The ECC circuit EC uses the supplied data Dini_E and code R to detect whether an error exists in the data Din_E read from the storage area DBA, and outputs the detection result as an error flag EFG. If a correctable error is detected in this detection, the ECC circuit EC corrects the error in the data Din_E and outputs it as data Dout to the subsequent circuit CBA.

[0044] Although not particularly limited, the error flag EFG is supplied to the processor, that is, the pre-stage circuit CBP. Therefore, the processor can detect, for example, the occurrence of an error that the ECC circuit EC cannot correct based on the error flag EFG.

[0045] It should be noted that in the following description, a static volatile memory (SRAM) is described as an example of the memory RM, but the present invention is not limited thereto. For example, the memory RM may be a dynamic volatile memory (DRAM), an electrically rewritable non-volatile memory (such as a flash memory), or an MRAM.

[0046] <<Overview of the ECC Circuit>>

[0047] Next, an overview of the ECC circuit EC will be described using Figure 1 As shown, the ECC circuit EC includes an encoder EC_E, a decoder EC_D, and a correction processing circuit (hereinafter also referred to as a correction circuit) EC_C. Figure 1 As shown later in the drawings, data Din to be written into the memory RM is supplied to the encoder EC_E. The encoder EC_E encodes the supplied data Din to generate code R, and writes the generated code R into the storage area RBA.

[0048] The decoder EC_D is supplied with the code R read from the storage area RBA and the data Din_E read from the storage area DBA. The decoder EC_D decodes these supplied data, detects whether an error has occurred, and if an error has occurred, notifies it with the error flag EFG. Further, if a correctable error has occurred, the decoder EC_D identifies the location of the error in the data Din_E.

[0049] The correction circuit EC_C is supplied with the data Din_E read from the storage area DBA and the data DD identifying the error location, and if a correctable error has occurred, corrects the error and outputs it as data Dout.

[0050] The correction circuit EC_C is supplied with the data Din_E read from the storage area DBA and the data DD identifying the error location, and if a correctable error has occurred, corrects the error and outputs it as data Dout.

[0051] Next, a configuration example of the encoder EC_E, decoder EC_D, and correction circuit EC_C will be described using the drawings. For ease of explanation, as an example, the case where the data Din supplied from the previous-stage circuit CBP to the memory RM is composed of 4 bits IN[0] to IN[3] (parallel 4 bits) is described. Of course, the number of bits in the data Din is not limited to this.

[0052] <<<Overview of Encoder EC_E>>>

[0053] Figure 2 is a block diagram showing an example of an encoder according to the first embodiment. The encoder EC_E includes three 3-input XOR circuits XR_E0 to XR_E2. Among the 4 bits IN[0] to IN[3] constituting the data Din, as Figure 2 shown, the data Din is supplied to the corresponding 3-input XOR circuits XR_E0 to XR_E2 in different combinations of 3 bits. For example, the XOR circuit XR_E0 is supplied with the data Din having the combination of bits IN[0], IN[1], and IN[2]. Similarly, 3 bits of the data Din are input to the XOR circuits XR_E1 and XR_E2. The outputs of the three 3-input XOR circuits XR_E0 to XR_E2 are output as bits R[0] to R[2] constituting the code R from the decoder EC_D to the storage area RBA of the memory RM.

[0054] Although not particularly limited, in the encoder EC_E according to the first embodiment, a buffer circuit BF_E is provided in front of the encoder, and through the buffer circuit BF_E, the data Din is supplied from the previous-stage circuit CBP (as Figure 1 shown). Of course, it is not necessary to provide the buffer circuit BF_E.

[0055] The encoder EC_E generates a code R composed of bits R[0] to R[2] having logical values according to the combination of the logical values of the bits IN[0] to IN[3] constituting the data Din, and writes the generated code into the storage area RBA of the memory RM.

[0056] <<<Overview of Decoder EC_D and Correction Circuit EC_C>>>

[0057] Figure 3 is a block diagram showing an example of a decoder and a correction circuit according to the first embodiment. As Figure 3 shown, the decoder EC_D includes three 4-input XOR circuits XR_D0 to XR_D2 and five 3-input AND circuits AD_D0 to AD_D3 and AD_EF.

[0058] As Figure 3As shown, four bits IN[0] to IN[3] of the data Din_E read from the storage area DBA of the memory RM shown in Figure 1 and three bits R[0] to R[2] of the code R read from the storage area RBA are supplied to the 4-input XOR circuits XR_D0 to XR_D2 in different combinations. For example, bits IN[0] to IN[2] and bit R[0] are input to the 4-input XOR circuit XR_D0, and bits IN[0], IN[1], IN[3] and bit R[2] are input to the 4-input XOR circuit XR_D2.

[0059] The outputs of the XOR circuits XR_D0 to XR_D2 are supplied to the 3-input AND circuits AD_D0 to AD_D3 and AD_EF. The circles drawn on the input sides of the 3-input AND circuits AD_D1 to AD_D3 and AD_EF indicate inversion. That is, at the parts marked with circles, the supplied data is inverted before being input to the AND circuits. As Figure 3 shown, in the 3-input AND circuits AD_D1 to AD_D3, the outputs from different XOR circuits are inverted (marked with circles) before being input.

[0060] For example, in the 3-input AND circuit AD_D1 corresponding to the first bit of the data Din, the output from the XOR circuit XR_D1 is inverted before being input. In contrast, in the 3-input AND circuit AD_D2 corresponding to the second bit of the data Din, the output from the XOR circuit XR_D2 is inverted before being input.

[0061] In the 3-input AND circuit AD_D0 corresponding to the zero bit of the data Din, all the outputs from the XOR circuits XR_D0 to XR_D2 are input without being inverted. In the 3-input AND circuit AD_EF corresponding to the error flag, all the outputs from the XOR circuits XR_D0 to XR_D2 are inverted before being input.

[0062] The correction circuit EC_C includes two-input XOR circuits XR_C0 to XR_C3 corresponding to bits IN[0] to IN[3] of the data Din. For the XOR circuit XR_C0 corresponding to the 0th bit of the data Din, the output of a three-input AND circuit AD_D0 corresponding to the 0th bit and the bit IN[0] is supplied. Similarly, for the XOR circuit XR_C1 corresponding to the 1st bit of the data Din, the output of a three-input AND circuit AD_D1 corresponding to the 1st bit and the bit IN[1] is supplied. In addition, for the XOR circuit XR_C2 corresponding to the 2nd bit of the data Din, the output of a three-input AND circuit AD_D2 corresponding to the 2nd bit and the bit IN[2] is supplied. Likewise, for the XOR circuit XR_C3 corresponding to the 3rd bit of the data Din, the output of a three-input AND circuit AD_D3 corresponding to the 3rd bit and the bit IN[3] is supplied. The outputs of the XOR circuits XR_C0 to XR_C3 are output from the correction circuit EC_C as the data Dout. Additionally, the output of the three-input AND circuit AD_EF becomes the error flag EFG.

[0063] In the data Din_E read from the memory RM, for example, if the logic value of one bit (e.g., Figure 3 the bit IN[1] therein) is inverted due to a soft error, the decoder EC_D uses the read data Din_E and the code R to identify the bit position of the bit (the 1st bit corresponding to the bit IN[1]) whose logic value has been inverted. The correction circuit EC_C corrects the logic value of the bit at the position identified by the decoder EC_D (correction is performed by inversion). At this time, the decoder EC_D notifies the occurrence of an error through the error flag EFG.

[0064] Although not particularly limited, in the first embodiment, similar to the Figure 2 encoder EC_E shown, each bit of the data Din_E and each bit of the code R are supplied to the decoder EC_D and the correction circuit EC_C through the buffer circuit BF_D. Of course, the buffer circuit BF_D may not be provided.

[0065] As Figure 2 and 3 shown, many XOR circuits are used in the ECC circuit EC. Therefore, if the number of elements constituting the XOR circuit is large, the occupied area of the ECC circuit CE becomes large. In the first embodiment, an XOR circuit that can be constituted by a smaller number of elements is provided. This makes it possible to suppress an increase in the occupied area of the ECC circuit.

[0066] <<Specific Example of ECC Circuit>>

[0067] Next, a specific example of the configuration of the ECC circuit according to the first embodiment will be explained using the accompanying drawings. The following description will be divided into parts corresponding to the encoder EC_E and parts corresponding to the decoder EC_D and the correction circuit EC_C.

[0068] <<Portion corresponding to encoder EC_E>>

[0069] Figure 4 is a block diagram showing an example of the ECC circuit according to the first embodiment. This drawing mainly shows the part corresponding to Figure 1 the encoder EC_E described above. In Figure 4 it, CBP and RBA correspond to the pre-stage circuit CBP and the storage area of the memory RM shown in Figure 1 The encoder EC_E includes an input circuit (first input circuit) E_IN, a processing circuit (first processing circuit) E_PR, an output circuit (first output circuit) E_OT, and a control circuit (first control circuit) E_CTE.

[0070] Bits IN[0] to IN[K - 1] of the data Din output from the pre-stage circuit CBP are input to the input circuit E_IN, and the input circuit E_IN outputs data (signals) corresponding to the input data to the processing circuit E_PR.

[0071] The processing circuit E_PR includes a plurality of logic circuits (hereinafter also referred to as unit logic circuits) LG_A. The plurality of logic circuits LG_A are not particularly limited, but in the first embodiment, their configurations are similar to each other. A detailed explanation will be omitted here because examples of the unit logic circuit LG_A will be described later using Figure 5 etc., but by connecting a plurality of unit logic circuits LG_A, a plurality of multi-input logic circuits having three or more inputs (such as Figure 2 the XOR circuits XR_E0 to XR_E2 shown) are realized. The logic circuit implemented by the plurality of unit logic circuits LG_A in the processing circuit E_PR performs a logic operation on the data (signals) from the input circuit E_IN. The result of the logic operation performed in the processing circuit E_PR is output as bits XQ[0] to XQ[N - 1] constituting the code to the output circuit E_OT.

[0072] The control circuit E_CTE receives an external clock signal ECLK and generates timing signals to control the input circuit E_IN, the processing circuit E_PR, and the output circuit E_OT. That is, the control circuit E_CTE generates a trigger signal TRG synchronized with the external clock signal ECLK and an inverted trigger signal TRGB inverted with respect to the trigger signal TRG, supplies them to the input circuit IN_U, and supplies the trigger signal TRG to the processing circuit E_PR. In addition, the control circuit E_CTE supplies a clock signal CLK synchronized with the external clock signal ECLK and an inverted clock signal CLKB inverted with respect to the clock signal CLK to the output circuit E_OT. The input circuit IN_U, the processing circuit E_PR, and the output circuit E_OT operate according to the timing signals (TRG, TRGB, CLK, CLKB) supplied from the control circuit E_CTE. The external clock signal ECLK supplied to the control circuit E_CTE is not particularly limited and is generated by a circuit block (not shown), such as a control circuit formed on a semiconductor chip CHP ( Figure 1 ).

[0073] The timing signal CCONT indicated by the dashed line will be described in the first modification example later, so it is omitted here.

[0074] <<<Example of the logic circuit LG_A>>>

[0075] Figure 5 is a circuit diagram showing the configuration of the cell logic circuit according to the first embodiment. The cell logic circuit LG_A includes two N-type MOS transistors (first N-type MOS transistor, second N-type MOS transistor) N1, N2, one P-type MOS transistor (first P-type MOS transistor) P1, and an inverter circuit (output driver) IV1. Each MOS transistor is provided with a first terminal T1 and a second terminal T2 and a gate terminal G for controlling conduction between the first terminal T1 and the second terminal T2. It should be noted that the first terminal T1 and the second terminal T2 correspond to the source terminal and the drain terminal of the MOS transistor, respectively. However, since the source terminal and the drain terminal are determined by the voltage at the terminals, if not necessary, the source terminal and the drain terminal are not specifically illustrated in this specification, but are described as the first terminal and the second terminal. In addition, to avoid complexity in the drawings, the symbols T1, T2, and G are mainly omitted in the subsequent drawings.

[0076] The first terminal T1 of the N-type MOS transistor N1 is connected to the input terminal A of the unit logic circuit LG_A and the gate terminal G of the N-type MOS transistor N2, and the first terminal T1 of the N-type MOS transistor N2 is connected to the input terminal B of the unit logic circuit LG_A and the gate terminal G of the N-type MOS transistor N1. Moreover, the second terminals T2 of the N-type MOS transistors N1 and N2 are connected to the composite node CB, and the input terminal of the inverter circuit IV1 and the second terminal T2 of the P-type MOS transistor P1 are also connected to the composite node CB. In addition, the first terminal T1 of the P-type MOS transistor P1 is connected to the power supply voltage (predetermined voltage) VDD, the gate terminal G of the P-type MOS transistor P1 is supplied with a trigger signal (first trigger signal) TRG, and the output terminal of the inverter circuit IV1 is connected to the output terminal C of the unit logic circuit LG_A.

[0077] When the P-type MOS transistor P1 is turned on by the trigger signal TRG, the composite node CB is connected to the power supply voltage VDD through the P-type MOS transistor P1. Therefore, the composite node CB including the input terminal of the inverter circuit IV1 is pre-charged with a voltage based on the power supply voltage VDD. Binary logic signals (first signal and second signal) are supplied to the input terminals A and B. During the processing period (logic operation cycle) after the pre-charge period, the unit logic circuit LG_A performs a logic operation ( Figure 5 exclusive OR operation in

[0078] <<<Operation example of logic circuit LG_A>>>

[0079] Figure 6 is a timing diagram for explaining the operation of the unit logic circuit according to the first embodiment. Using Figure 5 and 6 , the operation of the unit logic circuit LG_A, that is, the exclusive OR operation, is explained.

[0080] The period during which the trigger signal TRG is at a low level is the pre-charge period Tpr, and the period during which the trigger signal TRG is at a high level is the processing period Tlc. Figure 4 The control circuit E_CTE shown outputs the trigger signal TRG, which periodically changes between high / low levels synchronously with the external clock signal ECLK.

[0081] During the pre-charge period Tpr before the calculation start time TC_1, the trigger signal TRG goes low. Also, during the pre-charge period Tpr, a logic value 0 input signal (first signal) is supplied to the input terminal A, and a logic value 0 input signal (second signal) is also supplied to the input terminal B. Thus, the P-type MOS transistor P1 is turned on, and the N-type MOS transistors N1 and N2 are turned off, and the composite node CB is pre-charged with a voltage (high level) based on the power supply voltage VDD. Since the composite node CB is pre-charged to a high level, a low-level output signal will be output from the output terminal C. This pre-charge period Tpr can be regarded as the initialization cycle of the logic circuit LG_A. When regarded as the initialization cycle, the logic circuit LG_A is supplied with a first signal and a second signal with a logic value of 0 at initialization, and the logic circuit LG_A outputs an output signal with a logic value of 0.

[0082] During the calculation start time TC_1 and the subsequent processing period Tlc_1, the trigger signal TRG goes high, and the first signal and the second signal for logical operation are supplied to the input terminals A and B. In response to the high level of the trigger signal TRG, the P-type MOS transistor P1 is turned off. In Figure 6 the example, the first signal and the second signal are at a low level during the calculation start time TC_1 and the processing period Tlc_1. Since a low level is supplied to the gate terminals G of the N-type MOS transistors N1 and N2, both the N-type MOS transistors N1 and N2 remain turned off. Thus, during the processing period Tlc_1, the composite node CB maintains the pre-charge voltage, and the output terminal C continues to output an output signal with a logic value of 0.

[0083] During the pre-charge period Tpr after the processing period Tlc_1, the trigger signal TRG goes low again, and the composite node CB is pre-charged. At this time, the first signal and the second signal (logic value 0) at initialization are supplied to the input terminals A and B. At the start time TC_2 and during the processing period Tlc_2, a first signal with a logic value of 0 and a second signal with a logic value of 1 are supplied to the input terminals A and B. Thus, the voltage at the input terminal B becomes high, and the voltage at the input terminal A becomes low. Therefore, the N-type MOS transistor N1 changes to the on state, and the charge pre-charged at the composite node CB is discharged to the ground voltage VSS through the N-type MOS transistor N1, resulting in a high-level output signal being output from the output terminal C. It should be noted that at this time, the N-type MOS transistor N2 remains in the off state.

[0084] During the precharge period Tpr after the processing period Tlc_2, the trigger signal TRG becomes low again, and the composite node CB is precharged. Also, at this time, the first signal and the second signal at initialization are supplied to the input terminals A and B. At the start time TC_3 and during the processing period Tlc_3, the first signal with a logic value of 1 and the second signal with a logic value of 0 are supplied to the input terminals A and B. Therefore, the voltage at the input terminal A becomes high, and the voltage at the input terminal B becomes low. Accordingly, the N-type MOS transistor N2 changes to the on state, and the charge precharged at the composite node CB is discharged to the ground voltage VSS through the N-type MOS transistor N2, resulting in a high-level output signal being output from the output terminal C. It should be noted that at this time, the N-type MOS transistor N1 remains in the off state.

[0085] During the precharge period Tpr after the processing period Tlc_3, the trigger signal TRG becomes low again, and the composite node CB is precharged. Also, at this time, the first signal and the second signal at initialization are supplied to the input terminals A and B. At the start time TC_4 and during the processing period Tlc_4, the first signal with a logic value of 1 and the second signal are supplied to the input terminals A and B. Therefore, the voltages at the input terminals A and B become high. Since the voltages at the gate terminals G, the first terminals T1, and the second terminals T2 of the N-type MOS transistors N1 and N2 become high, the N-type MOS transistors N1 and N2 remain in the off state. Accordingly, the charge precharged at the composite node CB is not discharged to the ground voltage VSS through the N-type MOS transistors N1 and N2, and the voltage at the composite node CB is maintained at a high level, resulting in a low-level output signal being output from the output terminal C.

[0086] Therefore, during the processing period Tlc, an exclusive OR operation based on the first signal and the second signal supplied to the input terminals A and B is performed and output in the unit logic circuit LG_A. This processing period Tlc can also be regarded as a logic operation cycle.

[0087] In Figure 7 the circuit diagram shows an example of the input circuit E_IN and the processing circuit E_PR according to the first embodiment. Figure 4 The shown input circuit E_IN is composed of a plurality of unit input circuits IN_U corresponding to the bits IN[0] to IN[K - 1], and these bits constitute the data Din from the previous-stage circuit CBP. In Figure 7 as an example, four unit input circuits IN_U0 to IN_U3 corresponding to the bits IN[0] to IN[3] are shown. Since the configurations of the four unit input circuits are the same, the unit input circuit IN_U0 is described as an example.

[0088] The unit input circuit IN_U0 includes N-type MOS transistors N3 to N6 and P-type MOS transistors P2 and P3. The first terminal of the N-type MOS transistor N3 is connected to the first terminal of the P-type MOS transistor P2, the second terminal of the N-type MOS transistor N3 is connected to the second terminal of the P-type MOS transistor P2, the trigger signal TRG is supplied to the gate terminal of the N-type MOS transistor N3, and the inverted trigger signal TRGB is supplied to the gate terminal of the P-type MOS transistor P2. In addition, the first terminals of the MOS transistors N3 and P2 are connected to the input terminal D of the unit input circuit IN_U0, and the second terminals of the MOS transistors N2 and P2 are connected to the output terminal F of the unit input circuit IN_U0. Thus, a CMOS pass (transmission) gate composed of the MOS transistors N3 and P2, connected between the input terminal D and the output terminal F, and controlled by the trigger signal TRG (inverted trigger signal TRGB) is formed.

[0089] Similarly, a CMOS pass gate composed of the MOS transistors N4 and P3, connected between the input terminal E and the output terminal G, and controlled by the trigger signal TRG (inverted trigger signal TRGB) is formed.

[0090] The first terminals of the N-type MOS transistors N5 and N6 are connected to the ground voltage VSS (GND), and the second terminals are connected to the output terminals F and G of the unit input circuit IN_U0, and the inverted trigger signal TRGB is supplied to their gate terminals.

[0091] During the pre-charge period, when the trigger signal TRG is at a low level (the inverted trigger signal TRGB is at a high level), the N-type MOS transistors N5 and N6 are in the on state, and the N-type MOS transistors N3 and N4 are in the off state. At this time, the P-type MOS transistors P2 and P3 are also in the off state. That is, during the pre-charge period, the CMOS pass gate is in the non-conducting state, and the input terminals D, E and the output terminals F, G are electrically isolated from each other. At this time, the output terminals F, G are pre-charged to the ground voltage VSS. That is, the voltage at the output terminals F, G becomes a low level corresponding to the logic value 0.

[0092] During the processing (logic operation) cycle, when the trigger signal TRG is at a high level (the inverted trigger signal TRGB is at a low level), the N-type MOS transistors N5 and N6 are in the off state, and the N-type MOS transistors N3 and N4 and the P-type MOS transistors P2 and P3 are in the on state. That is, the output terminals F, G are electrically isolated from the ground voltage VSS, and are electrically connected to the input terminals D, E through the CMOS pass gate.

[0093] That is, during the precharge period, the unit input circuit IN_U0 outputs a logic value 0 as an initial value regardless of the logic value of the supplied bit, and during the processing period, it outputs the logic value of the supplied bit.

[0094] In the processing circuit E_PR according to the first embodiment, a single multi-input logic circuit is formed by connecting a plurality of dual-input unit logic circuits LG_A in a tree-like manner. Specifically, an eight-input exclusive-OR circuit is constructed by connecting seven unit logic circuits LG_A across three levels in a tree-like manner.

[0095] As Figure 7 shown, the input terminals A and B of the unit logic circuits LG_A10 to LG_A13 placed in the first stage of the tree are electrically connected to the output terminals F and G of the corresponding unit input circuits IN_U0 to IN_U3. Moreover, as Figure 7 shown, the input terminals A and B of the unit logic circuits LG_A20 and LG_A21 placed in the second stage are connected to the output terminals C of the unit logic circuits LG_A10 to LG_A13 placed in the first stage. In addition, as Figure 7 shown, the input terminals A and B of the unit logic circuit LG_A30 placed in the third stage are connected to the output terminals C of the unit logic circuits LG_A20 and LG_A21 placed in the second stage.

[0096] For example, when describing the unit logic circuit LG_A20 (the first logic circuit), the input terminals A and B of the second-stage unit logic circuit LG_A20 are electrically connected to the output terminals C of the first-stage unit logic circuits LG_A10 and LG_A11 (the second logic circuit and the third logic circuit), and the output terminal C of the second-stage unit logic circuit LG_A20 is electrically connected to the input terminal A of the third-stage unit logic circuit LG_A30.

[0097] During the precharge period, the output terminals F and G of the unit input circuit IN_U0 are precharged to the ground voltage VSS, thereby supplying the initial logic value 0 to the first-stage unit logic circuit group LG_A1. Moreover, in the unit logic circuit group LG_A1, during the precharge period, the composite node CB is precharged with a voltage based on the power supply voltage VDD instead of the ground voltage VSS. Therefore, during the precharge period, the initial logic value 0 is supplied to the second and subsequent stages of the unit logic circuit groups LG_A2 and LG_A3.

[0098] During the processing period, the exclusive-OR of the data Din (bits IN[0] to IN[7]) is sequentially determined in the first, second, and third stages, and the result of the exclusive-OR operation is output from the output terminal C of the third-stage unit logic circuit LG_A30.

[0099] In Figure 7 , although an example of a single 8-input logic circuit constructed using seven unit logic circuits is described, it is not limited to 8 inputs. Further, in processing circuit E_PR, as Figure 2 described, a plurality of multi-input logic circuits as shown in Figure 7 are provided and are electrically connected to each other to implement an encoder.

[0100] <<<Example of output circuit E_OT>>>

[0101] The data generated in processing circuit E_PR (e.g., the calculation result from the 8-input logic circuit shown in Figure 7 ) is output from processing circuit E_PR to output circuit E_OT as bits XQ[0] to XQ[N - 1] that form a code.

[0102] As Figure 4 shown, output circuit E_OT is provided with a plurality of unit output circuits OU_U corresponding to bits XQ[0] to XQ[N - 1]. Since the unit output circuits OU_U corresponding to bits XQ[0] to XQ[N - 1] have the same configuration, the unit output circuit OU_U0 corresponding to bit XQ[0] is described here as an example. Figure 8 is a circuit diagram showing a configuration example of the unit output circuit according to the first embodiment.

[0103] The unit output circuit OU_U0 includes N-type MOS transistors N7 to N9, P-type MOS transistors P4 to P6, and an inverter circuit IV2.

[0104] The first terminals of N-type MOS transistor N7 and P-type MOS transistor P4 are connected to each other, and their second terminals are also connected to each other. The clock signal CLK is supplied to the gate terminal of P-type MOS transistor P4, and the inverted clock signal CLKB is supplied to the gate terminal of N-type MOS transistor N7. Thus, a CMOS is formed by P-type MOS transistor P4 and N-type MOS transistor N7 through the gate. The input terminal of the CMOS through the gate is supplied with the corresponding bit XQ[0], and its output terminal is connected to the input terminal of inverter circuit IV2 and the output terminal of the clock inverter circuit CIV1 described next.

[0105] As Figure 8As shown, the clock inverter circuit CIV1 is composed of P-type MOS transistors P5 and P6 and N-type MOS transistors N8 and N9 connected in series between the power supply voltage VDD and the ground voltage VSS. The gate terminal of the P-type MOS transistor P5 and the gate terminal of the N-type MOS transistor N9 are connected to the output terminal of the inverter circuit IV2. The gate terminal of the P-type MOS transistor P6 is supplied with the inverted clock signal CLKB, and the gate terminal of the N-type MOS transistor N8 is supplied with the clock signal CLK. The connection node between the P-type MOS transistor P6 and the N-type MOS transistor N8 becomes the output terminal of the clock inverter circuit CIV1, and the gate terminals of the P-type MOS transistor P5 and the N-type MOS transistor N9 become the input terminals of the clock inverter circuit CIV1. The output terminal of the inverter circuit IV2 becomes the output terminal of the cell output circuit OU_U0, and the code R[0] corresponding to the bit XQ[0] is output from the cell output circuit OU_U0 to the storage area RBA of the memory RM (as Figure 4 shown).

[0106] In the cell output circuit OU_U0, when the clock signal CLK is at a low level (the inverted clock signal CLKB is at a high level), the CMOS becomes conductive through the gate, supplies the bit XQ[0] to the inverter circuit IV2, and when the clock signal CLK is at a high level, it becomes non-conductive and stops supplying the bit XQ[0] to the inverter circuit IV2. That is, during the period when the clock signal CLK is at a low level, the cell output circuit OU_U0 captures the bit XQ[0].

[0107] The input terminal of the inverter circuit IV2 is connected to the output terminal of the clock inverter circuit CIV1, and the output terminal of the inverter circuit IV2 is connected to the input terminal of the clock inverter circuit CIW1, thus forming a latch circuit FF. The latch circuit FF operates synchronously with the clock signal CLK (inverted clock signal CLKB) through the inverter circuit IV2 and the clock inverter circuit CIV1. When the clock signal CLK is at a high level (the inverted clock signal CLKB is at a low level), the latch circuit FF latches the logical value of the bit XQ[0] supplied through the CMOS through the gate.

[0108] Therefore, the cell output circuit OU_U0 captures the logical value of the bit XQ[0] during the period when the clock signal CLK is at a low level, and then, when the clock signal CLK goes high, it retains the captured logical value of the bit XQ[0]. The cell output circuit OU_U0 inverts (logical inversion) the captured logical value of the bit XQ[0] and outputs it as the code R[0].

[0109] <<Operation of the Encoder>>

[0110] Next, the operation of the encoder EC_E shown is explained using the accompanying drawings. Figure 4 The operation of the encoder EC_E shown. Figure 9 is a timing chart for explaining the operation of the encoder according to the first embodiment.

[0111] Figure 4 The control circuit E_CTE shown generates a clock signal CLK and a trigger signal TRG based on an external clock signal ECLK. Although Figure 9 not shown in, the control circuit E_CTE also generates an inverted clock signal CLKB and an inverted trigger signal TRGB. In the first embodiment, the control circuit E_CTE generates a trigger signal that rises in synchronization with the falling edge of the clock signal CLK as the trigger signal TRG.

[0112] In the first embodiment, the memory RM (as Figure 1 shown) starts its write and read operations in synchronization with the rising edge of the external clock signal ECLK (in Figure 9 , the clock signal CLK is in phase with ECLK). In Figure 9 , WTT indicates the period for writing to the storage area RBA of the memory RM (write period). The symbols TW0 to TW3 indicate write cycles. In the first embodiment, for a given write cycle in which the code R is written to the memory RM, the code R to be written in that given write cycle is generated in the write cycle before the given write cycle.

[0113] During the time t0 to t1 of the first write cycle TW0, the bits IN[0] to IN[K - 1] constituting the data Din are input to the input circuit E_IN. In Figure 9 , only the bit IN[0] among the bits IN[0] to IN[K - 1] is shown as an example. In the input circuit E_IN and the processing circuit E_PR, as Figures 5 - 7 described, precharging is performed during the period when the trigger signal TRG is at a low level (the inverted trigger signal TRGB is at a high level). Therefore, during the period from time t0 to t1 of the first write cycle TW0, the input circuit E_IN and the processing circuit E_PR are precharged. Since precharging is performed, the data (data constituted by the bits XQ[0] to XQ[N - 1]) supplied from the processing circuit E_PR to the output circuit E_OT becomes the precharged level. In Figure 9 , only the bit XQ[0] is shown as a representative, and the precharged level is at a high level (e.g., the power supply voltage VDD).

[0114] Furthermore, as Figure 8As described, during the period when the clock signal CLK is at a high level, the CMOS composed of the N-type MOS transistor N7 and the P-type MOS transistor P4 in the output circuit E_OT becomes non-conductive through the gate. Therefore, during the period from time t0 to t1 of the write cycle TW0, the data supplied to the output circuit E_OT is not output as the code R.

[0115] At time t1 of the write cycle TW0, when the trigger signal TRG changes to a high level (the inverted trigger signal TRGB is at a low level), as Figures 5 - 7 shown, the pre-charge in the input circuit E_IN and the processing circuit E_PR is completed, and the logical operation of the data Din is sequentially executed by the unit logic circuits arranged in a tree structure in the processing circuit E_PR, and during the period from time t1 to t2 of the cycle TW0, the code R (a bit string including the bit R[0]) is generated.

[0116] During the period from time t1 to t3 of the cycle TW0, since the clock signal CLK is at a low level (the inverted clock signal CLKB is at a high level), during this period, as Figure 8 described, the CMOS composed of the N-type MOS transistor N7 and the P-type MOS transistor P4 becomes conductive through the gate, and the code R generated during the period from time t1 to t2 of the write cycle TW0 is stored in the latch circuit FF of the output circuit E_OT, and the code R will be supplied to the memory RM.

[0117] During the period from time t2 to t3 of the write cycle TW0, during the write period WTT starting from time t0 of the subsequent write cycle TW1 (the same as time t3 of the previous write cycle TW0), the code R supplied to the memory RM is written into the storage area RBA of the memory RM.

[0118] During the write cycle TW1 from time t0 to t3, the same operations as those during the write cycle TW0 from time t0 to t3 are performed. The same is true for subsequent write cycles, such as TW3.

[0119] When the number of bits among the bits IN[0] to IN[K-1] with a logical value of 1 in the data Din is even, the processing circuit E_PR generates the bit R[0] of the code R with a logical value of 0, as shown during the period from time t2 to t3 of the write cycle TW0. On the contrary, if the number of bits among the bits IN[0] to IN[K-1] with a logical value of 1 in the data Din is odd, the processing circuit E_PR generates the bit R[0] of the code R with a logical value of 1, as shown during the period from time t2 to t3 of the write cycle TW1. Although the bit R[0] is mentioned as an example, this also applies to other bits.

[0120] According to the first embodiment, the processing circuit E_PR including the unit logic circuit LG_A and a plurality of unit logic circuits LG_A is a dynamic circuit that requires a precharge operation. That is, it is necessary to ensure a period (time) for performing the precharge operation. There is a concern that this cycle of the precharge operation may slow down the operation of the semiconductor device. However, according to the first embodiment, as Figure 9 shown, the period of the precharge operation partially overlaps with the write period WTT of the memory RM. Therefore, by causing the period of the precharge operation to be blocked by the write period WTT, the slowdown of the operation of the semiconductor device can be suppressed.

[0121] <<Related parts of decoder EC_D and correction circuit EC_C>>

[0122] Figure 10 is a block diagram showing an example of an ECC circuit according to the first embodiment. This drawing mainly shows the components corresponding to Figure 1 the decoder EC_D and the correction circuit EC_C described. In Figure 10 , RM (storage areas DBA + RBA) corresponds to Figure 1 the memory shown, and CBA corresponds to Figure 1 the subsequent circuit CBA shown. The decoder EC_D includes an input circuit (second input circuit) E_IN, a processing circuit (second processing circuit) E_PR, an output circuit (second output circuit) E_OT, and a control circuit (second control circuit) E_CTD.

[0123] The memory RM starts its read operation synchronously with the rising edge of the external clock signal ECLK. The code R and the data Din_E read from the storage areas RBA; DBA of the memory RM are input to the input circuit E_IN. The data and the code output from the input circuit E_IN are input to the processing circuit E_PR. The data (bits XQ[0] to XQ[N - 1]) processed in the processing circuit E_PA are input to the output circuit E_OT. The output circuit E_OT outputs the input data as data DD (bits DD[0] to DD[N - 1]) to the correction circuit EC_C.

[0124] The memory RM according to the first embodiment is not particularly limited, but includes Figure 10 the plurality of inverter circuits shown, and uses these inverter circuits, etc., to generate an output completion signal QSET based on the external clock signal ECLK, indicating the timing of the completion of the read operation.

[0125] The control circuit E_CTD is supplied with an external clock signal ECLK and an output completion signal QSET from the memory RM, and based on the external clock signal ECLK and the output completion signal QSET, the control circuit E_CTD generates a trigger signal TRG, an inverted trigger signal TRGB, a clock signal CLK, and an inverted clock signal CLKB.

[0126] The input circuit E_IN is similar to Figure 4 the input circuit E_IN shown. The main difference is that code R (R[0] to R[N-1]) and data Din_E are supplied from the memory RM to Figure 10 the input circuit E_IN shown. The output circuit E_OT is also similar to Figure 4 the output circuit E_OT shown. The main difference is that Figure 10 the output circuit E_OT shown outputs data (bits XQ[0] to XQ[N-1]) as data DD (bits DD[0] to DD[N-1]) to the correction circuit EC_C. In addition, the processing circuit E_PR is also similar to Figure 4 the processing circuit E_PR shown. The main difference is that in Figure 10 the processing circuit E_PR shown, a plurality of unit logic circuits LG_A are connected to form a logic circuit, such as Figure 3 the XOR circuits XR_D0 to XR_D2 described, and in addition, AND circuits AD_D0 to AD_D3, AD_EF described in Figure 3 are provided in the processing circuit E_PR.

[0127] Figure 10 The operations of the input circuit E_IN, the processing circuit E_PR, and the output circuit E_OT shown are similar to the operations described using Figures 4 - 8 and are thus omitted here.

[0128] Data DD (bits DD[0] to DD[N-1]) and data Din_E are supplied from the storage area DBA to the correction circuit EC_C. The correction circuit EC_C includes logic circuits, such as Figure 3 the XOR circuits XR_C0 to XR_C3 described, and corrects the bits that have an error, for example, and supplies the corrected data to the subsequent circuit CBA.

[0129] <<Operation of the decoder>>

[0130] Next, the operation of the decoder shown will be described using the drawings. Figure 10 The decoder shown. Figure 11 is a timing chart for explaining the operation of the decoder according to the first embodiment.

[0131] In Figure 11In this, ROT indicates an operation cycle (read cycle) for reading data Din_E and code R from memory RM. As Figure 11 shown, the starting point of read cycle ROT is the rising timing of clock signal CLK. In addition, symbols TR0 to TR3 indicate read cycles of data Din and code R.

[0132] In the first embodiment, trigger signal TRG and inverted trigger signal TRGB are generated by control circuit E_CTD based on the rising timing of output completion signal QSET. The pulse widths (widths in the time axis direction) of trigger signal TRG and inverted trigger signal TRGB are set by, for example, a delay circuit provided in control circuit E_CTD.

[0133] During times t0 to t2 of read cycle TR0, trigger signal TRG goes low. Thus, as Figure 9 explained, precharging is performed in input circuit E_IN and processing circuit E_PR. Since precharging is performed, bits XQ[0] to XQ[N - 1] output from processing circuit E_PR go high. In Figure 11 only bit XQ[0] is shown. In addition, precharging is shown in Figure 11 as being performed during the period from time t0 to t1.

[0134] When reading is completed at time t2 of read cycle TR0 and output completion signal QSET rises, in response, trigger signal TRG rises. Thus, input circuit E_IN captures data Din_E and bits R[0] to R[N - 1] of code R read from memory RM, and supplies them to processing circuit E_PR. In processing circuit E_PR, logical operations are performed. Result bits XQ[0] to XQ[N - 1] are generated between times t2 and t3 of read cycle TR0, and are supplied to output circuit E_OT.

[0135] Output circuit E_OT captures the operation result during the period when clock signal CLK is low, as Figure 8 shown, and when clock signal CLK changes to high, the captured result is stored in latch circuit FF. Thus, during times t0 to t1 of the next read cycle TR1, bits DD[0] to DD[N - 1] corresponding to result bits XQ[0] to XQ[N - 1] in processing circuit E_PR are supplied from output circuit E_OT to correction circuit EC_C.

[0136] In the decoder according to the first embodiment, the period of the precharging operation overlaps with a part of read cycle ROT for performing reading from memory RM. That is, it is possible to suppress the slowdown of the operation of the semiconductor device by hiding the precharging operation cycle during read cycle ROT.

[0137] Similar to Figure 4 the processing circuit E_PR for encoding EC_E shown, in the decoder EC_D and the processing circuit E_PR, if the number of bits with a logical value of 1 in the data input from the input circuit E_IN is even, the processing circuit E_PR generates a bit DD[0] with a logical value of 0 during the time t3 to t4 of the read cycle TR0, as shown. On the other hand, if the number of bits with a logical value of 1 in the data input from the input circuit E_IN is odd, the processing circuit E_PR generates a bit DD[0] with a logical value of 0 during the time t3 to t4 of the read cycle TR1, as shown.

[0138] The unit logic circuit LG_A related to the first embodiment and the processing circuit E_PR including a plurality of unit logic circuits LG_A are dynamic circuits that require a precharge operation. That is, it is necessary to ensure a period (time) for performing the precharge operation, and there is a concern that the operation of the semiconductor device may slow down. However, according to the first embodiment, as Figure 11 shown, the period of the precharge operation overlaps with a part of the read cycle ROT for reading from the memory RM. That is, since the precharge operation cycle can be hidden by the read cycle ROT, the slowdown of the semiconductor device operation can be suppressed.

[0139] In Figure 9 and 11 it is explained that the bits XQ[0] to XQ[N - 1] as the output from the processing circuit E_PR become high level due to precharge. On the other hand, in Figure 7 the configuration of the processing circuit shown, the output terminal C of the third - stage unit logic circuit LG_A30 becomes low level due to precharge. This is because a logic circuit (not shown) that causes a logic inversion is provided between the output of the third - stage unit logic circuit LG_A30 and the output of the processing circuit E_PR shown in Figure 7 To eliminate the logic inversion caused by the logic circuit not shown, the unit output circuit OU_U0 is configured to logically invert the output, as Figure 8 explained. Of course, the bits XQ[0] to XQ[N - 1] from the processing circuit E_PR may also become low level due to precharge.

[0140] <First Modification Example>

[0141] In the first modification example, Figure 4 the pre - stage circuit CBP and the control circuit E_CTE shown are changed. That is, the pre - stage circuit CBP is changed to generate a timing signal CCONT and supply it to the control circuit E_CTE. Similar to Figure 10 and 11Similar to the output completion signal QSET explained, when the processing in the current-stage circuit CBP is completed, the previous-stage circuit CBB generates a timing signal CCONT indicating completion. The control circuit E_CTE related to the first modification example generates a trigger signal TRG, an inverted trigger signal TRGB, a clock signal CLK, and an inverted clock signal CLKB based on the timing signal CCONT, which are timing signals according to the processing of the previous-stage circuit CBP. Figure 4 The remaining circuit blocks shown remain unchanged.

[0142] In the first modification example, once the processing in the previous-stage circuit CBP is completed, based on the completion of this processing, the input circuit E_IN, the processing circuit E_PR, and the output circuit E_OT will start their operations. This allows eliminating the delay loss in the sequential relationship and achieving acceleration.

[0143] <Second Modification Example>

[0144] Although Figures 1 - 11 an exclusive-OR circuit is described as the unit logic circuit LG_A, the second modification example explains a negative exclusive-OR circuit (also referred to as an XNOR circuit hereinafter).

[0145] FIG. 12 is a diagram for explaining the unit logic circuit according to the second modification example of the first embodiment. Here, Figure 12A a circuit diagram of the XNOR circuit constituting the unit logic circuit LG_AN is shown, and Figure 12B is a truth table showing the operation of the Figure 12A XNOR circuit.

[0146] As Figure 12A shown, the XNOR circuit includes P-type MOS transistors P7, P8, an N-type MOS transistor N10, and an inverter circuit IV3. These MOS transistors and the inverter circuit constitute a two-input XNOR circuit.

[0147] The first terminal of the P-type MOS transistor P7 is connected to the input terminal A of the XNOR circuit and the gate terminal of the P-type MOS transistor P8, and the first terminal of the P-type MOS transistor P8 is connected to the input terminal B of the XNOR circuit and the gate terminal of the P-type MOS transistor P7. In addition, the second terminals of the P-type MOS transistors P7, P8 are connected to the composite node CB, the input terminal of the inverter circuit IV3 is connected to this composite node, and the N-type MOS transistor N10 is connected between the composite node CB and the ground voltage VSS (GND). That is, the first terminal of the N-type MOS transistor N10 is connected to the ground voltage VSS, the second terminal is connected to the composite node CB, and the trigger signal TRG is supplied to the gate terminal. The output terminal of the inverter circuit IV3 is connected to the output terminal C of the XNOR circuit.

[0148] The XNOR circuit related to the second modification example operates in the order of a precharge period and a processing period, similar to Figure 5 and 6 the XOR circuit described. That is, during the precharge period, the trigger signal TRG is at a high level (logical value 1), and the N-type MOS transistor N10 is in the on state. Therefore, the composite node CB is precharged (discharged) with a voltage based on the ground voltage VSS. Thereafter, the trigger signal TRG changes to a low level (logical value 0), and it transitions to the processing period.

[0149] For example, during the processing period, as Figure 12B shown, when signals (first signal, second signal) of the same logical value (0, 0 or 1, 1) are supplied to the input terminals A, B, a logical value 1 is output from the output terminal C. On the other hand, when signals of different logical values are supplied to the input terminals A, B, a logical value 0 is output from the output terminal C. Therefore, a two-input XNOR circuit can be implemented with a smaller number of components.

[0150] In Figure 5 the XOR circuit shown and the XNOR circuit shown in FIG. 12, the P-type MOS transistor and the N-type MOS transistor can be changed to MOS transistors of the opposite conductivity type. For example, in Figure 5 , the MOS transistors N1, N2 can be changed to P-type MOS transistors, and the MOS transistor P1 can be changed to an N-type MOS transistor. In this case, the inverter circuit IV1 will be changed to a buffer circuit that does not perform an inversion operation. For example, such a non-inverting buffer circuit can be implemented by connecting an even number of inverter circuits in series, but this will increase the number of MOS transistors and result in an increase in the occupied area. To suppress the increase in the occupied area, it is desirable to have Figure 5 the configuration shown. Although the XOR circuit is described as an example, similar to the XNOR circuit, to suppress the increase in the occupied area, it is desirable to have the configuration shown in FIG. 12.

[0151] (Second Embodiment)

[0152] The first embodiment describes a semiconductor device equipped with an ECC circuit composed of a plurality of unit logic circuits. The circuit composed of a plurality of unit logic circuits is not limited to an ECC circuit. The second embodiment describes an example other than the ECC circuit. Specifically, it describes a multi-input parallel multiplier (hereinafter simply referred to as a multiplier) composed of a plurality of unit logic circuits.

[0153] Figure 13 is a block diagram showing the configuration of the multiplier according to the second embodiment. In Figure 13In [the figure], MUP indicates a multiplier formed on a semiconductor chip. The multiplier MUP is composed of a plurality of full adder circuits (full adders) FA, a plurality of half adder circuits (half adders) HA, and a plurality of AND circuits, as Figure 13 shown. Figure 13 The multiplier MUP shown multiplies first input data composed of bits X0 to X4 and second input data composed of bits Y0 to Y4, and calculates a multiplication result composed of bits Z0 to Z8 and a carry C.

[0154] FIG. 14 is a block diagram showing the configuration of an adder circuit according to the second embodiment. Here, Figure 14A the configuration of the full adder circuit FA is shown, and Figure 14B the configuration of the half adder circuit HA is shown. As Figure 14A shown, the full adder circuit FA is composed of three XOR circuits FA_1 to FA_3 and two AND circuits FA_4 to FA_5, and as Figure 14B shown, the half adder circuit HA is composed of one XOR circuit HA_1 and one AND circuit HA_2.

[0155] In the second embodiment, each of the three XOR circuits FA_1 to FA_3 constituting the Figure 14A shown full adder circuit FA is composed of the Figure 5 shown XOR circuit. Moreover, the XOR circuit HA_1 constituting the Figure 14B shown half adder circuit HA is composed of the Figure 5 shown XOR circuit. This allows the occupied area of the XOR circuit to be reduced and suppresses an increase in the occupied area of the multiplier MUP. Of course, not all of the XOR circuits in the full adder circuit FA and the half adder circuit HA constituting the multiplier MUP need to have the Figure 5 shown configuration.

[0156] (Third Embodiment)

[0157] Figure 15 is a block diagram showing an example of an ECC circuit according to the third embodiment. This drawing mainly shows the part corresponding to the Figure 1 described encoder EC_E. Figure 15 is similar to Figure 4 . The main difference is that in Figure 15 , there is no provision of Figure 4The input circuit E_IN shown, and bits IN[0] to IN[K - 1] of the data from the previous - stage circuit CBP are input to the processing circuit E_PR, and the processing circuit E_PR includes two types of unit logic circuits (the first unit logic circuit, the second unit logic circuit) LG_A, LG_B. In the processing circuit E_PR, each of the two types of unit logic circuits LG_A and LG_B is provided with a plurality of units.

[0158] The unit logic circuit (the second unit logic circuit) LG_A has Figure 5 the configuration shown, and operates as described in Figure 6 etc. On the other hand, the unit logic circuit (the first unit logic circuit) LG_B includes the functions of the unit logic circuit LG_A and the unit input circuit IN_U. In other words, the unit logic circuit LG_B is the addition of the function of the unit input circuit IN_U and the unit logic circuit LG_A.

[0159] Figure 16 is a circuit diagram showing the configuration of the unit logic circuit according to the third embodiment. The unit logic circuit LG_B includes N - type MOS transistors N11 to N14, P - type MOS transistors P9 to P11, and an inverter circuit IV4.

[0160] The first terminal T1 of the N - type MOS transistor (the first MOS transistor) N11 is connected to the input terminal A of the unit logic circuit LG_B, and its gate terminal G is connected to the input terminal B of the unit logic circuit LG_B via the source - drain (the first terminal - the second terminal) path of the P - type MOS transistor (the seventh MOS transistor) P11. In addition, the first terminal T1 of the N - type MOS transistor (the second MOS transistor) N12 is connected to the input terminal B of the unit logic circuit LG_B, and its gate terminal G is connected to the input terminal A of the unit logic circuit LG_B via the source - drain path of the P - type MOS transistor (the eighth MOS transistor) P10. The second terminals T2 of the N - type MOS transistors N11 and N12 are connected to the composite node CB, and the input terminal of the inverter circuit IV4 is connected to the composite node CB. The composite node CB is connected to the power - supply voltage VDD via the source - drain path of the P - type MOS transistor (the third MOS transistor) P9. In addition, the output terminal of the inverter circuit IV4 is connected to the output terminal C of the unit logic circuit LG_B.

[0161] The gate terminals G of the N - type MOS transistors N11 and N12 are connected to the ground voltage VSS via the source - drain paths of the N - type MOS transistors N14 and N13.

[0162] The trigger signal TRG is supplied to the gate terminal G of the P-type MOS transistor P9. Conversely, the inverted trigger signal TRGB is supplied to the gates of the N-type MOS transistors N13, N14 and the P-type MOS transistors P10, P11.

[0163] Figure 16 The N-type MOS transistors N11, N12 and the P-type MOS transistor P9 shown correspond to Figure 4 the N-type MOS transistors N1, N2 and the P-type MOS transistor P1 shown.

[0164] During the precharge period, the P-type MOS transistor P9 is turned on, and the composite node CB is precharged with a voltage based on the power supply voltage VDD. Also, during the precharge period, the N-type MOS transistors N13, N14 are turned on by the inverted trigger signal TRGB, and the P-type MOS transistors P10, P11 are turned off. Therefore, the N-type MOS transistors N11 and N12 are turned off, and the gate terminals G of the N-type MOS transistors N11 and N12 are electrically isolated from the input terminals B, A. Therefore, during the precharge period, a low-level logic value is output from the output terminal C as an initial value.

[0165] At the end of the precharge period and during the processing period, the trigger signal TRG goes high, and the inverted trigger signal TRGB goes low. Therefore, the N-type MOS transistors N13, N14 are turned off, and the P-type MOS transistors P10, P11 are turned on. Therefore, the input terminal A is electrically connected to the gate terminal G of the N-type MOS transistor N12 via the P-type MOS transistor P10. Similarly, the input terminal B is electrically connected to the gate terminal G of the N-type MOS transistor N11 via the P-type MOS transistor P11. Therefore, during the processing period, the operation of the N-type MOS transistors N11, N12 is similar to Figure 4 the N-type MOS transistors N1, N2 in, performs the exclusive logical sum on the signals supplied to the input terminals A, B, and outputs the result from the output terminal C.

[0166] For example, in Figure 7 the unit logic circuit LG_B is used as the first stage of the unit logic circuit group (LG_A10 to LG_A13). When Figure 16 the unit logic circuit LG_B shown is used as Figure 7 the unit logic circuit LG_A10 shown, the unit input circuit IN_U0 is omitted, and the bits IN[0], IN[1] are supplied to Figure 16The input terminals A and B of the unit logic circuit LG_B shown, and the output terminal C of the unit logic circuit LG_B is connected to the input terminal A of the second-stage unit logic circuit LG_A20. Of course, in this case, the second-stage unit logic circuit LG_A20 is composed of the unit logic circuit LG_A.

[0167] In this document, an example is shown in which the processing circuit in the encoder EC_E is composed of two types of unit logic circuits LG_A and LG_B, but it is not limited thereto. That is, the processing circuit in the decoder EC_D can also be composed of two types of unit logic circuits LG_A and LG_B. Of course, the processing circuits of both the encoder EC_E and the decoder EC_D can be composed of two types of unit logic circuits LG_A and LG_B.

[0168] According to the third embodiment, the input circuit E_IN can be omitted, thereby further reducing the number of components and further suppressing the increase in the occupied area.

[0169] Figure 17 and 18 is a diagram for explaining the effect of the ECC circuit according to the first embodiment. Here, Figure 17 is a diagram showing the effect of suppressing the increase in the occupied area, and Figure 18 is a diagram showing the acceleration of operation.

[0170] In Figure 17 , the horizontal axis indicates the number of gates composed of XOR circuits, and the vertical axis indicates the number of MOS transistors (Tr) required to form the gates. In the drawing, P = XOR(12Tr) indicates the case of forming a gate using the XOR circuit shown in Patent Document 1. In contrast, A = XOR(5Tr) indicates the case of forming a gate using the Figure 5 shown XOR circuit. Further, in Figure 17 , AR = XOR(5Tr) + peripheral circuit indicates the case where MOS transistors constituting the peripheral circuit are added to A = XOR(5Tr). In Figure 17 , as indicated by the downward arrow, according to the first embodiment, compared with using the XOR circuit shown in Patent Document 1, for example, about 2000 MOS transistors can be reduced, and the increase in the occupied area can be suppressed.

[0171] Figure 18 shows the speed of the semiconductor device equipped with the ECC circuit. In Figure 18 , P = ECC(XOT(12Tr)) indicates the operation when the ECC circuit is formed using the XOR circuit shown in Patent Document 1. Moreover, A = ECC(XOR(5Tr)) indicates using the Figure 5The case where the XOR circuit shown constitutes the ECC circuit is as described in the first embodiment. In Figure 18 it, SRAM indicates the time required for a read cycle to read data from the memory, and ECC indicates the time for the ECC circuit to perform error detection and correction on the data read from the memory.

[0172] For example, with the development of integration, the memory cells constituting the memory become smaller, and the reduction in reliability due to soft errors becomes a problem. Therefore, it is crucial to provide an ECC circuit in a semiconductor device.

[0173] However, the error detection and correction of the ECC circuit require time, which limits the acceleration. That is, for example, in the XOR circuit shown in Patent Document 1, since a plurality of MOS transistors are connected in series between the power supply voltage VDD (or the ground voltage VSS) and the output terminal, the voltage change at the output terminal becomes slow, slowing down the operation of the ECC circuit. In contrast, in the XOR circuit according to the first embodiment, it is possible to prevent the voltage change at the output terminal from slowing down, thereby accelerating the operation of the ECC circuit. Therefore, the sum of the time of the memory read cycle time and the time of the ECC circuit operation cycle can be shortened from Tcyc1 to Tcyc2, thereby achieving a speed increase.

[0174] Although the present invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from its gist.

Claims

1. A semiconductor device, comprising: A semiconductor chip is formed by multiple circuit blocks. The plurality of circuit blocks include: Memory; A first input circuit, used for outputting a signal; a first processing circuit including a plurality of logic circuits and processing the signal from the first input circuit; and a first output circuit for supplying an output of the first processing circuit to the memory, Each of the plurality of logic circuits comprises: a first N-type MOS transistor having a first terminal, a second terminal, and a first gate terminal for controlling conduction between the first terminal and the second terminal, the first terminal being supplied with a first signal from the first input circuit, and the first gate terminal being supplied with a second signal from the first input circuit; a second N-type MOS transistor having a third terminal, a fourth terminal, and a second gate terminal for controlling conduction between the third terminal and the fourth terminal, the second signal being supplied to the third terminal, and the first signal being supplied to the second gate terminal; an output driver having an input terminal connected to the second terminal of the first N-type MOS transistor and the fourth terminal of the second N-type MOS transistor; and a first P-type MOS transistor connected between the input terminal of the output driver and a predetermined voltage, and precharging the input terminal of the output driver with a voltage based on the predetermined voltage in response to a first trigger signal supplied to the gate terminal; The output driver of the logic circuit outputs a signal according to a result of a logic operation of the first signal and a second signal after being precharged by the first trigger signal.

2. The semiconductor device according to claim 1, wherein the plurality of logic circuits include a first logic circuit, a second logic circuit and a third logic circuit, and The output of the second logic circuit is supplied as the first signal to the first terminal and the second gate terminal of the first logic circuit, and the output of the third logic circuit is supplied as the second signal to the third terminal and the first gate terminal of the first logic circuit.

3. The semiconductor device according to claim 2, During a period in which the signal from the first output circuit is written into the memory, the output drivers in the first logic circuit, the second logic circuit, and the third logic circuit are precharged by the first trigger signal.

4. The semiconductor device according to claim 3, The plurality of circuit blocks further include: A front-end circuit for supplying signals to the memory and the first input circuit; as well as a first control circuit connected to the front-end circuit and the first processing circuit and outputting a timing signal according to the processing of the front-end circuit, The timing signal output from the first control circuit is supplied as the first trigger signal to the gate terminal of the first P-type MOS transistor in the first logic circuit.

5. The semiconductor device according to claim 4, The timing signal output from the first control circuit is supplied as the first trigger signal to the gate terminal of the first P-type MOS transistor in the second logic circuit and the third logic circuit.

6. The semiconductor device according to claim 5, The timing signal output from the first control circuit is supplied to the first input circuit and the first output circuit, and the first input circuit and the first output circuit operate according to the timing signal.

7. The semiconductor device according to claim 3, The plurality of circuit blocks include: a second input circuit to which a signal is supplied from the memory; a second processing circuit that processes the signal from the second input circuit and includes a plurality of logic circuits; as well as a second output circuit to which a signal is supplied from the second processing circuit, Each of the plurality of logic circuits in the second processing circuit comprises: a third N-type MOS transistor having a fifth terminal, a sixth terminal, and a third gate terminal for controlling conduction between the fifth terminal and the sixth terminal, the first signal from the second input circuit being supplied to the fifth terminal, and the second signal from the second input circuit being supplied to the third gate terminal; a fourth N-type MOS transistor having a seventh terminal, an eighth terminal, and a fourth gate terminal for controlling conduction between the seventh terminal and the eighth terminal, the second signal from the second input circuit being supplied to the seventh terminal, and the first signal from the second input circuit being supplied to the fourth gate terminal; an output driver having an input terminal connected to the sixth terminal of the third N-type MOS transistor and the eighth terminal of the fourth N-type MOS transistor; and a second P-type MOS transistor connected between the input terminal of the output driver and a predetermined voltage and precharging the input terminal of the output driver with a voltage based on the predetermined voltage in response to a second trigger signal supplied to the gate terminal, The output driver of the logic circuit in the second processing circuit outputs a signal according to the result of the logic operation of the first signal and the second signal after being precharged by the second trigger signal.

8. The semiconductor device according to claim 7, wherein the plurality of circuit blocks further include a second control circuit connected to the memory and outputting a timing signal according to the read operation in the memory, and The timing signal output from the second control circuit is supplied as the second trigger signal to the gate terminal of the second P-type MOS transistor in the logic circuit of the second processing circuit.

9. A semiconductor device comprising: A semiconductor chip is formed by multiple circuit blocks. The plurality of circuit blocks include: Memory; an input circuit to which a signal is supplied from the memory; Multiple logic circuits; a processing circuit for processing a signal from the input circuit; and an output circuit to which the signal from the processing circuit is supplied, Each of the plurality of logic circuits comprises: a first N-type MOS transistor having a first terminal, a second terminal, and a first gate terminal for controlling conduction between the first terminal and the second terminal, the first terminal being supplied with the first signal from the input circuit, and the first gate terminal being supplied with the second signal from the input circuit; a second N-type MOS transistor having a third terminal, a fourth terminal, and a second gate terminal for controlling conduction between the third terminal and the fourth terminal, the second signal being supplied to the third terminal, and the first signal being supplied to the second gate terminal; an output driver having an input terminal connected to the second terminal of the first N-type MOS transistor and the fourth terminal of the second N-type MOS transistor; and a P-type MOS transistor connected between the input terminal of the output driver and a predetermined voltage and precharging the input terminal of the output driver with a voltage based on the predetermined voltage in response to a trigger signal supplied to the gate terminal, The output driver of the logic circuit outputs a signal according to a result of a logic operation of the first signal and the second signal after being precharged by the trigger signal.

10. The semiconductor device according to claim 9, wherein the plurality of logic circuits include a first logic circuit, a second logic circuit and a third logic circuit, and The output of the second logic circuit is supplied as the first signal to the first terminal and the second gate terminal of the first logic circuit, and the output of the third logic circuit is supplied as the second signal to the third terminal and the first gate terminal of the first logic circuit.

11. The semiconductor device according to claim 10, During a period of reading a signal from the memory, the output drivers in the first logic circuit, the second logic circuit, and the third logic circuit are precharged by the trigger signal.

12. The semiconductor device according to claim 11, The plurality of circuit blocks further include: a control circuit connected to the memory and outputting a timing signal according to the read operation in the memory, The timing signal output from the control circuit is supplied as the trigger signal to the gate terminal of the P-type MOS transistor in the first logic circuit.

13. The semiconductor device according to claim 12, The timing signal output from the control circuit is supplied as the trigger signal to the gate terminals of the P-type MOS transistors in the second logic circuit and the third logic circuit.

14. The semiconductor device according to claim 13, The timing signal output from the control circuit is supplied to the input circuit and the output circuit, and the input circuit and the output circuit operate according to the timing signal.

15. A semiconductor device comprising: A front-stage circuit for generating a signal to be written into the memory; A processing circuit, used for processing the signal generated by the preceding circuit; as well as a memory into which the signal generated by the processing circuit and the signal generated by the preceding stage circuit are written, The processing circuit comprises: a plurality of first logic circuits to which the signal generated by the preceding stage circuit is supplied; and a plurality of second logic circuits to which signals from the plurality of first logic circuits are supplied, Each of the plurality of first logic circuits comprises: a first MOS transistor having a first terminal, a second terminal, and a first gate terminal for controlling conduction between the first terminal and the second terminal, and during a processing period, a first signal from the preceding stage circuit is supplied to the first terminal, and a second signal from the preceding stage circuit is supplied to the first gate terminal; a second MOS transistor having a third terminal, a fourth terminal, and a second gate terminal for controlling conduction between the third terminal and the fourth terminal, and during the processing period, the second signal is supplied to the third terminal and the first signal is supplied to the second gate terminal; a first output driver having an input terminal connected to the second terminal of the first MOS transistor and the fourth terminal of the second MOS transistor; and a third MOS transistor connected between the input terminal of the first output driver and a predetermined first voltage and precharging the input terminal of the first output driver with a voltage based on the predetermined first voltage during a precharge period before the processing period, Each of the plurality of second logic circuits comprises: a fourth MOS transistor having a fifth terminal, a sixth terminal, and a third gate terminal for controlling conduction between the fifth terminal and the sixth terminal, the fifth terminal being connected to an output terminal of an output driver of one of the plurality of first logic circuits, and the third gate terminal being connected to an output terminal of an output driver of another of the plurality of first logic circuits; a fifth MOS transistor having a seventh terminal, an eighth terminal, and a fourth gate terminal for controlling conduction between the seventh terminal and the eighth terminal, the seventh terminal being connected to the output terminal of the output driver of the other first logic circuit, and the fourth gate terminal being connected to the output terminal of the output driver of the one first logic circuit; a second output driver having an input terminal electrically connected to the sixth terminal of the fourth MOS transistor and the eighth terminal of the fifth MOS transistor; and A sixth MOS transistor is connected between the input terminal of the second output driver and the predetermined first voltage, and precharges the input terminal of the second output driver with a voltage based on the predetermined first voltage during the precharge period.

16. The semiconductor device according to claim 15, The first logic circuit includes a seventh MOS transistor connected between the preceding stage circuit and the first gate terminal of the first MOS transistor; and an eighth MOS transistor connected between the preceding stage circuit and the second gate terminal of the second MOS transistor, wherein during the precharge period, the first gate terminal of the first MOS transistor and the second gate terminal of the second MOS transistor are precharged with a voltage based on a predetermined second voltage, and During the processing period, the second signal is supplied to the first gate terminal of the first MOS transistor via the seventh MOS transistor, and the first signal is supplied to the second gate terminal of the second MOS transistor via the eighth MOS transistor.

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