Method for realizing large-size high-density interconnection of multiple computing chips through wafer-level process

Abstract

The invention belongs to the technical field of integrated circuit packaging, and particularly relates to a method for realizing large-size high-density interconnection of multiple computing chips through a wafer-level process. Comprising the following steps: spin-coating temporary bonding glue on a wafer; finishing front surface rewiring through a stepping photoetching machine; after the wiring layer is completed, inversely installing a capacitor, a resistor, a resin through hole or a silicon through hole; carrying out plastic packaging by using a resin material; thinning the resin material to expose the through hole; back wiring is completed through a contact type exposure machine, and multi-view-field interconnection is achieved; bonding a polyimide film on the surface of the wiring layer; removing the bonding glue, and separating the glass wafer; mounting core particles on the metal bonding pads of the single view field; carrying out plastic packaging by using a resin material; removing the polyimide film to expose the bonding pad; and completing ball mounting and scribing. Ultra-high density wiring is completed on a glass wafer through a stepping photoetching machine, ultra-high bandwidth interconnection of calculation and storage particles in an intelligent calculation chip is met, and the problem that re-wiring of ultra-thin line width and line distance cannot be achieved through a substrate material is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit packaging, and particularly relates to a method for realizing large-size and high-density interconnection of multiple computing chips through a wafer-level process. Background Art

[0002] With the rapid increase in the demand for the computing power of intelligent chips by cutting-edge technologies such as cloud computing and large models, Moore's Law has gradually come to an end. The traditional path to improving computing power is to increase the transistor density by reducing the size of advanced processes. Taking NVIDIA B200 as an example, the process node is 4nm, the number of transistors is 208 billion, and the computing power is 2250 TFLOPS@FP16. Entering the post-Moore era, the cost of chip manufacturing increases exponentially with the improvement of advanced processes. The expenditure on 5nm chips reaches 542 million US dollars, and most companies can no longer afford the chip development cost. Facing this problem, developers around the world are improving intelligent computing power by increasing the chip area, optimizing the chip architecture, etc.

[0003] Wafer integration technology is an excellent means to break through the lithography field size limit in wafer manufacturing and break through the chip computing power bottleneck. This technology designs and manufactures the entire semiconductor wafer as a complete integrated circuit. Compared with the traditional chip manufacturing process (cutting the wafer into individual chips and then packaging them), it can directly achieve ultra-high functional density integration at the wafer level, thereby improving system performance, reducing power consumption, and packaging costs. Since wafer integration technology needs to achieve seamless connection of circuits on the entire wafer, it is difficult to achieve through conventional lithography means. There are usually the following two solutions: 1. Repeatedly splicing and covering the pattern of a small-size photomask onto the complete wafer through a high-precision step-and-repeat lithography machine. This method requires high resolution and alignment progress of the lithography machine; 2. Using electron beam direct writing or laser direct writing, without a photomask, directly drawing circuit patterns on the wafer by computer-controlled light beams, but the speed is slow and it is only suitable for small-batch production.

[0004] The present invention aims at the urgent need to prepare wafer-level computing chips in large quantities and at low cost, and combines advanced packaging processes to achieve the preparation of wafer-level computing chips in large quantities and at low cost. Summary of the Invention

[0005] The object of the present invention is to provide a method for realizing large-size high-density interconnection of multiple computing chips through a wafer-level process, and the present invention mainly aims at the increasing computing power requirements of intelligent chips. Entering the post-Moore era, it is difficult to keep up with the growth demand of computing power relying on the progress of the process technology. In addition, the chip manufacturing cost has increased by leaps and bounds. Facing this problem, developers in various countries have achieved low-cost intelligent computing power improvement through advanced packaging processes represented by the system-on-chip technology. However, the system-on-chip technology has extremely high requirements for process equipment. In order to realize the stitching of the exposure field of view, lithography equipment with an order of magnitude higher precision is often required. In addition, the stitching process significantly increases the number of lithography masks used in each step, resulting in a substantial increase in the process cost. The present invention has the advantages of simple process, batch preparation, and low cost.

[0006] To solve the above technical problems, the present invention provides a method for realizing large-size high-density interconnection of multiple computing chips through a wafer-level process, so as to achieve low-cost and low-difficulty system-on-chip integration, including: Using a stepper lithography machine, a contact lithography machine and a vertical interconnection structure to realize double-sided interconnection and large-size computing chip package integration; Among them, on the front side of the wafer, a stepper lithography machine is used to realize ultra-high-density interconnection of computing die and memory die, and on the back side of the wafer, a contact lithography machine is used to realize multi-front-exposure field interconnection; The vertical interconnection structure is a TSV or TMV via.

[0007] Preferably, the stepper lithography machine and the contact lithography machine are used to complete double-sided wiring, realizing 1 to 8 layers of wiring, and the line width and line pitch are 2 μm to 50 μm.

[0008] Preferably, before the front side of the wafer is re-wired by a stepper lithography machine, it further includes: Using a glass wafer as a carrier wafer and spin-coating a temporary bonding adhesive on the glass wafer.

[0009] Preferably, after the front side of the wafer is re-wired by a stepper lithography machine, it further includes: Inverting capacitors, resistors and TSV or TMV vias at the corresponding pads; Using a resin material for encapsulation; Thinning the resin material to expose the TSV or TMV vias; According to the wiring requirements, the back side of the lithography machine is re-wired by a contact lithography machine to realize multi-field interconnection.

[0010] Preferably, after the back side of the lithography machine is re-wired by a contact lithography machine, it further includes: Bonding a polyimide film on the surface of the wiring layer; Removing the bonding adhesive and separating the glass wafer; Mount the computing die and the memory die on the metal pads in a single field of view; Perform plastic encapsulation using a resin material; Remove the polyimide film to expose the pads; Complete ball mounting and dicing.

[0011] Preferably, the thickness of the glass wafer is 300 μm to 1500 μm, the size is 8 inches or 12 inches, the thickness of the temporary bonding adhesive is 0.01 μm to 1 μm, the curing temperature is 200 °C to 400 °C, and the curing duration is 10 min to 2 h.

[0012] Preferably, the size of the plastic encapsulation is 8 inches or 12 inches, and the plastic encapsulation thickness is increased by 100 μm to 500 μm based on the thickest die among the computing die and the memory die.

[0013] Preferably, in the re - wiring process of the step - and - repeat lithography machine, the thickness of the passivation layer is 1 μm to 15 μm, the thickness of the wiring layer is 1 μm to 10 μm, the line width and line pitch are 2 μm to 20 μm, and the number of wiring layers is 1 to 8 layers.

[0014] Preferably, in the re - wiring process of the contact lithography machine, the thickness of the passivation layer is 3 μm to 20 μm, the line width and line pitch are 10 μm to 50 μm, and the number of wiring layers is 1 to 6 layers.

[0015] Preferably, in the multi - front - exposure field of view, the number of interconnected fields of view is at least 2 and at most the entire wafer surface.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention completes ultra - high - density wiring on a glass carrier plate through a step - and - repeat lithography machine, meets the ultra - high - bandwidth interconnection of computing and storage particles in intelligent computing chips, and solves the problem that the substrate material cannot achieve re - wiring with extremely fine line widths and line pitches. After the interconnection of the computing and storage particles is completed, the signal terminals are led out through the via - hole technology, and multiple exposure field interconnections are realized on the other side through a contact lithography machine. Since there is no exposure field size limit for the contact lithography machine, the exposure of the entire wafer surface can be directly completed, significantly reducing the process difficulty and processing cost. Although the accuracy of the contact lithography machine is lower than that of the step - and - repeat lithography machine, it can already meet the requirements in terms of I / O signal interconnection and lead - out. Description of the Drawings

[0017] Figure 1 It is a schematic diagram of spin - coating a temporary bonding adhesive on a glass wafer in the method of the present invention.

[0018] Figure 2 It is a schematic diagram of completing the first - side re - wiring using a step - and - repeat lithography machine in the method of the present invention.

[0019] Figure 3It is a schematic diagram of flip-chip capacitors, resistors, and TSV or TMV chips at corresponding pads after the rewiring layer is completed in the method of the present invention.

[0020] Figure 4 It is a schematic diagram of using resin material for plastic sealing in the method of the present invention.

[0021] Figure 5 It is a schematic diagram of thinning the resin material to expose the TSV or TMV through hole in the method of the present invention.

[0022] Figure 6 It is a schematic diagram of completing the rewiring layer on the other side by a contact exposure machine in the method of the present invention.

[0023] Figure 7 It is a schematic diagram of bonding a polyimide film on the surface of a wiring layer in the method of the present invention.

[0024] Figure 8 It is a schematic diagram of removing the bonding glue and separating the glass wafers by the debonding technology in the method of the present invention.

[0025] Figure 9 The schematic diagram is for mounting computing core particles and storage core particles on metal pads in the method of the present invention.

[0026] Figure 10 It is a schematic diagram of using resin material for plastic sealing in the method of the present invention.

[0027] Figure 11 The schematic diagram is a method of removing the polyimide film by pyrolysis to expose the solder pad in the present invention.

[0028] Figure 12 It is a schematic diagram of completing ball implantation and performing dicing as required in the method of the present invention.

[0029] Figure 13 Schematic diagram of the chip layout on the front and back sides of a 12-inch wafer in the method of the present invention. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0031] like Figures 1 to 13 As shown, an embodiment of the present invention provides a method for realizing large-size high-density interconnection of multiple computing chips through wafer-level technology, which specifically includes the following steps: (1) Use a glass wafer 101 as a carrier. The thickness of the glass wafer is 300 - 1500 μm, and the size is 8 inches or 12 inches. Spin-coat a temporary bonding adhesive 102 on the wafer by spin coating. The thickness of the adhesive is 0.01 - 1 μm. After spin coating, cure it. The curing temperature is 200 - 400 °C, and the curing duration is 10 min - 2 h, as Figure 1 shown; (2) On the glass wafer in step (1), complete the redistribution process through a stepper lithography machine (with high precision and exposure field limitation). The thickness of the passivation layer 103 is 1 - 15 μm, the thickness of the wiring layer 104 is 1 - 10 μm, the line width and line pitch are 2 - 20 μm, and the number of wiring layers is 1 - 8 layers, as Figure 2 shown; (3) After the wiring layer is completed, flip-chip multiple capacitors and resistors 106, and multiple TSVs (through-silicon vias) or TMVs (through-mold vias) 105 at the corresponding pads, as Figure 3 shown; (4) Use a resin material 107 for encapsulation. The encapsulation size is 8 inches or 12 inches, and the encapsulation thickness is the thickness of the thickest chip in step (3) plus 100 - 500 μm, as Figure 4 shown; (5) After step (4) is completed, thin the resin material 107 to expose the TSV or TMV vias 105, as Figure 5 shown; (6) According to the wiring requirements, complete the passivation layer 108 and the wiring layer 109 through a contact lithography machine (with low precision and no exposure field limitation). The number of wiring layers is 1 - 6 layers, the thickness of the passivation layer 108 is 3 - 20 μm, and the line width and line pitch of the wiring layer are 10 - 50 μm. In this step, realize the multi-field interconnection in step (2) during interconnection. The number of interconnection fields is from 2 to the entire wafer surface, as Figure 5 shown; (7) Bond a polyimide film 110 on the surface of the wiring layer to protect the wiring layer during subsequent processing, as Figure 7 shown; (8) Remove the bonding adhesive 102 through a debonding technique and separate the glass wafer 101, as Figure 8 shown; (9) Mount a computing die and a memory die 111 on the metal pads, as Figure 9 shown; (10) Use a resin material 112 for encapsulation. The encapsulation size is 8 inches or 12 inches, and the encapsulation thickness is the thickness of the thickest chip in step (9) plus 100 - 500 μm, as Figure 10 shown; (11) Remove the polyimide film 110 through a thermal decomposition method to expose the pads, as Figure 11 shown; (12) Complete ball planting 113 and dicing as required, such as Figure 12 shown.

[0032] As a preferred technical solution of the embodiment of the present invention, the above-mentioned glass wafer has a size of 12 inches and uses TMV for vertical interconnection. The preferred technical solution of the present invention specifically provides a method for realizing large-size and high-density interconnection of multiple computing chips through a wafer-level process. The specific steps are as follows: (1) Use a glass wafer as a carrier wafer. The thickness of the glass wafer is 1000 μm, and the size is 12 inches. Spin-coat a temporary bonding adhesive on the wafer by spin coating. The thickness of the adhesive is 0.1 μm. After spin coating, cure it. The curing temperature is 200 °C, and the curing duration is 30 min; (2) Complete the redistribution process through a step-and-repeat photolithography machine. The thickness of the passivation layer is 7 μm, the thickness of the wiring layer is 3 μm, the line width and line pitch are 3 μm, and the number of wiring layers is 3 layers; (3) After the wiring layer is completed, flip-chip capacitors, resistors, and TMV vias are placed at the corresponding pads; (4) Use a resin material for encapsulation. The encapsulation size is 12 inches, and the encapsulation thickness is 900 μm; (5) Thin the resin material to expose the TMV vias; (6) Complete the backside wiring through a contact photolithography machine according to the wiring requirements. The number of wiring layers is 3 layers, the thickness of the passivation layer is 10 μm, the line width and line pitch of the wiring layer are 10 μm, and 4-field interconnection is achieved during interconnection in this step; (7) Bond a polyimide film on the surface of the wiring layer to protect the wiring layer during subsequent processing in this way; (8) Remove the bonding adhesive through a debonding technique to separate the glass wafer; (9) Mount 1 computing die and 2 memory dies on the metal pads of a single field; (10) Use a resin material for encapsulation. The encapsulation size is 12 inches, and the encapsulation thickness is 600 μm; (11) Remove the polyimide film through a thermal decomposition method to expose the pads; (12) Complete ball planting and dicing according to the backside wiring size.

[0033] Realize high-density interconnection of 4 computing chips and 8 memory chips in a single shipped product.

[0034] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for realizing large-scale high-density interconnection of multiple computing chips through wafer-level technology, characterized in that: include: Through stepper lithography, contact lithography and vertical interconnection structure, double-sided interconnection and large-size computing chip packaging integration can be achieved; Among them, a stepper lithography machine is used on the front side of the wafer to achieve ultra-high density interconnection of computing core particles and storage core particles, and a contact lithography machine is used on the back side of the wafer to achieve multi-front exposure field of view interconnection; The vertical interconnection structure is a TSV or TMV through hole.

2. A method for realizing large-scale high-density interconnection of multiple computing chips through wafer-level technology as claimed in claim 1, characterized in that: The double-sided wiring is completed using a stepper lithography machine and a contact lithography machine, achieving 1 to 8 layers of wiring with a line width and line spacing of 2 μm to 50 μm.

3. The method for realizing large-scale high-density interconnection of multiple computing chips through wafer-level technology as claimed in claim 1, characterized in that: Before the wafer front side rewiring is completed by the stepper, it also includes: Use a glass wafer as a carrier and spin-coat temporary bonding adhesive on the glass wafer.

4. The method for realizing large-scale high-density interconnection of multiple computing chips by wafer-level process as claimed in claim 3, characterized in that: After the wafer front side rewiring is completed by the stepper, it also includes: Flip capacitors, resistors and TSV or TMV vias at corresponding pads; Use resin material for plastic sealing; Thinning the resin material to expose the TSV or TMV through hole; According to the connection requirements, the back side of the lithography machine is rewired through a contact lithography machine to achieve multi-field of view interconnection.

5. The method for realizing large-scale high-density interconnection of multiple computing chips through wafer-level technology as claimed in claim 4, characterized in that: After the backside rewiring of the lithography machine is completed by the contact lithography machine, it also includes: Bonding a polyimide film on the surface of the wiring layer; Remove bonding glue and separate glass wafers; Mounting computing cores and storage cores on metal pads in a single field of view; Use resin material for plastic sealing; Remove the polyimide film to expose the pad; Complete ball implantation and dicing.

6. The method for realizing large-scale high-density interconnection of multiple computing chips by wafer-level process as claimed in claim 3, characterized in that: The thickness of the glass wafer is 300μm~1500μm, the size is 8 inches or 12 inches, the thickness of the temporary bonding glue is 0.01μm~1μm, the curing temperature is 200℃~400℃, and the curing time is 10min~2h.

7. The method for realizing large-scale high-density interconnection of multiple computing chips by wafer-level process as claimed in claim 5, characterized in that: The size of the plastic package is 8 inches or 12 inches, and the thickness of the plastic package is 100 μm to 500 μm added to the thickest core particle between the calculation core particle and the storage core particle.

8. The method for realizing large-scale high-density interconnection of multiple computing chips through wafer-level technology as claimed in claim 1, characterized in that: In the rewiring process of the stepper lithography machine, the thickness of the passivation layer is 1 μm-15 μm, the thickness of the wiring layer is 1 μm-10 μm, the line width and line spacing are 2 μm-20 μm, and the number of wiring layers is 1-8.

9. The method for realizing large-scale high-density interconnection of multiple computing chips through wafer-level technology as claimed in claim 1, characterized in that: In the contact photolithography machine rewiring process, the thickness of the passivation layer is 3 μm to 20 μm, the line width and line spacing is 10 μm to 50 μm, and the number of wiring layers is 1 to 6 layers.

10. A method for realizing large-scale high-density interconnection of multiple computing chips by wafer-level process according to any one of claims 1 to 9, characterized in that: The number of interconnected fields of view of the multiple front exposure fields of view is at least 2 and at most the entire wafer.

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