Method for realizing large-size high-density interconnection of multiple computing chips through wafer-level process

Abstract

The present application belongs to the field of integrated circuit packaging technology, and particularly relates to a method for realizing large-size high-density interconnection of multiple computing chips through wafer-level process. The method comprises the following steps: spin-coating temporary bonding glue on a wafer; completing front-side rewiring through a step-by-step photoetching machine; after the completion of the rewiring layer, flip-chip capacitors, resistors, resin vias or silicon vias; using resin material for plastic packaging; thinning the resin material to expose the vias; completing back-side wiring through a contact-type exposure machine to realize multi-view interconnection; bonding a polyimide film on the surface of the rewiring layer; removing the bonding glue and separating the glass wafer; mounting a core particle on the metal pad of a single view field; using resin material for plastic packaging; removing the polyimide film to expose the pad; completing ball mounting and wafer dicing. The step-by-step photoetching machine is used to complete ultra-high-density wiring on the glass wafer, to meet the ultra-high-bandwidth interconnection of computing and storage particles in intelligent computing chips, and to solve the problem that the substrate material cannot realize rewiring with extremely fine line width and line spacing.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit packaging, and particularly relates to a method for realizing large-size high-density interconnection of multiple computing chips through wafer-level process. BACKGROUND

[0002] With the rapid increase in demand for intelligent chip computing power by cutting-edge technologies such as cloud computing and large models, Moore's Law has gradually come to an end. The traditional path for improving computing power is to increase transistor density by reducing advanced process size. For example, the Nvidia B200 has a process node of 4nm and a transistor count of 208 billion, with a computing power of 2250TFLOPS@FP16. In the post-Moore era, chip manufacturing prices jump with the increase in advanced processes, with a 5nm chip costing $542 million. Most companies cannot afford the cost of chip development. In the face of this problem, developers in various countries have increased chip area and optimized chip architecture to improve intelligent computing power.

[0003] Wafer integration technology is an excellent means to break through the field size limit of photolithography in wafer manufacturing and break through the bottleneck of chip computing power. This technology designs and manufactures the entire semiconductor wafer as a complete integrated circuit. Compared with the traditional chip manufacturing process (cutting the wafer into individual chips and then packaging), it can directly realize ultra-high functional density integration at the wafer level, thereby improving system performance, reducing power consumption, and reducing packaging costs. Since wafer integration technology requires seamless connection of circuits on the entire wafer, it is difficult to achieve through conventional photolithography methods. There are usually two solutions: 1. A small size photolithographic plate pattern is repeatedly spliced and overlaid onto a complete wafer through a high-precision stepping photolithography machine. This method requires high resolution and alignment progress of the photolithography machine; 2. Electron beam direct writing or laser direct writing is used, without the need for a photolithographic plate, and the circuit pattern is directly drawn on the wafer by computer control, but the speed is slow and only suitable for small batch production.

[0004] The present application addresses the urgent need for mass production and low-cost wafer-level computing chip preparation, combining advanced packaging processes to achieve mass production and low-cost wafer-level computing chip preparation. SUMMARY

[0005] The purpose of the present application is to provide a method for realizing large-size high-density interconnection of multiple computing chips through wafer-level process, and the present application mainly aims at the growing computing power demand of intelligent chips. In the post-Moore era, it is difficult to keep up with the demand for computing power growth by relying on process progress, and in addition, the cost of chip manufacturing has jumped. In the face of this problem, developers in various countries have realized low-cost intelligent computing power improvement through advanced packaging processes represented by system-on-chip technology. However, the system-on-chip technology has very high requirements for process equipment, and in order to realize exposure field splicing, it is often necessary to use photoetching equipment with an order of magnitude higher precision, in addition, the splicing process significantly increases the number of photoetching plates used at each step, resulting in a significant increase in process cost, while the present application has the advantages of simple process, batch production, low cost and the like.

[0006] To solve the above technical problems, the present application provides a method for realizing large-size high-density interconnection of multiple computing chips through wafer-level process, so as to realize system-on-chip integration at low cost and low difficulty, comprising:

[0007] Through a step-by-step photoetching machine, a contact photoetching machine and a vertical interconnection structure, double-sided interconnection and large-size computing chip packaging integration are realized;

[0008] Among them, the wafer front surface uses a step-by-step photoetching machine to realize ultra-high-density interconnection of computing chips and storage chips, and the wafer back surface uses a contact photoetching machine to realize multi-front exposure field interconnection;

[0009] The vertical interconnection structure is a TSV or TMV through hole.

[0010] Preferably, the step-by-step photoetching machine and the contact photoetching machine are used to complete double-sided wiring, realize 1-8 layers of wiring, and the line width and line spacing are 2-50 mu m.

[0011] Preferably, before completing the wafer front surface re-wiring through the step-by-step photoetching machine, it further comprises:

[0012] Using a glass wafer as a carrier, spin-coating a temporary bonding glue on the glass wafer.

[0013] Preferably, after completing the wafer front surface re-wiring through the step-by-step photoetching machine, it further comprises:

[0014] Inverting capacitors, resistors and TSV or TMV through holes at corresponding pads;

[0015] Using resin material for plastic packaging;

[0016] Thinning the resin material to expose the TSV or TMV through hole;

[0017] According to the wiring requirement, the contact photoetching machine is used to complete the back surface re-wiring of the photoetching machine to realize multi-field interconnection.

[0018] Preferably, after the back-end redistribution of the photolithography is completed by the contact photolithography machine, the method further comprises:

[0019] bonding a polyimide film on the surface of the wiring layer;

[0020] removing the bonding glue and separating the glass wafer;

[0021] mounting the computing and storage dies on the metal pads of a single field of view;

[0022] plastic packaging using resin material;

[0023] removing the polyimide film to expose the pads;

[0024] ball mounting and wafer dicing are completed.

[0025] Preferably, the thickness of the glass wafer is 300-1500 microns, and the size is 8 inches or 12 inches; the thickness of the temporary bonding glue is 0.01-1 microns, and the curing temperature is 200-400 degrees Celsius, and the curing time is 10 minutes to 2 hours.

[0026] Preferably, the plastic packaging size is 8 inches or 12 inches, and the plastic packaging thickness is increased by 100-500 microns based on the thickest die among the computing and storage dies.

[0027] Preferably, in the step-and-repeat photolithography redistribution process, the thickness of the passivation layer is 1-15 microns, the thickness of the wiring layer is 1-10 microns, the line width and line spacing are 2-20 microns, and the number of wiring layers is 1-8.

[0028] Preferably, in the contact photolithography redistribution process, the thickness of the passivation layer is 3-20 microns, the line width and line spacing are 10-50 microns, and the number of wiring layers is 1-6.

[0029] Preferably, the number of interconnection fields of the multi-field-of-view exposure is at least 2 and at most the entire wafer.

[0030] Compared with the prior art, the present application has the following beneficial effects:

[0031] The present application completes ultra-high-density wiring on a glass carrier plate through a step-and-repeat photolithography machine, meets the ultra-high-bandwidth interconnection of computing and storage dies in an intelligent computing chip, and solves the problem that the substrate material cannot realize redistribution of extremely fine line width and line spacing. After the interconnection of the computing and storage dies is completed, the signal terminals are led out through a via technology, and multiple exposure fields are interconnected through a contact photolithography machine on the other side. Since the contact photolithography machine has no size limitation on the exposure field, it can directly complete the exposure of the entire wafer, significantly reducing the process difficulty and processing cost. Although the precision of the contact photolithography machine is lower than that of the step-and-repeat photolithography machine, it can still meet the demand in I / O signal interconnection and leading-out. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of spin-coating temporary bonding adhesive onto a glass wafer in the method of the present invention.

[0033] Figure 2 This is a schematic diagram of the rewiring of the first surface using a stepper lithography machine in the method of the present invention.

[0034] Figure 3 This is a schematic diagram showing how, after the redistribution layer is completed in the method of the present invention, capacitors, resistors, and chips such as TSV or TMV are flip-chip mounted at the corresponding Pad.

[0035] Figure 4 This is a schematic diagram illustrating the use of resin material for molding in the method of the present invention.

[0036] Figure 5 This is a schematic diagram illustrating the process of thinning the resin material to expose TSV or TMV through-holes in the method of the present invention.

[0037] Figure 6 This is a schematic diagram of the rewiring layer on the other side completed by a contact exposure machine in the method of the present invention.

[0038] Figure 7 This is a schematic diagram of bonding a polyimide film to the surface of the wiring layer in the method of the present invention.

[0039] Figure 8 This is a schematic diagram illustrating the method of the present invention, which uses debonding technology to remove bonding adhesive and separate the glass wafer.

[0040] Figure 9 This is a schematic diagram of mounting computing and storage cores on metal pads in the method of the present invention.

[0041] Figure 10 This is a schematic diagram illustrating the use of resin material for molding in the method of the present invention.

[0042] Figure 11 This is a schematic diagram illustrating the process of removing the polyimide film by pyrolysis in the method of the present invention, thereby exposing the solder pads.

[0043] Figure 12 This is a schematic diagram illustrating the process of planting the bulbs and dividing them into sections according to requirements in the method of this invention.

[0044] Figure 13 This is a schematic diagram of the chip layout on the front and back sides of a 12-inch wafer in the method of the present invention. Detailed Implementation

[0045] The application will be described in further detail below with reference to the drawings and specific embodiments. The advantages and features of the application will become more apparent from the following description. It should be noted that the drawings are very simplified and all use non-precise proportions, only for the purpose of facilitating, clarifying and assisting in the description of the embodiments of the application.

[0046] As shown in Figures 1-13 , the embodiment of the application provides a method for realizing large-size high-density interconnection of multiple computing chips through a wafer-level process, specifically comprising the following steps:

[0047] (1) A glass wafer 101 is used as a carrier, the thickness of the glass wafer is 300-1500 μm, the size is 8 inches or 12 inches, a temporary bonding glue 102 is spin-coated on the wafer through a spin-coating method, the glue thickness is 0.01-1 μm, after the glue coating is completed, solidification is performed, the solidification temperature is 200-400 ℃, and the solidification time is 10 min-2 h, as shown in Figure 1 ;

[0048] (2) A rewiring process is completed on the glass wafer in step (1) through a stepper photolithography machine (high precision, with exposure field limitation), the thickness of the passivation layer 103 is 1-15 μm, the thickness of the wiring layer 104 is 1-10 μm, the line width and line distance are 2-20 μm, and the wiring layer number is 1-8 layers, as shown in Figure 2 ;

[0049] (3) After the wiring layer is completed, a plurality of capacitors and resistors 106 are inverted at the corresponding pads, a plurality of TSVs (silicon-based through holes) or TMVs (resin-based through holes) 105 are inverted, as shown in Figure 3 ;

[0050] (4) Plastic packaging is performed using resin material 107, the plastic packaging size is 8 inches or 12 inches, and the plastic packaging thickness is the thickest chip in step (3) plus 100-500 μm, as shown in Figure 4 ;

[0051] (5) After step (4) is completed, the resin material 107 is thinned to expose the TSV or TMV through hole 105, as shown in Figure 5 ;

[0052] (6) The passivation layer 108 and the wiring layer 109 are completed according to the connection requirement through a contact photolithography machine (low precision, without exposure field limitation), the wiring layer number is 1-6 layers, the thickness of the passivation layer 108 is 3-20 μm, the line width and line distance of the wiring layer are 10-50 μm, the multi-field interconnection in step (2) is realized at this step of interconnection, and the number of interconnection fields is 2 to the whole wafer, as shown in Figure 5 ;

[0053] (7) bonding polyimide film 110 on the surface of the wiring layer, in this way, the wiring layer is protected in the subsequent processing process, as shown in Figure 7 ;

[0054] (8) removing the bonding glue 102 by debonding technology, separating the glass wafer 101, as shown in Figure 8 ;

[0055] (9) mounting the computing chip and the storage chip 111 on the metal pad, as shown in Figure 9 ;

[0056] (10) plastic packaging using resin material 112, the plastic packaging size is 8 inches or 12 inches, the plastic packaging thickness is the thickest chip in step (9) plus 100-500 μm, as shown in Figure 10 ;

[0057] (11) removing the polyimide film 110 by pyrolysis, exposing the pad, as shown in Figure 11 ;

[0058] (12) completing the ball mounting 113 and cutting according to the requirements, as shown in Figure 12 .

[0059] As a preferred technical solution of the embodiment of the application, the size of the above glass wafer is 12 inches, and TMV is used for vertical interconnection, and the preferred technical solution of the application specifically provides a method for realizing large-size high-density interconnection of multiple computing chips through wafer-level process, and the specific steps are as follows:

[0060] (1) using a glass wafer as a carrier, the thickness of the glass wafer is 1000 μm, the size is 12 inches, and a temporary bonding glue is spin-coated on the wafer by spin coating, the glue thickness is 0.1 μm, after the glue coating is completed, solidification is carried out, the solidification temperature is 200 °C, and the solidification time is 30 min;

[0061] (2) completing the rewiring process by a stepper photolithography machine, the passivation layer thickness is 7 μm, the wiring layer thickness is 3 μm, the line width and distance are 3 μm, and the wiring layer number is 3;

[0062] (3) after the wiring layer is completed, the corresponding pad is inverted to the capacitor, the resistor, and the TMV through hole;

[0063] (4) plastic packaging using resin material, the plastic packaging size is 12 inches, and the plastic packaging thickness is 900 μm;

[0064] (5) thinning the resin material to expose the TMV through hole;

[0065] (6) Backside routing is completed by contact lithography machine according to the connection requirement, the number of routing layer is 3, the thickness of passivation layer is 10 μm, the line width and distance of routing layer is 10 μm, 4 field of view interconnections are realized in this step;

[0066] (7) Polyimide film is bonded on the surface of routing layer, which protects the routing layer in the subsequent processing;

[0067] (8) The bonded glue is removed by debonding technology, and the glass wafer is separated;

[0068] (9) One computing chip and two memory chips are mounted on the metal pad of single field of view;

[0069] (10) Plastic package is completed by using resin material, the size of plastic package is 12 inches, and the thickness of plastic package is 600 μm;

[0070] (11) Polyimide film is removed by pyrolysis, and the pad is exposed;

[0071] (12) Ball mounting is completed, and the wafer is cut according to the size of backside routing.

[0072] 4 computing chips and 8 memory chips high-density interconnection are realized in single shipment product.

[0073] The above description is only the description of the preferred embodiment of the present application, and does not limit the scope of the present application, any change and modification of the present application made by the ordinary skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A method for implementing large size high density interconnection of multiple computing chips through wafer level process, characterized in that, The application relates to a double-sided interconnection and large-size computing chip package integration method. The front surface of a wafer is used to realize super-high-density interconnection of computing chips and storage chips by using a stepper, and the back surface of the wafer is used to realize multi-front-exposure field interconnection by using a contact-type photolithography machine. The vertical interconnection structure is a TSV or TMV through hole. The double-sided wiring is completed by using the stepper and the contact-type photolithography machine, 1-8 wiring layers are realized, and the line width and line spacing are 2-50 mu m.

2. The method of claim 1, wherein the method is implemented by a wafer level process. Before the front surface of the wafer is rewired by the stepper, the following steps are further included:

3. The method of claim 1, wherein the method is implemented by a wafer level process. A glass wafer is used as a carrier, and temporary bonding glue is spin-coated on the glass wafer. After the front surface of the wafer is rewired by the stepper, the following steps are further included:

4. The method of claim 3, wherein the method is implemented by a wafer level process. Capacitors, resistors and TSV or TMV through holes are inverted at corresponding pads; Resin material is used for plastic packaging; The resin material is thinned to expose the TSV or TMV through holes; According to the connection requirement, the back surface of the wafer is rewired by the contact-type photolithography machine to realize multi-field interconnection. After the back surface of the wafer is rewired by the contact-type photolithography machine, the following steps are further included:

5. The method of claim 4, wherein the method is implemented by a wafer level process. Polyimide film is bonded on the surface of the wiring layer; The bonding glue is removed, and the glass wafer is separated; Computing chips and storage chips are attached to the metal pads in a single field; Resin material is used for plastic packaging; The polyimide film is removed to expose the pads; Ball mounting and wafer slicing are completed. The thickness of the glass wafer is 300-1500 mu m, the size is 8 inches or 12 inches, the thickness of the temporary bonding glue is 0.01-1 mu m, the curing temperature is 200-400 DEG C, and the curing time is 10 min-2 h.

6. The method of claim 3, wherein the method is characterized by: The plastic packaging size is 8 inches or 12 inches, and the plastic packaging thickness is increased by 100-500 mu m based on the thickest chip among the computing chips and the storage chips.

7. The method of claim 5, wherein the method is implemented by a wafer level process. In the rewiring process of the stepper, the thickness of the passivation layer is 1-15 mu m, the thickness of the wiring layer is 1-10 mu m, the line width and line spacing are 2-20 mu m, and the number of wiring layers is 1-8.

8. The method of claim 1, wherein the method is implemented by a wafer level process. In the rewiring process of the contact-type photolithography machine, the thickness of the passivation layer is 3-20 mu m, the line width and line spacing are 10-50 mu m, and the number of wiring layers is 1-6.

9. The method of claim 1, wherein the method is implemented by a wafer level process. The number of interconnection fields of the multi-front-exposure field is at least 2 and at most the whole wafer.

10. The method of claim 1-9, wherein the method is implemented by a wafer level process. ​

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