Multi-layer epitaxial intelligent semiconductor device and preparation method

Abstract

The present invention relates to a multi-layer epitaxial intelligent semiconductor device and a preparation method thereof, including a main semiconductor and a functional semiconductor. The functional semiconductor includes a functional isolation region and a functional active region disposed inside the functional isolation region. The functional isolation region includes a first functional column of a second conductivity type, which is disposed in a first conductivity type epitaxial layer. A second functional column of the second conductivity type is disposed on the front surface of the first functional column of the second conductivity type and is connected to the first functional column of the second conductivity type. The width of the second functional column of the second conductivity type in the first direction is smaller than the width of the first functional column of the second conductivity type in the first direction. The functional active region includes a third functional column of the second conductivity type and is disposed in the first conductivity type epitaxial layer. The width of the third functional column of the second conductivity type along the first direction is greater than the width of the second functional column of the second conductivity type along the first direction. The present invention has the effects of stable isolation voltage, smoother isolation electric field, and effectively reducing the peak electric field.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a multi-layer epitaxial intelligent semiconductor device and a manufacturing method thereof. Background Art

[0002] A semiconductor device is an electronic device with conductivity between that of a good conductor and an insulator, which utilizes the special electrical properties of semiconductor materials to perform specific functions. It can be used to generate, control, receive, transform, amplify signals, and perform energy conversion. With the rapid development of emerging industries such as new energy, there is an increasing demand for high-power, high-voltage withstand, and high-reliability power semiconductor devices. Among them, as a new type of power device, the superjunction device is widely used in high-voltage and high-power power electronic equipment due to its advantages of low on-resistance and high breakdown voltage.

[0003] An intelligent superjunction semiconductor device is based on a common superjunction device and integrates functional semiconductors such as a sampling semiconductor, a starting semiconductor, and a high-resistance R, or only integrates one of the sampling semiconductor and the starting semiconductor, and their functions are independent of each other and do not affect each other during the working state. The superjunction product is composed of multiple groups of P / N columns connected alternately. To ensure the independence of functional semiconductors from each other, isolation design is required between functional semiconductors. For the isolation design, it is also achieved through the arrangement of P / N columns. When arranging the isolation P / N columns, the isolation voltage between MOS and the breakdown voltage of the die need to be considered.

[0004] Currently, in the prior art, as shown in Figure 1 For the isolation design of an intelligent superjunction semiconductor device, only by designing horizontal P / N columns between vertical P / N columns for isolation. Although this isolation design can meet the breakdown voltage requirements of the die, in actual process, after the active regions of the sampling semiconductor and the starting semiconductor go through the process of high-temperature annealing, they will be connected to the main active region of the device, resulting in unstable isolation voltage, large fluctuations, and even a situation where it is lower than 50V. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a multi-layer epitaxial intelligent semiconductor device to solve the technical problems of unstable isolation voltage, large fluctuations, and low isolation voltage in the prior art.

[0006] The present invention provides a multi-layer epitaxial intelligent semiconductor device, including a main semiconductor and at least one functional semiconductor integrally arranged, the functional semiconductor is arranged in the main semiconductor, and the functional semiconductor includes a functional isolation region and a functional active region arranged inside the functional isolation region;

[0007] The functional isolation region, the functional active region, and the main semiconductor share a first-conductivity-type substrate and a first-conductivity-type epitaxial layer, and the first-conductivity-type epitaxial layer is disposed on the front surface of the first-conductivity-type substrate;

[0008] The functional isolation region includes:

[0009] At least two second-conductivity-type first functional columns are disposed in the first-conductivity-type epitaxial layer;

[0010] A second-conductivity-type second functional column is disposed on the front surface of each of the second-conductivity-type first functional columns and is connected to the second-conductivity-type first functional column, and the width of the second-conductivity-type second functional column in the first direction is smaller than the width of the second-conductivity-type first functional column in the first direction;

[0011] The functional active region includes at least two second-conductivity-type third functional columns disposed in the first-conductivity-type epitaxial layer, and the width of the second-conductivity-type third functional column in the first direction is greater than the width of the second-conductivity-type second functional column in the first direction;

[0012] For each of the second-conductivity-type first functional columns, at least two second-conductivity-type second functional columns are provided and are all connected to the corresponding second-conductivity-type first functional column. The two second-conductivity-type second functional columns are arranged in parallel, and the adjacent two second-conductivity-type second functional columns are separated by the intermediate first-conductivity-type epitaxial layer;

[0013] The width of the second-conductivity-type second functional column in the first direction is set to be half of the width of the second-conductivity-type first functional column in the first direction.

[0014] Optionally, the first-conductivity-type epitaxial layer includes a plurality of sub-epitaxial layers stacked in sequence. The sub-epitaxial layer includes a plurality of first sub-epitaxial layers and a plurality of second sub-epitaxial layers. The second sub-epitaxial layer is disposed on the front surface of the first sub-epitaxial layer, and the first sub-epitaxial layer and the second sub-epitaxial layer are stacked in sequence;

[0015] The second-conductivity-type first functional column is disposed in the first sub-epitaxial layer and extends toward the second sub-epitaxial layer. The second-conductivity-type second functional column is disposed in the second sub-epitaxial layer. The second-conductivity-type third functional column extends from the first sub-epitaxial layer near the first-conductivity-type substrate toward the second sub-epitaxial layer until it extends into the second sub-epitaxial layer.

[0016] Optionally, the sub-epitaxial layer includes a plurality of third sub-epitaxial layers, and the plurality of third sub-epitaxial layers are stacked in sequence on the front surface of the second sub-epitaxial layer;

[0017] The functional isolation region further includes a fourth functional pillar of the second conductivity type, which is disposed in the third sub-epitaxial layer and extends along the stacking direction of the plurality of sub-epitaxial layers until it is connected to the corresponding functional pillar of the second conductivity type;

[0018] The width of the fourth functional pillar of the second conductivity type in the first direction is greater than the width of the second functional pillar of the second conductivity type in the first direction.

[0019] Optionally, N layers of sub-epitaxial layers are sequentially stacked, wherein the thickness of the nth sub-epitaxial layer is not greater than the thickness of the (n - 1)th sub-epitaxial layer, and the thickness of the nth sub-epitaxial layer is less than the thickness of the first sub-epitaxial layer.

[0020] Optionally, a field oxide layer is disposed on the front surface of the first conductivity type epitaxial layer, and the field oxide layer is disposed in the region of the corresponding functional isolation region on the first conductivity type epitaxial layer.

[0021] Optionally, the functional semiconductor is set as a sampling semiconductor and / or a starting semiconductor.

[0022] Optionally, the main semiconductor includes:

[0023] At least two main pillars of the second conductivity type, extending from the front surface to the back surface of the first conductivity type epitaxial layer;

[0024] A body region of the second conductivity type, disposed on the front surface of the first conductivity type epitaxial layer and within the first conductivity type epitaxial layer;

[0025] A source region of the first conductivity type, disposed on the front surface of the body region of the second conductivity type and within the body region of the second conductivity type;

[0026] A gate structure, disposed between two adjacent main pillars of the second conductivity type and on the front surface of the second conductivity type epitaxial layer.

[0027] The present invention also provides a method for manufacturing a multi-layer epitaxial intelligent semiconductor device, including:

[0028] Select a first conductivity type substrate, and grow a first sub-epitaxial layer on the first conductivity type substrate;

[0029] Through photolithographic masking, inject second conductivity type ions into the corresponding functional isolation region, functional active region, and partial regions of the main semiconductor of the first sub-epitaxial layer to form a first functional pillar region of the second conductivity type, a third functional pillar region of the second conductivity type, and a main pillar region of the second conductivity type;

[0030] Continuously epitaxially grow multiple layers of the first sub-epitaxial layer, and continuously implant ions of the second conductivity type;

[0031] Continuously epitaxially grow multiple layers of the second sub-epitaxial layer, and implant ions of the second conductivity type to form multiple rows of second conductivity type second functional pillar regions, second conductivity type third functional pillar regions, and second conductivity type main pillar regions;

[0032] Continuously epitaxially grow multiple layers of the third sub-epitaxial layer and implant ions of the second conductivity type in partial regions of the multiple layers of the third sub-epitaxial layer to form multiple rows of second conductivity type fourth functional pillar regions, second conductivity type third functional pillar regions, and second conductivity type main pillar regions;

[0033] Advance at high temperature, diffuse and connect to form second conductivity type first functional pillars, second conductivity type second functional pillars, second conductivity type third functional pillars, second conductivity type fourth functional pillars, and second conductivity type main pillars;

[0034] Grow a field oxide layer on the front surface of the first conductivity type epitaxial layer, and etch away the field oxide layer in the main semiconductor and functional active region areas;

[0035] Grow a gate oxide layer on the front surface of the first conductivity type epitaxial layer in the main semiconductor and functional active region areas, and deposit polysilicon on the gate oxide layer to form a gate structure;

[0036] Inject ions of the second conductivity type on the front surface of the first conductivity type epitaxial layer without a gate structure and a field oxide layer, and advance at high temperature to form a second conductivity type body region;

[0037] Through photolithographic masking, inject ions of the first conductivity type in partial regions on the front surface of the second conductivity type body region, and advance at high temperature to form a first conductivity type source region;

[0038] Deposit an insulating dielectric layer on the front surface of the first conductivity type epitaxial layer, and deposit metal on the front surface of the insulating dielectric layer to form a front metal layer, and deposit metal on the back surface of the first conductivity type substrate to form a back metal layer,

[0039] The technical solution of the present invention has the following advantages:

[0040] 1. The multi-layer epitaxial intelligent semiconductor device provided by the present invention isolates the functional active region by arranging a first functional column of a second conductivity type and a second functional column of a second conductivity type in the functional isolation region, and the width of the second functional column of the second conductivity type in the first direction is smaller than the width of the first functional column of the second conductivity type in the first direction. The isolation effect is better than that of only arranging P / N columns in the functional isolation region before. After the semiconductor structure undergoes a high-temperature annealing process, the independence of the functional active region can still be ensured, the isolation voltage is stable, the isolation electric field is smoother, and the peak electric field is effectively reduced. Therefore, it can ensure a stable isolation voltage under the condition that the main semiconductor voltage remains unchanged, increase the design window, and can reach more than 200V.

[0041] 2. The setting of multiple first sub-epitaxial layers and multiple second epitaxial layers in the multi-layer epitaxial intelligent semiconductor device provided by the present invention enables the formation of a first functional column of a second conductivity type layer by layer within the first sub-epitaxial layer and the formation of a second functional column of a second conductivity type layer by layer within the second sub-epitaxial layer. The connection of the first functional column of the second conductivity type and the second functional column of the second conductivity type can be achieved by high-temperature promotion. In production, the original production process does not need to be changed too much. Only when growing the first sub-epitaxial layer and the second sub-epitaxial layer, it is necessary to inject ions of the second conductivity type, which is more convenient for forming the first functional column of the second conductivity type and the second functional column of the second conductivity type. Especially when the first functional column of the second conductivity type and the second functional column of the second conductivity type form a Y-shaped structure, compared with other preparation methods, it can not only obtain the advantages brought by the multi-layer epitaxial technology, but also form the Y-shaped structure more quickly, conveniently and stably, without multiple trench digging and filling. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as a limitation of the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 It is a schematic diagram of the prior art in the background technology of the present invention;

[0044] Figure 2 It is a schematic diagram of the structure of the multi-layer epitaxial intelligent semiconductor device of the present invention;

[0045] Figure 3 For Figure 2 an enlarged view of part A in;

[0046] Figure 4 It is a front-end step diagram of the preparation method of the intelligent semiconductor device of the present invention;

[0047] Figure 5 This is the back-end process diagram of the preparation method of the intelligent semiconductor device in the present invention.

[0048] Explanation of reference numerals:

[0049] 1. Substrate of the first conductivity type; 2. Epitaxial layer of the first conductivity type; 21. Sub-epitaxial layer; 211. First sub-epitaxial layer; 212. Second sub-epitaxial layer; 213. Third sub-epitaxial layer; 3. First functional pillar of the second conductivity type; 31. First functional pillar region of the second conductivity type; 4. Second functional pillar of the second conductivity type; 41. Second functional pillar region of the second conductivity type; 5. Third functional pillar of the second conductivity type; 51. Third functional pillar region of the second conductivity type; 6. Fourth functional pillar of the second conductivity type; 61. Fourth functional pillar region of the second conductivity type; 7. Field oxide layer; 8. Main pillar of the second conductivity type; 81. Main pillar region of the second conductivity type; 9. Body region of the second conductivity type; 10. Source region of the first conductivity type; 11. Gate structure; 12. Gate oxide layer; 13. Insulating dielectric layer; 14. Front metal layer; 15. Back metal layer; 16. Main semiconductor; 17. Functional isolation region; 18. Functional active region. Detailed implementation manners

[0050] Next, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the description of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0051] Unless otherwise clearly specified and defined, terms such as "arranged", "installed", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific situations.

[0052] The orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the present invention is usually placed during use. It is only for the convenience of description and simplification of description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0053] The terms "first", "second", "third", etc. are only used to distinguish components with similar attributes, rather than indicating or implying relative importance or a specific order.

[0054] The term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion. In addition to the elements listed, it may also include other elements not specifically listed.

[0055] Embodiment

[0056] The present invention provides a multi-layer epitaxial intelligent semiconductor device. The semiconductor device is set as a MOSFET device or an IGBT device. In this embodiment, the MOSFET device is taken as an example. The MOSFET device includes an N-type MOSFET device and a P-type MOSFET device. For the N-type MOSFET device, the first conduction type is N-type and the second conduction type is P-type; for the P-type MOSFET device, the first conduction type is P-type and the second conduction type is N-type. In this embodiment, the N-type MOSFET device is taken as an example.

[0057] Refer to Figure 2 and Figure 3 As shown, the multi-layer epitaxial intelligent semiconductor device includes a main semiconductor 16 and at least one functional semiconductor integratedly arranged. In this embodiment, the functional semiconductor is set as a sampling semiconductor and / or a starting semiconductor. Further, in this embodiment, one sampling semiconductor and one starting semiconductor are provided.

[0058] Specifically, the functional semiconductor is arranged inside the main semiconductor 16 and surrounded by the main semiconductor 16. The functional semiconductor includes a functional isolation region 17 and a functional active region 18 arranged inside the functional isolation region 17 and surrounded by the functional isolation region 17. The functional active region 18, the functional isolation region 17 and the main semiconductor 16 share a first conduction type substrate 1 and a first conduction type epitaxial layer 2. The first conduction type epitaxial layer 2 is arranged on the front side of the first conduction type substrate 1.

[0059] The first conduction type epitaxial layer 2 includes a plurality of sub-epitaxial layers 21 stacked in sequence. The sub-epitaxial layer 21 includes a plurality of first sub-epitaxial layers 211 and a plurality of second sub-epitaxial layers 212. The second sub-epitaxial layer 212 is arranged on the front side of the first sub-epitaxial layer 211. The first sub-epitaxial layer 211 and the second sub-epitaxial layer 212 are stacked in sequence.

[0060] The functional isolation region 17 includes a first functional pillar 3 of a second conductivity type and a second functional pillar 4 of a second conductivity type. Among them, at least two first functional pillars 3 of a second conductivity type are provided, which are arranged in the first sub-epitaxial layer 211 and extend from the lowermost first sub-epitaxial layer 211 into the uppermost first sub-epitaxial layer 211. The second functional pillar 4 of a second conductivity type is arranged corresponding to the first functional pillar 3 of a second conductivity type. At each position of the first functional pillar 3 of a second conductivity type, a second functional pillar 4 of a second conductivity type is provided. The second functional pillar 4 of a second conductivity type is arranged in the second sub-epitaxial layer 212 on the front side of the first functional pillar 3 of a second conductivity type and extends from the lowermost second sub-epitaxial layer 212 into the uppermost second sub-epitaxial layer 212. The second functional pillar 4 of a second conductivity type is connected to the first functional pillar 3 of a second conductivity type to form an integral body. The width of the second functional pillar 4 of a second conductivity type in the first direction is smaller than the width of the first functional pillar 3 of a second conductivity type in the first direction;

[0061] At this time, the functional active region 18 includes a third functional pillar 5 of a second conductivity type. At least two third functional pillars 5 of a second conductivity type are provided, and they extend from the first sub-epitaxial layer 211 close to the first conductivity type substrate 1 towards the second sub-epitaxial layer 212 until they extend into the uppermost second sub-epitaxial layer 212. The width of the third functional pillar 5 of a second conductivity type in the first direction is larger than the width of the second functional pillar 4 of a second conductivity type in the first direction, and the width of the third functional pillar 5 of a second conductivity type in the first direction is the same as the width of the first functional pillar 3 of a second conductivity type in the first direction. In Figure 1 the direction indicated by the arrow x is the first direction.

[0062] The traditional functional isolation region 17 is a P / N column with a single width. Charge balance depends on the precise control of doping concentration. During the high-temperature annealing process, the influence of lateral diffusion of doping ions is large, and it is easy to connect with the active region, resulting in the effective carrier concentration in the column region deviating from the designed value, destroying charge balance, and then reducing the isolation voltage. By providing a first functional column 3 of the second conductivity type and a second functional column 4 of the second conductivity type in the functional isolation region 17, and the width of the second functional column 4 of the second conductivity type in the first direction is less than the width of the first functional column 3 of the second conductivity type in the first direction, the functional active region 18 is isolated. Since the width of the second functional column 4 of the second conductivity type in the first direction is less than the width of the first functional column 3 of the second conductivity type in the first direction, the relative influence of the lateral distance during high-temperature annealing is smaller, and the charge distribution is more refined, with a low charge imbalance degree. The boundary with the main semiconductor 16 can still be maintained clear at high temperatures, avoiding carrier interdiffusion with adjacent regions and resulting in connection with the main semiconductor 16. The isolation effect is better than that of only setting P / N columns in the functional isolation region 17 before, and the independence of the functional active region 18 can still be ensured after the semiconductor device undergoes the high-temperature annealing process;

[0063] At the same time, by reducing the column width of the second functional column 4 of the second conductivity type, a secondary electric field step is formed on the side close to the active region, making the electric field distribution stepped. By discretizing the charge distribution, the electric field concentration effect of the traditional single-column structure is reduced, and the peak electric field is lowered, so that the isolation electric field is smoother, effectively reducing the peak electric field and avoiding local breakdown. Since the peak electric field is reduced, it is possible to ensure a stable isolation voltage while the voltage of the main semiconductor 16 remains unchanged, increasing the design window, which can reach more than 200V.

[0064] In addition, the setting of multiple first sub-epitaxial layers 211 and multiple second sub-epitaxial layers 212 enables the formation of the first functional column 3 of the second conductivity type layer by layer within the first sub-epitaxial layer 211, and the formation of the second functional column 4 of the second conductivity type layer by layer within the second sub-epitaxial layer 212. The connection of the first functional column 3 of the second conductivity type and the second functional column 4 of the second conductivity type can be achieved by high-temperature promotion, without multiple trench etching and filling. In production, it is more convenient than the deep trench process to form the first functional column 3 of the second conductivity type and the second functional column 4 of the second conductivity type.

[0065] As a specific implementation manner, two second-conductive-type second functional columns 4 corresponding to each second-conductive-type first functional column 3 are provided, and one ends of the two second-conductive-type second functional columns 4 facing the second-conductive-type first functional column 3 are both connected to the second-conductive-type first functional column 3. The two second-conductive-type second functional columns 4 are arranged in parallel. The width of the second-conductive-type second functional column 4 in the first direction is set to be half of the width of the second-conductive-type first functional column 3 in the first direction. Adjacent second-conductive-type second functional columns 4 are separated by the middle second sub-epitaxial layer 212. The width ratio of the second-conductive-type second functional column 4 to the second sub-epitaxial layer 212 therebetween is kept consistent with the width ratio of the second-conductive-type first functional column 3 to the first sub-epitaxial layer 211 therebetween;

[0066] By setting the number of the second-conductive-type second functional columns 4 to two and setting the width of the two second-conductive-type second functional columns 4 to be half of the width of the second-conductive-type first functional column 3, it is ensured that the width ratio of the second-conductive-type second functional column 4 to the first-conductive-type epitaxial layer 2 therebetween is kept consistent with the width ratio of the second-conductive-type first functional column 3 to the first-conductive-type epitaxial layer 2 therebetween, avoiding that only one second-conductive-type second functional column 4 is provided on the front surface of the second-conductive-type first functional column 3, and at this time the width of the second-conductive-type second functional column 4 is less than the width of the second-conductive-type first functional column 3, resulting in that the width of the first-conductive-type epitaxial layer 2 between adjacent second-conductive-type second functional columns 4 will become more than twice the width of the second-conductive-type second functional column 4. In order to ensure charge balance, it is necessary to adjust the ion concentration in the first-conductive-type epitaxial layer 2 between the two second-conductive-type second functional columns 4 here again, which invisibly increases the preparation steps, improves the preparation cost, and increases the preparation time. In this embodiment, two second-conductive-type second functional columns 4 are provided at each second-conductive-type first functional column 3, and the size ratio is the same as that of the first-conductive-type epitaxial layer 2 between the second-conductive-type first functional column 3 below, which can directly ensure the upper and lower charge balance without additionally adjusting the ion concentration, reducing the preparation steps, the preparation cost and time.

[0067] In addition, when the number of the second-conductive-type second functional columns 4 is set to two, the second-conductive-type second functional column 4 and the second-conductive-type first functional column 3 form a Y-shaped structure at this time. By preparing the Y-shaped structure in a multi-epitaxial manner, compared with other preparation methods, it can not only obtain the advantages brought by the multi-epitaxial technology, but also form the Y-shaped structure more quickly, conveniently and stably. The preparation of the Y-shaped structure is further more convenient. Only when multi-epitaxy is performed, it is only necessary to inject second-conductive-type ions.

[0068] As an alternative embodiment, the sub-epitaxial layer 21 further includes a plurality of third sub-epitaxial layers 213. The plurality of third sub-epitaxial layers 213 are sequentially stacked on the front side of the second sub-epitaxial layer 212. At each second-conductive-type first functional pillar 3, a second-conductive-type fourth functional pillar 6 is correspondingly provided. The second-conductive-type fourth functional pillar 6 is disposed within the third epitaxial layer and extends from the back side to the front side of the third epitaxial layer. One end of the second-conductive-type fourth functional pillar 6 is connected to two corresponding second-conductive-type second functional pillars 4. The width of the second-conductive-type fourth functional pillar 6 in the first direction is greater than the width of the second-conductive-type second functional pillar 4 in the first direction. And in this embodiment, it can be further set that the width of the second-conductive-type fourth functional pillar 6 is the same as or close to the width of the second-conductive-type first functional pillar 3. Through the setting of the second-conductive-type fourth functional pillar 6, when other structures are provided on the front side of the first-conductive-type epitaxial layer 2, it is the same as the conventional setting, and there is no need to adjust the parameters or dimensions of other structures just because only the second-conductive-type second functional pillar 4 is provided, making the production more convenient. Additionally, at this time, the second-conductive-type third functional pillar 5 extends into the third sub-epitaxial layer 213 until it extends into the uppermost third sub-epitaxial layer 213.

[0069] As a specific embodiment, the sub-epitaxial layer 21 is sequentially stacked with n layers from the front side of the first-conductive-type substrate 1 towards the second-conductive-type body region 9, that is, in the upward direction. Among them, the thickness of the nth sub-epitaxial layer 21 is not greater than the thickness of the (n - 1)th sub-epitaxial layer 21, and the thickness of the nth sub-epitaxial layer 21 is less than the thickness of the first sub-epitaxial layer 21. In this embodiment, the sub-epitaxial layer 21 is provided with 7 - 13 layers. Further, in this embodiment, the sub-epitaxial layer 21 is provided with 8 layers. By gradually reducing the thickness of the plurality of sub-epitaxial layers 21 from bottom to top, the electric field is evenly distributed, making the electric field more evenly distributed within the entire first-conductive-type epitaxial layer 2, improving the breakdown voltage capability of the device, effectively controlling the electric field gradient of each sub-epitaxial layer 21, enabling the electric field to gradually change between different layers, avoiding the possible sudden change of the electric field in a single sub-epitaxial layer 21, refining the current-carrying capacity, and achieving charge balance.

[0070] On the front surface of the first-conductivity-type epitaxial layer 2, a field oxide layer 7 is provided. The field oxide layer 7 is disposed in the region of the corresponding functional isolation region 17 on the first-conductivity-type epitaxial layer 2. Additionally, the main semiconductor 16 includes second-conductivity-type main columns 8, a second-conductivity-type body region 9, a first-conductivity-type source region 10, and a gate structure 11. Among them, at least two second-conductivity-type main columns 8 are provided. The second-conductivity-type main columns 8 extend from the front surface of the first-conductivity-type epitaxial layer 2 towards the back surface of the first-conductivity-type epitaxial layer 2. The width of the second-conductivity-type main columns 8 in the first direction is the same as the width of the second-conductivity-type first functional column 3 in the first direction. The second-conductivity-type body region 9 is disposed on the front surface of the first-conductivity-type epitaxial layer 2 and is located within the first-conductivity-type epitaxial layer 2. The first-conductivity-type source region 10 is disposed on the front surface of the second-conductivity-type body region 9 and is located within the second-conductivity-type body region 9. The gate structure 11 is disposed between two adjacent second-conductivity-type main columns 8 and is disposed on the front surface of the second-conductivity-type epitaxial layer. A gate oxide layer 12 is provided between the gate structure 11 and the first-conductivity-type epitaxial layer 2.

[0071] An insulating dielectric layer 13 is deposited on the front surface of the first-conductivity-type epitaxial layer 2, and the insulating dielectric layer 13 is etched to form a metal contact via. The metal contact via is opened corresponding to the second-conductivity-type body region 9. Metal is deposited on the surface of the insulating dielectric layer 13, and the metal contact via is filled to form a front metal layer 14. Metal is deposited on the back surface of the first-conductivity-type substrate 1 to form a back metal layer 15.

[0072] Embodiment 2

[0073] Refer to Figures 4 - 5 As shown, this embodiment provides a method for manufacturing an intelligent semiconductor device, including:

[0074] S1, select a first-conductivity-type substrate 1, and grow a first layer of first sub-epitaxial layer 211 on the first-conductivity-type substrate 1. Among them, the first-conductivity-type substrate 1 selects N-type silicon as the substrate, and the first sub-epitaxial layer 211 is grown by an epitaxial process;

[0075] S2, through photolithographic masking, inject second-conductivity-type ions into the regions of the corresponding functional isolation region 17, functional active region 18, and main semiconductor 16 on the first sub-epitaxial layer 211, so as to form a second-conductivity-type first functional column region 31, a second-conductivity-type third functional column region 51, and a second-conductivity-type main column region 81;

[0076] S3, continuously epitaxially grow multiple layers of the first sub-epitaxial layer 211 and inject second-conductivity-type ions into partial regions of the multiple layers of the first sub-epitaxial layer 211 to form multiple rows of second-conductivity-type first functional column regions 31, second-conductivity-type third functional column regions 51, and second-conductivity-type main column regions 81;

[0077] S4. Continuously epitaxially grow multiple layers of the second sub-epitaxial layer 212 on the first sub-epitaxial layer 211, and implant ions of the second conduction type into partial regions of the multiple layers of the second sub-epitaxial layer 212 to form multiple rows of second-conduction-type second functional pillar regions 41, second-conduction-type third functional pillar regions 51, and second-conduction-type main pillar regions 81.

[0078] S5. Continuously epitaxially grow multiple layers of the third sub-epitaxial layer 213 on the second sub-epitaxial layer 212, and implant ions of the second conduction type into partial regions of the multiple layers of the third sub-epitaxial layer 213 to form multiple rows of second-conduction-type fourth functional pillar regions 61, second-conduction-type third functional pillar regions 51, and second-conduction-type main pillar regions 81, where each row of the second-conduction-type third functional pillar regions 51 and the second-conduction-type main pillar regions 81 in S2, S3, and S4 are in the same row.

[0079] S6. High-temperature drive, diffuse the second-conduction-type first functional pillar region 31, second-conduction-type second functional pillar region 41, second-conduction-type third functional pillar region 51, second-conduction-type fourth functional pillar region 61, and second-conduction-type main pillar region 81, so that each row of the second-conduction-type first functional pillar region 31, second-conduction-type second functional pillar region 41, second-conduction-type third functional pillar region 51, second-conduction-type fourth functional pillar region 61, and second-conduction-type main pillar region 81 are diffused and connected to form the second-conduction-type first functional pillar 3, second-conduction-type second functional pillar 4, second-conduction-type third functional pillar 5, second-conduction-type fourth functional pillar 6, and second-conduction-type main pillar 8, and the second-conduction-type first functional pillar 3 is connected to the corresponding two second-conduction-type second functional pillars 4 and one second-conduction-type fourth functional pillar 6.

[0080] S7. Grow a field oxide layer 7 on the front surface of the first-conduction-type epitaxial layer 2, and etch away the field oxide layer 7 in the regions of the main semiconductor 16 and the functional active region 18.

[0081] S8. Grow a gate oxide layer 12 on the front surface of the first-conduction-type epitaxial layer 2 in the regions of the main semiconductor 16 and the functional active region 18, and etch away a part of it so that the gate oxide layer 12 at this time is located between two second-conduction-type third functional pillars 5 and between two second-conduction-type main pillars 8. Deposit polysilicon on the remaining part of the gate oxide layer 12 to form a gate structure 11.

[0082] S9. There are gaps between the gate structure 11 and the second-conduction-type third functional pillar 5 and between the gate structure 11 and the second-conduction-type main pillar 8, and there is no restriction of the gate oxide layer 12 and the field oxide layer 7. Inject ions of the second conduction type into the front surface of the first-conduction-type epitaxial layer 2 without the gate structure 11 and the field oxide layer 7, and perform high-temperature drive to form a second-conduction-type body region 9.

[0083] S10. Through photolithographic masking, inject first-conductivity-type ions into a partial area on the front surface of the second-conductivity-type body region 9, and perform high-temperature drive to form two first-conductivity-type source regions 10.

[0084] S11. Deposit an insulating dielectric layer 13 on the front surface of the first-conductivity-type epitaxial layer 2 so that the insulating dielectric layer 13 wraps the gate structure 11 and the field oxide layer 7. Then, etch the insulating dielectric layer 13 to etch out a plurality of through holes in the insulating dielectric layer 13, thereby forming metal contact through holes. The metal contact through holes are located above the second-conductivity-type body region 9. And during etching, an additional 0.3 mm to 0.4 mm is etched into the first-conductivity-type epitaxial layer 2 to ensure that the insulating dielectric layer 13 can be completely removed, exposing the metal contact points, and ensuring the stability and reliability of the electrical connection.

[0085] Deposit metal on the front surface of the insulating dielectric layer 13 and fill the metal contact through holes to form a front metal layer 14, and deposit metal on the back surface of the first-conductivity-type substrate 1 to form a back metal layer 15.

[0086] As described above, the above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A multi-layer epitaxial intelligent semiconductor device, characterized in that, It includes a main semiconductor with an integrated setting and at least one functional semiconductor. The functional semiconductor is disposed within the main semiconductor. The functional semiconductor includes a functional isolation region and a functional active region disposed inside the functional isolation region. The functional isolation region, the functional active region, and the main semiconductor share a first-conductivity-type substrate and a first-conductivity-type epitaxial layer. The first-conductivity-type epitaxial layer is disposed on the front side of the first-conductivity-type substrate. The functional isolation region includes: At least two second-conductivity-type first functional pillars disposed within the first-conductivity-type epitaxial layer. A second-conductivity-type second functional pillar disposed on the front side of each of the second-conductivity-type first functional pillars and connected to the second-conductivity-type first functional pillar. The width of the second-conductivity-type second functional pillar in the first direction is less than the width of the second-conductivity-type first functional pillar in the first direction. The functional active region includes at least two second-conductivity-type third functional pillars disposed within the first-conductivity-type epitaxial layer. The width of the second-conductivity-type third functional pillar in the first direction is greater than the width of the second-conductivity-type second functional pillar in the first direction. For each of the second-conductivity-type first functional pillars, there are at least two corresponding second-conductivity-type second functional pillars, and they are all connected to the corresponding second-conductivity-type first functional pillar. The two second-conductivity-type second functional pillars are arranged in parallel, and adjacent two second-conductivity-type second functional pillars are separated by the intermediate first-conductivity-type epitaxial layer. The width of the second-conductivity-type second functional pillar in the first direction is set to be half of the width of the second-conductivity-type first functional pillar in the first direction.

2. The multi-layer epitaxial intelligent semiconductor device according to claim 1, characterized in that, The first-conductivity-type epitaxial layer includes a plurality of sub-epitaxial layers stacked in sequence. The sub-epitaxial layer includes a plurality of first sub-epitaxial layers and a plurality of second sub-epitaxial layers. The second sub-epitaxial layer is disposed on the front side of the first sub-epitaxial layer, and the first sub-epitaxial layer and the second sub-epitaxial layer are stacked in sequence. The second-conductivity-type first functional pillar is disposed within the first sub-epitaxial layer and extends towards the second sub-epitaxial layer. The second-conductivity-type second functional pillar is disposed within the second sub-epitaxial layer. The second-conductivity-type third functional pillar extends from within the first sub-epitaxial layer close to the first-conductivity-type substrate towards the second sub-epitaxial layer direction until it extends into the second sub-epitaxial layer.

3. The multi-layer epitaxial intelligent semiconductor device according to claim 2, characterized in that, The sub-epitaxial layer includes a plurality of third sub-epitaxial layers, and the plurality of third sub-epitaxial layers are stacked in sequence on the front side of the second sub-epitaxial layer. The functional isolation region further includes a second-conductivity-type fourth functional pillar. The second-conductivity-type fourth functional pillar is disposed within the third sub-epitaxial layer and extends along the stacking direction of the plurality of sub-epitaxial layers until it is connected to the corresponding second-conductivity-type functional pillar. The width of the second-conductivity-type fourth functional pillar in the first direction is greater than the width of the second-conductivity-type second functional pillar in the first direction.

4. The multi-layer epitaxial intelligent semiconductor device according to claim 2, characterized in that, The sub-epitaxial layers are stacked in sequence for N layers, where the thickness of the nth sub-epitaxial layer is not greater than that of the (n - 1)th sub-epitaxial layer, and the thickness of the nth sub-epitaxial layer is less than that of the first sub-epitaxial layer.

5. The multi-layer epitaxial intelligent semiconductor device according to claim 1, characterized in that, A field oxide layer is provided on the front surface of the first-conductivity-type epitaxial layer, and the field oxide layer is provided in the area of the corresponding functional isolation region on the first-conductivity-type epitaxial layer.

6. The multi-layer epitaxial intelligent semiconductor device according to claim 1, characterized in that, The functional semiconductor is set as a sampling semiconductor and / or a starting semiconductor.

7. The multi-layer epitaxial intelligent semiconductor device according to any one of claims 1-6, characterized in that, The main semiconductor includes: At least two second-conductivity-type main columns extending from the front surface to the back surface of the first-conductivity-type epitaxial layer; A second-conductivity-type body region provided on the front surface of the first-conductivity-type epitaxial layer and located within the first-conductivity-type epitaxial layer; A first-conductivity-type source region provided on the front surface of the second-conductivity-type body region and located within the second-conductivity-type body region; A gate structure provided between two adjacent second-conductivity-type main columns and on the front surface of the second-conductivity-type epitaxial layer.

8. A method for preparing a multi-layer epitaxial intelligent semiconductor device, characterized in that, It includes: Select a first-conductivity-type substrate and grow a layer of first sub-epitaxial layer on the first-conductivity-type substrate; Through photolithographic masking, implant second-conductivity-type ions into the corresponding functional isolation region, functional active region, and partial regions of the main semiconductor of the first sub-epitaxial layer to form a second-conductivity-type first functional column region, a second-conductivity-type third functional column region, and a second-conductivity-type main column region; Continuously epitaxially grow multiple layers of the first sub-epitaxial layer and continuously implant second-conductivity-type ions; Continuously epitaxially grow multiple layers of the second sub-epitaxial layer and implant second-conductivity-type ions to form multiple rows of second-conductivity-type second functional column regions, second-conductivity-type third functional column regions, and second-conductivity-type main column regions; Continuously epitaxially grow multiple layers of the third sub-epitaxial layer and implant second-conductivity-type ions in partial regions of the multiple layers of the third sub-epitaxial layer to form multiple rows of second-conductivity-type fourth functional column regions, second-conductivity-type third functional column regions, and second-conductivity-type main column regions; High-temperature drive to diffusely connect to form a second-conductivity-type first functional column, a second-conductivity-type second functional column, a second-conductivity-type third functional column, a second-conductivity-type fourth functional column, and a second-conductivity-type main column; Grow a field oxide layer on the front surface of the first-conductivity-type epitaxial layer and etch away the field oxide layer in the regions of the main semiconductor and the functional active region; Grow a gate oxide layer on the front surface of the first-conductivity-type epitaxial layer in the regions of the main semiconductor and the functional active region, and deposit polysilicon on the gate oxide layer to form a gate structure; Implant second-conductivity-type ions on the front surface of the first-conductivity-type epitaxial layer without a gate structure and a field oxide layer and perform high-temperature drive to form a second-conductivity-type body region; Through photolithographic masking, implant first-conductivity-type ions into partial regions on the front surface of the second-conductivity-type body region and perform high-temperature drive to form a first-conductivity-type source region; Deposit an insulating dielectric layer on the front surface of the first-conductivity-type epitaxial layer and deposit metal on the front surface of the insulating dielectric layer to form a front metal layer, and deposit metal on the back surface of the first-conductivity-type substrate to form a back metal layer.

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