Ping-pong self-stabilization zero-loop ripple suppression precision operational amplifier

Abstract

The invention discloses a ping-pong self-stabilization zero-loop ripple suppression precision operational amplifier, which comprises a high-frequency path and a low-frequency path, and is characterized in that the high-frequency path comprises a third transconductance amplifier Gm3 and a fourth transconductance amplifier Gm4; the low-frequency path comprises a first transconductance amplifier Gm1-Gm3, a second transconductance amplifier Gm1-Gm3, a first chopper Cop1-Cop2, a second chopper Cop1-Cop2 and a ping-pong self-stabilization zero ripple suppression loop, and the ping-pong self-stabilization zero ripple suppression loop is used for suppressing offset voltage and output ripple generated by the low-frequency path. The invention designs a ping-pong self-stabilizing zero ripple suppression feedback (AZCFB) loop, the self offset voltage of the ripple suppression loop is eliminated by adopting an automatic zeroing technology, and the residual offset is filtered by a chopper and a filter. In addition, a high-pass filter is used for eliminating the influence of AZCFB loop sampling node direct-current potential deviation on output ripples, and the purpose of restraining the output ripples is achieved.

Description

Technical Field

[0001] The present invention relates to a precision operational amplifier with ping-pong auto-zero loop ripple suppression, belonging to the field of integrated circuit technology. Background Art

[0002] Operational amplifiers with low noise and low offset are key components in high-precision systems such as the front-end sampling of sensor circuits, high-precision reference buffers, and ADC drivers. To meet the requirements of high-precision systems, the mismatch voltage must be reduced to the microvolt level, the temperature drift of the mismatch voltage must be reduced, and low in-band noise must be achieved in the circuit. Traditional precision operational amplifier technologies include chopper technology and auto-zero technology, each with its own advantages and limitations. Chopper technology does not introduce low-frequency noise aliasing, but it generates significant output ripple, resulting in an excessive output offset voltage. On the other hand, although auto-zero technology generates the minimum output ripple, it causes low-frequency noise aliasing. In comparison, chopper technology has been more widely used due to its advantages in reducing low-frequency noise and improving power efficiency.

[0003] In addition, the academic and industrial communities have been actively researching methods to suppress the ripple of chopper circuits to reduce the mismatch voltage of precision operational amplifiers. Among them, the auto-calibrated feedback loop technology (ACFB technology) is widely used. The ACFB technology can effectively suppress the mismatch voltage in the low-frequency path. However, due to loop delay and clock skew, the offset voltage of the ACFB itself will cause output ripple. In addition, the offset voltage in the high-frequency path will cause a DC offset at the sampling node of the ACFB, resulting in greater output ripple and higher output offset voltage. Some scholars choose to trim the amplifier offset voltage to eliminate the offset ripple, but this will increase the complexity of circuit design, and the trimming process will also lead to an increase in cost. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a precision operational amplifier with ping-pong auto-zero loop ripple suppression, which uses the auto-zero technology to eliminate the offset voltage of the ripple suppression loop itself, and the remaining offset is filtered by a chopper and a filter. A high-pass filter is also used to eliminate the influence of the DC potential offset at the sampling node of the AZCFB loop on the output ripple, so as to achieve the purpose of suppressing the output ripple.

[0005] The present invention adopts the following technical solutions to solve the above technical problems:

[0006] A ping-pong self-stabilizing zero-loop ripple suppression precision operational amplifier, comprising a high-frequency path and a low-frequency path. The high-frequency path includes a third transconductance amplifier Gm3 and a fourth transconductance amplifier Gm4; the low-frequency path includes a first to third transconductance amplifier Gm1-Gm3, a first to second chopper Chop1-Chop2, and a ping-pong self-stabilizing zero ripple suppression loop, and the ping-pong self-stabilizing zero ripple suppression loop is used to suppress the offset voltage and output ripple generated by the low-frequency path;

[0007] The positive input signal of the operational amplifier is connected to the positive input terminal of the fourth transconductance amplifier Gm4, and the negative input signal is connected to the negative input terminal of the fourth transconductance amplifier Gm4; the positive output terminal of the fourth transconductance amplifier Gm4 is connected to the positive input terminal of the third transconductance amplifier Gm3, and the negative output terminal is connected to the negative input terminal of the third transconductance amplifier Gm3; the positive input signal of the operational amplifier is connected to the positive input terminal of the first transconductance amplifier Gm1 through the first chopper Chop1, and the negative input signal is connected to the negative input terminal of the first transconductance amplifier Gm1 through the first chopper Chop1; the negative output terminal of the first transconductance amplifier Gm1 is connected to the positive input terminal of the second transconductance amplifier Gm2 through the second chopper Chop2, and the positive output terminal of the first transconductance amplifier Gm1 is connected to the negative input terminal of the second transconductance amplifier Gm2 through the second chopper Chop2; the negative output terminal of the second transconductance amplifier Gm2 is connected to the positive input terminal of the third transconductance amplifier Gm3, and the positive output terminal of the second transconductance amplifier Gm2 is connected to the negative input terminal of the third transconductance amplifier Gm3; the output of the third transconductance amplifier Gm3 is used as the output of the operational amplifier;

[0008] The ping-pong self-stabilizing zero ripple suppression loop includes a first to second self-zeroing amplifier Gmaz1-Gmaz2, a fifth a transconductance amplifier Gm5a, a fifth b transconductance amplifier Gm5b, a sixth to seventh transconductance amplifier Gm6-Gm7, a third chopper Chop3, a filter SC_NF, a high-pass filter HPF, a first to second switch unit AZ1-AZ2, a first to second zeroing capacitor C1a-C2a, a third to fourth zeroing capacitor C1b-C2b, and a fifth to sixth integration capacitor Cint1-Cint2;

[0009] The non-inverting input terminal of the high-pass filter HPF is connected to the inverting input terminal of the second transconductance amplifier Gm2, and the inverting input terminal is connected to the non-inverting input terminal of the second transconductance amplifier Gm2; the non-inverting and inverting output terminals of the high-pass filter HPF are connected to the input terminal of the fifth a transconductance amplifier Gm5a through the first switching unit AZ1, and at the same time, the non-inverting and inverting output terminals of the high-pass filter HPF are connected to the input terminal of the fifth b transconductance amplifier Gm5b through the first switching unit AZ1; the non-inverting and inverting output terminals of the fifth a transconductance amplifier Gm5a are connected to the input terminal of the third chopper Chop3 through the second switching unit AZ2, and the non-inverting and inverting output terminals of the fifth b transconductance amplifier Gm5b are connected to the input terminal of the third chopper Chop3 through the second switching unit AZ2, and the output terminal of the third chopper Chop3 is connected to the non-inverting and inverting input terminals of the sixth transconductance amplifier Gm6; the non-inverting output terminal of the sixth transconductance amplifier Gm6 is connected to the non-inverting input terminal of the seventh transconductance amplifier Gm7 through the filter SC_NF, and the inverting output terminal of the sixth transconductance amplifier Gm6 is connected to the inverting input terminal of the seventh transconductance amplifier Gm7 through the filter SC_NF; a fifth integration capacitor Cint1 is connected between the inverting input terminal and the non-inverting output terminal of the sixth transconductance amplifier Gm6, and a sixth integration capacitor Cint2 is connected between the non-inverting input terminal and the inverting output terminal of the sixth transconductance amplifier Gm6; the non-inverting and inverting outputs of the seventh transconductance amplifier Gm7 are fed back to the first transconductance amplifier Gm1;

[0010] The negative input terminal of the first auto-zero amplifier Gmaz1 is grounded through the first zero-adjusting capacitor C1a, the positive input terminal of the first auto-zero amplifier Gmaz1 is grounded through the second zero-adjusting capacitor C2a, and the non-inverting and inverting outputs of the first auto-zero amplifier Gmaz1 are fed back to the fifth a transconductance amplifier Gm5a; the inverting output terminal of the fifth a transconductance amplifier Gm5a is connected to the inverting input terminal of the first auto-zero amplifier Gmaz1 through the second switching unit AZ2, and the non-inverting output terminal of the fifth a transconductance amplifier Gm5a is connected to the positive input terminal of the first auto-zero amplifier Gmaz1 through the second switching unit AZ2;

[0011] The positive input terminal of the second auto-zero amplifier Gmaz2 is grounded through the fourth zero-adjusting capacitor C2b, the inverting input terminal of the second auto-zero amplifier Gmaz1 is grounded through the third zero-adjusting capacitor C1b, and the non-inverting and inverting outputs of the first auto-zero amplifier Gmaz1 are fed back to the fifth b transconductance amplifier Gm5b; the inverting output terminal of the fifth b transconductance amplifier Gm5b is connected to the positive input terminal of the second auto-zero amplifier Gmaz2 through the second switching unit AZ2, and the non-inverting output terminal of the fifth b transconductance amplifier Gm5b is connected to the inverting input terminal of the second auto-zero amplifier Gmaz2 through the second switching unit AZ2.

[0012] Compared with the prior art, the present invention adopts the above technical solutions and has the following technical effects:

[0013] The present invention designs a ping-pong self-stabilizing zero ripple suppression (AZCFB) loop to suppress the ripple and offset voltage generated by Gm1; uses the ping-pong self-stabilizing zero technology to eliminate the ripple and offset voltage generated by Gm5a and Gm5b in the AZCFB loop itself; uses a high-pass filter to eliminate the output ripple caused by the offset voltages of the feed-forward stages Gm4 and Gm2, ultimately achieving the purpose of suppressing the overall output ripple of the operational amplifier and reducing the offset voltage of the operational amplifier. Description of the Drawings

[0014] Figure 1 is the circuit structure diagram of the ping-pong self-stabilizing zero loop ripple suppression precision operational amplifier proposed by the present invention;

[0015] Figure 2 is the overall working timing diagram of the precision operational amplifier proposed by the present invention;

[0016] Figure 3 is the self-stabilizing zero structure and switch timing diagram of the AZCFB loop proposed by the present invention;

[0017] Figure 4 is the circuit schematic diagram of the high-pass filter proposed by the present invention. Detailed Embodiments

[0018] The following details the embodiments of the present invention. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described by referring to the drawings are exemplary and are only used to explain the present invention and cannot be construed as a limitation of the present invention.

[0019] As Figure 1 shown, the present invention proposes a ping-pong self-stabilizing zero loop ripple suppression precision operational amplifier, which includes a low-frequency path composed of transconductance amplifiers Gm1, Gm2, Gm3, choppers Chop1, Chop2, and a ping-pong self-stabilizing zero ripple suppression loop, and a high-frequency path composed of transconductance amplifiers Gm4 and Gm3.

[0020] The non-inverting input signal of the operational amplifier is connected to the non-inverting input terminal of the fourth transconductance amplifier Gm4, and the inverting input signal is connected to the inverting input terminal of the fourth transconductance amplifier Gm4; the non-inverting output terminal of the fourth transconductance amplifier Gm4 is connected to the non-inverting input terminal of the third transconductance amplifier Gm3, and the inverting output terminal is connected to the inverting input terminal of the third transconductance amplifier Gm3; the non-inverting input signal of the operational amplifier is connected to the non-inverting input terminal of the first transconductance amplifier Gm1 through the first chopper Chop1, and the inverting input signal is connected to the inverting input terminal of the first transconductance amplifier Gm1 through the first chopper Chop1; the inverting output terminal of the first transconductance amplifier Gm1 is connected to the non-inverting input terminal of the second transconductance amplifier Gm2 through the second chopper Chop2, and the non-inverting output terminal of the first transconductance amplifier Gm1 is connected to the inverting input terminal of the second transconductance amplifier Gm2 through the second chopper Chop2; the inverting output terminal of the second transconductance amplifier Gm2 is connected to the non-inverting input terminal of the third transconductance amplifier Gm3, and the non-inverting output terminal of the second transconductance amplifier Gm2 is connected to the inverting input terminal of the third transconductance amplifier Gm3; the output of the third transconductance amplifier Gm3 is used as the output of the operational amplifier.

[0021] The AZCFB loop contains a ping-pong self-zeroing structure composed of Gm5a, Gmaz1, Gm5b, and Gmaz2, and together with the chopper Chop3, integrator Gm6, filter SC_NF, high-pass filter HPF, and Gm7, it constitutes a ripple suppression loop.

[0022] The non-inverting input terminal of the high-pass filter HPF is connected to the inverting input terminal of the second transconductance amplifier Gm2, and the inverting input terminal is connected to the non-inverting input terminal of the second transconductance amplifier Gm2; the non-inverting and inverting output terminals of the high-pass filter HPF are connected to the input terminal of the fifth a transconductance amplifier Gm5a through the first switch unit AZ1, and at the same time, the non-inverting and inverting output terminals of the high-pass filter HPF are connected to the input terminal of the fifth b transconductance amplifier Gm5b through the first switch unit AZ1; the non-inverting and inverting output terminals of the fifth a transconductance amplifier Gm5a are connected to the input terminal of the third chopper Chop3 through the second switch unit AZ2, and the non-inverting and inverting output terminals of the fifth b transconductance amplifier Gm5b are connected to the input terminal of the third chopper Chop3 through the second switch unit AZ2, and the output terminal of the third chopper Chop3 is connected to the non-inverting and inverting input terminals of the sixth transconductance amplifier Gm6; the non-inverting output terminal of the sixth transconductance amplifier Gm6 is connected to the non-inverting input terminal of the seventh transconductance amplifier Gm7 through the filter SC_NF, and the inverting output terminal of the sixth transconductance amplifier Gm6 is connected to the inverting input terminal of the seventh transconductance amplifier Gm7 through the filter SC_NF; a fifth integration capacitor Cint1 is connected between the inverting input terminal and the non-inverting output terminal of the sixth transconductance amplifier Gm6, and a sixth integration capacitor Cint2 is connected between the non-inverting input terminal and the inverting output terminal of the sixth transconductance amplifier Gm6; the non-inverting and inverting outputs of the seventh transconductance amplifier Gm7 are fed back to the first transconductance amplifier Gm1.

[0023] The negative input terminal of the first auto-zero amplifier Gmaz1 is grounded through the first zero-adjusting capacitor C1a, and the positive input terminal of the first auto-zero amplifier Gmaz1 is grounded through the second zero-adjusting capacitor C2a. The positive and negative outputs of the first auto-zero amplifier Gmaz1 are fed back to the fifth a transconductance amplifier Gm5a. The negative output terminal of the fifth a transconductance amplifier Gm5a is connected to the negative input terminal of the first auto-zero amplifier Gmaz1 through the second switching unit AZ2, and the positive output terminal of the fifth a transconductance amplifier Gm5a is connected to the positive input terminal of the first auto-zero amplifier Gmaz1 through the second switching unit AZ2.

[0024] The positive input terminal of the second auto-zero amplifier Gmaz2 is grounded through the fourth zero-adjusting capacitor C2b, and the negative input terminal of the second auto-zero amplifier Gmaz1 is grounded through the third zero-adjusting capacitor C1b. The positive and negative outputs of the first auto-zero amplifier Gmaz1 are fed back to the fifth b transconductance amplifier Gm5b. The negative output terminal of the fifth b transconductance amplifier Gm5b is connected to the positive input terminal of the second auto-zero amplifier Gmaz2 through the second switching unit AZ2, and the positive output terminal of the fifth b transconductance amplifier Gm5b is connected to the negative input terminal of the second auto-zero amplifier Gmaz2 through the second switching unit AZ2.

[0025] The main part of the operational amplifier is a three-stage Miller compensation circuit with a feed-forward stage (Gm4). The ripple suppression loop mainly suppresses the offset and ripple introduced by the low-frequency path. The timing diagram of the overall operation of the circuit is as Figure 2 shown, and the operation process and working principle are as follows:

[0026] First, the input chopper (Chop1) modulates the input signal to the chopping frequency, and then Gm1 amplifies the input offset voltage Vos1.

[0027] Second, the second-stage chopper (Chop2) modulates the output signal of Gm1 to demodulate the input signal back to the DC signal. Conversely, the offset voltage of Gm1 is modulated to the chopping frequency.

[0028] Third, the high-pass filter isolates the DC signal while transmitting the AC signal. Therefore, the high-frequency AC signal generated by Vos1 at the output terminal of Chop2 (Vsample) is transmitted to the auto-zero circuit of the AZCFB loop and amplified by Gm5a and Gm5b.

[0029] Fourth, the auto-zero circuit can eliminate the offset voltage existing in itself. In addition, the AC signal will be amplified by Gm5a and Gm5b and modulated back to the DC signal by the third-stage chopper (Chop3). The DC output signal of Chop3 is amplified by Gm6 and then filtered by the switched-capacitor notch filter (SC_NF) to generate a clean DC offset correction voltage (Vcorr) for Gm1.

[0030] Finally, Gm7 corrects the offset voltage of Gm1, reducing the output ripple caused by the offset voltage.

[0031] The periods of the first switching unit AZ1 and the second switching unit AZ2 are the same, the periods of the first chopper Chop1, the second chopper Chop2, the third chopper Chop3, and the filter SC_NF are the same, and the period of the first switching unit AZ1 is 1 / 2 of the period of the first chopper Chop1. When using the ripple suppression loop, it is necessary to ensure that the loop gain is large enough, at least greater than 80 dB. Considering the loop stability requirements, the AZCFB loop bandwidth can be set to 100 KHz and below.

[0032] Figure 3 This is the internal connection relationship and switching timing diagram of the ping-pong auto-zero circuit proposed by the present invention, including transconductance amplifiers Gm5a, Gmaz1, Gm5b, Gmaz2, and switches S1 to S16. For the auto-zero loop, Figure 3 The power consumption ratios of Gm5a,b and Gmaz1,2 in the loop need to be reasonably adjusted so that the potentials at the input ports of Gmaz1,2 are not saturated. The residual offset voltage of the auto-zero loop is as follows:

[0033]

[0034] Using the auto-zero technology can reduce the offset voltage by A vAz times. In addition, the residual offset voltage will be modulated into a high-frequency signal by Chop3 and then filtered by a switched-capacitor notch filter (SC_NF) to further reduce the ripple introduced by the first stage of the AZCFB loop. Better elimination of the offset voltage can reduce the transistor size and power consumption of the auto-zero circuit.

[0035] Figure 4 This is the structural diagram of the high-pass filter proposed by the present invention, including a buffer with its input terminal connected to the common-mode signal VCM, capacitors C1, C2, and resistors R1, R2. The resistors R1, R2 of the high-pass filter need to be large enough, as shown in the following formula:

[0036]

[0037] When the chopping frequency is 200 kHz and the capacitance is 2 pF, the capacitance impedance is close to 398 kΩ. Therefore, a resistor much larger than the capacitor impedance is required. In addition, to ensure the stability of the input operating points of Gm5a and Gm5b, it is necessary to provide a stable common-mode voltage on the resistor side. As Figure 4 shown, a buffer is used to provide a stable DC voltage for the high-pass filter, ensuring that the input DC operating points of Gm5a and Gm5b remain stable near VCM.

[0038] The above embodiments are only used to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the present invention.

Claims

1. A ping-pong self-stabilizing zero loop ripple suppression precision operational amplifier, characterized in that: It includes a high-frequency path and a low-frequency path, the high-frequency path includes a third transconductance amplifier Gm3 and a fourth transconductance amplifier Gm4; the low-frequency path includes first to third transconductance amplifiers Gm1-Gm3, first to second choppers Chop1-Chop2 and a ping-pong self-stabilizing zero ripple suppression loop, and the ping-pong self-stabilizing zero ripple suppression loop is used to suppress the offset voltage and output ripple generated by the low-frequency path; The positive phase input signal of the operational amplifier is connected to the positive phase input terminal of the fourth transconductance amplifier Gm4, and the negative phase input signal is connected to the negative phase input terminal of the fourth transconductance amplifier Gm4; the positive phase output terminal of the fourth transconductance amplifier Gm4 is connected to the positive phase input terminal of the third transconductance amplifier Gm3, and the negative phase output terminal is connected to the negative phase input terminal of the third transconductance amplifier Gm3; the positive phase input signal of the operational amplifier is connected to the positive phase input terminal of the first transconductance amplifier Gm1 through the first chopper Chop1, and the negative phase input signal is connected to the negative phase input terminal of the first transconductance amplifier Gm1 through the first chopper Chop1. The inverting output terminal of the first transconductance amplifier Gm1 is connected to the non-inverting input terminal of the second transconductance amplifier Gm2 via the second chopper Chop2, and the non-inverting output terminal of the first transconductance amplifier Gm1 is connected to the inverting input terminal of the second transconductance amplifier Gm2 via the second chopper Chop2; the inverting output terminal of the second transconductance amplifier Gm2 is connected to the non-inverting input terminal of the third transconductance amplifier Gm3, and the non-inverting output terminal of the second transconductance amplifier Gm2 is connected to the inverting input terminal of the third transconductance amplifier Gm3; the output of the third transconductance amplifier Gm3 is used as the output of the operational amplifier; The ping-pong self-stabilizing zero ripple suppression loop includes first to second self-zeroing amplifiers Gmaz1-Gmaz2, a fifth a transconductance amplifier Gm5a, a fifth b transconductance amplifier Gm5b, sixth to seventh transconductance amplifiers Gm6-Gm7, a third chopper Chop3, a filter SC_NF, a high-pass filter HPF, first to second switch units AZ1-AZ2, first to second zeroing capacitors C1a-C2a, third to fourth zeroing capacitors C1b-C2b and fifth to sixth integrating capacitors Cint1-Cint2; The positive phase input terminal of the high pass filter HPF is connected to the negative phase input terminal of the second transconductance amplifier Gm2, and the negative phase input terminal is connected to the positive phase input terminal of the second transconductance amplifier Gm2; the positive phase and negative phase output terminals of the high pass filter HPF are connected to the input terminal of the fifth a transconductance amplifier Gm5a through the first switch unit AZ1, and the positive phase and negative phase output terminals of the high pass filter HPF are connected to the input terminal of the fifth b transconductance amplifier Gm5b through the first switch unit AZ1; the positive phase and negative phase output terminals of the fifth a transconductance amplifier Gm5a are connected to the input terminal of the third chopper Chop3 through the second switch unit AZ2, and the positive phase and negative phase output terminals of the fifth b transconductance amplifier Gm5b are connected to the input terminal of the third chopper Chop3 through the second switch unit AZ2. 3, the output end of the third chopper Chop3 is connected to the positive phase and negative phase input ends of the sixth transconductance amplifier Gm6; the positive phase output end of the sixth transconductance amplifier Gm6 is connected to the positive phase input end of the seventh transconductance amplifier Gm7 via the filter SC_NF, and the negative phase output end of the sixth transconductance amplifier Gm6 is connected to the negative phase input end of the seventh transconductance amplifier Gm7 via the filter SC_NF; a fifth integrating capacitor Cint1 is connected between the negative phase input end and the positive phase output end of the sixth transconductance amplifier Gm6, and a sixth integrating capacitor Cint2 is connected between the positive phase input end and the negative phase output end of the sixth transconductance amplifier Gm6; the positive phase and negative phase outputs of the seventh transconductance amplifier Gm7 are fed back to the first transconductance amplifier Gm1; The inverting input terminal of the first self-zeroing amplifier Gmaz1 is grounded via the first zeroing capacitor C1a, the non-inverting input terminal of the first self-zeroing amplifier Gmaz1 is grounded via the second zeroing capacitor C2a, and the non-inverting output and the non-inverting output of the first self-zeroing amplifier Gmaz1 are fed back to the fifth a transconductance amplifier Gm5a; the inverting output terminal of the fifth a transconductance amplifier Gm5a is connected to the inverting input terminal of the first self-zeroing amplifier Gmaz1 via the second switch unit AZ2, and the non-inverting output terminal of the fifth a transconductance amplifier Gm5a is connected to the non-inverting input terminal of the first self-zeroing amplifier Gmaz1 via the second switch unit AZ2; The positive phase input terminal of the second self-zeroing amplifier Gmaz2 is grounded via the fourth zeroing capacitor C2b, the negative phase input terminal of the second self-zeroing amplifier Gmaz1 is grounded via the third zeroing capacitor C1b, and the positive phase and negative phase outputs of the first self-zeroing amplifier Gmaz1 are fed back to the fifth b transconductance amplifier Gm5b; the negative phase output terminal of the fifth b transconductance amplifier Gm5b is connected to the positive phase input terminal of the second self-zeroing amplifier Gmaz2 via the second switch unit AZ2, and the positive phase output terminal of the fifth b transconductance amplifier Gm5b is connected to the negative phase input terminal of the second self-zeroing amplifier Gmaz2 via the second switch unit AZ2.

2. The ping-pong self-stabilizing zero loop ripple suppression precision operational amplifier according to claim 1, characterized in that: The first switch unit AZ1 includes first to eighth switches S1-S8, the positive phase output terminal of the high pass filter HPF is connected to the inverting input terminal of the first switch unit AZ1, and the inverting output terminal is connected to the positive phase input terminal of the first switch unit AZ1; the positive phase output terminal of the high pass filter HPF is connected to the inverting input terminal of the fifth a transconductance amplifier Gm5a through the fifth switch S5, and the positive phase output terminal of the high pass filter HPF is connected to the inverting input terminal of the fifth b transconductance amplifier Gm5b through the seventh switch S7; the inverting output terminal of the high pass filter HPF is connected to the positive phase input terminal of the fifth a transconductance amplifier Gm5a through the sixth switch S6, and the inverting output terminal of the high pass filter HPF is connected to the positive phase input terminal of the fifth b transconductance amplifier Gm5b through the eighth switch S8; The external common-mode signal VCM is connected to the non-inverting input terminal of the fifth a-transconductance amplifier Gm5a via the first switch S1, and to the inverting input terminal of the fifth a-transconductance amplifier Gm5a via the second switch S2; the external common-mode signal VCM is connected to the non-inverting input terminal of the fifth b-transconductance amplifier Gm5b via the third switch S3, and to the inverting input terminal of the fifth b-transconductance amplifier Gm5b via the fourth switch S4.

3. The ping-pong self-stabilizing zero loop ripple suppression precision operational amplifier according to claim 2, characterized in that: The second switch unit AZ2 includes ninth to sixteenth switches S9-S16, the inverting output terminal of the fifth a-transconductance amplifier Gm5a is connected to the inverting input terminal of the first self-zeroing amplifier Gmaz1 via the eleventh switch S11, and the positive-phase output terminal of the fifth a-transconductance amplifier Gm5a is connected to the positive-phase input terminal of the first self-zeroing amplifier Gmaz1 via the twelfth switch S12; the inverting output terminal of the fifth a-transconductance amplifier Gm5a is connected to the inverting output terminal of the second switch unit AZ2 via the tenth switch S10, and the positive-phase output terminal of the fifth a-transconductance amplifier Gm5a is connected to the positive-phase output terminal of the second switch unit AZ2 via the ninth switch S9; The positive phase output terminal of the fifth b transconductance amplifier Gm5b is connected to the inverting input terminal of the second self-zeroing amplifier Gmaz2 via the sixteenth switch S16, and the inverting output terminal of the fifth b transconductance amplifier Gm5b is connected to the positive phase input terminal of the second self-zeroing amplifier Gmaz2 via the fifteenth switch S15; the positive phase output terminal of the fifth b transconductance amplifier Gm5b is connected to the positive phase output terminal of the second switch unit AZ2 via the thirteenth switch S13, and the inverting output terminal of the fifth b transconductance amplifier Gm5b is connected to the inverting output terminal of the second switch unit AZ2 via the fourteenth switch S14; When the first, second, seventh, eighth, eleventh, twelfth, thirteenth and fourteenth switches S1, S2, S7, S8, S11, S12, S13 and S14 are closed, the third, fourth, fifth, sixth, ninth, tenth, fifteenth and sixteenth switches S3, S4, S5, S6, S9, S10, S15 and S16 are opened; when the first, second, seventh, eighth, eleventh, twelfth, thirteenth and fourteenth switches S1, S2, S7, S8, S11, S12, S13 and S14 are opened, the third, fourth, fifth, sixth, ninth, tenth, fifteenth and sixteenth switches S3, S4, S5, S6, S9, S10, S15 and S16 are closed.

4. The ping-pong self-stabilizing zero loop ripple suppression precision operational amplifier according to claim 1, characterized in that: The periods of the first switch unit AZ1 and the second switch unit AZ2 are the same, the periods of the first chopper Chop1 , the second chopper Chop2 , the third chopper Chop3 and the filter SC_NF are the same, and the period of the first switch unit AZ1 is 1 / 2 of the period of the first chopper Chop1 .

5. The ping-pong self-stabilizing zero loop ripple suppression precision operational amplifier according to claim 1, characterized in that: The gain of the ping-pong self-stabilizing zero ripple suppression loop is at least 80dB, and the bandwidth is 100KHz or less. The loop uses automatic zeroing technology to eliminate part of the loop's own offset voltage. The residual offset voltage formula is as follows: Among them, V os,res Represents the residual offset voltage, A vAz is the auto-zero loop gain, V os5a,b represents the input offset voltage of the fifth transconductance amplifier Gm5a and the fifth transconductance amplifier Gm5b, G maz1,2 represents the transconductance of the first auto-zero amplifier Gmaz1 and the second auto-zero amplifier Gmaz2, V osaz1,2 represents the input offset voltage of the first auto-zero amplifier Gmaz1 and the second auto-zero amplifier Gmaz2, G m5a,b represents the transconductance of the fifth transconductance amplifier a Gm5a and the fifth transconductance amplifier b Gm5b, Δq 11,12 represents the charge injection mismatch value of the eleventh switch S11 and the twelfth switch S12, C 1a,2a Indicates the values ​​of the first zero adjustment capacitor C1a and the second zero adjustment capacitor C2a.

6. The ping-pong self-zeroing loop ripple suppression precision operational amplifier according to claim 1, characterized in that: The high-pass filter HPF includes seventh to eighth capacitors C1-C2, first to second resistors R1-R2 and a buffer, the positive phase input terminal of the high-pass filter HPF is connected to the output terminal of the buffer via the seventh capacitor C1 and the first resistor R1, and the negative phase input terminal of the high-pass filter HPF is connected to the output terminal of the buffer via the eighth capacitor C2 and the second resistor R2; the positive phase input terminal of the buffer is connected to the external common mode signal VCM, the negative phase input terminal of the buffer is connected to the output terminal, the common terminal of the seventh capacitor C1 and the first resistor R1 is used as the positive phase output terminal of the high-pass filter HPF, and the common terminal of the eighth capacitor C2 and the second resistor R2 is used as the negative phase output terminal of the high-pass filter HPF; The first to second resistors R1-R2 satisfy the following formula: Among them, Vin AZCFB represents the voltage ratio of the high-pass filter HPF output signal to the input signal, f is the chopping frequency, C represents the value of the seventh capacitor C1 and the eighth capacitor C2, and R represents the value of the first resistor R1 and the second resistor R2.

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