Gate driving device

Abstract

Provided is a gate drive device capable of adjusting a constant of a circuit element in accordance with a driven transistor. This gate drive device is provided with: a first transistor and a second transistor which are connected in series between a first node of a first voltage and a second node of a second voltage lower than the first voltage, the connection nodes being output nodes of the gate drive device, and which operate complementarily; a first charge transistor and a first negative bias transistor connected in series between the first node and a third node having a third voltage lower than the first voltage and higher than the second voltage, the connection node being connected to a capacitance node connected to one electrode of a first capacitor provided externally; and a logic circuit that controls each transistor, the first diode having an anode connected to the other electrode of the first capacitor and the second node, and a cathode connected to the third node.

Description

Technical Field

[0001] The present invention relates to a gate drive device for driving a semiconductor switching device. Background Art

[0002] As an existing gate drive device, for example, a gate drive circuit disclosed in Patent Document 1 is cited. In Patent Document 1 Figure 1 discloses a structure in which, in a gate drive circuit that generates positive and negative voltage pulses with the source or emitter of a main switching element as a reference potential, there are a control power source connected to the source or emitter of the main switching element, a capacitor, a charging unit that charges the capacitor through the control power source, and the gate capacitance of the main switching element is charged or discharged using the charge stored in the capacitor.

[0003] In the gate drive circuit of Patent Document 1, during the period when the main switching element is turned on, the capacitor is charged, and when the main switching element is turned off, a negative bias is applied to the gate of the main switching element from the capacitor. Therefore, a high-speed cut-off operation can be performed without using a power source for the negative bias, and the on-off loss is reduced.

[0004] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2009-200891

[0005] In the technology disclosed in Patent Document 1, since the capacitor required for applying the negative bias and the diode that functions as a switching unit constituting the charging unit are built in the gate drive circuit, there is a problem that it is difficult to adjust the constants of the capacitor and the diode in matching with the main switching element. Summary of the Invention

[0006] The present invention has been proposed to solve the above problems, and an object thereof is to provide a gate drive device capable of adjusting the constants of circuit elements in matching with the driven transistor.

[0007] The gate driving device related to the present invention drives the gate of a transistor. The gate driving device has a gate driving circuit, a first capacitor, and a first diode. The gate driving circuit has: a first transistor of a first conductivity type and a second transistor of a second conductivity type, which are connected in series between a first node to which a first voltage is applied and a second node to which a second voltage lower than the first voltage is applied. The connection node is the output node of the gate driving device, and the first transistor and the second transistor operate complementarily; a first charging transistor and a first negative bias transistor, which are connected in series between the first node and a third node to which a third voltage lower than the first voltage and higher than the second voltage is applied. The connection node is connected to a capacitance node connected to one electrode of the first capacitor provided externally; and a logic circuit that controls the first transistor, the second transistor, the first charging transistor, and the first negative bias transistor. The anode of the first diode is connected to the other electrode of the first capacitor and the second node, and the cathode is connected to the third node.

[0008] Effect of the Invention

[0009] According to the gate driving device related to the present invention, it is possible to adjust the constants of circuit elements in matching with the transistor to be driven, and it is possible to adjust the negative bias applied to the transistor. Description of the Drawings

[0010] Figure 1 It is a circuit diagram showing the structure of the gate driving device according to Embodiment 1 related to the present invention.

[0011] Figure 2 It is a diagram showing the control timing of the gate driving device according to Embodiment 1 related to the present invention.

[0012] Figure 3 It is a circuit diagram showing the structure of the gate driving device according to Embodiment 2 related to the present invention.

[0013] Figure 4 It is a diagram showing the control timing of the gate driving device according to Embodiment 2 related to the present invention.

[0014] Figure 5 It is a circuit diagram showing the structure of the gate driving device according to Embodiment 3 related to the present invention.

[0015] Figure 6 It is a diagram showing the control timing of the gate driving device according to Embodiment 3 related to the present invention.

[0016] Figure 7 It is a circuit diagram showing the structure of the gate driving device according to Embodiment 4 related to the present invention.

[0017] Figure 8 It is a diagram showing the control timing of the gate driving device according to Embodiment 4 of the present invention.

[0018] Figure 9 It is a circuit diagram showing the structure of the gate driving device according to Embodiment 5 of the present invention.

[0019] Figure 10 It is a diagram showing the control timing of the gate driving device according to Embodiment 5 of the present invention.

[0020] Figure 11 It is a circuit diagram showing the structure of the gate driving device according to Embodiment 6 of the present invention.

[0021] Figure 12 It is a diagram showing the control timing of the gate driving device according to Embodiment 6 of the present invention.

[0022] Figure 13 It is a circuit diagram showing the structure of the gate driving device according to Embodiment 7 of the present invention.

[0023] Figure 14 It is a diagram showing the control timing of the gate driving device according to Embodiment 7 of the present invention.

[0024] Figure 15 It is a circuit diagram showing the structure of Modification 1 of Embodiment 7 of the present invention.

[0025] Figure 16 It is a circuit diagram showing the structure of Modification 1 of Embodiment 7 of the present invention.

[0026] Figure 17 It is a circuit diagram showing the structure of Modification 1 of Embodiment 7 of the present invention.

[0027] Figure 18 It is a circuit diagram showing the structure of Modification 2 of Embodiment 7 of the present invention.

[0028] Figure 19 It is a diagram showing the control timing of Modification 2 of Embodiment 7 of the present invention. Detailed Embodiments

[0029] <Embodiment 1>

[0030] Figure 1 It is a circuit diagram showing the structure of the gate driving device 100 according to Embodiment 1 of the present invention. As Figure 1As shown, the gate drive device 100 drives a power device, namely, a high-voltage MOS transistor T1 of the N-channel type (hereinafter referred to as "N-type"). The gate drive device 100 includes a gate drive IC 101 configured as an integrated circuit (IC), a diode D1 and a capacitor C1 provided outside the gate drive IC 101 for adjusting the turn-off speed of the power device.

[0031] The gate drive IC 101 has a VCC terminal (first node) for supplying a VCC voltage (first voltage) from a DC power supply PW, an OUT terminal (output node) for supplying an output signal to the MOS transistor T1, a VEE terminal (second terminal) supplied with a VEE voltage (second voltage), a CP terminal (capacitor node) connected to the capacitor C1, a GND terminal (third node) at a GND voltage (third voltage), and an IN terminal supplied with an input signal.

[0032] The gate drive IC 101 includes a gate logic circuit GL, a P-channel type (hereinafter referred to as "P-type") main source MOS transistor P1 (main source PMOS) connected in series between the VCC terminal and the VEE terminal (second node), and an N-type main sink MOS transistor N1 (main sink NMOS).

[0033] In addition, a P-type charging MOS transistor P2 (charging PMOS) and an N-type negative bias MOS transistor NB (negative bias NMOS) are connected in series between an internal terminal OP supplied with the VCC voltage and the GND terminal.

[0034] Logic signals are input from the gate logic circuit GL to the gates of the MOS transistor P1, the MOS transistor N1, the MOS transistor P2, and the MOS transistor NB, respectively.

[0035] The source of the MOS transistor P1 is connected to the VCC terminal, its drain and the drain of the MOS transistor N1 are connected to the OUT terminal, and the source of the MOS transistor N1 is connected to the VEE terminal.

[0036] The drain of the MOS transistor P2 and the drain of the MOS transistor NB are connected to the CP terminal, and the source of the MOS transistor NB is connected to the GND terminal.

[0037] The cathode of the diode D1 is connected to the GND terminal, its anode is connected to one electrode of the capacitor C1 and to the VEE terminal, and the other electrode of the capacitor C1 is connected to the CP terminal.

[0038] By inputting a high-potential signal (H signal) to the IN terminal, the gate logic circuit GL performs first output switching control, inputting a low-potential signal (L signal) to the gates of MOS transistor P1 and MOS transistor N1, turning on MOS transistor P1 and turning off MOS transistor N1, and switching the output from the OUT terminal from the low-potential signal (L signal) to the H signal.

[0039] Meanwhile, the gate logic circuit GL performs charging control, that is, also inputting the L signal to the gates of MOS transistor P2 and MOS transistor NB, turning on MOS transistor P2 and turning off MOS transistor NB, and charging the capacitor C1 connected to the CP terminal.

[0040] By inputting the L signal to the IN terminal, the gate logic circuit GL performs second output switching control, that is, inputting the H signal to the gates of MOS transistor P1 and MOS transistor N1, turning off MOS transistor P1 and turning on MOS transistor N1, and switching the output from the OUT terminal from the H signal to the L signal.

[0041] Meanwhile, the gate logic circuit GL performs negative bias application control, that is, also inputting the H signal to the gates of MOS transistor P2 and MOS transistor NB, turning off MOS transistor P2 and turning on MOS transistor NB, and applying a negative bias to the OUT terminal via the VEE terminal.

[0042] Figure 2 It is a diagram showing the control timing of the gate driver IC 101. As Figure 2 shown, if an H signal is input to the input terminal, that is, the IN terminal, in order to turn on MOS transistor T1, MOS transistor P1 (main-source type PMOS) turns on, MOS transistor N1 (main-drain type NMOS) turns off, and the voltage of the OUT terminal rises to the VCC voltage (high potential). While the voltage of the OUT terminal is rising, MOS transistor P2 (charging PMOS) turns on, and MOS transistor NB (negative bias NMOS) turns off. At this time, if the forward voltage of diode D1 is set to VF, the voltage VC of the capacitor C1 connected to the CP terminal is charged to VCC - VF (V).

[0043] On the other hand, if an L signal is input to the IN terminal in order to turn off MOS transistor T1, MOS transistor P1 turns off, MOS transistor N1 turns on, and the voltage of the OUT terminal is at a low potential. While the voltage of the OUT terminal is decreasing, MOS transistor P2 turns off, and MOS transistor NB turns on.

[0044] At this time, the voltage of the VEE terminal becomes -VC (-VCC + VF(V)) due to the discharge of the capacitor C1, and a negative bias is applied to the gate of the MOS transistor T1. The charge discharged through the capacitor C1 is charged during the next period when the voltage of the OUT terminal is at a high level.

[0045] In this way, in the gate driving device 100, by applying a negative bias to the gate of the MOS transistor T1 when the MOS transistor T1 is turned off, the charge accumulated in the gate capacitance of the MOS transistor T1 can be discharged at high speed, and the cut-off operation can be speeded up. And since the diode D1 and the capacitor C1 for adjusting the cut-off speed of the MOS transistor T1 are provided outside the gate driving IC 101, the constants of the diode D1 and the capacitor C1 can be flexibly adjusted according to the specifications of the MOS transistor T1.

[0046] In addition, in the first embodiment, a high-voltage MOS transistor is exemplified as the power device, but an IGBT (Insulated Gate Bipolar Transistor) or a SiC-MOS composed of a silicon carbide (SiC) semiconductor can be used as the power device. Also, the signal logics of the IN terminal and the OUT terminal can be reversed.

[0047] <Embodiment 2>

[0048] Figure 3 It is a circuit diagram showing the structure of the gate driving device 200 according to the second embodiment of the present invention. As Figure 3 shown, the gate driving device 200 drives a power device, that is, an n-channel high-voltage MOS transistor T1. The gate driving device 200 has a gate driving IC 201, a diode D1 and a capacitor C1 provided outside the gate driving IC 201 for adjusting the cut-off speed of the power device.

[0049] In addition, in addition to Figure 1 the structure of the gate driving IC 101 shown, the gate driving IC 201 further has: voltage dividing resistors R1 and R2 which are connected in series between the internal terminal OP and GND; and a comparator CP1 whose non-inverting input (V+) is connected to the OUT terminal, and whose inverting input (V-) is connected to the midpoint of the voltage dividing resistors R1 and R2 to input the midpoint potential Vt1, and outputs an output voltage to the gate logic circuit GL. In addition, in Figure 3 the same structures as those of the gate driving IC 101 are denoted by the same reference numerals, and the repeated description is omitted.

[0050] By inputting an H signal to the IN terminal, the gate logic circuit GL performs first output switching control to switch the output from the OUT terminal from an L signal to an H signal. As a result, the voltage at the OUT terminal rises and reaches the threshold voltage, i.e., the midpoint potential Vt1 (V) of the voltage-dividing resistors R1 and R2. The output voltage of the comparator CP1 becomes high. At the same time, charge control is performed, i.e., the MOS transistor P2 is turned on and the MOS transistor NB is turned off to charge the capacitor C1 connected to the CP terminal.

[0051] In addition, by inputting an L signal to the IN terminal, the gate logic circuit GL performs second output switching control to switch the output from the OUT terminal from an H signal to an L signal. The voltage at the OUT terminal drops and reaches the midpoint potential Vt1 (V). The output voltage of the comparator CP1 becomes low. At the same time, negative bias application control is performed, i.e., the MOS transistor P2 is turned off and the MOS transistor NB is turned on to apply a negative bias to the OUT terminal via the VEE terminal.

[0052] Figure 4 It is a diagram showing the control timing of the gate driver IC 201. As Figure 4 shown, if an H signal is input to the IN terminal to turn on the MOS transistor T1, the MOS transistor P1 (main-source type PMOS) is turned on and the MOS transistor N1 (main-drain type NMOS) is turned off. The voltage at the OUT terminal rises to the VCC voltage (high potential). Simultaneously with the voltage at the OUT terminal rising and reaching the midpoint potential Vt1 (V) of the voltage-dividing resistors R1 and R2 detected by the comparator CP1, the MOS transistor P2 (charging PMOS) is turned on and the MOS transistor NB (negative-bias NMOS) is turned off. At this time, the voltage VC of the capacitor C1 connected to the CP terminal is charged to VCC - VF (V).

[0053] On the other hand, if an L signal is input to the IN terminal to turn off the MOS transistor T1, the MOS transistor P1 is turned off and the MOS transistor N1 is turned on. The voltage at the OUT terminal drops. Simultaneously with the voltage at the OUT terminal reaching the midpoint potential Vt1 (V) detected by the comparator CP1, the MOS transistor P2 is turned off and the MOS transistor NB is turned on.

[0054] At this time, the voltage of the VEE terminal becomes -VC (-VCC + VF (V)) through the discharge of the capacitor C1, and a negative bias is applied to the gate of the MOS transistor T1. The charge discharged by the capacitor C1 is charged during the next period when the voltage at the OUT terminal is high.

[0055] Thus, in the gate driving device 200, when disconnecting the MOS transistor T1, a negative bias is applied to the gate of the MOS transistor T1. At this time, however, the voltage of the OUT terminal is monitored by the comparator CP1, and the negative bias is applied to the gate of the MOS transistor T1 after reaching the midpoint potential Vt1(V) of the voltage dividing resistors. Therefore, compared with the case where the negative bias is applied rapidly from the state where the voltage of the OUT terminal is at a high potential, the charge of the capacitor C1 is less likely to be consumed, and the variation of the negative bias level is suppressed.

[0056] In addition, when turning on the MOS transistor T1, the voltage of the OUT terminal is also monitored by the comparator CP1, and the capacitor C1 is charged after reaching the midpoint potential Vt1(V) of the voltage dividing resistors. Therefore, compared with the case where the capacitor C1 is charged from the state where the voltage of the OUT terminal is at a low potential, the situation where current flows backward to the gate of the MOS transistor T1 is suppressed, and the unstable operation of the MOS transistor T1 can be prevented.

[0057] <Embodiment 3>

[0058] Figure 5 It is a circuit diagram showing the structure of a gate driving device 300 according to Embodiment 3 of the present invention. As Figure 5 shown, the gate driving device 300 drives a power device, i.e., an N-type high-voltage MOS transistor T1. The gate driving device 300 includes a gate driving IC 301, a diode D1 and a capacitor C1 which are provided outside the gate driving IC 301 and are used to adjust the cut-off speed of the power device.

[0059] In addition, the gate driving IC 201 further includes, in addition to the structure of the gate driving IC 201 shown Figure 3 : voltage dividing resistors R3 and R4 which are connected in series between an internal terminal OP and GND; and a comparator CP2 whose non-inverting input (V+) is connected to the CP terminal, and whose inverting input (V-) is connected to the midpoint of the voltage dividing resistors R3 and R4 to input the midpoint potential Vt2, and outputs an output voltage to the gate logic circuit GL. In addition, in Figure 5 those, the same reference numerals are given to the same structures as those of the gate driving IC 201, and the repeated description is omitted.

[0060] By inputting an H signal to the IN terminal, the gate logic circuit GL performs first output switching control to switch the output from the OUT terminal from an L signal to an H signal. As a result, the voltage of the OUT terminal rises and reaches the midpoint potential Vt1 (V) of the voltage dividing resistors R1 and R2. The output voltage of the comparator CP1 becomes high. At the same time, charging control is performed, that is, the MOS transistor P2 is turned on, the MOS transistor NB is turned off, and the capacitor C1 connected to the CP terminal is charged. However, as the capacitor C1 is charged, the voltage of the CP terminal rises and reaches the threshold voltage, that is, the midpoint potential Vt2 (V) of the voltage dividing resistors R3 and R4. At the same time, the charging control is stopped.

[0061] Figure 6 It is a diagram showing the control timing of the gate driver IC 301. As Figure 6 shown, if an H signal is input to the IN terminal to turn on the MOS transistor T1, the MOS transistor P1 (main-source type PMOS) is turned on and the MOS transistor N1 (main-drain type NMOS) is turned off, and the voltage of the OUT terminal rises to the VCC voltage (high potential). Simultaneously with the voltage of the OUT terminal rising detected by the comparator CP1 and reaching the midpoint potential Vt1 (V) of the voltage dividing resistors R1 and R2, the MOS transistor P2 (charging PMOS) is turned on and the MOS transistor NB (negative bias NMOS) is turned off. At this time, charging is performed until the comparator CP2 detects that the voltage VC of the capacitor C1 connected to the CP terminal reaches the midpoint potential Vt2 (V) of the voltage dividing resistors R3 and R4. If it is detected that the comparator CP2 reaches the midpoint potential Vt2 (V), the comparator CP2 sets the output voltage to a low potential. If the output voltage of the comparator CP2 becomes low, the gate logic circuit GL sets the gate voltage of the MOS transistor P2 to high to turn off the MOS transistor P2 and stop the charging control of the capacitor C1. As a result, the voltage VC of the capacitor C1 connected to the CP terminal becomes Vt2 - VF (V).

[0062] On the other hand, if an L signal is input to the IN terminal to turn off the MOS transistor T1, the MOS transistor P1 is turned off and the MOS transistor N1 is turned on, and the voltage of the OUT terminal drops. Simultaneously with the comparator CP1 detecting that the voltage of the OUT terminal reaches the midpoint potential Vt1 (V), the MOS transistor NB is turned on. The MOS transistor P2 is turned off when the CP terminal is charged to the desired voltage.

[0063] At this time, the voltage of the VEE terminal becomes -VC (-Vt2 + VF (V)) through the discharge of the capacitor C1, and a negative bias is applied to the gate of the MOS transistor T1. The charge discharged by the capacitor C1 is charged during the next period when the voltage of the OUT terminal is high.

[0064] As described above, in the gate drive device 300, when the MOS transistor T1 is turned off, a negative bias is applied to the gate of the MOS transistor T1. At this time, however, the voltage VC of the capacitor C1 connected to the CP terminal is monitored by the comparator CP2, and the capacitor C1 is charged until the comparator CP2 detects that the voltage has reached the midpoint potential Vt2 (V) of the voltage dividing resistors R3 and R4. If the output voltage of the comparator CP2 becomes low, the gate logic circuit GL stops the charging control of the capacitor C1 by turning off the MOS transistor P2. Therefore, the charging amount of the capacitor C1 can be adjusted, and the application level of the negative bias can be set to -VC (-Vt2 + VF (V)). Therefore, compared with the case where the voltage of the VEE terminal becomes -VC (-VCC + VF (V)) determined by the VCC voltage of the DC power supply PW, the application level of the negative bias can be adjusted freely.

[0065] <Embodiment 4>

[0066] Figure 7 is a circuit diagram showing the structure of a gate drive device 400 according to Embodiment 4 of the present invention. As Figure 7 shown, the gate drive device 400 drives a power device, that is, an N-type high-voltage MOS transistor T1. The gate drive device 400 includes a gate drive IC 401, a diode D1 and a capacitor C1 that are provided outside the gate drive IC 401 and are used to adjust the turn-off speed of the power device.

[0067] In addition, the gate drive IC 201 further includes, in addition to the Figure 3 structure of the gate drive IC 201 shown: an N-type MOS transistor NL for negative level adjustment, whose drain is connected to the internal terminal OP; voltage dividing resistors R5 and R6 that are connected in series between the source of the MOS transistor NL and GND; and an amplifier AP, whose non-inverting input (V+) is connected to the output of the gate logic circuit GL, and whose inverting input (V-) is connected to the midpoint of the voltage dividing resistors R5 and R6, and the output voltage is input to the gate of the MOS transistor NL.

[0068] In addition, the Figure 3 P-type charging MOS transistor P2 (charging PMOS) of the gate drive IC 201 shown is replaced with an N-type charging MOS transistor N2 (charging NMOS). And it has a delay circuit DL that delays the signal of the gate logic circuit GL and outputs it to the gate of the MOS transistor N2 as a signal of the source potential (VDD) of the MOS transistor NL.

[0069] The delay circuit DL has inverters IV1 and IV2 connected in series. The signal of the gate logic circuit GL is input to the inverter IV1, and the output of the inverter IV2 is output to the gate of the MOS transistor N2. The inverter IV2 has an inverter circuit (not shown) that operates between the potential (VDD) of the source of the MOS transistor NL and GND. In addition, in Figure 7 structures identical to those of the gate driver IC 201 are denoted by the same reference numerals, and repeated descriptions are omitted.

[0070] By inputting an H signal to the IN terminal, the gate logic circuit GL performs first output switching control to switch the output from the OUT terminal from an L signal to an H signal. As a result, the voltage of the OUT terminal rises to reach the midpoint potential Vt1 (V) of the voltage dividing resistors R1 and R2, and the output voltage of the comparator CP1 becomes high. At the same time, charge control is performed, that is, the MOS transistor N2 is turned on, the MOS transistor NB is turned off, and the capacitor C1 connected to the CP terminal is charged. However, as the capacitor C1 is charged and the voltage of the CP terminal rises, the gate voltage of the MOS transistor N2 reaches VDD, and at the same time, the charge control stops.

[0071] Figure 8 is a diagram showing the control timing of the gate driver IC 401. As Figure 8 shown, if an H signal is input to the IN terminal to turn on the MOS transistor T1, the MOS transistor P1 (main-source type PMOS) is turned on, the MOS transistor N1 (main-drain type NMOS) is turned off, and the voltage of the OUT terminal rises to the VCC voltage (high potential). Simultaneously with the voltage of the OUT terminal rising to reach the midpoint potential Vt1 (V) of the voltage dividing resistors R1 and R2 as detected by the comparator CP1, the MOS transistor N2 (charge NMOS) is turned on, and the MOS transistor NB (negative bias NMOS) is turned off. At this time, the capacitor C1 connected to the CP terminal is charged until the gate voltage of the MOS transistor N2 reaches VDD. At this time, the voltage VC of the capacitor C1 connected to the CP terminal is charged to VDD - VF (V).

[0072] On the other hand, if an L signal is input to the IN terminal to turn off the MOS transistor T1, the MOS transistor P1 is turned off, the MOS transistor N1 is turned on, the voltage of the OUT terminal drops, and simultaneously with the voltage of the OUT terminal reaching the midpoint potential Vt1 (V) of the voltage dividing resistors R1 and R2 as detected by the comparator CP1, the MOS transistor N2 is turned off, and the MOS transistor NB is turned on.

[0073] At this time, the voltage of the VEE terminal becomes -VC (-VDD + VF(V)) due to the discharge of the capacitor C1, and a negative bias is applied to the gate of the MOS transistor T1. The charge discharged through the capacitor C1 is charged during the next period when the voltage of the OUT terminal is at a high potential.

[0074] As described above, in the gate driving device 400, when the MOS transistor T1 is turned on, the capacitor C1 connected to the CP terminal is charged until the gate voltage of the MOS transistor N2 reaches VDD. Here, the voltage VDD is obtained by the product of the current flowing through the constant current circuit composed of the amplifier AP and the N-type negative level adjustment MOS transistor NL and the voltage dividing resistors R5 and R6. By inputting the midpoint potential Vt3(V) of the voltage dividing resistors R5 and R6 to the inverting input (V-) of the amplifier AP, the voltage VDD can be adjusted by the voltage dividing resistance value formed by the voltage dividing resistors R5 and R6. Therefore, by supplying the voltage VDD lower than the VCC voltage as the gate voltage of the MOS transistor N2 for charging the capacitor C1, the capacitor C1 is only charged to the gate voltage VDD, and overcharging can be prevented.

[0075] In addition, the gate driving IC 401 has a delay circuit DL that delays the signal of the gate logic circuit GL, but it is a circuit for matching the supply timing of the gate voltage of the MOS transistor N2 with the delay generated until the voltage VDD is obtained through the constant current circuit composed of the amplifier AP and the MOS transistor NL.

[0076] <Embodiment 5>

[0077] Figure 9 It is a circuit diagram showing the structure of a gate driving device 500 according to Embodiment 5 of the present invention. As Figure 9 shown, the gate driving device 500 drives a power device, that is, an n-channel high-voltage MOS transistor T1. The gate driving device 500 has a gate driving IC 501 and a capacitor C1 provided outside the gate driving IC 501 for adjusting the cut-off speed of the power device.

[0078] In addition, the gate driving IC 501 further has, in addition to Figure 7 the structure of the gate driving IC 401 shown: a P-type driving MOS transistor DP (driving PMOS) whose source is connected to an internal terminal OP; and an N-type diode replacement MOS transistor DN whose gate is connected to the drain of the MOS transistor DP, the drain is connected to GND, and the source is connected to the VEE terminal. In addition, a resistor R7 is connected between the drain of the MOS transistor DP and the source of the MOS transistor DN. In addition, in Figure 9In the figure, the same reference numerals are assigned to the same structures as those of the gate driver IC 401, and repeated descriptions are omitted.

[0079] By inputting an H signal to the IN terminal, the gate logic circuit GL performs a first output switching control to switch the output from the OUT terminal from an L signal to an H signal. As a result, the voltage of the OUT terminal rises and reaches the midpoint potential Vt1 (V) of the voltage dividing resistors R1 and R2. The output voltage of the comparator CP1 becomes high. At the same time, a charging control is performed, that is, the MOS transistor N2 is turned on, the MOS transistor NB is turned off, and the capacitor C1 connected to the CP terminal is charged. At the same time, the MOS transistor DP is turned on, and the MOS transistor DN is turned on.

[0080] Figure 10 It is a diagram showing the control timing of the gate driver IC 501. As Figure 10 shown, if an H signal is input to the IN terminal to turn on the MOS transistor T1, the MOS transistor P1 (main-source type PMOS) is turned on, the MOS transistor N1 (main-drain type NMOS) is turned off, and the voltage of the OUT terminal rises to the VCC voltage (high potential). Simultaneously with the voltage of the OUT terminal rising detected by the comparator CP1 and reaching the midpoint potential Vt1 (V) of the voltage dividing resistors R1 and R2, the MOS transistor N2 (charging NMOS) is turned on, and the MOS transistor NB (negative bias NMOS) is turned off. At this timing, the MOS transistor DP (driving PMOS) is turned on, so that an H signal is input to the gate of the MOS transistor DN, and the MOS transistor DN is turned on. At this time, the capacitor C1 connected to the CP terminal is charged until the gate voltage of the MOS transistor N2 reaches VDD, and the voltage VC of the capacitor C1 becomes VDD (V).

[0081] On the other hand, if an L signal is input to the IN terminal to turn off the MOS transistor T1, the MOS transistor P1 is turned off, the MOS transistor N1 is turned on, the voltage of the OUT terminal drops, and simultaneously with the voltage of the OUT terminal reaching the midpoint potential Vt1 (V) of the voltage dividing resistors R1 and R2 detected by the comparator CP1, the MOS transistor N2 is turned off, and the MOS transistor NB is turned on. At this timing, the MOS transistor DP is turned off, and the MOS transistor DN is also turned off.

[0082] At this time, the voltage of the VEE terminal becomes -VC (-VDD (V)) through the discharge of the capacitor C1, and a negative bias is applied to the gate of the MOS transistor T1. The charge discharged through the capacitor C1 is charged during the next period when the voltage of the OUT terminal is high.

[0083] As described above, in the gate driving device 500, only the capacitor C1 for adjusting the turn-off speed of the power device is provided outside the gate driving IC 501, and the diode D1 provided in the gate driving devices 100 to 400 of the first to fourth embodiments is not provided. Instead of the diode, a MOS transistor DN is built in the gate driving IC 501.

[0084] Therefore, in the gate driving devices 100 to 400, the amount of the forward voltage VF of the diode D1 is subtracted from the negative bias applied voltage, but in the gate driving device 500, the amount of the forward voltage VF is not subtracted. The voltage charged in the capacitor C1 can be directly applied as a negative bias to the gate of the MOS transistor T1, and the turn-off operation of the MOS transistor T1 can be further speeded up. In addition, by incorporating the diode function into the gate driving IC 501, the gate driving device 500 can be miniaturized and low cost can be achieved.

[0085] <Embodiment 6>

[0086] Figure 11 FIG. is a circuit diagram showing the structure of a gate driving device 600 according to Embodiment 6 of the present invention. As Figure 11 shown, the gate driving device 600 drives a power device, that is, an n-channel high-voltage MOS transistor T1. The gate driving device 600 includes a gate driving IC 601 and a capacitor C1 provided outside the gate driving IC 601 for adjusting the turn-off speed of the power device.

[0087] In addition, the gate driving IC 601 further includes, in addition to the structure of the gate driving IC 501 shown Figure 9 : an N-type rapid charging MOS transistor RCN (rapid charging NMOS) whose drain is connected to an internal terminal OP and whose source is connected to a CP terminal; and a delay circuit DL1 that delays the signal of the gate logic circuit GL and outputs, as a signal of the source potential (VDD) of the negative level adjustment MOS transistor NL, to the gate of the MOS transistor RCN.

[0088] The delay circuit DL1 includes inverters IV3 and IV4 connected in series. The signal of the gate logic circuit GL is input to the inverter IV3, and the output of the inverter IV4 is output to the gate of the MOS transistor RCN. The inverter IV4 has an inverter circuit (not shown) that operates between the potential (VDD) of the source of the MOS transistor NL and GND. In addition, in Figure 11 , the same reference numerals are given to the same structures as those of the gate driving IC 501, and redundant descriptions are omitted.

[0089] Figure 12This is a diagram showing the control timing of the gate driver IC 601. Figure 12 The timing from the start of the VCC power supply of the gate driver IC 601, i.e., the DC power supply PW, is shown. When the DC power supply PW starts, before the VCC voltage reaches the voltage Vpor, the MOS transistor RCN (rapid charge NMOS) is turned on, and the capacitor C1 is rapidly charged. Here, the voltage Vpor is the threshold voltage of an unillustrated power-on reset circuit that monitors the power supply voltage VCC built in the gate driver IC 601.

[0090] After that, if an H signal is input to the IN terminal to turn on the MOS transistor T1, the MOS transistor P1 (main source type PMOS) is turned on, the MOS transistor N1 (main drain type NMOS) is turned off, and the voltage of the OUT terminal rises to the VCC voltage (high potential). Simultaneously with the detection by the comparator CP1 that the voltage of the OUT terminal has risen to the midpoint potential Vt1 (V) of the voltage dividing resistors R1 and R2, charge control is performed, that is, the MOS transistor N2 (charge NMOS) is turned on, the MOS transistor NB (negative bias NMOS) is turned off, and the capacitor C1 connected to the CP terminal is charged. At the same time, the MOS transistor DP is turned on, and the MOS transistor DN is turned on. At this time, the capacitor C1 connected to the CP terminal is charged until the gate voltage of the MOS transistor N2 reaches VDD, and the voltage VC of the capacitor C1 becomes VDD (V).

[0091] On the other hand, if an L signal is input to the IN terminal to turn off the MOS transistor T1, the MOS transistor P1 is turned off, the MOS transistor N1 is turned on, the voltage of the OUT terminal drops, and simultaneously with the detection by the comparator CP1 that the voltage of the OUT terminal has reached the midpoint potential Vt1 (V) of the voltage dividing resistors R1 and R2, the MOS transistor N2 is turned off, and the MOS transistor NB is turned on. At this timing, the MOS transistor DP is turned off, and the MOS transistor DN is also turned off.

[0092] At this time, the voltage of the VEE terminal becomes -VC (-VDD (V)) through the discharge of the capacitor C1, and a negative bias is applied to the gate of the MOS transistor T1. The charge discharged through the capacitor C1 is charged during the next period when the voltage of the OUT terminal is at a high potential.

[0093] As described above, in the gate driver device 600, a MOS transistor RCN (rapid charge NMOS) for the initial charge of the capacitor C1, which is not provided in the gate driver devices 100 to 500 of the first to fifth embodiments, is added. Therefore, by rapidly charging the capacitor C1 when the DC power supply PW of the gate driver IC 601 starts, the on / off of the MOS transistor T1 can be started in a state where the capacitor C1 is charged to a specified voltage.

[0094] In addition, the gate driving IC 601 has a delay circuit DL1 that delays the signal of the gate logic circuit GL, but it is a circuit for matching the supply timing of the gate voltage of the MOS transistor RCN with the delay generated until the voltage VDD is obtained through the constant current circuit composed of the amplifier AP and the MOS transistor NL.

[0095] <Embodiment 7>

[0096] Figure 13 It is a circuit diagram showing the structure of the gate driving device 700 according to Embodiment 7 of the present invention. As Figure 13 shown, the gate driving device 700 drives the power device, that is, an N-type high-voltage MOS transistor T1. The gate driving device 700 has a gate driving IC 701 and a capacitor C1 provided outside the gate driving IC 701 for adjusting the cut-off speed of the power device.

[0097] In addition, the gate driving IC 701, in addition to Figure 9 the structure of the gate driving IC 501 shown, further has an N-type charging MOS transistor N3 (charging NMOS2) and a negative bias MOS transistor NB2 (negative bias NMOS2) connected in series between the internal terminal OP and GND. The drain of the MOS transistor N3 is connected to the internal terminal OP, and the source is connected to the drain of the MOS transistor NB2. The source of the MOS transistor NB2 is connected to GND, and a diode D2 and a diode D3 are connected in series between the source and the VEE terminal.

[0098] The cathode of the diode D2 is connected to the source of the MOS transistor NB2, the anode of the diode D2 is connected to the cathode of the diode D3, and the anode of the diode D3 is connected to the VEE terminal.

[0099] In addition, a capacitor C2 is provided between the source of the MOS transistor N3 and the anode of the diode D2.

[0100] In addition, it has an inverter IV6 whose output is connected to the gate of the MOS transistor N3, an AND circuit AG whose output is connected to the input of the inverter IV6, and an oscillation circuit OS connected to one input of the AND circuit AG. The output of the inverter IV1 is connected to the other input of the AND circuit AG, the output of the AND circuit AG is connected to the input of the inverter IV6, and is also connected to the gate of the MOS transistor NB2. In addition, in Figure 13 this, the same reference numerals are given to the same structures as those of the gate driving IC 501, and the repeated description is omitted.

[0101] By inputting an H signal to the IN terminal, the gate logic circuit GL performs first output switching control to switch the output from the OUT terminal from an L signal to an H signal. As a result, the voltage of the OUT terminal rises and reaches the midpoint potential Vt1 (V) of the voltage dividing resistors R1 and R2, and the output voltage of the comparator CP1 becomes high. At the same time, charge control is performed, that is, the MOS transistor N2 is turned on, the MOS transistor NB is turned off, and the capacitor C1 connected to the CP terminal is charged. At the same time, the MOS transistor N3 (charge NMOS2) is turned on, and the MOS transistor NB2 (negative bias NMOS2) is turned off, and a charging operation is also performed on the capacitor C2.

[0102] In addition, by inputting an L signal to the IN terminal, the gate logic circuit GL performs second output switching control to switch the output from the OUT terminal from an H signal to an L signal. As a result, the voltage of the OUT terminal drops and reaches the midpoint potential Vt1 (V), and the output voltage of the comparator CP1 becomes low. At the same time, negative bias application control is performed, that is, the MOS transistor P2 is turned off, the MOS transistor NB is turned on, and a negative bias is applied to the OUT terminal via the VEE terminal. At the same time, the MOS transistor N3 (charge NMOS2) is turned off, and the MOS transistor NB2 (negative bias NMOS2) is repeatedly turned on and off corresponding to the frequency of the oscillation circuit OS, and the capacitor C1 is charged by the charge stored in the capacitor C2, and the discharge of the capacitor C1 is suppressed.

[0103] Figure 14 It is a diagram showing the control timing of the gate drive IC 701. As Figure 14 shown, if an H signal is input to the IN terminal to turn on the MOS transistor T1, the MOS transistor P1 (main source type PMOS) is turned on, the MOS transistor N1 (main drain type NMOS) is turned off, and the voltage of the OUT terminal rises to the VCC voltage (high potential). At the same time as the voltage of the OUT terminal detected by the comparator CP1 rises and reaches the midpoint potential Vt1 (V) of the voltage dividing resistors R1 and R2, the MOS transistor N2 (charge NMOS) is turned on, the MOS transistor NB (negative bias NMOS) is turned off, the MOS transistor N3 (charge NMOS2) is turned on, and the MOS transistor NB2 (negative bias NMOS2) is turned off.

[0104] At this time, the capacitor C1 connected to the CP terminal is charged until the gate voltage of the MOS transistor N2 reaches VDD, and the voltage VC of the capacitor C1 becomes VDD (V).

[0105] On the other hand, if an L signal is input to the IN terminal to turn off the MOS transistor T1, the MOS transistor P1 turns off, the MOS transistor N1 turns on, the voltage of the OUT terminal drops, and simultaneously with the comparator CP1 detecting that the voltage of the OUT terminal reaches the midpoint potential Vt1 (V) of the voltage dividing resistors R1 and R2, the MOS transistor N2 turns off, the MOS transistor NB turns on, the MOS transistor N3 turns off, and the MOS transistor NB2 repeats turning on and off corresponding to the frequency of the oscillation circuit OS.

[0106] At this time, the voltage of the VEE terminal becomes -VC (-VDD (V)) through the discharge of the capacitor C1, and a negative bias is applied to the gate of the MOS transistor T1. The charge discharged by the capacitor C1 is charged during the next period when the voltage of the OUT terminal is at a high potential. However, when the negative bias is being applied, the MOS transistor NB2 repeats turning on and off, and thus, through the charge of the capacitor C2, the capacitor C1 is charged, suppressing the discharge of the capacitor C1. This state is represented by the waveform of the voltage CV2 between the capacitor C2 and the source of the MOS transistor N3.

[0107] In the case where the MOS transistor N2 that charges the capacitor C1 turns off, that is, when the negative bias is being applied, the charge of the capacitor C1 gradually decreases, and the negative bias level decreases. For example, even if the initial voltage of the VEE terminal is -10V, it changes to -9V, -8V. At this time, by turning on the MOS transistor N3, the capacitor C2 is charged, and then by turning on the MOS transistor NB2, a negative voltage (-10V) is generated between the diode D2 and the diode D3. The anode of the diode D3 is -8V, the cathode is -10V, and the diode D3 becomes forward-biased. Therefore, through the charge of the capacitor C2, the capacitor C1 is charged, and the voltage of the VEE terminal approaches from -8V to -10V. When the negative bias is being applied, by repeating such an operation, the capacitor C2 is used to charge the capacitor C1 while discharging it, suppressing the decrease in the negative bias level of the VEE terminal.

[0108] As described above, in the gate driving device 700, by providing the capacitor C2, even when the negative bias is being applied, the capacitor C1 can be charged through the charge of the capacitor C2, the discharge of the capacitor C1 can be suppressed, and the variation of the negative bias voltage can be suppressed.

[0109] <Modification Example 1>

[0110] The gate driving IC 701 of the seventh embodiment described above is for Figure 9The structure of the gate drive IC 501 of Embodiment 5 shown adds the structures of the MOS transistor N3 (charging NMOS2) and the MOS transistor NB2 (negative bias NMOS2), but it can also be added to the structures of the gate drive ICs 101 - 103 of Embodiments 1 - 3.

[0111] <Example of addition to Embodiment 1>

[0112] Figure 15 It is a circuit diagram showing the structure of the gate drive IC 101A obtained by adding the MOS transistor N3 (charging NMOS2) and the MOS transistor NB2 (negative bias NMOS2) to the gate drive IC 101 of Embodiment 1. In addition, in Figure 15 for, the same reference numerals are assigned to the same structures as those of the gate drive IC 101 shown in Figure 1 and repeated descriptions are omitted.

[0113] In Figure 15 the shown gate drive IC 101A, the logic signal from the gate logic circuit GL is input to the gate of the MOS transistor P2 (charging PMOS) and is also input to the AND circuit AG. In addition, it is the same as the charging circuit of the capacitor C1 formed by the capacitor C2 connected to the MOS transistor N3 and the MOS transistor NB2 of the gate drive IC 701 of Embodiment 7 shown in Figure 13 . Also, no external diode D1 is provided in the gate drive IC 101A.

[0114] <Example of addition to Embodiment 2>

[0115] Figure 16 It is a circuit diagram showing the structure of the gate drive IC 201A obtained by adding the MOS transistor N3 (charging NMOS2) and the MOS transistor NB2 (negative bias NMOS2) to the gate drive IC 201 of Embodiment 2. In addition, in Figure 16 for, the same reference numerals are assigned to the same structures as those of the gate drive IC 201 shown in Figure 3 and repeated descriptions are omitted.

[0116] In Figure 16 the shown gate drive IC 201A, the logic signal from the gate logic circuit GL is input to the gate of the MOS transistor P2 (charging PMOS) and is also input to the AND circuit AG. In addition, it is the same as the charging circuit of the capacitor C1 formed by the capacitor C2 connected to the MOS transistor N3 and the MOS transistor NB2 of the gate drive IC 701 of Embodiment 7 shown in Figure 13 . Also, no external diode D1 is provided in the gate drive IC 201A.

[0117] <Additional Example of Embodiment 3>

[0118] Figure 17 This is a circuit diagram showing the structure of a gate driver IC 301A obtained by adding an MOS transistor N3 (charging NMOS2) and an MOS transistor NB2 (negative bias NMOS2) to the gate driver IC 301 of Embodiment 3. In addition, in Figure 17 , for the same structure as that of the gate driver IC 301 shown in Figure 5 , the same reference numerals are used, and repeated descriptions are omitted.

[0119] In Figure 17 the shown gate driver IC 301A, the logic signal from the gate logic circuit GL is input to the gate of the MOS transistor P2 (charging PMOS) and is also input to the AND circuit AG. In addition, it is the same as the charging circuit of the capacitor C1 formed by the capacitor C2 connected to the MOS transistors N3 and NB2 of the gate driver IC 701 of Embodiment 7 shown in Figure 13 . Also, no external diode D1 is provided in the gate driver IC 301A.

[0120] <Modification 2>

[0121] Figure 13 The shown gate driver IC 701 of Embodiment 7 has diodes D2 and D3 connected in series between the source and the VEE terminal for adjusting the turn-off speed of the power device, but the diodes D2 and D3 can be replaced with N-type diode replacement MOS transistors of the gate driver IC 501 of Embodiment 5.

[0122] Figure 18 This is a circuit diagram showing the structure of a gate driver IC 701A obtained by replacing the diodes D2 and D3 of the gate driver IC 701 of Embodiment 7 with N-type diode replacement MOS transistors. In addition, in Figure 18 , for the same structure as that of the gate driver IC 701 shown in Figure 13 , the same reference numerals are used, and repeated descriptions are omitted.

[0123] As shown in Figure 18As shown, in the gate driver IC 701A, an N-type diode connected in series between the source of the MOS transistor NB2 and the VEE terminal is used instead of the MOS transistor DN2 (diode-substituted NMOS2) and the MOS transistor DN3 (diode-substituted NMOS3). The source of the MOS transistor DN2 is connected to GND, the drain is connected to the source of the MOS transistor DN3, and the drain of the MOS transistor DN3 is connected to the VEE terminal. A capacitor C2 is connected between the MOS transistor DN2 and the MOS transistor DN3.

[0124] In addition, the output of the AND circuit AG is connected to the input of the inverter IV6 and is also connected to the gate of the MOS transistor NB2 and the level-shifting circuit LS. The level-shifting circuit LS is a circuit that changes the potential of a signal from the GND reference to the VEE reference. The inverter IV7 is connected to the output of the level-shifting circuit LS, and the inverter IV8 is connected to the output of the inverter IV7. The inverters IV7 and IV8 operate between the VCC voltage and the VEE voltage. The output of the inverter IV7 is input to the gate of the MOS transistor DN2, and the output of the inverter IV8 is input to the gate of the MOS transistor DN3.

[0125] Figure 19 It is a diagram showing the control timing of the gate driver IC 701A. As Figure 19 shown, the control timing of the gate driver IC 701A is basically the same as Figure 14 the control timing of the gate driver IC 701 shown, but by repeatedly turning on and off the gate signals of the MOS transistor DN2 and the MOS transistor DN3 in correspondence with the frequency of the oscillation circuit OS, it is synchronized with the charging and discharging cycle of the capacitor C2.

[0126] As described above, in the gate driver IC 701A, since the MOS transistor DN2 (diode-substituted NMOS2) and the MOS transistor DN3 (diode-substituted NMOS3) are built in, the negative bias application voltage charged in the capacitor C1 is applied to the gate of the MOS transistor T1, and the cut-off operation of the MOS transistor T1 can be further speeded up. In addition, by incorporating the diode function into the gate driver IC 701A, the gate driver device 500 can be miniaturized and low cost can be achieved.

[0127] The present invention described above is summarized in the appended claims.

[0128] (Appended Claim 1)

[0129] A gate driver device that drives the gate of a transistor,

[0130] The gate driver device includes a gate driver circuit, a first capacitor, and a first diode.

[0131] The gate driving circuit has:

[0132] A first transistor of a first conductivity type and a second transistor of a second conductivity type, which are connected in series between a first node to which a first voltage is applied and a second node to which a second voltage lower than the first voltage is applied, and a connection node is an output node of the gate driving device, and the first transistor and the second transistor operate complementarily;

[0133] A first charging transistor and a first negative bias transistor, which are connected in series between the first node and a third node to which a third voltage lower than the first voltage and higher than the second voltage is applied, and a connection node is connected to a capacitance node connected to one electrode of the first capacitor provided outside; and

[0134] A logic circuit that controls the first transistor, the second transistor, the first charging transistor, and the first negative bias transistor,

[0135] The anode of the first diode is connected to the other electrode of the first capacitor and the second node, and the cathode is connected to the third node.

[0136] (Supplementary Note 2)

[0137] A gate driving device that drives the gate of a transistor,

[0138] The gate driving device has a gate driving circuit and a first capacitor,

[0139] The gate driving circuit has:

[0140] A first transistor of a first conductivity type and a second transistor of a second conductivity type, which are connected in series between a first node to which a first voltage is applied and a second node to which a second voltage lower than the first voltage is applied, and a connection node is an output node of the gate driving device, and the first transistor and the second transistor operate complementarily;

[0141] A first charging transistor and a first negative bias transistor, which are connected in series between the first node and a third node to which a third voltage lower than the first voltage and higher than the second voltage is applied, and a connection node is connected to a capacitance node connected to one electrode of the first capacitor provided outside;

[0142] A diode replaces the transistor and is connected between the second node and the third node;

[0143] A driving transistor that drives the gate of the diode replacing the transistor; and

[0144] A logic circuit that controls the first transistor, the second transistor, the first charging transistor, the first negative bias transistor, and the driving transistor.

[0145] (Supplementary Note 3)

[0146] The gate driving device according to Supplementary Note 1 or 2, wherein

[0147] The gate driving circuit monitors the voltage of the output node.

[0148] When the voltage of the output node increases from the second voltage and reaches the threshold voltage, the logic circuit performs charging control, that is, turns on the first charging transistor, turns off the first negative bias transistor, and charges the first capacitor.

[0149] When the voltage of the output node decreases from the first voltage and reaches the threshold voltage, the logic circuit performs negative bias application control, that is, turns off the first charging transistor, turns on the first negative bias transistor, and applies a negative bias to the first transistor.

[0150] (Supplementary Note 4)

[0151] The gate driving device according to Supplementary Note 3, wherein

[0152] The gate driving circuit monitors the voltage of the capacitance node.

[0153] The logic circuit turns off the first charging transistor at the time point when the voltage of the capacitance node reaches the threshold voltage, and ends the charging control.

[0154] (Supplementary Note 5)

[0155] The gate driving device according to Supplementary Note 3, wherein

[0156] The first conductivity type is P-type.

[0157] The second conductivity type is N-type.

[0158] The first charging transistor is an N-type first MOS transistor.

[0159] A gate voltage lower than the first voltage is generated by the gate driving circuit and supplied to the gate of the first MOS transistor.

[0160] (Supplementary Note 6)

[0161] The gate driving device according to Supplementary Note 5, wherein

[0162] The gate drive circuit further includes a second charging transistor connected between the first node and the capacitor node.

[0163] The second charging transistor is an N-type second MOS transistor.

[0164] The logic circuit controls the second MOS transistor in the following manner: when the power supply supplying the first voltage starts up, before the first voltage reaches the threshold voltage from the third voltage, the second MOS transistor is kept turned on, and after reaching the threshold voltage, the second MOS transistor is turned off.

[0165] (Supplementary Note 7)

[0166] The gate drive device according to Supplementary Note 2, wherein

[0167] The gate drive circuit further includes:

[0168] A third charging transistor and a second negative bias transistor, which are connected in series between the first node and the third node;

[0169] A second diode and a third diode, which are connected in series between the third node and the second node; and

[0170] A second capacitor, which is connected between the connection node of the third charging transistor and the second negative bias transistor and the connection node of the second diode and the third diode.

[0171] The gate drive circuit monitors the voltage of the output node.

[0172] When the voltage of the output node increases from the second voltage and reaches the threshold voltage, the logic circuit performs charging control, that is, turns on the first charging transistor, turns off the first negative bias transistor, and charges the first capacitor.

[0173] When the voltage of the output node decreases from the first voltage and reaches the threshold voltage, the logic circuit performs negative bias application control of turning off the first charging transistor, turning on the first negative bias transistor, and applying a negative bias to the first transistor. At the same time, the logic circuit turns off the third charging transistor, repeats the control of turning on and off the second negative bias transistor, and repeats the charge and discharge of the second capacitor.

[0174] (Supplementary Note 8)

[0175] The gate drive device according to Supplementary Note 7, wherein

[0176] The gate drive circuit has an oscillation circuit,

[0177] The gate drive circuit repeatedly gives an on signal and an off signal to the gate of the second negative bias transistor corresponding to the frequency of the oscillation circuit.

Claims

1. A gate driving device, which drives the gate of a transistor, The gate driving device includes a gate driving circuit, a first capacitor and a first diode. The gate drive circuit comprises: a first transistor of a first conductivity type and a second transistor of a second conductivity type, which are connected in series between a first node to which a first voltage is applied and a second node to which a second voltage lower than the first voltage is applied, the connection node being an output node of the gate driving device, and the first transistor and the second transistor operate complementarily; a first charging transistor and a first negative bias transistor connected in series between the first node and a third node to which a third voltage lower than the first voltage and higher than the second voltage is applied, wherein the connection node is connected to a capacitance node connected to one electrode of the first capacitor provided externally; and a logic circuit that controls the first transistor, the second transistor, the first charging transistor, and the first negative bias transistor, The first diode has an anode connected to the other electrode of the first capacitor and the second node, and a cathode connected to the third node.

2. A gate driving device, which drives the gate of a transistor, The gate driving device comprises a gate driving circuit and a first capacitor. The gate drive circuit comprises: a first transistor of a first conductivity type and a second transistor of a second conductivity type, which are connected in series between a first node to which a first voltage is applied and a second node to which a second voltage lower than the first voltage is applied, the connection node being an output node of the gate driving device, and the first transistor and the second transistor operate complementarily; a first charging transistor and a first negative bias transistor connected in series between the first node and a third node to which a third voltage lower than the first voltage and higher than the second voltage is applied, wherein the connection node is connected to a capacitance node connected to one electrode of the first capacitor provided externally; A diode replaces the transistor and is connected between the second node and the third node; A driving transistor that drives the diode instead of the gate of the transistor; as well as A logic circuit controls the first transistor, the second transistor, the first charging transistor, the first negative bias transistor, and the driving transistor.

3. The gate driving device according to claim 1 or 2, wherein: The gate drive circuit monitors the voltage of the output node. When the voltage at the output node increases from the second voltage to reach a threshold voltage, the logic circuit performs charging control, that is, turns on the first charging transistor and turns off the first negative bias transistor to charge the first capacitor. When the voltage at the output node decreases from the first voltage to reach the threshold voltage, the logic circuit performs negative bias application control, that is, turns off the first charging transistor and turns on the first negative bias transistor to apply a negative bias to the first transistor.

4. The gate driving device according to claim 3, wherein: The gate drive circuit monitors the voltage of the capacitor node. The logic circuit turns off the first charging transistor when the voltage at the capacitor node reaches a threshold voltage, thereby terminating the charging control.

5. The gate driving device according to claim 3, wherein: The first conductivity type is P type, The second conductivity type is N type, The first charging transistor is an N-type first MOS transistor, A gate voltage lower than the first voltage is generated by the gate driving circuit and supplied to the gate of the first MOS transistor.

6. The gate driving device according to claim 5, wherein: The gate drive circuit further includes a second charging transistor connected between the first node and the capacitor node. The second charging transistor is an N-type second MOS transistor. The logic circuit controls the second MOS transistor in the following manner, that is, when the power supply supplying the first voltage is started, the second MOS transistor is kept on before the first voltage reaches a threshold voltage from the third voltage, and the second MOS transistor is turned off after reaching the threshold voltage.

7. The gate driving device according to claim 2, wherein: The gate drive circuit also has: a third charging transistor and a second negative biasing transistor, which are connected in series between the first node and the third node; a second diode and a third diode connected in series between the third node and the second node; and a second capacitor connected between a connection node between the third charging transistor and the second negative bias transistor and a connection node between the second diode and the third diode, The gate drive circuit monitors the voltage of the output node. When the voltage at the output node increases from the second voltage to reach a threshold voltage, the logic circuit performs charging control, that is, turns on the first charging transistor and turns off the first negative bias transistor to charge the first capacitor. When the voltage at the output node decreases from the first voltage to reach the threshold voltage, the logic circuit performs negative bias application control to turn off the first charging transistor, turn on the first negative bias transistor, and apply a negative bias to the first transistor. At the same time, the logic circuit turns off the third charging transistor, repeats the control of turning on and off the second negative bias transistor, and repeats the charging and discharging of the second capacitor.

8. The gate driving device according to claim 7, wherein: The gate drive circuit has an oscillation circuit. The gate drive circuit repeatedly applies an on signal and an off signal to the gate of the second negative bias transistor in accordance with a frequency of the oscillation circuit.

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