Driving circuit compatible with various interface standards

Abstract

The invention discloses a driving circuit compatible with various interface standards. The driving circuit comprises a power supply adaptation module, a first push-pull output module and a second push-pull output module, the power supply adaptation module is connected between a positive power supply and a first node; the first push-pull output module and the second push-pull output module are connected in parallel between the first node and a negative power supply; the power supply adaptation module is set to provide a current source for the first node when driving is carried out according to the first interface standard; providing a voltage source to the first node when driving according to a second interface standard; when driving is carried out according to a first interface standard, the first push-pull output module and the second push-pull output module are combined into a differential pair and output a differential signal; when driving is carried out according to a second interface standard, the first push-pull output module and the second push-pull output module work independently and output single-ended signals respectively. The driving circuit can be compatible with various interface standards to realize differential output or single-ended output.

Description

Technical Field

[0001] This document relates to circuit technology, particularly to a drive circuit compatible with multiple interface standards. Background Art

[0002] MIPI (Mobile Industry Processor Interface) is a set of open standards and specifications developed for mobile application processors, mainly used for the connection and data transmission between components inside mobile devices (such as smartphones and tablets). These standards and specifications are designed to meet the requirements of mobile devices for high performance, low power consumption, and small size.

[0003] The physical layer interface standard of MIPI includes two operating modes: HS (High-Speed) mode and LP (Lower-Power) mode. The HS mode uses differential signal transmission and is commonly used for the transmission of high-resolution video data and image sensor data, especially in cases such as screen refresh and video shooting that require high data transmission rates. The LP mode uses single-ended signal transmission and is commonly used for the transmission of device control signals, data handshaking processes, and communication when the device enters the low-power state. The common-mode output signal of the HS mode is between 150 mV and 250 mV, and the differential signal voltage is between 140 mV and 270 mV. The single-ended signal voltage in the LP mode is usually between 0 - 1.2 V.

[0004] LVCMOS (Low-Voltage CMOS) is a widely used logic level standard designed to provide low-power and high-speed digital signal transmission. It supports multiple different voltage ranges, including 1.8 V, 2.5 V, and 3.3 V, etc.

[0005] The voltage standards of the MIPI interface standard and the LVCMOS interface standard are different, so usually different drive circuits are required. Summary of the Invention

[0006] An embodiment of this application provides a drive circuit compatible with multiple interface standards, including: a power supply adaptation module, a first push-pull output module, and a second push-pull output module; the power supply adaptation module is connected between the positive power supply and the first node, and the first push-pull output module and the second push-pull output module are connected in parallel between the first node and the negative power supply; The power supply adaptation module is configured to provide a current source to the first node when driving according to the first interface standard; and provide a voltage source to the first node when driving according to the second interface standard; When driven according to the first interface standard, the first push-pull output module and the second push-pull output module are combined into a differential pair and output a differential signal; when driven according to the second interface standard, the first push-pull output module and the second push-pull output module work independently and output single-ended signals respectively.

[0007] An embodiment of the present application provides a driving circuit compatible with multiple interface standards. When driven according to the first interface standard, the power supply adaptation module provides a current source to the first node; when driven according to the second interface standard, the power supply adaptation module provides a voltage source to the first node; when driven according to the first interface standard, the first push-pull output module and the second push-pull output module are combined into a differential pair and output a differential signal; when driven according to the second interface standard, the first push-pull output module and the second push-pull output module work independently and output single-ended signals respectively. The driving circuit provided by the embodiment of the present application can be compatible with multiple interface standards to achieve differential output or single-ended output.

[0008] Other features and advantages of the present application will be described in the subsequent specification, and some of them will become obvious from the specification, or be understood by implementing the present application. Other advantages of the present application can be achieved and obtained through the solutions described in the specification and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. They are used together with the embodiments of the present application to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0010] Figure 1 It is a schematic structural diagram of a driving circuit compatible with multiple interface standards provided by an embodiment of the present application; Figure 2 It is a schematic circuit diagram of a power supply adaptation module provided by an embodiment of the present application; Figure 3 It is a schematic circuit diagram of a first push-pull output module and a second push-pull output module provided by an embodiment of the present application; Figure 4a It is a schematic diagram of a load connection for differential output provided by an embodiment of the present application; Figure 4b It is a schematic diagram of a load connection for single-ended output provided by an embodiment of the present application; Figure 5 It is a schematic circuit diagram of another first push-pull output module and a second push-pull output module provided by an embodiment of the present application; Figure 6a It is a schematic circuit diagram of a first resistor unit and a second resistor unit provided by an embodiment of the present application (with fixed resistance values); Figure 6bAnother circuit structure diagram of the first resistor unit and the second resistor unit provided by the embodiment of the present application (the resistance value is adjustable); Figure 7 A circuit structure diagram of the first output adjustment module and the second output adjustment module provided by the embodiment of the present application; Figure 8a Another circuit structure diagram of the first output adjustment module and the second output adjustment module provided by the embodiment of the present application; Figure 8b Yet another circuit structure diagram of the first output adjustment module and the second output adjustment module provided by the embodiment of the present application; Figure 9 A circuit structure diagram of another drive circuit compatible with multiple interface standards provided by the embodiment of the present application. Detailed implementation manners

[0011] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the detailed implementation manners, many other combination ways of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0012] The present application includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in the present application can also be combined with any conventional features or elements to form a unique invention solution. Any feature or element of any embodiment can also be combined with features or elements from other invention solutions to form another unique invention solution. Therefore, it should be understood that any feature shown and / or discussed in the present application can be implemented alone or in any suitable combination. Therefore, the embodiments are not subject to other restrictions except those made according to the appended claims and their equivalent replacements. In addition, various modifications and changes can be made within the protection scope of the appended claims.

[0013] In addition, when describing exemplary embodiments, the specification may have presented methods and / or processes as a particular sequence of steps. However, to the extent that the method or process does not depend on a particular order of the steps described herein, the method or process should not be limited to the particular order of steps described. As will be understood by those of ordinary skill in the art, other sequences of steps are possible. Accordingly, the particular order of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method and / or process should not be limited to performing their steps in the order written, as those skilled in the art can readily understand that such orders may vary and still remain within the spirit and scope of the embodiments of the present application.

[0014] Unless otherwise defined, the technical terms or scientific terms used in the disclosure of the embodiments of the present application shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present application pertains. The terms "first", "second" and similar terms used in the embodiments of the present application do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "comprising" or "including" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0015] Those skilled in the art can understand that the transistors adopted in all embodiments of the present application can be field effect transistors or other devices with the same characteristics. The field effect transistors used in the embodiments of the present application can be MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). MOSFETs have advantages such as high input impedance, fast switching and low power consumption. According to the channel type, they can be divided into N-channel MOSFETs (NMOS) and P-channel MOSFETs (PMOS). In the embodiments of the present application, to distinguish the two poles (source and drain) of the field effect transistor other than the gate, one of the poles is referred to as the first pole and the other as the second pole. The first pole is the source and the second pole is the drain, or the first pole is the drain and the second pole is the source. In addition, the gate of the transistor is referred to as the control pole.

[0016] Embodiments of the present application provide a drive circuit compatible with multiple interface standards. As Figure 1As shown in the figure, a driving circuit compatible with multiple interface standards includes: a power supply adaptation module 1, a first push-pull output module 2, and a second push-pull output module 3; the power supply adaptation module is connected between the positive power supply VCC and the first node N1, and the first push-pull output module and the second push-pull output module are connected in parallel between the first node and the negative power supply VSS; The power supply adaptation module is configured to provide a current source to the first node N1 when driving according to the first interface standard; and provide a voltage source to the first node when driving according to the second interface standard; When driving according to the first interface standard, the first push-pull output module and the second push-pull output module are combined into a differential pair and output a differential signal; when driving according to the second interface standard, the first push-pull output module and the second push-pull output module work independently and output single-ended signals respectively.

[0017] In the driving circuit compatible with multiple interface standards provided by the embodiments of the present application, the power supply adaptation module provides a current source to the first node when driving according to the first interface standard; provides a voltage source to the first node when driving according to the second interface standard; when driving according to the first interface standard, the first push-pull output module and the second push-pull output module are combined into a differential pair and output a differential signal; when driving according to the second interface standard, the first push-pull output module and the second push-pull output module work independently and output single-ended signals respectively. The driving circuit provided by the embodiments of the present application can be compatible with multiple interface standards to achieve differential output or single-ended output.

[0018] In an exemplary embodiment, as Figure 2 shown, the power supply adaptation module includes: a current source unit 11 and a first switch unit 13; the current source unit and the first switch unit are connected in parallel between the positive power supply VCC and the first node N1; The power supply adaptation module is configured to control the first switch unit to disconnect according to the first control signal S1 when driving according to the first interface standard; and control the first switch unit to conduct to short-circuit the current source unit according to the first control signal S1 when driving according to the second interface standard.

[0019] In an exemplary embodiment, the first switch unit includes a transistor.

[0020] In an exemplary embodiment, as Figure 3 shown, the first push-pull output module includes: a first transistor M1 and a second transistor M2; the second push-pull output module includes: a third transistor M3 and a fourth transistor M4; A first pole of the first transistor is connected to the first node, a second pole of the first transistor is connected to the first output terminal OUT1, and a control pole of the first transistor is connected to the first input terminal IN1; The first pole of the second transistor is connected to the negative power supply VSS, the second pole of the second transistor is connected to the first output terminal OUT1, and the control pole of the second transistor is connected to the first input terminal IN1; The first pole of the third transistor is connected to the first node, the second pole of the third transistor is connected to the second output terminal OUT2, and the control pole of the third transistor is connected to the second input terminal IN2; The first pole of the fourth transistor is connected to the negative power supply VSS, the second pole of the fourth transistor is connected to the second output terminal OUT2, and the control pole of the fourth transistor is connected to the second input terminal IN2; Wherein, the first transistor and the third transistor are P-type transistors, and the second transistor and the fourth transistor are N-type transistors; the on-resistance values of the second transistor and the fourth transistor are equal.

[0021] In an exemplary embodiment, as Figure 4a shown, when driving according to the first interface standard, a load RL is connected between the first output terminal and the second output terminal; a first input signal is input to the first input terminal and a second input signal is input to the second input terminal, and the phases of the first input signal and the second input signal are opposite.

[0022] In an exemplary embodiment, as Figure 4b shown, when driving according to the second interface standard, a first load RL1 is connected between the first output terminal and the negative power supply and / or a second load RL2 is connected between the second output terminal and the negative power supply; a first input signal is input to the first input terminal and / or a second input signal is input to the second input terminal, and the first input signal and the second input signal are two independent signals.

[0023] In an exemplary embodiment, as Figure 5 shown, the first push-pull output module 2 further includes: a first resistor unit 21; the second push-pull output module 3 further includes: a second resistor unit 31; The first resistor unit is arranged between the first output terminal OUT1 and the second pole of the second transistor; The second resistor unit is arranged between the second output terminal OUT2 and the second pole of the fourth transistor; Wherein, the resistance value of the first resistor unit is equal to the resistance value of the second resistor unit.

[0024] In an exemplary embodiment, as Figure 6a shown, the first resistor unit includes: a first resistor R1; the second resistor unit includes: a second resistor R2.

[0025] In an exemplary embodiment, as Figure 6bAs shown, the first resistor unit 21 includes: N first controlled resistor sub-units 211 connected in parallel; the second resistor unit 31 includes: N second controlled resistor sub-units 311 connected in parallel; the i-th first controlled resistor sub-unit 211(i) and the i-th second controlled resistor sub-unit 311(i) are paired to form the i-th controlled resistor sub-unit pair; N is an integer greater than 1; ; For the i-th controlled resistor sub-unit pair, the i-th first controlled resistor sub-unit 211(i) therein includes: the i-th second switch unit 2111(i) and the i-th first resistor R1(i) connected in series; the i-th second controlled resistor sub-unit 311(i) therein includes: the i-th third switch unit 3111(i) and the i-th second resistor R2(i) connected in series; the i-th second switch unit 2111(i) is configured to conduct or disconnect under the control of the i-th second control signal S2(i); the i-th third switch unit 3111(i) is configured to conduct or disconnect under the control of the i-th second control signal S2(i); the resistance values of the i-th first resistor R1(i) and the i-th second resistor R2(i) are equal; the on-resistance values of the i-th second switch unit and the i-th third switch unit are equal.

[0026] In an exemplary embodiment, the i-th second switch unit 2111(i) and the i-th third switch unit 3111(i) of the i-th controlled resistor sub-unit pair include N-type transistors or P-type transistors with the same electrical parameters. Among them, the electrical parameters include: DC parameters, AC parameters, dynamic parameters, power parameters, thermal parameters, etc.

[0027] In an exemplary embodiment, the resistance values of the first resistor unit and the second resistor unit are controlled by N second control signals (S2(1), S2(2)…, S2(N)). For example, when the N second control signals are all valid signals (controlling the second switch unit and the third switch unit to conduct), the first resistor unit includes N first controlled resistor sub-units connected in parallel. Assuming the resistance value of each first controlled resistor sub-unit is r1, then the resistance value of the first resistor unit is r1 / N; the second resistor unit includes N second controlled resistor sub-units connected in parallel. Assuming the resistance value of each second controlled resistor sub-unit is r2, then the resistance value of the second resistor unit is r2 / N.

[0028] When the drive circuit uses Figure 5When the first push-pull output module and the second push-pull output module shown are driven according to the first interface standard, a load RL is connected between the first output terminal and the second output terminal. Assume that the voltage value of the first output signal output by the first output terminal is Vout1, the voltage value of the second output signal output by the second output terminal is Vout2, the resistance value of the first resistor unit is R1, the resistance value of the second resistor unit is R2, R1 = R2, the resistance value of the load is RL, and the current value output by the current source is I. The first transistor and the third transistor are P-type transistors, the second transistor and the fourth transistor are N-type transistors with the same electrical parameters, and the on-resistance of the second transistor is , and the on-resistance of the fourth transistor is . For the convenience of calculation, the equivalent resistance after connecting the first resistor unit and the second transistor in series is denoted as . ; The equivalent resistance after connecting the second resistor unit and the fourth transistor in series is denoted as , ; .

[0029] When the first input signal is at a low level and the second input signal is at a high level, the first transistor and the fourth transistor are turned on, and the second transistor and the third transistor are turned off. Vout1 and Vout2 can be calculated using the following formulas (1.1) and (1.2).

[0030] (1.1) (1.2) The differential-mode voltage V DM of the output differential signal can be calculated using the following formula (1.3).

[0031] (1.3) The common-mode voltage V CM of the output differential signal can be calculated using the following formula (1.4).

[0032] (1.4) When the first input signal is at a high level and the second input signal is at a low level, the second transistor and the third transistor are turned on, and the first transistor and the fourth transistor are turned off. Vout1 and Vout2 can be calculated using the following formulas (1.5) and (1.6).

[0033] (1.5) (1.6) The differential-mode voltage V DMIt can be calculated using the following formula (1.7).

[0034] (1.7) The common - mode voltage V of the output differential signal CM It can be calculated using the following formula (1.8).

[0035] (1.8) By setting the current value of the current source, the differential - mode voltage value of the output differential signal can be set. By setting the resistance values of the first resistor unit and the second resistor unit, the common - mode voltage value of the output differential signal can be set.

[0036] In an exemplary embodiment, as Figure 7 shown, the drive circuit compatible with multiple interface standards further includes: a first output adjustment module 4 and a second output adjustment module 5; the first output adjustment module 4 includes: a third resistor unit 41 and a fourth switch unit 43 connected in series; the second output adjustment module 5 includes: a fourth resistor unit 51 and a fifth switch unit 53 connected in series; The first output adjustment module is disposed between the first output terminal OUT1 and the negative power supply VSS; The second output adjustment module is disposed between the second output terminal OUT2 and the negative power supply VSS; The fourth switch unit is set to be turned on or off under the control of the third control signal S3; The fifth switch unit is set to be turned on or off under the control of the third control signal S3; The resistance values of the third resistor unit and the fourth resistor unit are equal; the on - resistance values of the fourth switch unit and the fifth switch unit are equal.

[0037] In an exemplary embodiment, the fourth switch unit and the fifth switch unit include N - type transistors or P - type transistors with the same electrical parameters. Among them, the electrical parameters include: DC parameters, AC parameters, dynamic parameters, power parameters, and thermal parameters, etc.

[0038] In an exemplary embodiment, as Figure 8a shown, the third resistor unit includes: a third resistor R3; the fourth resistor unit includes: a fourth resistor R4.

[0039] In an exemplary embodiment, as Figure 8bAs shown, the third resistor unit 41 includes: M third controlled resistor sub-units 411 connected in parallel; the fourth resistor unit 51 includes: M fourth controlled resistor sub-units 511 connected in parallel; the j-th third controlled resistor sub-unit 411(j) and the j-th fourth controlled resistor sub-unit 511(j) are paired to form the j-th controlled resistor sub-unit pair; M is an integer greater than 1; ; For the j-th controlled resistor sub-unit pair, the j-th third controlled resistor sub-unit 411(j) therein includes: the j-th fourth switch unit 4111(j) and the j-th third resistor R3(j) connected in series; the j-th fourth controlled resistor sub-unit 511(j) therein includes: the j-th fifth switch unit 5111(j) and the j-th fourth resistor R4(j) connected in series; the j-th fourth switch unit 4111(j) is arranged to be turned on or off under the control of the j-th fourth control signal S4(j); the j-th fifth switch unit 5111(j) is arranged to be turned on or off under the control of the j-th fourth control signal S4(j); the resistance values of the j-th third resistor R3(j) and the j-th fourth resistor R4(j) are equal; the on-resistance values of the j-th fourth switch unit and the j-th fifth switch unit are equal.

[0040] In an exemplary embodiment, the j-th fourth switch unit 4111(j) and the j-th fifth switch unit 5111(j) of the j-th controlled resistor sub-unit pair include N-type transistors or P-type transistors with the same electrical parameters.

[0041] In an exemplary embodiment, the resistance values of the third resistor unit and the fourth resistor unit are controlled by M fourth control signals (S4(1), S4(2), …, S4(M)). For example, when all M fourth control signals are valid signals (controlling the fourth switch unit and the fifth switch unit to be turned on), the third resistor unit includes M third controlled resistor sub-units connected in parallel. Assuming the resistance value of each third controlled resistor sub-unit is r3, then the resistance value of the third resistor unit is r3 / M; the fourth resistor unit includes M fourth controlled resistor sub-units connected in parallel. Assuming the resistance value of each fourth controlled resistor sub-unit is r4, then the resistance value of the fourth resistor unit is r4 / M.

[0042] Figure 9 A schematic diagram of a drive circuit compatible with multiple interface standards is provided. As Figure 9As shown in the figure, a drive circuit compatible with multiple interface standards includes: a power supply adaptation module 1, a first push-pull output module 2, a second push-pull output module 3, a first output adjustment module 4, and a second output adjustment module 5; the power supply adaptation module is connected between the positive power supply VCC and the first node N1, and the first push-pull output module and the second push-pull output module are connected in parallel between the first node and the negative power supply VSS; The power supply adaptation module includes: a current source unit 11 and a first switch unit 13; the current source unit and the first switch unit are connected in parallel between the positive power supply VCC and the first node N1; The first push-pull output module includes: a first transistor M1, a first resistor unit 21, and a second transistor M2; The second push-pull output module includes: a third transistor M3, a second resistor unit 31, and a fourth transistor M4; The first pole of the first transistor is connected to the first node, the second pole of the first transistor is connected to the first output terminal OUT1, and the control pole of the first transistor is connected to the first input terminal IN1; The first resistor unit 21 is provided between the first output terminal OUT1 and the second pole of the second transistor; The first pole of the second transistor is connected to the negative power supply VSS, the second pole of the second transistor is connected to the first output terminal OUT1, and the control pole of the second transistor is connected to the first input terminal IN1; The first pole of the third transistor is connected to the first node, the second pole of the third transistor is connected to the second output terminal OUT2, and the control pole of the third transistor is connected to the second input terminal IN2; The second resistor unit 31 is provided between the second output terminal OUT2 and the second pole of the fourth transistor; The first pole of the fourth transistor is connected to the negative power supply VSS, the second pole of the fourth transistor is connected to the second output terminal OUT2, and the control pole of the fourth transistor is connected to the second input terminal IN2; The resistance values of the first resistor unit and the second resistor unit are equal; the first transistor and the third transistor are P-type transistors, the second transistor and the fourth transistor are N-type transistors; the on-resistance values of the second transistor and the fourth transistor are equal; The first output adjustment module 4 includes: a third resistor unit 41 and a fourth switch unit 43 connected in series; the second output adjustment module 5 includes: a fourth resistor unit 51 and a fifth switch unit 53 connected in series; The first output adjustment module is provided between the first output terminal OUT1 and the negative power supply VSS; The second output adjustment module is provided between the second output terminal OUT2 and the negative power supply VSS; The fourth switching unit is set to conduct or disconnect under the control of the third control signal S3; The fifth switching unit is set to conduct or disconnect under the control of the third control signal S3; The resistance values of the third resistor unit and the fourth resistor unit are equal; the on-resistance values of the fourth switching unit and the fifth switching unit are equal.

[0043] In an exemplary embodiment, the first interface standard includes: the high-speed mode of the physical layer interface standard of MIPI; the second interface standard includes: the LVCMOS standard, or the low-power mode of the physical layer interface standard of MIPI.

[0044] In an exemplary embodiment, when driving according to the first interface standard, a first data signal and a second data signal with opposite phases are respectively input to the first input terminal and the second input terminal.

[0045] In an exemplary embodiment, when driving according to the first interface standard and the data transfer rate is greater than the first threshold, the level of the third control signal is set to the first level; when driving according to the second interface standard, the level of the third control signal is set to the second level; wherein, the first level can make the fourth switching unit and the fifth switching unit conduct, and the second level can make the fourth switching unit and the fifth switching unit disconnect.

[0046] When the data transfer rate is high (high-frequency signal), relatively serious electromagnetic wave reflection phenomena may occur on the differential signal transmission line. By connecting the first output adjustment module and the second output adjustment module, the output impedance of the driving circuit can be matched with the impedance on the differential signal transmission line, thereby reducing or eliminating the electromagnetic wave reflection on the transmission line.

[0047] Figure 9 For the shown driving circuit compatible with multiple interface standards, when driving according to the first interface standard and the data transfer rate is higher than the first threshold, the third control signal is a valid signal (able to make the fourth switching unit and the fifth switching unit conduct), a load RL is connected between the first output terminal and the second output terminal. Assuming the voltage value of the first output signal output by the first output terminal is Vout1, the voltage value of the second output signal output by the second output terminal is Vout2, the resistance value of the first resistor unit is R1, the resistance value of the second resistor unit is R2, R1 = R2, the resistance value of the third resistor unit is R3, the resistance value of the fourth resistor unit is R4, R3 = R4, the resistance value of the load is RL, the current value output by the current source is I, the first transistor and the third transistor are P-type transistors, the second transistor and the fourth transistor are N-type transistors, the on-resistance value of the second transistor is and the on-resistance value of the fourth transistor is , ; The on-resistance value of the fourth switch unit is , and the on-resistance value of the fifth switch unit is , . For the convenience of calculation, the equivalent resistance after the first resistor unit and the second transistor are connected in series is denoted as , ; The equivalent resistance after the second resistor unit and the fourth transistor are connected in series is denoted as , ; . The equivalent resistance after the third resistor unit and the fourth switch unit are connected in series is denoted as , ; The equivalent resistance after the fourth resistor unit and the fifth switch unit are connected in series is denoted as , ; . " / / " is the symbol for two resistors connected in parallel.

[0048] When the first input signal is at a low level, the second input signal is at a high level, and the third control signal is a valid signal (the first level), the first transistor, the fourth transistor, the fourth switch unit, and the fifth switch unit are turned on, the second transistor and the third transistor are turned off, and Vout1 and Vout2 can be calculated using the following formulas (2.1) and (2.2).

[0049] (2.1) (2.2) The differential-mode voltage V of the output differential signal DM can be calculated using the following formula (2.3).

[0050] (2.3) The common-mode voltage V of the output differential signal CM can be calculated using the following formula (2.4).

[0051] (2.4) When the first input signal is at a high level, the second input signal is at a low level, and the third control signal is a valid signal (the first level), the second transistor, the third transistor, the fourth switch unit, and the fifth switch unit are turned on, the first transistor and the fourth transistor are turned off, and Vout1 and Vout2 can be calculated using the following formulas (2.5) and (2.6).

[0052] (2.5) (2.6) The differential-mode voltage V of the output differential signalDM It can be calculated using the following formula (2.7).

[0053] (2.7) The common-mode voltage V of the output differential signal CM It can be calculated using the following formula (2.8).

[0054] (2.8) The resistance values of the first resistor unit and the second resistor unit are equal, and the resistance values of the third resistor unit and the fourth resistor unit are equal. By adjusting the resistance values of the first resistor unit (the second resistor unit) and / or the third resistor unit (the fourth resistor unit), the common-mode voltage value and the differential-mode voltage value of the output differential signal can be adjusted.

[0055] When the first input signal is at a low level, the second input signal is at a high level, and the third control signal is a valid signal (the first level), the first transistor, the fourth transistor, the fourth switch unit, and the fifth switch unit are turned on, and the second transistor and the third transistor are turned off. Assume that the internal resistance of the current source unit is (the internal resistance of an ideal current source approaches infinity). The output impedance of the first output terminal It can be calculated using the following formula (3.1). The output impedance of the second output terminal It can be calculated using the following formula (3.2).

[0056] (3.1) (3.2) Because the internal resistance of the current source unit is very large, the equivalent resistance after the internal resistance of the current source unit is connected in series with the first transistor is much larger than the equivalent resistance after the third resistor unit and the fourth switch unit are connected in series , so the output impedance of the first output terminal can be approximately calculated using the following formula (3.3).

[0057] (3.3) When the first input signal is at a high level, the second input signal is at a low level, and the third control signal is a valid signal (the first level), the second transistor, the third transistor, the fourth switch unit, and the fifth switch unit are turned on, and the first transistor and the fourth transistor are turned off. The output impedance of the first output terminal It can be calculated using the following formula (3.4). The output impedance of the second output terminal It can be calculated using the following formula (3.5).

[0058] (3.4) (3.5) Since the internal resistance of the current source unit is very large, the equivalent resistance after the internal resistance of the current source unit is connected in series with the third transistor is much larger than the equivalent resistance after the fourth resistor unit and the fifth switch unit are connected in series , so the output impedance of the second output terminal can be approximately calculated using the following formula (3.6).

[0059] (3.6) By adjusting the resistance values of the third resistor unit and the fourth resistor unit, the output impedance of the first output terminal and the output impedance of the second output terminal can be made close to the load resistance RL, thereby achieving the purpose of impedance matching.

[0060] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and appropriate combinations thereof. In the hardware implementation, the division of the functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be executed by several physical components in cooperation. Some or all of the components can be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassette, tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, a communication medium typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0061] In addition, terms such as "first", "second", etc. are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include at least one such feature.

[0062] In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0063] In the present application, unless otherwise clearly specified and defined, terms such as "installed", "connected", "joined", "fixed", etc. shall be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal connection of two components or the interaction relationship between two components, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0064] In the description of this specification, descriptions with reference to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0065] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A driving circuit compatible with multiple interface standards, comprising: A power adapter module, a first push-pull output module, and a second push-pull output module; The power adapter module is connected between the positive power supply and the first node, and the first push-pull output module and the second push-pull output module are connected in parallel between the first node and the negative power supply; A power adapter module, configured to provide a current source to the first node when driving according to the first interface standard; and to provide a voltage source to the first node when driving according to the second interface standard; When driven according to the first interface standard, the first push-pull output module and the second push-pull output module are combined into a differential pair and output differential signals; when driven according to the second interface standard, the first push-pull output module and the second push-pull output module work independently and output single-ended signals respectively.

2. The driving circuit according to claim 1, characterized in that: The power adapter module comprises: a current source unit and a first switch unit; the current source unit and the first switch unit are connected in parallel between the positive power supply and the first node; The power adapter module is configured to control the first switch unit to be disconnected according to a first control signal when driven according to a first interface standard; and to control the first switch unit to be turned on according to the first control signal to short-circuit the current source unit when driven according to a second interface standard.

3. The driving circuit according to claim 1, characterized in that: The first push-pull output module includes: a first transistor and a second transistor; the second push-pull output module includes: a third transistor and a fourth transistor; A first electrode of the first transistor is connected to a first node, a second electrode of the first transistor is connected to a first output terminal, and a control electrode of the first transistor is connected to a first input terminal; A first electrode of the second transistor is connected to a negative power supply, a second electrode of the second transistor is connected to the first output terminal, and a control electrode of the second transistor is connected to the first input terminal; A first electrode of the third transistor is connected to the first node, a second electrode of the third transistor is connected to the second output terminal, and a control electrode of the third transistor is connected to the second input terminal; A first electrode of the fourth transistor is connected to a negative power supply, a second electrode of the fourth transistor is connected to a second output terminal, and a control electrode of the fourth transistor is connected to a second input terminal; The first transistor and the third transistor are P-type transistors, the second transistor and the fourth transistor are N-type transistors, and the on-resistance values ​​of the second transistor and the fourth transistor are equal.

4. The driving circuit according to claim 3, characterized in that: The first push-pull output module further includes: a first resistance unit; the second push-pull output module further includes: a second resistance unit; The first resistance unit is arranged between the first output terminal and the second electrode of the second transistor; The second resistance unit is arranged between the second output terminal and the second electrode of the fourth transistor; The resistance value of the first resistance unit is equal to the resistance value of the second resistance unit.

5. The driving circuit according to claim 4, characterized in that: The first resistance unit includes: a first resistor; the second resistance unit includes: a second resistor; or The first resistance unit includes: N first controlled resistance subunits arranged in parallel; the second resistance unit includes: N second controlled resistance subunits arranged in parallel; the i-th first controlled resistance subunit and the i-th second controlled resistance subunit are paired to form the i-th controlled resistance subunit pair; N is an integer greater than 1; ; For the i-th controlled resistor sub-unit pair, the i-th first controlled resistor sub-unit includes: the i-th second switch unit and the i-th first resistor connected in series; the i-th second controlled resistor sub-unit includes: the i-th third switch unit and the i-th second resistor connected in series; the i-th second switch unit is set to be turned on or off under the control of the i-th second control signal; the i-th third switch unit is set to be turned on or off under the control of the i-th second control signal; the resistance values ​​of the i-th first resistor and the i-th second resistor are equal; the resistance values ​​of the on-resistances of the i-th second switch unit and the i-th third switch unit are equal.

6. The driving circuit according to claim 3 or 4, characterized in that: The driving circuit compatible with multiple interface standards further includes: a first output regulating module and a second output regulating module; The first output regulating module comprises: a third resistance unit and a fourth switch unit connected in series; the second output regulating module comprises: a fourth resistance unit and a fifth switch unit connected in series; The first output regulating module is arranged between the first output terminal and the negative power supply; The second output regulating module is arranged between the second output terminal and the negative power supply; The fourth switch unit is configured to be turned on or off under the control of a third control signal; The fifth switch unit is configured to be turned on or off under the control of the third control signal; The resistance values ​​of the third resistance unit and the fourth resistance unit are equal; the resistance values ​​of the on-resistances of the fourth switch unit and the fifth switch unit are equal.

7. The driving circuit according to claim 6, characterized in that: The third resistor unit includes: a third resistor; the fourth resistor unit includes: a fourth resistor; or The third resistance unit includes: M third controlled resistance subunits arranged in parallel; the fourth resistance unit includes: M fourth controlled resistance subunits arranged in parallel; the jth third controlled resistance subunit and the jth fourth controlled resistance subunit are paired to form a jth controlled resistance subunit pair; M is an integer greater than 1; ; For the jth controlled resistance sub-unit pair, the jth third controlled resistance sub-unit includes: the jth fourth switch unit and the jth third resistor connected in series; the jth fourth controlled resistance sub-unit includes: the jth fifth switch unit and the jth fourth resistor connected in series; the jth fourth switch unit is set to be turned on or off under the control of the jth fourth control signal; the jth fifth switch unit is set to be turned on or off under the control of the jth fourth control signal; the resistance values ​​of the jth third resistor and the jth fourth resistor are equal; the resistance values ​​of the on-resistances of the jth fourth switch unit and the jth fifth switch unit are equal.

8. The driving circuit according to claim 6, characterized in that: When driven according to the first interface standard and the data transmission rate is greater than the first threshold, the level of the third control signal is set to the first level; when driven according to the second interface standard, the level of the third control signal is set to the second level; wherein the first level can turn on the fourth switch unit and the fifth switch unit, and the second level can turn off the fourth switch unit and the fifth switch unit.

9. The driving circuit according to claim 1, characterized in that: The first interface standard includes: the high-speed mode of the physical layer interface standard of the mobile industry processor interface MIPI; The second interface standard includes: low voltage CMOS logic level standard LVCMOS, or low power consumption mode of MIPI physical layer interface standard.

10. The driving circuit according to claim 1, characterized in that: When driving according to the first interface standard, a load is connected between the first output terminal and the second output terminal; a first input signal is input to the first input terminal and a second input signal is input to the second input terminal, and the first input signal and the second input signal have opposite phases; When driven according to the second interface standard, a first load is connected between the first output terminal and the negative power supply and / or a second load is connected between the second output terminal and the negative power supply; a first input signal is input into the first input terminal and / or a second input signal is input into the second input terminal, and the first input signal and the second input signal are two independent signals.

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