MDAC circuit of assembly line analog-to-digital converter

Abstract

The invention relates to an MDAC circuit of a pipelined analog-to-digital converter. The technical problems that in the prior art, an assembly line ADC is large in stage number and large in delay are solved, and jitter signal injection is facilitated. According to the technical scheme, the circuit comprises a first sampling capacitor array, a second sampling capacitor array, a first feedback capacitor array, a second feedback capacitor array and an operational amplifier. According to the further technical scheme, the circuit further comprises a first bridge capacitor, a first correction capacitor array, a second bridge capacitor and a second correction capacitor array. According to the technical scheme, the operational amplifiers of the adjacent sub-conversion stages are shared, so that one operational amplifier is saved, and the overall power consumption of the ADC is effectively reduced. The single conversion stage can adopt high-resolution conversion processing, the serial stage number of the whole assembly line analog-to-digital converter is reduced, and the assembly line delay is reduced. The capacitors of two adjacent sub-conversion stages are shared, so that the number of the capacitors is reduced, and the layout area of an integrated circuit is reduced.

Description

Technical Field

[0001] This application relates to the technical field of Analog-to-Digital Converters (ADCs), particularly to pipelined analog-to-digital converters. Specifically, it relates to an MDAC (Multiplying Digital-to-Analog Converter) circuit of a pipelined analog-to-digital converter. Background Art

[0002] As a bridge between the analog world and digital signal systems, analog-to-digital converters provide raw data for digital processing systems, and thus are necessarily required to preferably have both high conversion speed and high conversion accuracy. Nowadays, the technical routes of analog-to-digital converters with both high precision and high throughput rate generally have two directions, successive approximation (SAR) and pipelined architectures. Pipelined analog-to-digital conversion is widely used in instrumentation, communication base stations, high-speed imaging, and precision test equipment. However, with the development of technology and the improvement of system requirements, as the precision of traditional pipelined analog-to-digital converters increases, the serial working mode determines that only by continuously increasing the number of sub-converters can higher resolution be achieved, and the consequent problem is that the pipeline delay is too large, increasing the complexity of the system. For example, a 14-bit pipelined analog-to-digital converter is internally decomposed into 7 sub-pipeline stages of 2.5 bits and 1 3-bit fully parallel ADC, and its pipeline delay is at least 7 cycles. At the same time, the higher the throughput rate, the more sub-pipeline stages there are, and the more residue amplifiers there are between stages, and the greater its power consumption is.

[0003] Compared with the other technical route of high-speed and high-precision converters, the successive approximation architecture is characterized by low power consumption and no pipeline delay, etc. Under certain specific application conditions, traditional pipelined analog-to-digital converters cannot meet system requirements.

[0004] Figure 1 Fig. shows a pipelined ADC structure formed by L (L is an integer, L>1) stages of sub-ADCs, where two adjacent sub-ADCs share one MDAC. MDAC is an important circuit module in a pipelined analog-to-digital converter, which is responsible for performing functions such as signal sampling, amplification, and residue calculation, and is generally implemented using a switched-capacitor circuit.

[0005] As shown in Figure 2 , are schematic diagrams of two traditional MDAC circuit structures. It consists of a sampling capacitor C S , a feedback capacitor C F , an operational amplifier RA, several sampling switches (φ S ) and several timing switches (φ H ). Figure 2The a circuit is a traditional charge redistribution type MDAC structure. Figure 2 The b circuit is another traditional capacitor switching type MDAC structure. The difference between the two structures lies in whether a fixed feedback capacitor is added. In the charge redistribution type MDAC, during the sampling phase, the sampling capacitor C S samples the signal, and the feedback capacitor C F and the operational amplifier are in the reset state, connected to the common mode level. During the amplification phase, the lower plate of the sampling capacitor C S is connected to the common mode level. Assuming that the operational amplifier has infinite gain and infinite bandwidth, all the charge will be transferred to the output node VOUT; in the capacitor switching type structure, there is no fixed feedback capacitor. When the sampling capacitor C S enters the hold phase after sampling the signal, it directly connects the input to the output of the operational amplifier to complete holding and amplification.

[0006] If the common mode of the active devices driving the pipelined analog-to-digital converter is inconsistent with the common mode of the input signal of the ADC, the charge redistribution structure has more advantages. From the perspective of the feedback coefficient, the feedback coefficient of the capacitor switching type structure is higher, and it will perform better in terms of loop bandwidth, noise power, and offset gain. Generally, the first sub-conversion stage of the pipelined analog-to-digital converter uses the MDAC with the charge redistribution structure, and the subsequent pipeline stages use the capacitor switching type MDAC.

[0007] The redundant coding algorithm of the commonly used pipelined analog-to-digital converter today was proposed in the 1990s. The digital codes of each stage are added with dislocation through a delay circuit to obtain the final output code. Taking the commonly used 1.5-bit pipelined structure as an example, it has 2 comparators, and the output digital codes are 00, 01, 10. The offset voltage that the comparator can tolerate is increased to 0.25VREF (reference level), so as to eliminate the influence of the comparator offset voltage on the performance of the ADC. Later, the idea of 1.5bit / stage was extended to n.5 bits per stage. When this redundant coding correction scheme is applied to high-speed and high-precision pipelined ADCs, there are problems such as uneven quantization intervals, different errors in different quantization regions, and differences in the linearity of the output curve, which affect the performance of the ADC. Moreover, generally, the sub-conversion stage is selected from 3.5bit / stage, 2.5bit / stage, and 1.5bit / stage. The effective number of bits of a single conversion stage is relatively small, and the number of pipeline stages increases, resulting in a relatively large pipeline delay.

[0008] On the other hand, random signal processing is widely used in various fields of academia and industry. In a pipelined analog-to-digital converter, a pseudo-random signal, also known as a dither signal, is used to improve the linearity of the ADC, which is a very mature technology. The principle is to inject a PN sequence (dither) that is not related to the input signal VIN into the signal path to modulate VIN, and extract the actual gain error and capacitance mismatch in the digital domain to calibrate the digital output of the pipelined ADC. The injection position and extraction scheme of the dither signal are diverse, and according to different MDAC circuit structures, the injection of the dither signal in the MDAC circuit is completed. Summary of the Invention

[0009] The main object of the present application is to provide an MDAC circuit for a pipelined analog-to-digital converter to solve the technical problems of the existing pipelined ADC with many stages and large delay, and to facilitate the injection of the dither signal.

[0010] To achieve the above object, according to one aspect of the specific embodiments of the present application, there is provided an MDAC circuit for a pipelined analog-to-digital converter, including a first sampling capacitor array, a second sampling capacitor array, a first feedback capacitor array, a second feedback capacitor array, and an operational amplifier; characterized in that:

[0011] The lower plate of each sampling capacitor in the first sampling capacitor array is connected to the input signal VIN- through a first switch and to the reference level or ground level through a second switch; the upper plate is connected to the negative input terminal of the operational amplifier;

[0012] The lower plate of each sampling capacitor in the second sampling capacitor array is connected to the input signal VIN+ through a first switch and to the reference level or ground level through a second switch; the upper plate is connected to the positive input terminal of the operational amplifier;

[0013] The lower plate of each capacitor in the first feedback capacitor array is connected to the negative input terminal of the operational amplifier; the upper plate is connected to the negative output terminal of the amplifier through a second switch and to the reference level or ground level through a third switch;

[0014] The lower plate of each capacitor in the second feedback capacitor array is connected to the positive input terminal of the operational amplifier; the upper plate is connected to the negative output terminal of the amplifier through a second switch and to the reference level or ground level through a third switch;

[0015] The first switch, the second switch, and the third switch are controlled by three non-overlapping clocks;

[0016] The connection of the second switch to the reference level or ground level is controlled by the binary code output by the first sampling;

[0017] The third switch is connected to a reference level or a ground level and is controlled by a binary code output from a second sampling.

[0018] In some embodiments:

[0019] The first sampling capacitor array and the second sampling capacitor array each include n capacitors, where n = 2 K , K is the resolution of the first sampling, and K ≥ 1;

[0020] The first feedback capacitor array and the second feedback capacitor array each include N capacitors, a fixed capacitor, and a matching capacitor. N is the resolution of the second sampling, N ≥ 1, and n and N are integers, with n > N.

[0021] In some embodiments:

[0022] The n capacitors have equal capacitances.

[0023] In some embodiments:

[0024] The capacitance of the n capacitors = unit capacitance.

[0025] In some embodiments:

[0026] The capacitances of the N capacitors are 1C, 2C... 2 N-1 C, where C is the unit capacitance.

[0027] In some embodiments:

[0028] The capacitance of the matching capacitor is C, where C is the unit capacitance.

[0029] In some embodiments:

[0030] It further includes a first bridging capacitor, a first correction capacitor array, a second bridging capacitor, and a second correction capacitor array;

[0031] The upper plate of the first bridging capacitor is connected to the negative input terminal of the operational amplifier, and the lower plate is connected to the upper plates of each capacitor in the first correction capacitor array;

[0032] The lower plate of each capacitor in the first feedback capacitor array is connected to a ground level or a reference level through a first switch;

[0033] The upper plate of the second bridging capacitor is connected to the positive input terminal of the operational amplifier, and the lower plate is connected to the upper plates of each capacitor in the second correction capacitor array;

[0034] The lower plate of each capacitor in the second feedback capacitor array is connected to a ground level or a reference level through a first switch.

[0035] In some embodiments:

[0036] The first correction capacitor array includes M capacitors, where M is the number of bits of the injected dither signal.

[0037] In some embodiments:

[0038] All the capacitors in the first sampling capacitor array, the second sampling capacitor array, the first feedback capacitor array, the second feedback capacitor array, the first correction capacitor array, and the second correction capacitor array are co-centered.

[0039] In some embodiments:

[0040] The lower plate of each capacitor in the first feedback capacitor array is connected to the ground level or the reference level through a first switch and is controlled by the number of bits of the dither signal;

[0041] The lower plate of each capacitor in the second feedback capacitor array is connected to the ground level or the reference level through a first switch and is controlled by the number of bits of the dither signal.

[0042] According to the technical solution of the present application and the further improved technical solution in some exemplary embodiments, the present application has the following beneficial effects:

[0043] In the technical solution of the present application, the operational amplifiers of two adjacent sub-conversion stages can be shared, thus saving one operational amplifier and effectively reducing the overall power consumption of the ADC. In the present application, a single conversion stage can adopt high-resolution conversion processing, the number of serial stages of the entire pipelined analog-to-digital converter is reduced, the pipeline delay is reduced, and even no pipeline delay can be achieved. The present application uses the feedback capacitor splitting technology to share the capacitors of two adjacent sub-conversion stages, reduces the number of capacitors, reduces the integrated circuit layout area, and indirectly reduces the influence of capacitor mismatch error at the same time. The present application designs the feedback capacitor as a segmented capacitor array, which is convenient for injecting the dither signal for digital calibration, and the amplitude of the injected pseudo-random signal is controllable, with a simple structure and easy to implement. The segmented arrays of the sampling capacitor and the feedback capacitor in the present application are beneficial to the matching of the capacitors on the layout, further reducing the capacitor matching error and being conducive to improving the conversion accuracy.

[0044] The following further describes the present application in conjunction with the drawings and specific embodiments. The additional aspects and advantages of the present application will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present application. Description of the Drawings

[0045] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The specific embodiments, illustrative embodiments and their descriptions of the present application are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0046] Figure 1Schematic diagram of the pipeline ADC structure in the prior art.

[0047] Figure 2 Schematic diagrams of two typical MDAC circuit structures in the prior art; among them, Figure a is the schematic diagram of the charge redistribution type MDAC circuit structure, and Figure b is the schematic diagram of the capacitor switching type MDAC circuit structure.

[0048] Figure 3 Schematic diagram of the MDAC circuit structure of Embodiment 1 of the present application.

[0049] Figure 4 Schematic diagram of the driving pulse waveforms of the first switch, the second switch, and the third switch.

[0050] Figure 5 Schematic diagram of the MDAC circuit structure of Embodiment 2 of the present application. Detailed implementation manners

[0051] It should be noted that, without conflict, the specific implementation manners, exemplary embodiments, and features therein in the present application can be combined with each other. The present application will now be described in detail with reference to the accompanying drawings and the following content.

[0052] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the specific implementation manners and exemplary embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the specific implementation manners and exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the specific implementation manners and exemplary embodiments in the present application, all other implementation manners and embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0053] The MDAC circuit of the pipelined analog-to-digital converter of the present application includes a first sampling capacitor array C S , a first feedback capacitor array C F , a second feedback capacitor array C F ', and an operational amplifier RA.

[0054] The first sampling capacitor array C S is composed of capacitors C S1 , C S2 , …, C Sn , the second sampling capacitor array C S ' is composed of capacitors C S1 ', C S2 ', …, C Sn ', and the first feedback capacitor array C F , is composed of capacitors C F1 , C F2 , …, CFN , C FT , C FB consists of the second feedback capacitor array C F ’, which is composed of capacitors C F1 ’, C F2 ’, …, C FN ’, C FT ’, C FB ’. Capacitors C FT and C FB as well as C FT ’ and C FB ’ are respectively called matching capacitors and fixed capacitors, and their main function is to match and adjust the gain of the operational amplifier.

[0055] During the first sampling conversion, in the sampling phase, the first sampling capacitor array C S1 , C S2 , …, C Sn samples the input signal VIN-, and the second sampling capacitor array C S1 ’, C S2 ’, …, C Sn ’ samples the input signal VIN+. In the amplification phase, the upper plates of all the capacitors in the first feedback capacitor array C F are connected to VO1-, and the upper plates of all the capacitors in the second feedback capacitor array C F ’ are connected to VO1+. The lower plates of the capacitors C S1 ’, C S2 ’, …, C Sn ’ and the capacitors C S1 , C S2 , …, C Sn are respectively connected to the ground potential (0 level) or the reference voltage VREF according to the output results of the adjacent upper-level sub-ADC, completing the sampling and residue amplification of the first-stage signal.

[0056] During the second sampling conversion, in the sampling phase, the upper plates of all the capacitors in the first feedback capacitor array C F are all connected to the negative output terminal VO1- of the operational amplifier, and the upper plates of all the capacitors in the second feedback capacitor array C F ’ are all connected to the positive output terminal VO1+ of the operational amplifier. In the amplification phase, C F will be split into capacitors with a fixed ratio, and according to the results of the first sampling conversion, its lower plates will be respectively connected to the ground potential or the reference voltage VREF. The same is true for C F ’, completing the sampling and residue amplification of the second-stage signal.

[0057] Both the first sampling conversion and the second sampling conversion adopt the integer redundant coding correction method, and the resolution of a single conversion stage can be designed as 8 bits, 7 bits, 6 bits, 5 bits, 4 bits, 3 bits, etc.

[0058] Two adjacent sub-ADCs share an operational amplifier, and the capacitor C F and C F ' serves as the feedback capacitor in the first sampling conversion and as the sampling capacitor and the feedback capacitor in the second sampling conversion. Similar to the capacitor-switching type MDAC, through operational amplifier sharing and capacitor splitting sharing, the overall power consumption and the influence of capacitor mismatch error are significantly reduced.

[0059] Based on the basic architecture of the MDAC circuit of this application, in the above-mentioned first sampling conversion, the first feedback capacitor array C F and the second feedback capacitor array C F ' are connected by a bridging capacitor to add a series of binary proportional capacitors, and their lower plates are respectively connected to the ground potential or the reference voltage V REF controlled by the level of the dither signal, so as to complete the injection of the dither signal in the MDAC circuit.

[0060] Embodiment 1

[0061] The schematic diagram of the MDAC circuit structure in this embodiment is as shown in Figure 3 The first sampling capacitor array C S and the second sampling capacitor array C S ' serve as sampling capacitors and are respectively composed of C S1 , C S2 , …, C Sn and C S1 ', C S2 ', …, C Sn '. In the first sampling capacitor array C S , the lower plates of all capacitors are connected to the input signal VIN- through the first switch θ1 and are connected to the reference voltage V REF or the ground potential through the second switch θ2. In the second sampling capacitor array C S ', the lower plates of all capacitors are connected to the input signal VIN+ through the first switch θ1 and are connected to the reference voltage V REF or the ground potential through the second switch. The upper plates of all capacitors in the first sampling capacitor array C S and the second sampling capacitor array C S ' are respectively connected to the negative input terminal - and the positive input terminal + of the operational amplifier RA. The sub-Kbits Flash-ADC performs K bits of analog-to-digital conversion on the input signals VIN+ and VIN-, and the output is a 2 K -bit binary code, which is responsible for controlling the first sampling capacitor array CS and the second sampling capacitor array C S ’s lower plate is specifically connected to the ground potential or the reference voltage V REF . When the binary code is at a high level, it corresponds to all the lower plates of the capacitors in the first sampling capacitor array C S being connected through the second switch θ2 to the reference voltage V REF , and all the lower plates of the capacitors in the corresponding second sampling capacitor array C S ’ being connected to the ground potential. When the binary code is at a low level, it corresponds to all the lower plates of the capacitors in the first sampling capacitor array C S being connected through the second switch θ2 to the ground potential, and all the lower plates of the capacitors in the corresponding second sampling capacitor array C S ’ being connected to the reference voltage V REF .

[0062] In the first sampling capacitor array C of this embodiment S and the second sampling capacitor array C S ’, the number of capacitors n = 2 K , K is the resolution of the first sampling, K≥1. The capacitances of all the capacitors are equal: C S1 = C S2 = … = C Sn , C S1 ’ = C S2 ’ = … = C Sn ’. The MDAC circuit of this application has a fully differential symmetric structure, so C Sn = C Sn ’. To simplify capacitor matching and save the integrated circuit layout, in this benefit, the capacitor C Sn = C Sn ’ = C, and C is the unit capacitor.

[0063] In this embodiment, the first feedback capacitor array C F and the second feedback capacitor array C F ’ are respectively composed of capacitors C F1 , C F2 , …, C FN , C FT , C FB and C F1 ’, C F2 ’, …, C FN ’, C FT ’, C FB ’. In the first feedback capacitor array C F , all the lower plates of the capacitors are connected to the upper plates of all the capacitors in the first sampling capacitor array C s , which is also the negative input terminal - of the operational amplifier RA. In the second feedback capacitor array C F ’, all the lower plates of the capacitors are connected to the second sampling capacitor array CS The upper plates of all the capacitors in ' are also the positive input terminal + of the operational amplifier RA. The first feedback capacitor array C F In, the upper plates of all the capacitors are connected to the negative output VO1- of the operational amplifier RA through the second switch θ2 and can be connected to the ground potential or the reference voltage V REF , which depends on the N-bit binary code of the second sampling conversion. In the second feedback capacitor array C F ’, the upper plates of all the capacitors are connected to the positive output VO1+ of the operational amplifier RA through the second switch θ2 and can be connected to the ground potential or the reference voltage V REF , which also depends on the N-bit binary code of the second sampling conversion.

[0064] In this embodiment, the capacitor C F1 = 1C, C F2 = 2C, C F3 = 4C,..., C FN = 2 N-1 C, the capacitor C F1 ’ = 1C, C F2 ’ = 2C, C F3 ’ = 4C,..., C FN ’ = 2 N-1 C, where C is the unit capacitor and N is the resolution of the second sampling conversion. This way of taking values in a geometric progression is convenient for the matching of capacitors on the layout, and is also beneficial to improving the matching accuracy and saving the layout area.

[0065] The capacitor C FT = TC, C FB = BC, C FT ’ = TC, C FB ’ = BC, C is the unit capacitor, and B and T are integers greater than or equal to 1. The value of T is jointly determined by the operational amplifier gain A1 of the first sampling conversion, the operational amplifier gain A2 of the second sampling conversion, and the resolution N of the first sampling conversion.

[0066] Figure 4 is the non-overlapping clock timing schematic diagram of the MDAC circuit of this application. θ1, θ2, and θ3 represent non-overlapping clock phases (also used for the marking of the corresponding switches), which are respectively used to control the first switch, the second switch, and the third switch. The corresponding switch conducts when the high level is applied. When θ1 is set to the high level, the first switch conducts, controlling the sampling of the first sampling capacitor array C S and the second sampling capacitor array C S ’, as well as the analog-to-digital conversion of the sub-ADC; when θ2 is set to the high level, the second switch conducts, controlling the first capacitor array C S and the second capacitor array C S’ Connection relationship of the lower plate of the capacitor, and the first feedback capacitor array C F and the second feedback capacitor array C F ’ Connection of the upper plate of the capacitor to the output terminal, complete the amplification and residual error calculation of the first sampling conversion, and the sampling operation of the second sampling conversion; when θ3 is at high level, the third switch conducts, controlling the first feedback capacitor array C F and the second feedback capacitor array C F ’ Connection relationship of the upper plate of the capacitor, complete the amplification and residual error calculation of the second sampling conversion.

[0067] After the clock phase θ1 is set to high level, when θ2 is set to high level, the first sampling conversion completes the sampling, holding, and amplification and difference calculation operations of the input signal. When the clock phase θ1 is at high level, the lower plates of the capacitors C S1 , C S2 , …, C Sn are all connected to the input signal VIN-, and the lower plates of the capacitors C S1 ’, C S2 ’, …, C Sn ’ are all connected to the input signal VIN+, completing the sampling of the fully differential input signal. At the same time, the sub-Kbits Flash-ADC performs Kbits analog-to-digital conversion on the differential input signal, generating 2 K bits of binary code. The upper plates of all the capacitors in the feedback capacitor arrays C F and C F ’ are respectively connected to the output terminals VO1- and VO1+. When the clock phase θ2 is at high level, all the capacitors in the sampling capacitor arrays C S and C S ’ are disconnected from the input signals VIN+ and VIN-, and according to the 2 K bits of binary code, control the lower plates of the corresponding sampling capacitor arrays C S and C S ’ to be connected to 0V, or the reference voltage V REF , and the actions of the lower plates of the capacitors in the first sampling capacitor array C S and the second sampling capacitor array C S ’ are opposite. At this stage, the MDAC circuit is similar to the traditional charge redistribution structure. According to the charge conservation, the amplification gain A1 of the half circuit is

[0068] (C S1 +C S2 +…+C Sn ) / (C F1 +C F2 +…+C FN +C FT +C FB) By adopting a charge redistribution MDAC structure, the common-mode level of the differential input signal can be set arbitrarily, and the applicable scenarios are more extensive.

[0069] After the clock phase θ2 is set to high level, when θ3 is set to high level, the operations of sampling, holding, and amplifying and subtracting the second sampling conversion completion signal are performed. When the clock phase θ2 is at high level, the upper plates of the capacitors in the first feedback capacitor array C F and the second feedback capacitor array C F ’ are respectively connected to VO1- and VO1+ to sample the output signal of the first sampling conversion. At the same time, the sub Nbits Sub-ADC performs analog-to-digital conversion on the output signal of the first sampling conversion to generate an Nbits binary coding result. When the clock phase θ3 is at high level, the Nbits conversion data controls C F1 、C F2 、…、C FN ’s upper plates are respectively connected to 0V or the reference voltage V REF . That is, if the Nth conversion data is at high level, the upper plate of the capacitor C FN is connected to the reference voltage V REF . If the Nth conversion data is at low level, the upper plate of the capacitor C FN is connected to 0V. The upper plates of the capacitors C F1 ’、C F2 ’、…、C FN ’ move in the opposite way.

[0070] C FT =(C S1 +C S2 +…+C Sn ) / A1-(C F1 +C F2 +…+C FN )-C F / A2, C FT ’=(C S1 ’ +C S2 ’ +…+C Sn ’ )

[0071] / A1-(C F1 ’+C F2 ’+…+C FN ’)-C F ’ / A2. The upper plates of the capacitors C FT and C FT ’ are both connected to 0V. The upper plates of the capacitors C FB and C FB ’ remain in place and are respectively connected to VO1- and VO1+. The first sampling capacitor array C Sand the second sampling capacitor array C S ’, the lower plates of the capacitors remain in place without change. With the cooperation of the operational amplifier RA, the operations of amplifying the second sampling conversion and obtaining the residual difference can be completed. At this stage, the MDAC circuit is similar to the traditional capacitor switching structure. According to the charge conservation, the amplification gain A2 of the half circuit is = (C F1 +C F2 +…+C FN +C FT +C FB ) / C FB . At this time, the feedback coefficient of the MDAC circuit is higher, which is beneficial to reducing the adverse effects brought by static errors and dynamic errors.

[0072] The Kbits in the first sampling conversion determine that the resolution of the first sampling conversion is K. The adjacent Nbits in the second sampling conversion determine that the resolution of the second sampling conversion is N. Where K and N can be integers such as 8bits, 7bits, 6bits, 5bits, 4bits, 3bits, etc.

[0073] Embodiment 2

[0074] Attached Figure 5 is a schematic diagram of the dither signal injection scheme of the MDAC circuit of the present invention. On the basis of Figure 4 , the circuit of the dashed box 100 is added, including the first bridging capacitor C DQ , the first correction capacitor array C DM composed of M capacitors, C DM-1 , C D2 , C D1 , the second bridging capacitor C DQ ’, the second correction capacitor array C DM ’ composed of M capacitors, C DM-1 ’, C D2 ’, C D1 ’, where M is the number of bits of the injected dither signal. The upper plate of the first bridging capacitor C DQ is connected to the lower plate of the C F capacitor. The lower plate of the first bridging capacitor C DQ is connected to the upper plates of the first correction capacitor array C DM , C DM-1 , C D2 , C D1 . The lower plates of the first correction capacitor array C DM , C DM-1 , C D2 , C D1 can be connected to 0V or the reference voltage V REF through a single-pole double-throw switch. The second bridging capacitor CDQ The upper plate of '' is connected to C F The lower plate of the '' capacitor, C DQ The lower plate of '' is connected to the second calibration capacitor array C DM '', C DM-1 '', C D2 '', C D1 The upper plates of '', the second calibration capacitor array C DM '', C DM-1 '', C D2 '', C D1 The lower plates of '' are connected to 0V or the reference voltage V through a single-pole double-throw switch REF . Among them, the capacitor C D1 = C D1 '' = 1C, C D2 = C D2 '' = 2C,..., C DM = C DM '' = 2 M-1 C, where C is the unit capacitor.

[0075] When the clock phase θ1 is set to high level, the jitter signal levels of Mbits respectively control the single-pole double-throw switches of the lower plates of the capacitors in the corresponding calibration capacitor array, and are connected to 0V or the reference voltage V REF , that is, when the Mbit = 1, the lower plate of the capacitor in the corresponding calibration capacitor array is connected to the reference voltage V REF ; when the Mbit = 0, the lower plate of the capacitor is connected to 0V. When the clock phases θ2 and θ3 are set to high level, the connection relationship of the lower plates of the capacitors remains unchanged, and the analog-domain MDAC injection of the multi-bit jitter signal can be completed.

[0076] In this application, all the capacitors in the first sampling capacitor array, the second sampling capacitor array, the first feedback capacitor array, the second feedback capacitor array, the first calibration capacitor array and the second calibration capacitor array share the common centroid, so as to minimize the capacitor mismatch error as much as possible. Moreover, in each capacitor array, the capacitors are designed in the form of a geometric sequence as much as possible, which is convenient for capacitor matching and layout, is beneficial to reducing the matching error and improving the capacitor accuracy.

[0077] To sum up, the MDAC circuit of the high-precision pipelined analog-to-digital converter of this application flexibly adopts the integer-type redundant coding correction method, uses the capacitor splitting and sharing technology, and performs serial operation of adjacent two-stage sub-conversions, saving the power consumption of an operational amplifier and the capacitor area, and reducing the error of capacitor mismatch. Based on the new MDAC circuit, the analog-domain injection of the jitter signal for digital calibration can be easily completed, the injection amplitude is controllable, the circuit design is flexible, and the reliability is high, and it can be more widely applied in the design of high-speed and high-precision pipelined analog-to-digital converters.

[0078] The above are only the embodiments of the present invention, and do not thus limit the patent scope of the present invention. Any equivalent structures made by using the content of the specification and drawings of the present invention, directly or indirectly applied in other related technical fields, are similarly within the patent protection scope of the present invention.

Claims

1. An MDAC circuit of a pipeline analog-to-digital converter, comprising a first sampling capacitor array, a second sampling capacitor array, a first feedback capacitor array, a second feedback capacitor array, and an operational amplifier; characterized in that: The lower plate of each sampling capacitor in the first sampling capacitor array is connected to the input signal VIN- through a first switch, and is connected to the reference level or ground level through a second switch; the upper plate is connected to the negative input terminal of the operational amplifier; The lower plate of each sampling capacitor in the second sampling capacitor array is connected to the input signal VIN+ through a first switch and connected to the reference level or ground level through a second switch; the upper plate is connected to the positive input terminal of the operational amplifier; The lower plate of each capacitor in the first feedback capacitor array is connected to the negative input terminal of the operational amplifier; the upper plate is connected to the negative output terminal of the amplifier through the second switch, and is connected to the reference level or the ground level through the third switch; The lower plate of each capacitor in the second feedback capacitor array is connected to the positive input terminal of the operational amplifier; the upper plate is connected to the negative output terminal of the amplifier through the second switch, and is connected to the reference level or the ground level through the third switch; The first switch, the second switch and the third switch are controlled by three non-overlapping clocks; The second switch connection reference level or ground level is controlled by the binary code output by the first sampling; The third switch is connected to a reference level or a ground level controlled by a binary code output by the second sampling.

2. The MDAC circuit of a pipeline analog-to-digital converter according to claim 1, characterized in that: The first sampling capacitor array and the second sampling capacitor array each include n capacitors, n=2 K , K is the resolution of the first sampling, K ≥ 1; The first feedback capacitor array and the second feedback capacitor array each include N capacitors, a fixed capacitor and a matching capacitor, N is the resolution of the second sampling, N≥1, n, N are integers, n>N.

3. The MDAC circuit of a pipeline analog-to-digital converter according to claim 2, characterized in that: The n capacitors have equal capacities.

4. The MDAC circuit of a pipeline analog-to-digital converter according to claim 3, characterized in that: The n capacitor capacities = unit capacitance.

5. The MDAC circuit of a pipeline analog-to-digital converter according to claim 2, characterized in that: The N capacitor capacities are 1C, 2C, . . . 2 N-1 C, C is the unit capacitance.

6. The MDAC circuit of a pipeline analog-to-digital converter according to claim 2, characterized in that: The matching capacitor capacity is C, where C is the unit capacitance.

7. The MDAC circuit of a pipeline analog-to-digital converter according to claim 1, characterized in that: Also includes a first bridging capacitor, a first correction capacitor array, a second bridging capacitor, and a second correction capacitor array; The upper plate of the first bridge capacitor is connected to the negative input terminal of the operational amplifier, and the lower plate is connected to the upper plate of each capacitor in the first correction capacitor array; The lower plate of each capacitor in the first feedback capacitor array is connected to a ground level or a reference level through a first switch; The upper plate of the second bridge capacitor is connected to the positive input terminal of the operational amplifier, and the lower plate is connected to the upper plate of each capacitor in the second correction capacitor array; The lower plate of each capacitor in the second feedback capacitor array is connected to a ground level or a reference level through a first switch.

8. The MDAC circuit of a pipeline analog-to-digital converter according to claim 7, characterized in that: The first correction capacitor array and the second correction capacitor array each include M capacitors, where M is the number of bits of the injected jitter signal.

9. The MDAC circuit of a pipeline analog-to-digital converter according to claim 7, characterized in that: All capacitors in the first sampling capacitor array, the second sampling capacitor array, the first feedback capacitor array, the second feedback capacitor array, the first correction capacitor array and the second correction capacitor array share a common centroid.

10. The MDAC circuit of a pipeline analog-to-digital converter according to claim 7, characterized in that: The lower plate of each capacitor in the first feedback capacitor array is connected to the ground level or the reference level through the first switch and is controlled by the number of bits of the jitter signal; The lower plate of each capacitor in the second feedback capacitor array is connected to the ground level or the reference level through the first switch, and the ground level or the reference level is controlled by the number of bits of the jitter signal.

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