Analog-to-digital converter with auto-zero residual amplification circuit

Abstract

The invention relates to an analog-to-digital converter with an auto-zero residual amplification circuit. Examples of an analog-to-digital converter (ADC) are disclosed herein to enable automatic zeroing to be performed by amplifying a signal to improve a signal-to-noise ratio. The ADC may generate a first digital code representing an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to generate a digital output code representing the analog input signal. The ADC may generate the second digital code using a first observed value and a second observed value representing an analog residual value of the residual.

Description

[0001] This application is a divisional application of the invention patent application with the application date of August 11, 2021, the application number of 202110917306.3, and the invention title of "Analog-to-Digital Converter with Automatic Zeroing Residual Amplification Circuit". Technical Field

[0002] The present disclosure generally relates to the field of electronic circuits, and more specifically but not exclusively to a system and method for data conversion. Background Art

[0003] Analog signals and / or values can be generated in various circuit elements, such as signal generators, sensors, and antennas. However, there may be many situations where having a digital signal or value may be beneficial, such as for processing or storing the signal or value. To take advantage of the benefits of having a digital signal or value when generating an analog signal or value, analog-to-digital converters (ADCs) have been developed to convert analog signals or values into digital signals or values.

[0004] A signal can be a sequence of time-based values. A digital value can be represented by a code. The name of the code (e.g., CODE1) can refer to the digital value represented by the code. Some (but not all) digital values can be represented by codes using binary weighted coding. The resolution of a digital value or code represented by multiple bits can refer to binary weighted coding, regardless of the way it is physically encoded.

[0005] In many electronic applications, an analog input value is converted into a digital output value (e.g., for further digital processing or storage). For example, in a precision measurement system, an electronic device has one or more sensors for making measurements, and these sensors can generate analog values. The analog values can be provided as inputs to an ADC to generate digital output values for further processing or storage.

[0006] ADCs can be found in many places, such as broadband communication systems, automatic test equipment, audio systems, vehicles, factory automation systems, etc. An ADC can convert analog electrical values representing real-world phenomena such as light, sound, temperature, flow, or pressure. Designing an ADC is a very important task because each application may have different requirements in terms of speed, performance, power consumption, cost, and size. As the applications that require ADCs grow, the demand for accurate and reliable conversion performance also grows.

[0007] Some applications may require precise and accurate analog value conversion, thus requiring a precision ADC (precision means precise and / or accurate). The specifications required for a precision ADC may include low noise and small and stable offsets. A constant zero offset may be desirable. The design goal of the ADC and other circuits may be a constant zero offset, but defects in the manufacturing process, mismatches in nominally identical semiconductor devices, atomic-level charge migration, etc. may make the circuit offset potentially non-zero, and it may vary with changes in parameters such as time, temperature, and / or supply voltage. An auto-zero (AZ) circuit may be used in a precision ADC to stabilize a potentially non-zero offset (i.e., reduce the potentially non-zero offset and / or substantially prevent changes in the potentially non-zero offset). The offset of the auto-zero circuit may be substantially zero (such as less than 100 microvolts including variations). However, traditional AZ circuits may increase the broadband noise level, which is disadvantageous when low noise and low power are required simultaneously. When an AZ circuit is used, the power consumption of the precision ADC may have to be increased to reduce the noise to an acceptable level. There is a need for low-power ADCs, including low-power, low-offset, and low-noise precision ADCs.

[0008] Several AZ circuits have been developed. Figure 1 An AZ amplifier circuit 120 of the prior art is shown. The AZ amplifier circuit 120 may operate in two phases: Phase 1 ( Figure 1 with the mark Φ1 in) and Phase 2 ( Figure 1 with the mark Φ2 in). Phase 1 and Phase 2 do not overlap in time, and the operation may be repeated periodically or aperiodically. Switches 113 and 107 are closed (conductive) during Phase 1, otherwise they are open (non-conductive). Similarly, switches 115p, 115m are closed during Phase 2, otherwise they are open. The voltage input voltage output amplifier circuit 121 has two input terminals 103p, 103m and two output terminals 105p, 105m. In one example, terminal 103m and terminal 105m are connected together and share a common potential, such as ground or 0 V. In Phase 1, the input terminals 103p, 103m are short-circuited by switch 107, which forms a nominal zero voltage on the input terminals 103p, 103m. The amplifier circuit 121 has a potentially non-zero offset, such as OS = 1 mV. During Phase 1 when switch 107 is closed, an amplified offset may be observed at terminals 105p, 105m. For example, if the amplifier circuit 121 has a voltage gain factor, GAIN = 200, then the amplified offset GAIN∙OS = 200∙1 mV = 200 mV is observed as the voltage between output terminals 105p and 105m. Note that the offset OS may be an undesired artifact of the amplifier circuit 121, and the AZ amplifier circuit 120 does not have to include any circuitry for intentionally providing a non-zero offset OS. Thus, Figure 1No (and there should be no) source or any other circuitry for providing or representing the offset OS is shown, and the offset OS may be (but need not be) nominally zero. An amplified non-zero offset can be observed as a non-zero voltage between terminals 105p and 105m even if the voltage between terminals 103p and 103m is exactly zero.

[0009] Capacitor 109 is configured between terminal 105p and terminal 111p. Switch 113 shorts terminal 111p and 105m during phase 1, whereby the amplified offset can be observed as the voltage across capacitor 109. During the transition from phase 1 to phase 2, switch 113 is slightly opened before switch 107 is opened, whereby the observed amplified offset is sampled across capacitor 109. The voltage VRES (i.e., the analog value) applied at its input terminals 101p, 101m to the AZ amplifier circuit 120 is provided to amplifier circuit 121 at terminals 103p, 103m via switches 115p, 115m closed during phase 2. On the one hand, if (VRES>0), then a voltage greater than the amplified offset GAIN∙OS is observed between terminals 105p and 105m, and a voltage greater than zero is observed between terminals 111p and 105m. On the other hand, if (VRES<0), then a voltage less than the amplified offset GAIN∙OS is observed between terminals 105p and 105m, and a voltage less than zero is observed between terminals 111p and 105m. Thus, the polarity of the voltage VRES applied at the input (terminals 101p, 101m) of the AZ amplifier circuit 120 corresponds to the polarity of the amplified voltage GAIN∙VRES observed at the output (terminals 111p, 105m) of the AZ amplifier circuit 120. When the polarities correspond, the effective offset of the AZ amplifier circuit 120 can be zero. Even if the offset OS of amplifier circuit 121 is non-zero, the effective offset of the AZ amplifier circuit 120 can be zero. The two-phase operation of the AZ amplifier circuit 120 can substantially cancel (i.e., reduce to a small value, nominally zero) the potential non-zero offset of amplifier circuit 121. A circuit, process, or operation configured to operate using multiple phases and substantially cancel a potential non-zero offset may be referred to as an “auto-zero” circuit, process, or operation. Note that the auto-zero operation may require little or no knowledge of the circuit's potential non-zero offset. The AZ circuit (e.g., AZ amplifier circuit 120) provides nominal operation (e.g., amplification) during only one of the multiple phases (e.g., phase 2) of its operation (e.g., phase 1 and phase 2).

[0010] The AZ amplifier circuit 120 exemplifies that the offset OS can be amplified and observed in one phase. The combination of the input VRES and the offset OS can be amplified and observed in another phase. The AZ amplifier circuit 120 combines and outputs the combination of the two observed values, whereby the combined contribution from the offset OS can be substantially zero. Specifically, the first observed value GAIN∙OS and the second observed value GAIN∙(VRES + OS) are combined such that the contribution of the offset in one observed value can be substantially canceled by an equal and opposite (having equal magnitude and opposite polarity) contribution of the offset from the other observed value. For example, the combination of the two observed values is GAIN∙(VRES + OS) - GAIN∙OS = GAIN∙VRES. The contribution of the input VRES to the combined output is GAIN∙VRES. The contribution of the offset OS to the combined output may be substantially zero, GAIN∙(OS - OS) = 0. The auto-zero offset may nominally be zero. The AZ circuit can suppress low-frequency noise modeled as an offset that varies with time.

[0011] Figure 1 The successful operation of the AZ amplifier circuit 120 in FIG. depends on the observed value sampled on the capacitor 109 in phase 1, which remains substantially unchanged during the subsequent phase 2. To achieve this, the AZ amplifier circuit 120 is coupled to an amplifier (or buffer) circuit 117, which is configured to draw very little charge (if any) passing through the capacitor 109 from the terminal 111p during phase 2. When referring to the input VRES, the offset of the amplifier circuit 117 is suppressed by the gain factor provided by the AZ amplifier circuit 120, such as GAIN = 200. In some applications, the amplifier circuit 117 is an auto-zero amplifier circuit, such as the AZ amplifier circuit 120. In some embodiments, the capacitor 109 is divided into two parts (not shown) and the first half-capacitor is configured to be in series with the terminal 105p and the second half-capacitor is configured to be in series with the terminal 105m.

[0012] Figure 2Shows another type of prior art AZ amplifier circuit 220. The voltage input voltage output amplifier circuit 221 that performs auto-zeroing has a pair of input terminals 203p and 203m and a pair of output terminals 205p and 205m. It further has an auxiliary input 211 for applying an auxiliary (control) voltage. The effective (auto-zero) offset of the AZ amplifier circuit 220 is a combination of the potential non-zero offset of the amplifier circuit 221 and the auxiliary voltage applied at the input 211 to cancel the offset contribution. The amplifier circuit 221 is a two-stage amplifier circuit well-known to a person of ordinary skill in the art (PHOSITA). It includes an input gm stage (i.e., a transconductance circuit, not shown) coupled to the input terminals 203p and 203m and an output stage (e.g., a transimpedance stage, not shown) coupled to the output terminals 205p and 205m. An auxiliary gm stage (not shown) is coupled to the input 211 and the input gm stage. The currents provided by the input gm stage and the auxiliary gm stage are combined such that the current provided by the auxiliary gm stage can cancel the offset of the input gm stage. The auxiliary voltage is sampled and stored on a capacitor 209 coupled to the input 211. The capacitor 209 is not directly coupled to the output terminals 205p, 205m. When the switch 213 is open, the first terminal of the capacitor 209 connected to the input 211 is substantially floating. The output terminals 205p, 205m of the amplifier circuit 221 are also the output terminals of the AZ amplifier circuit 220. The input impedance of the optional load circuit 217 may be relatively unimportant, and the AZ amplifier circuit 220 may be more versatile in use than Figure 1 the AZ amplifier circuit 120.

[0013] The AZ amplifier circuit 220 operates in two phases: Phase 1 ( Figure 2 the mark Φ1 in Figure 2 ), and Phase 2 (

[0014] the mark Φ2 in ). During Phase 1, the switch 207 is closed to apply a zero voltage across the terminals 203p and 203m. The amplified combination of the potential non-zero offset and the auxiliary voltage is observed as the voltage at the terminals 205p, 205m, which are connected to the gm stage (transconductance stage circuit) 223. The switch 213 couples the gm stage 223 to the capacitor 209 and the input 211 during Phase 1. The polarity of the amplified combination nominally determines the polarity of the current provided by the gm stage 223, which can accordingly increase or decrease the auxiliary voltage at the input 211 during Phase 1 when the switch 213 is closed. The negative feedback operating mode ensures that the auxiliary voltage at the input 211 is substantially stable at the end of Phase 1, and the amplified combination at the terminals 205p, 205m can be substantially zero.

[0014] During the transition from stage 1 to stage 2, switch 213 is turned on for a period of time before switch 207 is turned on. This effectively samples the substantially stable auxiliary voltage on capacitor 209 and holds it at input 211 during stage 2. Switch 219 is closed during stage 2 to divert the current available from gm stage 223. Alternatively, gm stage 223 is turned off temporarily during stage 2 to save power, and / or disconnected from terminals 205p, 205m via a switch (not shown). The analog input value VRES is applied to the AZ amplifier circuit 220 at input terminals 201p, 201m. The analog input value is provided to amplifier circuit 221 at terminals 203p, 203m via switches 215p, 215m that are closed during stage 2.

[0015] The operation of AZ amplifier circuit 220 is as follows. In stage 1, the negative feedback operation regulates the auxiliary voltage such that when the auxiliary voltage is sampled on capacitor 209, the combined offset and amplification of the auxiliary voltage is substantially zero at or near the end of stage 1. The amplified contribution from the sampled auxiliary voltage can be substantially equal and opposite to the amplified contribution from the offset. The sampled auxiliary voltage is the first observed value of the amplified offset.

[0016] In stage 2, amplifier circuit 221 amplifies the combination of input VRES, offset, and the sampled auxiliary voltage. The amplified combination is observed and output at terminals 205p, 205m. The contribution of the offset to the amplified combination can be substantially equal and opposite to the contribution of the sampled auxiliary voltage to the amplified combination, and these two contributions can substantially cancel each other out at terminals 205p, 205m. This is an auto-zero operation. Thus, the amplified combination observed and output at terminals 205p, 205m responds to VRES and substantially not to the offset of amplifier circuit 221. The sampled auxiliary voltage is the first observed value of the amplified offset, and it is combined with the second observed value of the amplified offset during stage 2.

[0017] Different types of auto-zero amplifiers are known in the prior art. A common characteristic is that they operate in multiple stages and apply a nominally zero voltage at the input during one of the multiple operating stages. Another common characteristic is that the observed values obtained during the multiple stages are combined to substantially cancel the potential non-zero offset.

[0018] An auto-zero amplifier can be configured to amplify the residual value in an analog-to-digital converter (ADC) circuit. Figure 3 A block diagram of an ADC 300 including a residual amplifier 320 is shown. In some examples, the residual amplifier 320 is Figure 2The AZ amplifier circuit 220 shown in. The ADC 300 receives the analog voltage VIN(t). The sample and hold (S / H) circuit 301 samples VIN(t) at the sampling time (t = T0) and outputs the held analog value VIN. The first quantizer (ADC1) 303 is configured to receive the analog value VIN and derive a first digital value (CODE1) representing VIN. The digital value CODE1 is a relatively low-resolution digital representation of VIN. For example, CODE1 can be a 5-bit digital representation of VIN. As a step of a method for deriving a higher-resolution and more accurate digital representation of VIN, the ADC 300 derives and processes the residue of VIN relative to CODE1. Specifically, the digital-to-analog converter (DAC) 305 derives an analog representation of CODE1, and the difference between VIN and the analog representation of CODE1 is the residue value VRES. The residue value VRES is amplified by the residue amplifier 320, and the second quantizer (ADC2) 330 is configured to derive a digital representation CODE2 of the residue value VRES considering the gain factor A provided by the residue amplifier 320. The combination of CODE1 and CODE2 is a high-resolution accurate representation of VIN.

[0019] The accuracy that the ADC 300 can achieve can basically depend on the accuracy achieved by the DAC 305 and the residue amplifier 320. For comparison, the accuracy of the ADC1 303 may be relatively less important, provided that CODE2 is an accurate representation of the residue value VRES. The accuracy required by the ADC2 330 is less than the overall accuracy provided by the ADC 300, provided that the absolute value of the gain factor A of the residue amplifier 320 is greater than 1. The upper limit of the gain factor A depends on the resolution and accuracy of CODE1 representing VIN. For example, if CODE1 has a 5-bit resolution and the accuracy does not cause the residue amplifier 320 and / or the ADC2 330 to be overloaded / saturated, the gain factor A = 16 is used.

[0020] For clarity, the ADC1 and / or the ADC2 can be referred to as "quantizer" instead of ADC. PHOSITA recognizes that Figure 3 the ADC2 330 in can be implemented in an overall recursive structure as Figure 3 the ADC 300. The so-called pipelined ADC is a well-known example of the ADC 300, where the ADC2 330 is a cascade of several similar stages.

[0021] Figure 3The block diagram representation of the ADC 300 in [the context] includes any one of several types of analog-to-digital converters that include a residue amplifier 320. For example, the ADC 300 can be a so-called hybrid SAR ADC, where CODE1 is at least partially derived by using a successive approximation type algorithm (PHOSITA recognizes that SAR ADC stands for "successive approximation register analog-to-digital converter". PHOSITA is familiar with the design and operation of SAR ADCs). In another example, CODE1 is derived from a flash type ADC1 303 configured to receive VIN. In other examples, CODE1 is provided by a flash or other type of ADC configured to receive VIN(t), and the operation (e.g., the operation of sampling VIN(t)) is synchronized with the operation of the S / H circuit 301. In still other examples, Figure 3 the ADC1 303 in [the context] is a SAR quantizer, a hybrid SAR quantizer, a VCO-based quantizer, a two-step quantizer, a multi-step quantizer, or a pipelined quantizer that provides a digital value CODE1, which is a relatively high-resolution representation of VIN (such as, CODE1 may have a resolution of 10 bits or higher). Thus, Figure 3 the ADC1 303 in [the context] is a representation of a certain type of circuit or a certain type of method that provides a digital representation CODE1 of VIN. The ADC 300 derives an analog residue value VRES as the difference between the analog representation of the digital value CODE1 and the analog value VIN. In one example, a capacitive digital-to-analog converter (CDAC) circuit receives the analog value VIN and the digital value CODE1, and generates the analog residue value VRES based on the analog value VIN and the digital value CODE1. One term could be that VRES is the residue of VIN with respect to CODE 1, or equivalently (changing the polarity) VRES is the residue of CODE 1 with respect to VIN. The magnitude and other properties of the residue VRES depend on how CODE1 is derived to represent VIN, specifically including (but not limited to) the resolution and accuracy of CODE1.

[0022] The accuracy achievable by the ADC 300 depends substantially on the accuracy achievable by the DAC 305 and the residue amplifier 320. Some methods include deriving VIN by sampling a combination of the analog input value VIN(t) and an analog dither value. These methods can generalize the operations of the S / H circuit 301 and the DAC 305, which are combined via a capacitive digital-to-analog converter (CDAC) circuit. In another method, a high-resolution digital value CODE1 that allows a high gain factor A of the residue amplifier 320 is derived (if needed). Thus, many variants of the ADC circuit can be configured to incorporate the low-offset residue amplifier circuit described herein.

[0023] Figure 4 is shown corresponding to Figure 3Example ADC 400 of a block diagram. It is a differential ADC 400 that receives the analog input voltage difference VIN(t) = Vp(t) - Vm(t) at input terminals 401p and 401m. During the acquisition phase ( Figure 4 marked as Φ0 in Figure 4 ), switches 403p, 403m, 405p, 405m are closed, and the analog input voltage is applied to capacitor arrays 407p, 407m. At the sampling moment (t = T0) at the end or near the end of the acquisition phase, sampling switches 405p, 405m are opened to isolate the differential charge amounts at nodes 409p, 409m. Input switches 403p, 403m are opened after a short delay (such as 200 picoseconds) after the sampling moment. Capacitor arrays 407p, 407m are part of a CDAC structure. A PHOSITA is familiar with the CDAC structure. Capacitor array 407p has a shared terminal connected to terminal 409p and multiple N1 terminals connected to input switch 403p (compared with Figure 2 U.S. Patent 8,810,443). Thus, input switch 403p can be a switch array with a shared terminal connected to input terminal 401p and multiple N1 terminals connected to capacitor array 407p. The same applies to 407m, 409m, 403m, and 401m.

[0024] Figure 4 Part Figure 4 shows a first quantizer ADC1 implemented as a pair of quantizers ADC1p 411p and ADC1m 411m, which are configured to separately process each of the voltages Vp(t) and Vm(t) applied at input terminals 401p, 401m (each voltage is observed relative to a predetermined potential such as ground or 0V). When sampling switches 405p, 405m are opened, quantizers 411p and 411m sample Vp(t) and Vm(t) at the sampling moment (t = T0). Thus, the positive input digital value CODE1p represents the value Vp(T0) of Vp(t) at the sampling moment, and the negative input digital value CODE1m represents the value Vm(T0) of Vm(t) at the sampling moment. The positive and negative digital values CODE1 = CODE1p - CODE1m represent the analog input value VIN = Vp(T0) - Vm(T0) at the sampling moment. In another embodiment, a single differential quantizer ADC1 is configured to provide the digital value CODE1 to represent VIN = Vp(T0) - Vm(T0) without having to separately process each input Vp(t) and Vm(t).

[0025] The digital value CODE1p applied via switches 413p, 415p causes the analog value (e.g., voltage) at terminal 409p to be the residual VRESp of Vp(T0) relative to CODE1p. Similarly, CODE1m is applied via switches 413m, 415m such that the analog value (e.g., voltage) at terminal 409m is the residual VRESm ofVm(T0) relative to CODE1m. Switches 413p, 413m connect each capacitor in capacitor arrays 407p, 407m to the first / high reference potential VH in response to respective bits of CODE1p and CODE1m. Similarly, switches 415p, 415m connect each capacitor in capacitor arrays 407p, 407m to the second / low reference potential VL in response to respective bits of CODE1p and CODE1m. The capacitors in capacitor array 407p or capacitor array 407m are connected to VH or VL in response to the bits of CODE1p or CODE1m. The term capacitive digital-to-analog converter (CDAC) can be used to describe capacitor arrays 407p, 407m and the associated switches and reference potentials.

[0026] Accordingly, an analog value is sampled on the CDAC (e.g., Vp(T0) is sampled on one or more capacitors in capacitor array 407p via switches 403p and 405p); a digital value is applied to the CDAC (e.g., the reference potentials VH or VL to which switches 413p, 415p selectively connect the respective capacitors of capacitor array 407p in response to CODE1p); and the CDAC provides an analog value that is the residual of the sampled analog value relative to the digital code (e.g., the potential / voltage at node 409p is the residual VRESp of Vp(T0) relative to CODE1p).

[0027] The residue amplifier 420 is configured to receive a residue value VRES = VRESp - VRESm (e.g., the voltage between nodes 409p and 409m), which represents the residue of the analog value VIN = Vp(T0) - Vm(T0) relative to the digital value CODE1 = CODE1p - CODE1m. The residue amplifier 420 provides an amplified residue value A∙VRES that is processed by the quantizer circuit ADC2 430. The ADC2 430 is configured to provide a digital value CODE2 that represents the residue VRES of VIN = Vp(T0) - Vm(T0) relative to CODE1 = CODE1p - CODE1m, taking into account the gain factor A provided by the residue amplifier 420. The digital circuit 440 combines CODE1p, CODE1m, and CODE2 to provide a digital output code DOUT, which can be a high-resolution representation of VIN = Vp(T0) - Vm(T0). For example, the ADC 400 provides an output code DOUT with a resolution of 20 bits or 24 bits. To achieve high precision, the digital circuit 440 optionally receives and processes calibration information. The calibration information includes a plurality of codes representing the capacitance ratios of the capacitors in the capacitor arrays 407p, 407m. The calibration information is obtained / measured as part of the manufacturing process and stored in a memory device (not shown). The accuracy achievable by the ADC 400 is substantially limited by the offset and noise levels of the residue amplifier 420. Conventional AZ residue amplifiers (e.g., Figure 2 the AZ amplifier circuit 220) can provide good offset stability, but the noise level is relatively high / poor. In contrast, non-auto-zero residue amplifiers can provide relatively low / good noise and power operation, but their offset stability may be relatively poor. SUMMARY OF THE INVENTION

[0028] Examples of some analog-to-digital converters (ADCs) are disclosed herein that can perform auto-zeroing by amplifying a signal to improve the signal-to-noise ratio. The ADC can generate a first digital code representing an analog input signal and a second digital code based on a residue from the first digital code, and can combine the first digital code and the second digital code to generate a digital output code representing the analog input signal. The ADC can utilize a first observation value and a second observation value of an analog residue value representing the residue to generate the second digital code.

[0029] Some embodiments disclosed herein may include an analog-to-digital converter (ADC) circuit that includes a sample quantization residue generation (SQRG) circuit, an auto-zero residue amplification circuit, a quantizer circuit, and a digital circuit. The sample quantization residue generation (SQRG) circuit may generate a first digital code based at least in part on an analog input value received by the ADC circuit and may generate an analog residue value based at least in part on the first digital code and the analog input value. The auto-zero residue amplification circuit may amplify the analog residue value to produce a first observation of the amplified analog residue value; and may produce a second observation of the amplified analog residue value. The quantizer circuit may produce a second digital code that represents at least a combination of the first observation and the second observation. The digital circuit is configured to produce a digital output code that represents the analog input value, wherein the first digital code and the second digital code are combined to produce the digital output code.

[0030] Some embodiments disclosed herein may include an auto-zero residue amplification circuit for offset cancellation, the auto-zero residue amplification circuit including an amplification circuit and one or more switches. The amplification circuit is configured to amplify a first observation of an analog residue value and a second observation of the analog residue value received by the auto-zero residue amplification circuit, the analog residue value being a residue of a digital code generated by an analog-to-digital conversion of an analog input value, wherein the amplified first observation and the amplified second observation will be used together with the digital code to produce a digital output code that represents the analog input value. The one or more switches are coupled between the amplification circuit and an input of the auto-zero residue amplification circuit, the analog residue value being received via the input of the auto-zero residue amplification circuit, wherein the one or more switches will selectively apply the first observation and the second observation to the amplification circuit.

[0031] The auto-zero residue amplifier may be configured to operate in two phases, wherein an input residue value may be amplified and observed in two phases. Similar to a conventional auto-zero amplifier, the two observations may be combined to substantially cancel a potential non-zero offset of the active circuit configured to provide amplification. It may be advantageous to space the two observations closely in time. However, unlike a conventional auto-zero amplifier, both observations include an amplified residue value. Accordingly, the combined observation of the amplified residue values includes a relatively high signal level (residue value) compared to the noise level. The noise level may be normalized by the signal level, and the relative noise level may be substantially lower than the noise level of a conventional auto-zero residue amplifier circuit. The relatively low noise level facilitates an ADC with substantially reduced noise and power operation, which is a significant improvement. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The present disclosure can be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industrial standard practice, the various features are not drawn to scale and are for illustrative purposes only. Where scale is explicitly or implicitly shown, it provides only an illustrative example. In other embodiments, for the sake of clarity of discussion, the dimensions of the various features may be increased or decreased arbitrarily.

[0033] Figure 1 An AZ amplifier circuit of the prior art is shown.

[0034] Figure 2 Another type of prior art AZ amplifier circuit is shown.

[0035] Figure 3 A block diagram of an ADC including a residue amplifier is shown.

[0036] Figure 4 An example ADC corresponding to the Figure 3 block diagram is shown.

[0037] Figure 5 A first example embodiment of an ADC circuit including an auto-zero residue amplifier circuit according to various embodiments is shown.

[0038] Figure 6 An example quantizer ADC2 that can be used to replace ADC2 in Figure 5 according to various embodiments is shown.

[0039] Figure 7A Another example embodiment of an ADC circuit according to various embodiments is shown.

[0040] Figure 7B An example timing diagram of an ADC circuit according to various embodiments of Figure 7A is shown.

[0041] Figure 7C An example ADC circuit including a modified AZ residue amplifier circuit according to various embodiments is shown.

[0042] Figure 7D Another example embodiment of an ADC circuit according to various embodiments, including a modified AZ residue amplifier circuit, is shown. Detailed Description

[0043] Numerous different embodiments or examples are provided below for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples or sometimes in different figures. This repetition is for simplicity and clarity purposes and does not itself specify a particular relationship between the various embodiments and / or configurations discussed. Different embodiments may have different advantages, and no particular advantage is required for any embodiment.

[0044] Figure 5 An example first embodiment of an ADC circuit 500 including an auto - zero residue amplifier circuit 520 in accordance with the present teachings is shown. A sample - quantization residue generation circuit (SQRG circuit) 510 may be implemented, where the SQRG circuit 510 may include Figure 4 one or more features of the SQRG circuit 410. The function of the SQRG circuit may be similar to Figure 3 the function of the ADC 300 portion indicated by 310 in Figure 5 The terminals 501p and 501m in Figure 4 may respectively correspond to the terminals 401p and 401m in Figure 4 . Additionally, the terminals 509p and 509m may respectively correspond to the terminals 409p and 409m. Thus, the SQRG circuit 510 may provide an analog residue value VRES that represents the residue of the analog input value VIN = Vp(T0)-Vm(T0) relative to the first digital value CODE1 = CODE1p - CODE1m, where T0 is a specific time at which the sample is generated. For example, the SQRG circuit 510 may receive the analog input value VIN via the terminals 501p and 501m, where in the illustrated embodiment, the analog input value VIN includes a differential voltage, and where the voltage provided via the terminal 501p may include the positive component of the differential voltage, and the voltage provided via the terminal 501m may include the negative component of the differential voltage. The SQRG circuit 510 may include an ADC1 (such as ADC1 303 ( Figure 3 )) that generates a first digital value CODE1 based on the analog input value VIN. In the illustrated embodiment, the first digital value CODE1 may be represented by a positive digital component value CODE1p that represents the positive component of the differential voltage of the input value VIN and a negative digital component value CODE1m that represents the negative component of the differential voltage of the analog input value VIN. The SQRG circuit 510 may output the first digital value CODE1. In the illustrated embodiment, the first digital value CODE1 output by the SQRG circuit 510 may include the positive digital component value CODE1p and the negative digital component value CODE1m.

[0045] The SQRG circuit 510 may further include a DAC (such as DAC 305 ( Figure 3 )) for generating an analog representation of a first digital value CODE1. For example, the DAC may receive the first digital value CODE1 from the ADC1 and generate an analog representation of the first digital value CODE1. In the illustrated embodiment, where the first digital value CODE1 is represented by a positive digital component value CODE1p and a negative digital component value CODE1m, the DAC may receive the positive digital component value CODE1p and the negative digital component value CODE1m and may generate an analog representation of the positive digital component value CODE1p and an analog representation of the negative digital component value CODE1m to form an analog representation of the first digital value CODE1.

[0046] The SQRG circuit 510 may further include a subtractor circuitry (such as subtractor circuitry 308 ( Figure 3 )) to generate a residual value VRES between the analog input value VIN and the analog representation of the first digital value CODE1. Specifically, the subtractor circuitry 308 may receive the analog input value VIN and the analog representation of the first digital value CODE1 and generate the residual value VRES from the analog input value VIN and the analog representation of the first digital value CODE1. The residual value VRES may be output by the SQRG circuit 510. In the illustrated embodiment, the residual value VRES may be output as a positive analog component value at terminal 509p and as a negative analog component value at terminal 509m, where the positive analog component value and the negative analog component value form a differential representation of the residual value VRES. The residual value VRES may be provided by the SQRG circuit 510 to the auto-zero residual amplifier circuit 520 of the ADC circuit 500. In another embodiment, the digital value CODE1 may be provided as a single code rather than a pair of codes (CODE1p, CODE1m). In another embodiment, VRES may be a residual of CODE1 relative to a combination of the analog input value Vp(T0)-Vm(T0) and a dither value. Depending on a set of design objectives, the resolution of CODE1 may be relatively low (such as 5 bits or less), medium, or relatively high (such as 10 bits or more).

[0047] The auto-zeroing residual amplifier circuit 520 can operate in two phases (phase 2 and phase 3). The illustrated auto-zeroing residual amplifier circuit 520 includes indications of which switches are closed in which phase, where the switch with the Φ2 mark above it is closed in phase 2 and open in phase 3, and where the switch with the Φ3 mark above it is closed in phase 3 and open in phase 2. For example, switches 503p and 503m can be closed in phase 2 and open in phase 3. Switches 505p and 505m can be open in phase 2 and closed in phase 3. Phase 2 can occur during a first time period, and phase 3 can occur during a second time period, where the first time period and the second time period may not overlap in time. Phase 2 and phase 3 can be repeated periodically or aperiodically.

[0048] The active circuit configured to provide the amplifier circuit 521 can receive an analog residual value of a first polarity (such as +VRES) as an input during phase 2. For example, during phase 2, switches 503p and 503m can be closed, while switches 505p and 505m can be open. Switches 503p and 503m can couple the SQRG circuit 510 to the amplifier circuit 521. The SQRG circuit 510 can provide the analog residual value VRES to the amplifier circuit 521 via switches 503p and 503m, where the positive analog component value of the analog residual value VRES is provided to the first input of the amplifier circuit 521 via switch 503p, and the negative analog component value of the analog residual value VRES is provided to the second input of the amplifier circuit 521 via switch 503m. Additionally, during phase 3, the active circuit can receive an analog residual value of a second polarity opposite to the first polarity as an input (such as -VRES). For example, during phase 3, switches 505p and 505m can be closed, while switches 503p and 503m can be open. Switches 505p and 505m can couple the SQRG circuit 510 to the amplifier circuit 521. The SQRG circuit 510 can provide the analog residual value VRES to the amplifier circuit 521 via switches 505p and 505m, where the positive analog component value of the analog residual value VRES is provided to the second input of the amplifier circuit 521 via switch 505m, and the negative analog component value of the analog residual value VRES is provided to the first input of the amplifier circuit 521 via switch 505p.

[0049] The amplifier circuit 521 can generate a first amplified combination A∙(OS + VRES) of the residual value VRES and the potential non-zero offset OS during stage 2, and the amplifier circuit 521 can generate its second amplified combination A∙(OS - VRES) during stage 3. For example, the amplifier circuit 521 can provide the first amplified combination A∙(OS + VRES) to the ADC2 530 at or near the end of stage 2, and the amplifier circuit 521 can provide the second amplified combination A∙(OS - VRES) to the ADC2 530 at or near the end of stage 3. In this embodiment, the AZ amplifier circuit 520 itself does not combine the two amplified combinations A∙(OS + VRES) and A∙(OS - VRES).

[0050] The two amplified combinations are available / observable at two different stages (stage 2 and stage 3) of the operation but not simultaneously. For example, the first amplified combination A∙(OS + VRES) can be available / observable at or near the end of stage 2 at the output of the amplifier circuit 521, and the second amplified combination A∙(OS - VRES) can be available / observable at or near the end of stage 3 at the output of the amplifier circuit 521. The ADC2 530 can observe the first combination A∙(OS + VRES) at or near the end of stage 2, and the ADC2 530 can generate a digital value CODE2p to represent A∙(OS + VRES). The ADC2 530 can further observe the second combination A∙(OS - VRES) at or near the end of stage 3, and it can generate a digital value CODE2m to represent A∙(OS - VRES). The ADC2 530 can provide the positive digital component value CODE2p and the negative digital component value CODE2m at different times in the order corresponding to when the ADC2 530 observes each digital value.

[0051] The ADC circuit 500 can combinatorially amplify the remaining two observed values. In the illustrated embodiment, the digital circuit 540 can be coupled to the ADC2 530 at the output of the ADC2 530 and can receive the positive digital component value CODE2p and the negative digital component value CODE2m from the ADC2 530. The two observed values that can be individually quantized by the ADC2 530 (represented by the positive digital component value CODE2p and the negative digital component value CODE2m generated by the ADC2 530) can be digitally combined by the digital circuit 540 configured to calculate the digital value CODE2 = CODE2p - CODE2m. When CODE2p and CODE2m are combined by subtraction, the potential non-zero offset OS of the amplifier circuit 521 can be substantially canceled in CODE2. This may be an auto-zero operation. CODE2 can represent the amplified analog residual value 2∙A∙VRES, or can be scaled by the nominal amplification factor 2∙A to represent VRES. By canceling the potential non-zero offset OS and amplifying the analog residual value VRES, the auto-zero residual amplifier circuit 520 can produce an improved signal-to-noise ratio representation of the analog residual value VRES compared to a conventional ADC with auto-zero, while maintaining or reducing the power consumption of the ADC 500. Compared to a conventional ADC, this can result in an improvement in ADC operation and / or a reduction in ADC power consumption.

[0052] The digital circuit 540 can be configured to derive a high-resolution representation DOUT of the analog input value VIN = Vp(T0) - Vm(T0) by calculating DOUT = CODE1p - CODE1m + (CODE2p - CODE2m) / (2∙A). In another embodiment, the digital circuit 540 can be configured to calculate DOUT = CODE1p - CODE1m + CODE2p - CODE2m. For example, the digital circuit 540 can be coupled to the SQRG circuit 510 and can receive a first digital code CODE1 representing the analog signal VIN from the SQRG circuit 510. The digital circuit 540 can be further coupled to the ADC2 530 and can receive the digital value CODE2 from the ADC2 530. In the illustrated embodiment, where the first digital code CODE1 and the digital value CODE2 are represented differentially, the digital circuit 540 can receive the positive digital component value CODE1p and the negative digital component value CODE1m to represent the first digital code CODE1, and can receive the positive digital component value CODE2p and the negative digital component value CODE2m representing the digital value CODE2. The digital circuit system can generate an output code DOUT of the analog input value VIN by calculating either equation for the output code DOUT. The output code DOUT can also respond to calibration information. The calibration information can include codes representing potential mismatches of the amplification factor A of the SQRG circuit 510 and / or ADC2 530 and / or potential mismatches of parameters. The calibration information can be derived during the production process (e.g., production testing), or it can be derived during operation by foreground and / or background calibration processes, while the ADC circuit 500 can be deployed for applications (e.g., factory automation).

[0053] In another embodiment, the ADC2 530 can be implemented as two separate quantizers. A first quantizer ADC2p (not shown) can observe A∙(OS + VRES) at or near the end of stage 2 and provide a digital value CODE2p to represent A∙(OS + VRES). Another quantizer ADC2m (not shown) can observe A∙(OS - VRES) at or near the end of stage 3 and provide a digital value CODE2m to represent A∙(OS - VRES). CODE1p, CODE1m, CODE2p, CODE2m can be combined as described above. One potential advantage of implementing the ADC2 using two separate quantizers is that the two observed values may be spaced closer in time. This can improve the suppression of low-frequency noise from the amplification circuit 521.

[0054] The advantages of the AZ residue amplification circuit 520 may be easily overlooked. The two observed values available for deriving CODE2 both represent the amplified residue value (A･VRES) and the amplified offset (A･OS). Compare this with the operation of a conventional AZ amplifier (e.g., asFigure 1 and 2 as shown), where only one of the two observations includes an amplified residual value (A·VRES), and both observations include an amplified offset (A·OS). Compared with a conventional AZ amplifier, the payload signal content (VRES) of the AZ amplifier circuit 520 can be substantially higher (better). Each observation may be affected in part by broadband noise from active circuits configured for amplification ( Figure 5 amplifier circuit 521 in; Figure 1 amplifier circuit 121 in; Figure 2 amplifier circuit 221 in). For the ADC circuit 500, when the amplified residual value VRES is as shown in Figure 5 , the signal-to-noise ratio (residual noise ratio) may be better. Compared with a conventional AZ residual amplifier circuit ( Figure 1 120 in; Figure 2 220 in), for a given noise specification, the improved signal-to-noise ratio can significantly reduce the power consumption of the AZ residual amplifier circuit 520 (such as nearly 4 times). Therefore, in one embodiment, the present teachings help to significantly reduce the power consumption of a precision ADC. In another embodiment, the present teachings help to significantly improve the signal-to-noise ratio of a precision ADC for a given power budget (such as 20 mW).

[0055] Figure 6 shows an example quantizer ADC2 630 that can be used in place of Figure 5 ADC2 530 in. ADC2 630 can combine the two observations in the analog domain, and it can perform a single analog-to-digital (A / D) conversion operation to derive a digital value CODE2 to represent the combination of the two observations. Thus, when implemented in place of ADC2 530 in the ADC circuit 500, ADC2 630 can receive amplified combinations (such as a first amplified combination A·(OS + VRES) and a second amplified combination A·(OS - VRES)) and can output a digital value CODE2 representing the combination of the amplified combinations.

[0056] ADC2 630 can be a fully differential structure including a positive-side CDAC 601p and a negative-side CDAC 601m. The first observation can consist of an amplified analog residual value, such as A·(OS + VRES), provided to ADC2630 by Figure 5 the AZ residual amplifier circuit 520 in. When the sampling switches 625p and 625m are opened at or near the end of phase 2, the first observation is sampled on capacitors 623p and 623m at or near the end of phase 2 (where the switches that are closed during phase 2 are marked with Φ2 in Figure 6 and can be associated with Figure 5be consistent with Φ2 in ). The connection switch 627p and the connection switch 627m can be turned on after a delay (e.g., 200 ps) after the sampling switches 625p and 625m are turned on.

[0057] The second observation value can be composed of an amplified analog residual value, such as A･(OS-VRES), provided to the ADC2 630 by Figure 5 the AZ residual amplifier 520 in. When the sampling switches 635p and 635m are turned on at the end or near the end of stage 3, the second observation value can be sampled on the capacitors 633p and 633m at the end or near the end of stage 3 (where the switches to be closed in stage 3 are Figure 6 marked as Φ3 in and can be consistent with Figure 5 Φ3 in ). Compared with the first observation value, the sampling polarity of the second observation value can be opposite to the polarities of the positive-side CDAC 601p and the negative-side CDAC 601m. Specifically, the amplified analog residual values of the first observation value and the second observation value can each be represented by a differential voltage. Closing the switches 627p and 627m during stage 2 may cause the positive component of the differential voltage of the first observation value to be sampled on the capacitor 623p of the positive-side CDAC 601p, and the negative component of the differential voltage of the first observation value to be sampled on the capacitor 623m of the negative-side CDAC 601m. Closing the switches 637p and 637m during stage 3 may cause the negative component of the differential voltage of the second observation value to be sampled on the capacitor 633p of the positive-side CDAC 601p, and the positive component of the differential voltage of the second observation value to be sampled on the capacitor 633m of the negative-side CDAC 601m. Therefore, the polarities of the first observation value and the second observation value may be opposite to the polarities of the positive-side CDAC 601p and the negative-side CDAC 601m because the positive and negative components of the differential voltage of the observation values are swapped between the positive-side CDAC 601p and the negative-side CDAC 601m between stage 2 and stage 3. The connection switch 637p and the connection switch 637m can be turned on after a delay (such as 200 ps) after the sampling switches 635p and 635m are turned on. The ADC2 630 can perform a SAR-type ADC conversion operation during stage 4 after stage 2 and stage 3 ( Figure 6 the switches to be closed during stage 4 in are marked as Φ4).

[0058] Phases 2, 3, and 4 may not overlap in time, and they may be repeated periodically or aperiodically. For example, Phase 2 may occur during a first time period, Phase 3 may occur during a second time period after the first time period, and Phase 4 may occur during a third time period after the second time period. In some embodiments, the order of the time periods of Phase 2 and Phase 3 may be swapped such that the first time period in which Phase 2 occurs is after the second time period in which Phase 3 occurs. The aperiodic operation may randomly select the sequence of Phase 2 and Phase 3 substantially before Phase 4 (i.e., in one conversion cycle, the phase sequence may be 0, 1, 2, 3, 4, and in another conversion cycle, the phase sequence may be 0, 1, 3, 2, 4). The exemplary embodiment may operate with a periodic phase sequence (0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1...).

[0059] Switches 641p and 643p may be closed during Phase 4, whereby the first and second observed values sampled on capacitors 623p and 633p during Phases 2 and 3 may be combined through a charge sharing operation; the combined value may be represented by the charge value at node 603p. Since the polarities of the first and second observed values applied to the positive-side CDAC 601p are opposite, the combination through the charge sharing operation may result in the combination of the positive component of the differential voltage of the first observed value sampled on capacitor 623p and the negative component of the differential voltage of the second observed value sampled on capacitor 633p. The charge value at node 603p may further include the charge value sampled on segment 605p of CDAC 601p at or near the end of Phase 3. The charge value sampled on CDAC segment 605p may be a fixed value. In another embodiment, it may be a dither value.

[0060] As described, the negative-side CDAC 601m may operate in a manner similar to the positive-side CDAC 601p. Specifically, switches 641m and 643m may be closed during Phase 4, whereby the observed values sampled on capacitors 623m and 633m during Phases 2 and 3 may be combined through a charge sharing operation and represented by the charge value at node 603m. Since the polarities of the first and second observed values applied to the negative-side CDAC 601m are opposite, the combination through the charge sharing operation may result in the combination of the negative component of the differential voltage of the first observed value sampled on capacitor 623m and the positive component of the differential voltage of the second observed value sampled on capacitor 633m. The charge at node 603m may further include the charge value sampled on segment 605m of CDAC 601m at or near the end of Phase 3. The charge value sampled on CDAC segment 605m may be a fixed value. In another embodiment, it may be a dither value.

[0061] A PHOSITA recognizes that a digital state machine 607, which may be referred to as a SAR (successive approximation register), can be configured to provide a successive approximation sequence of codes to continuously reduce the uncertainty range of the difference observed by a comparison circuit 609. The comparison circuit 609 can direct the SAR 607 to select a single code in the successive approximation sequence of codes. The resulting code provided by the SAR 607 can be a digital value CODE2 that represents a combination of two observed values. Specifically, CODE2 can represent a residual value VRES. The contribution of a potential non-zero offset OS of a circuit configured to provide amplification can be substantially canceled in CODE2 because the contribution from the first observed value can be equal and opposite to the contribution from the second observed value. For example, swapping the polarities of the first observed value and the second observed value with respect to the positive-side CDAC 601p and the negative-side CDAC 601m may result in a differential voltage in which one observed value is treated as negative with respect to the other. For the sake of understanding, it can be considered that the positive component of the differential voltage of the first observed value is applied to the positive-side CDAC 601p, and the negative component of the differential voltage of the first observed value is applied to the negative-side CDAC 601m, resulting in the first observed value being positive, e.g., A･(OS + VRES). The positive component of the differential voltage of the second observed value is applied to the negative-side CDAC 601m, and the negative component of the differential voltage of the second observed value is applied to the positive-side CDAC 601p, resulting in the second observed value being negative, e.g., -(A･(OS - VRES)). The combination of the first observed value and the second observed value can result in the positive first observed value and the negative second observed value being added together, resulting in a value in which the offset OS is substantially canceled and the amplified residual value A･VRES is substantially doubled. For example, the combination of the positive first observed value and the negative second observed value may produce a value of 2･A･VRES. The switches 611p (i.e., the switches located within the dashed rectangle 611p) and the switches 611m (i.e., the switches located within the dashed rectangle 611m) can connect individual capacitors in the CDAC 601p and the CDAC 601m to a high reference potential VH or a low reference potential VL in response to the states of the respective bits of each code in the successive approximation sequence of codes. A PHOSITA recognizes that the operation of the switch 611p can compensate for the operation of the switch 611m in the fully differential ADC2 630. The description herein of how the CDAC 601p operates should also be equivalent to the description of how the CDAC 601m operates.

[0062] The switches 611p for driving capacitors 623p and 633p can be controlled by a single bit of each code in the code successive approximation sequence. Thus, with respect to the code successive approximation sequence, capacitors 623p and 633p can be switched as a single capacitor (C / 4 + C / 4), and the nominal size (capacitance) of said capacitor is twice the size (capacitance) of the largest capacitor (C / 4) in the CDAC segment 605p. In one embodiment, the nominal weight factors of the respective bits in the CDAC 601p that can be switched during the SAR ADC operation mode can be scaled in binary proportion (e.g., having weight factors: 1 / 2, 1 / 4, 1 / 8, 1 / 16...). In another embodiment, the nominal weight factors of the respective bits in the modified CDAC (not shown) can include redundancy (e.g., having weight factors: 1 / 2, 1 / 4, 1 / 8, 1 / 8, 1 / 16, 1 / 32, 1 / 64, 1 / 64, 1 / 128...). The resolution of the ADC2 630 can be relatively low (such as 5 bits or less), medium, or relatively high (such as 10 bits or more).

[0063] PHOSITA recognizes that the ADC2 630 can be modified to incorporate any type of A / D conversion principle (including but not limited to SAR ADC, pipelined ADC, VCO-based ADC, flash ADC, cyclic ADC, interpolation ADC, hybrid ADC, etc.). The ADC2 630 can be configured to sample and convert a combination of multiple analog values. In some embodiments, an ADC can be implemented that can be configured to sample and convert a combination of an analog input value and a dither value (i.e., multiple two analog values). The two analog values can be sampled on separate segments of the CDAC. Figure 6 The ADC2 630 can be configured to sample and convert a combination of a first analog value (such as, A･(OS + VRES)), a second analog value (such as, A･(OS - VRES)), and a third analog value (such as a fixed value or a dither value applied via the switches 611p and 611m). Thus, the ADC2 630 can be configured to sample and convert a combination of multiple three analog values. Multiple analog values can be sampled on multiple segments of the CDAC 601p (e.g., capacitors 623p, capacitors 633p, and the CDAC segment 605p). Each segment can contain one or more capacitors, which can be switched individually or jointly during the A / D conversion operation mode. Multiple analog values can be sampled individually on separate segments of the CDAC at multiple nominally different sampling moments (e.g., at or near the end of phase 2 and at or near the end of phase 3). The respective segments of the CDAC configured to sample multiple analog values can be combined before or as part of the analog-to-digital conversion operation (e.g., the switches 641p and 643p can be closed in phase 4). Figure 6The switches 643p, 643m, 635p, and 635m may nominally be redundant or superfluous, but they can be included to mitigate secondary artifacts such as switched charge injection familiar to the PHOSITA. The PHOSITA is also familiar with many types of circuits and methods for A / D converting analog values represented as the amount of charge isolated at a node of the CDAC (e.g., node 603p), i.e., after sampling it as described herein. Thus, no further description of how to construct and operate the comparator circuit 609, the SAR circuit 607, and / or the switches 611p and 611m is needed herein.

[0064] In another embodiment, Figure 6 the ADC2 630 may be configured to provide an A / D conversion operation in which the switches 611p and 611m may connect the capacitors 623p, 633p, 623m, and 633m to a set of predefined potentials (such as, they may all be connected to VH) during phase 4, regardless of any bit of any code in the successive approximation code sequence provided by the SAR 607. Thus, the CDAC segment 605p may be configured to sample multiple input values (such as, A･(OS + VRES) and A･(OS - VRES)) on multiple segments of the CDAC (such as the first capacitor 623p and the second capacitor 633p), the segments being different from the CDAC segments (such as segment 605p) configured to apply codes via switches (such as switch 611p) during the A / D conversion operation in the successive approximation sequence.

[0065] In another embodiment, the switches 611p and 611m cannot drive the capacitors 623p, 633p, 623m, and 633m during phase 4 or at any time. Instead, during phase 4, Figure 6 the left terminals of the capacitors 623p, 633p, 623m, and 633m in Figure 6Four switches not shown are shorted to each other (and they may not be connected to any fixed potential). During stage 4, the purpose of nominally shorting and floating the four terminals may be to suppress the common-mode components of the first observation and the second observation (such as A･(OS+VRES) and A･(OS-VRES)). CDAC segment 605p and CDAC segment 605m may be switched according to the successive approximation sequence provided by SAR 607. CDAC segment 605p and CDAC segment 605m may be scaled relative to capacitor 623p, capacitor 623m, capacitor 633p, and capacitor 633m to provide a CODE2 scaling ratio relative to the reference voltage difference (VH-VL) and the full-scale input range of ADC2 630. For example, the size of each capacitor in CDAC segment 605p and CDAC segment 605m may be reduced by a factor of 3 to compensate for a potential 3-fold reduction in the full-scale input range.

[0066] In another embodiment, quantizer ADC2 may be configured to sample and combine more than two (such as 3, 4, 5...) observations and derive a digital value CODE2 to represent a weighted combination of more than two observations. For example, capacitor 623p and capacitor 623m may each be divided into two half-size (C / 8) capacitors and be configured with switches to sample the analog values at 2 different time points (such as at or near the end of stage 2a and at or near the end of stage 2b). Quantizer ADC2 may be incorporated into a modified ADC circuit similar to Figure 5 the ADC circuit 500. The control circuit may provide switch control signals to provide a modified operation stage sequence: (stage 0, stage 1, stage 2a, stage 3, stage 2b, stage 4). Stage 2 may be an OR combination of stage 2a and stage 2b. Specifically, Figure 5The switches 503p and 503m of the AZ amplifier circuit 520 in can be closed in phase 2a and phase 2b. Thus, the AZ amplifier circuit 520 can be configured to provide amplified analog residual value sequences: A･(OS + VRES) during phase 2a; A･(OS - VRES) during phase 3; A･(OS + VRES) during phase 2b. The first value A･(OS + VRES) can be observed and sampled on the first half (C / 8) of capacitors 623p and 623m during phase 2a. The second value A･(OS - VRES) can be observed and sampled on (C / 4) of capacitors 633p and 633m during phase 3. The third value A･(OS + VRES) can be observed and sampled on the second half (C / 8) of capacitors 623p and 623m during phase 2b. The potential non - zero offset of the amplifier circuit 521 can be substantially cancelled in CODE2, which can represent a weighted combination of 3 sampled observations. Thus, the modified ADC circuit 500 that includes the quantizer ADC2 and operates with a modified phase sequence can be configured to provide auto - zero operation for the potential non - zero offset of the circuit 521, where the circuit 521 is configured to provide amplification. Compared with the prior - art ADC circuits, the modified ADC circuit 500 can provide improved robustness against secondary artifacts such as charge injection, and / or it can provide improved suppression of low - frequency noise. ADC2 can be configured to observe and combine any number (two or more) of amplified analog residual values. It can be configured to combine multiple observations with nominally uniform or non - uniform weights. The example embodiments described herein can be configured to apply nominally non - uniform weighting: [+0.25; - 0.50; +0.25]. The weighting factor (-0.50) may occupy significantly more weight (such as greater than 20% weight) than the other two weighting factors (+0.25; +0.25). The three weighting factors can represent the nominal weighting of the first observed amplified analog residual value, the second observed amplified analog residual value, and the third observed amplified analog residual value. In another embodiment, the first weighting factor can be substantially equal to the second weighting factor (such as, the absolute value of each of the two weighting factors can be within the range of ±5%, e.g., [-0.48; +0.52]).

[0067] Figure 7A FIG. 4 shows another example embodiment of an ADC circuit 700 in accordance with the present teachings. The ADC circuit 700 can have a structure similar to Figure 3 that of the ADC circuit 300. It can include a sample quantization residual generation (SQRG) circuit 710 (respectively associated with Figure 3 , Figure 4 and Figure 5compared with the SQRG circuits 310, 410, and 510), the auto-zeroing residual amplifier circuit 720 (compared with the residual amplifier circuit 320 and the amplifier circuit 420 in Figure 3 and Figure 4 respectively) and the quantizer circuit ADC2 730 (compared with the ADC2 330 and ADC2 430 in Figure 3 and Figure 4 respectively).

[0068] The amplified analog residual value can be the differential charge amount provided via the terminals 707p and 707m. The amplified analog residual value can be derived in part by combining the observed values of two (or more) amplified analog residual values to provide an auto-zeroing operation. The ADC2 730 can receive an analog value (e.g., differential charge amount) from the AZ residual amplifier circuit 720 and perform an A / D conversion operation to provide a digital value CODE2, which can represent the analog residual value VRES. The analog residual value VRES can be the voltage difference output by the SQRG circuit 710 at the terminals 709p and 709m. Therefore, the AZ residual amplifier circuit 720 can be configured to combine two (or more) observed values as part of an auto-zeroing operation and output a differential charge amount (i.e., analog value) to the ADC circuit 730.

[0069] Figure 7B shows Figure 7A an example timing diagram of the ADC circuit 700. The AZ residual amplifier circuit 720 can provide amplification by integrating the analog value within a predefined period TINT. The analog value can be derived from the residual value VRES, which is received from the SQRG circuit 710. The first observed value can be obtained during stage 2 ( Figure 7B labeled as Φ2 in

[0070] ), during which the transconductance circuit (GM circuit) 721 can receive the residual value VRES via the switches 703p and 703m and provide a differential output current GM·(VRES + OS). As shown, OS can be a potential non-zero offset of the circuit 721 configured to provide amplification, and GM can be the transconductance factor (i.e., voltage-current gain factor). The differential output current can be integrated on the capacitors 743p and 743m for a predetermined period TINT to accumulate a differential charge amount Q2 = TINT·GM·(VRES + OS) on the capacitors 743p and 743m. The differential charge amount Q2 can be the first observed value of the amplified analog residual value. In stage 3 ( Figure 7BA second observation value can be obtained during the period marked as Φ3 in the figure, where the GM circuit 721 can receive the residual value VRES via the switches 705p and 705m and provide a differential output current via the switches 715p and 715m. The residual value VRES of the second observation value received by the GM circuit 721 can have a polarity opposite to that of the residual value VRES of the first observation value. Specifically, the residual value VRES output by the SQRC circuit 710 can be a differential voltage. In stage 2, when the switches 703p and 703m are closed, the positive component of the residual voltage of the first observation value is provided to the first input of the GM circuit 721, and the negative component of the residual voltage of the first observation value is provided to the second input of the GM circuit 721. In stage 2, when the switches 705p and 705m are closed, the positive component of the residual voltage of the second observation value is provided to the second input of the GM circuit 721, and the negative component of the residual voltage of the second observation value is provided to the first input of the GM circuit 721, thereby having a polarity opposite to that of the residual voltage of the first observation value provided to the GM circuit 721. In addition, the polarity of the output of the GM circuit 721 can be opposite to the polarities of the first observation value and the second observation value. Specifically, for the first observation value, closing the switches 713p and 713m during stage 2 can cause the first output of the GM circuit 721 to be coupled to the capacitor 743p, and the second output of the GM circuit 721 to be coupled to the capacitor 743m. For the second observation value, closing the switches 715p and 715m during stage 3 may cause the first output of the GM circuit 721 to be coupled to the capacitor 745m, and the second output of the GM circuit 721 to be coupled to the capacitor 745p. Since the capacitor 743p and the capacitor 745p are used to generate the positive component when combining the observation values (as described below), and the capacitor 743m and the capacitor 745m are used to generate the negative component when combining the observation values, the polarity of the GM circuit 721 can be opposite to the polarity of the combination of the first observation value and the second observation value. The differential output current can be integrated on the capacitors 745p and 745m for a predefined period TINT to accumulate a differential charge amount Q3 = TINT･GM･(VRES - OS) on the capacitors 745p and 745m. The differential charge amount Q3 can be the second observation value that amplifies the analog residual value.

[0071] When the switches 723p, 723m, 725p, 725m, 753p, 753m, 755p and 755m can be closed, in stage 4 ( Figure 7A and Figure 7BAt the beginning (marked as Φ4), two (or more) observed values are combined. Charge sharing operations may occur between capacitor 743p and capacitor 745p, and between capacitor 743m and capacitor 745m, which combine the two (or more) observed values (e.g., Q2 and Q3). The combined observed values may be amplified analog residual values, which are represented by the charge quantity Q = Q2 + Q3 = 2･TINT･GM･VRES and can be obtained via terminal 707p and terminal 707m. Specifically, a zero voltage between terminal 707p and terminal 707m may indicate that during stage 4, the differential charge quantity Q = Q2 + Q3 may have been transmitted by terminal 707p and terminal 707m. ADC2 730 may be a SAR-type ADC including a comparison circuit 761. The SAR state machine 763 may be configured to derive a digital value CODE2, for which the voltage between terminal 707p and terminal 707m may be approximately zero (the degree of approximation may depend on CODE2 and the resolution of ADC2 730).

[0072] The term "amplification" may not be limited to signal processing where the input value and the output value have the same nature (such as voltage input - voltage output or current input - current output). For example, the AZ residual amplifier circuit 720 may be a voltage input - charge output amplification circuit, and its amplification factor A may be expressed in units such as coulombs / volt. A relatively large amplification factor A may indicate that when the noise sources within ADC2 730 are related to the input (e.g., terminal 701p and terminal 701m), their contribution to the overall noise level of the ADC circuit 700 is relatively small.

[0073] Switch 765p and switch 765m may apply a first predetermined bias voltage to terminal 707p and terminal 707m, while the SAR state machine 763 may be configured with a predetermined reset code during stage 3 (i.e., the SAR state machine 763 may be in a predetermined reset state). Optionally, the second predetermined bias voltage may be the same as the first predetermined bias voltage and may be applied via switch 733p, switch 733m, switch 735p, and switch 735m. Optionally, the third predetermined potential may be the same as the first and / or second predetermined bias voltage and may be applied via switch 723p, switch 723m, switch 725p, and switch 725m. The first predetermined bias voltage, the second predetermined bias voltage, and the third predetermined bias voltage may not be marked in Figure 7A marked out.

[0074] Figure 7BThe example timing diagram in shows that switches 723p, 723m, 725p, 725m, 733p, 733m, 735p, and 735m can be closed before stage 2, whereby capacitors 743p, 743m, 745p, and 745m can be reset to a predetermined voltage and charge (e.g., nominally zero differential voltage and zero differential charge). Additionally, before stage 2, switches 703p, 703m, 713p, and 713m may be closed, and the differential current GM·(OS + VRES) can flow through switches 713p, 723p, 713m, and 723m. Stage 2 can begin when switches 723p and 723m are opened and the differential current flows through capacitors 743p and 743m, as well as switches 713p, 733p, 713m, and 733m. Stage 2 can end after a predefined period TINT when switches 733p and 733m are opened and the differential charge Q2 = TINT·GM·(OS + VRES) is effectively sampled on capacitors 743p and 743m. Switches 723p and 723m can be closed after a delay (such as 200 ps) after opening switches 733p and 733m, for example, to provide a path for the current flowing through GM circuit 721. Switches 703p, 703m, 705p, 705m, 713p, 713m, 715p, and 715m can be switched at substantially the same time to prepare for obtaining a second observation during stage 3. The control signals (Φ2x and Φ3x) for controlling switches 703p, 703m, 705p, 705m, 713p, 713m, 715p, and 715m can be non-overlapping in time, for example, to avoid establishing a transient conductive path between terminals 709p and 709m (compared to Figure 4 terminals 409p and 409m in ). The non-overlapping period can be very short, such as 200 ps. A PHOSITA is familiar with the use of non-overlapping control signals and with implementing circuits to generate switch control signals, including non-overlapping switch control signals.

[0075] Figure 7BAn example timing diagram shows that switches 725p, 725m, 735p, and 735m can be closed before stage 3, whereby capacitors 745p and 745m can be reset to a predetermined voltage and charge (e.g., nominally zero differential voltage and zero differential charge). Additionally, before stage 3, switches 705p, 705m, 715p, and 715m can be closed, and the differential current GM·(VRES - OS) can flow through switches 715p, 725p, 715m, and 725m. Stage 3 can begin when switches 725p and 725m are opened and the differential current flows through capacitors 745p and 745m and switches 715p, 735p, 715m, and 735m. Stage 3 may end after a predefined period TINT when switches 735p and 735m are opened and the differential charge Q3 = TINT·GM·(VRES - OS) is effectively sampled on capacitors 745p and 745m. Switches 725p and 725m can be closed after a delay (such as 200 ps) after opening switches 735p and 735m, for example, to provide a current flow path for the current of GM circuit 721. After completing stage 3, the residual voltage VRES may not be needed, and the SQRG circuit 710 can be reset at the start of stage 4.

[0076] The SAR ADC 730 can be configured to receive the amplified residual value Q = Q2 + Q3 and provide a digital value CODE2 to represent the analog residual value VRES through a successive approximation charge balancing operation provided during stage 4. A digital circuit (not shown) can be configured to receive and combine CODE1p, CODE1m, and CODE2 (and optional calibration information) to derive and output a code DOUT to represent the analog input value VIN = Vp(T0) - Vm(T0). The method for combining CODE1p, CODE1m, and CODE2 can include correcting the mismatch of the CDAC capacitor ratios (e.g., digital correction) and / or any other known and / or useful techniques.

[0077] Figure 7C shows compared to Figure 7A the AZ residual amplifier circuit 720 of, an example ADC circuit 702 that includes a modified AZ residual amplifier circuit 722. The SQRG circuit 710 and the ADC2 circuit 730 are the same in Figure 7A the ADC circuit 700 of and Figure 7C the ADC circuit 702 of. More generally, the same reference numbers can correspond to Figure 7A and Figure 7C the same parts of. Figure 7BThe timing diagram can be applied to either or both of the ADC circuit 700 and the ADC circuit 702. The AZ residue amplifier circuit 722 can be an extension of the AZ residue amplifier circuit 720. Specifically, the AZ residue amplifier circuit 722 can have 4 capacitors (capacitor 741p, capacitor 741m, capacitor 747p, and capacitor 747m) added to the AZ residue amplifier circuit 720. The capacitor 741p and the capacitor 741m can be configured to provide negative feedback to the GM circuit 721 when the switches 703p, 703m, 713p, and 713m are closed (Φ2x = 1). When the switches 705p, 705m, 715p, and 715m are closed (Φ3x = 1), the capacitor 747p and the capacitor 747m can be configured to provide negative feedback to the GM circuit 721. The durations TINT of phases 2 and 3 (see Figure 7B ) can be long enough to allow the GM circuit 721 to substantially stabilize to the asymptotic output voltage and the nominally zero input voltage (which the PHOSITA recognizes as a "virtual short circuit"). Various defects in the GM circuit 721 can result in a non-zero virtual short circuit input voltage. Such defects may include a potentially non-zero offset OS.

[0078] The AZ residue amplifier circuit 722 can be configured to operate as a charge input charge output AZ residue amplifier circuit. When the GM circuit 721 approaches the asymptotic state in phase 2 and / or phase 3, charge can be transferred via the terminals 709p and 709m and the negative feedback capacitors 741p, capacitor 741m, capacitor 747p, and capacitor 747m. The output impedance of the SQRG circuit 710 can be capacitive (see Figure 4; The SQRG circuit 710 can be implemented as the SQRG circuit 410). The SQRG circuit 710 can provide an analog residue value that can be expressed as the charge quantity QRES = VRES･C, where C can be the capacitance (e.g., output impedance) characterizing the SQRG circuit 710. A zero voltage between terminal 709p and terminal 709m can indicate the charge quantity QRES transmitted via terminal 709p and terminal 709m since the self-sampling moment (t = T0), and the charge quantity QRES represents the analog residue value. The AZ residue amplifier circuit 722 can amplify QRES during stage 2 and store the first observed value of the amplified residue value as the charge Q2 = A･(VRES + OS)･C = A･(QRES + OS･C) on capacitor 743p and capacitor 743m. The AZ amplifier circuit 722 can further amplify QRES during stage 3 and store the second observed value of the amplified residue value as the charge Q3 = A･(VRES - OS)･C = A･(QRES - OS･C) on capacitor 745p and capacitor 745m. The two observed values can be combined through a charge sharing operation Q = Q2 + Q3 = 2A･QRES at the beginning of stage 4 (as described for the AZ amplifier circuit 720).

[0079] In stage 2, switch 725p and switch 725m can be closed, and switch 723p and switch 723m can be opened. Then, the GM circuit 721 can tend to an asymptotic state by transmitting charge (nominally QRES) via terminal 709p and terminal 709m and capacitor 741p and capacitor 741m to establish a virtual short-circuit voltage at its input (e.g., OS is nominally zero). When switch 725p and switch 725m are closed shortly after stage 2, the transmitted charge can be returned (shipped back) via terminal 709p and terminal 709m and capacitor 741p and capacitor 741m (see the timing diagram in Figure 7B . Subsequently, in stage 3, switch 725p and switch 725m can be closed, and switch 723p and switch 723m can be closed. Then, the GM circuit 721 can tend to an asymptotic state by transmitting charge (nominally QRES) via terminal 709p and terminal 709m and capacitor 747p and capacitor 747m to establish a virtual short-circuit voltage at its input.

[0080] The first amplification factor for the operation of the AZ amplifier circuit 722 during stage 2 can be substantially a function of the ratio of the capacitances of capacitor 743p and capacitor 743m and capacitor 741p and capacitor 741m. The second amplification factor for the operation of the AZ amplifier circuit 722 during stage 3 can be substantially a function of the capacitance ratio of capacitor 745p and capacitor 745m and capacitor 747p and capacitor 747m. The first amplification factor and the second amplification factor can be nominally the same. Capacitor 743p, capacitor 743m, capacitor 745p, and capacitor 745m can be nominally the same. Capacitor 741p, capacitor 741m, capacitor 747p, and capacitor 747m can be nominally the same.

[0081] In comparison, the amplification factor of the AZ amplifier circuit 720 ( Figure 7A ) can be a combination of the time period (TINT), transconductance (GM), and capacitance. In one comparison, the amplification factor of the AZ residual amplifier circuit 722 may be relatively insensitive to variations in the manufacturing process compared to the AZ residual amplifier circuit 720. In another comparison, the AZ residual amplifier circuit 720 may be relatively less sensitive to noise from the GM circuit 721 compared to the AZ amplifier circuit 722. Whether the AZ residual amplifier circuit 720 is superior to the AZ residual amplifier circuit 722 (or vice versa) may depend on one or more design goals. In another embodiment, Figure 7C the ADC circuit 702 of Figure 7B may be configured to not be fully stable during stage 2 and stage 3. For example, the predefined time period TINT shown in the timing diagram of

[0082] The operation of the AZ amplifier 722 may not significantly depend on the linear capacitors 741p, 741m, 743p, 743m, 745p, 745m, 747p, and 747m (the linear capacitors can provide a linear relationship between voltage and charge). In some embodiments, the capacitors 741p, 741m, 743p, 743m, 745p, 745m, 747p, and 747m may be implemented using somewhat non-linear MOS capacitors, i.e., MOS (metal oxide semiconductor) semiconductor devices that are biased to provide a relatively constant (such as ±10%) capacitance over the voltage range used in operation. MOS capacitors may be relatively smaller and less costly than MOM (metal oxide metal) capacitors, which may be relatively more linear. Any insulating barrier structure configured to store charge (including many semiconductor devices) can be used to implement the capacitors 741p, 741m, 743p, 743m, 745p, 745m, 747p, and / or 747m. One of ordinary skill in the art will recognize that MOS semiconductors do not need to be constructed with a metal gate terminal, and the general term / acronym "MOS" (metal oxide semiconductor) should not be construed as a limitation on the materials used to fabricate semiconductor devices. The term "MOS semiconductor device" should include a wide range of semiconductor devices, including nominally non-conductive barriers (which may or may not be made of an oxide). Any capacitor or other circuit component described in this teaching may be at least slightly non-linear. If the common-mode voltages at nodes 709p, terminals 709m, nodes 707p, and terminals 707m are made substantially equal (such as within ±50 mV), the charge input - charge output operation of the AZ amplifier circuit 722 may largely cancel out a significant amount of capacitor non-linearity. In other words, even if the capacitors 741p, 741m, 743p, 743m, 745p, 745m, 747p, and 747m are relatively less linear, the charge input - charge output operation of the AZ amplifier circuit 722 can be substantially linear. The common-mode voltage can be a function of the bias voltage applied via switches 733p, 733m, 735p, and 735m ( Figure 7C ) and the bias voltage applied via switches 405p and 405m in the SQRG circuit 710 ( Figure 4 ), which can be implemented as Figure 4 the SQRG circuit 410.

[0083] Figure 7D Another exemplary embodiment of the ADC circuit 704 is shown, including a modified AZ residue amplifier circuit 724. Compared to Figure 7CThe AZ residue amplification circuit 722, Figure 7C The four capacitors (capacitor 741p, capacitor 741m, capacitor 747p, capacitor 747m) of Figure 7C can be replaced by two capacitors (capacitor 771p and capacitor 771) and four switches (switch 773p, switch 773m, switch 775p, and switch 775m). Compared to the AZ residue amplification circuit 722, the benefit of the AZ residue amplification circuit 724 is its reduced sensitivity to noise from the GM circuit 721.

[0084] Figure 7D The AZ circuit 724 of Figure 7D can be further modified (partially) by replacing the GM circuit 721 with a voltage input - voltage output circuit configured to provide amplification. An example voltage input - voltage output amplification circuit can be a two - stage amplifier circuit including well - known Miller - type frequency compensation. Other embodiments can include other types of circuits configured to provide amplification.

[0085] Example embodiments

[0086] The following examples are illustrated.

[0087] Example 1 can include an analog - to - digital converter (ADC) circuit for receiving an analog input value and providing a digital output code representing the analog input value. The ADC circuit includes a sample - quantization residue generation (SQRG) circuit configured to receive the analog input value and provide a first digital code derived at least in part from the analog input value, the SQRG circuit further configured to provide an analog residue value derived at least in part from the analog input value and the first code; an auto - zero residue amplification circuit configured to receive and amplify the analog residue value and provide a first observation value and a second observation value of the amplified analog residue value; a quantizer circuit configured to derive a second code representing at least the combination of the first observation value and the second observation value of the amplified analog residue value; and a digital circuit configured to combine at least the first code and the second code to derive the digital output code.

[0088] Example 2 can include the ADC circuit of Example 1, wherein the first code is derived at least in part from the combination of the analog input value and a dither value.

[0089] Example 3 may include the ADC circuit according to Example 1, wherein the auto-zero residual amplifier circuit includes an active circuit configured to provide amplification, the active circuit being configured to receive the analog residual value in a first polarity to provide a first observation of the amplified analog residual value, the active circuit further being configured to receive the analog residual value in a second polarity opposite to the first polarity to provide a second observation of the amplified analog residual value.

[0090] Example 4 may include the ADC circuit according to Example 1, wherein the auto-zero residual amplifier circuit includes an active circuit having a potentially non-zero offset, the potentially non-zero offset contributing to the first observation and the second observation of the amplified analog residual value, and wherein a combination of the first observation and the second observation of the amplified analog residual value substantially cancels the contribution of the offset to the second code.

[0091] Example 5 may include the ADC circuit according to Example 1, wherein the auto-zero amplifier circuit is further configured to produce a third observation of the amplified analog residual value, and wherein the second code provided by the quantizer circuit represents a weighted combination of the first observation, the second observation, and the third observation of the amplified residual value.

[0092] Example 6 may include the ADC circuit according to Example 5, wherein the weighted combination applies substantially more weight to at least one of the three observations of the amplified residual value.

[0093] Example 7 may include the ADC circuit according to Example 1, wherein the second code provided by the quantizer circuit is a weighted combination of the first observation and the second observation of the amplified residual value, and wherein an absolute value of a first weighting factor for the first observation of the amplified residual value is substantially the same as a second weighting factor for the second observation of the amplified residual value.

[0094] Example 8 may include the ADC circuit according to Example 1, wherein the quantizer circuit derives a third code to represent the first observation of the amplified analog residual value and further derives a fourth code to represent the second observation of the amplified analog residual value, and wherein the second code is derived at least in part by combining the third code and the fourth code.

[0095] Example 9 may include the ADC circuit according to Example 1, wherein the first observation and the second observation of the amplified analog residual value are represented by a first analog value and a second analog value, respectively, the first analog value and the second analog value being combined to provide a combined analog value.

[0096] Example 10 may include the ADC circuit according to Example 9, wherein the first analog value and the second analog value are combined by a charge sharing operation.

[0097] Example 11 may include the ADC circuit according to Example 1, wherein the quantizer circuit includes a CDAC circuit, and the CDAC circuit is configured to sample the first observation value of the amplified residual value on a first segment of the CDAC circuit, and is further configured to sample the second observation value of the amplified residual value on a second segment of the CDAC circuit.

[0098] Example 12 may include the ADC circuit according to Example 11, wherein the first segment and the second segment of the CDAC circuit are used for digital-to-analog conversion of a plurality of codes in a successive approximation code sequence.

[0099] Example 13 may include the ADC circuit of Example 1, wherein the quantizer circuit includes a successive approximation register (SAR) state machine.

[0100] Example 14 may include the ADC circuit according to Example 1, wherein the analog residual value is the amount of charge provided as an input to the auto-zero residual amplifier circuit.

[0101] Example 15 may include the ADC circuit according to Example 14, wherein the quantizer circuit is configured to receive the amount of charge representing the combination of the first observation value and the second observation value of the amplified analog residual value.

[0102] Example 16 may include the ADC circuit according to Example 15, wherein the semiconductor device is configured to store the amount of charge representing one of the two observations of the amplified residual value.

[0103] Example 17 may include the ADC circuit according to Example 1, wherein the resolution of the first code is at least 10 bits.

[0104] Example 18 may include the ADC circuit according to Example 1, wherein the auto-zero residual amplifier circuit is configured to provide amplification by integrating, over a predefined period of time, substantially an analog quantity derived from the analog residual value.

[0105] Example 19 may include the ADC circuit according to Example 1, wherein the auto-zero residual amplifier circuit is configured to provide amplification by stabilizing at a predefined fraction of an asymptotic value, and wherein the predefined fraction is at most 98%.

[0106] Example 20 may include the ADC circuit according to Example 1, wherein the SQRG circuit is configured to derive the first code at least in part by deriving a residue relative to a code having a resolution that is at least 3 bits less than the resolution of the first code.

[0107] Example 21 may include an analog-to-digital converter (ADC) circuit including a sampling quantization residue generation (SQRG) circuit configured to generate a first digital code based at least in part on an analog input value received by the ADC circuit and to generate an analog residue value based at least in part on the first digital code and the analog input value; an auto-zero residue amplification circuit configured to amplify the analog residue value, generate a first observation of the amplified analog residue value, and generate a second observation of the amplified analog residue value; a quantizer circuit configured to generate a second digital code representing at least a combination of the first observation and the second observation; and a digital circuit configured to generate a digital output code representing the analog input value, wherein the first digital code and the second digital code are combined to generate the digital output code.

[0108] Example 22 may be based on the ADC circuit of Example 21, wherein the auto-zero residue amplification circuit includes an amplification circuit configured to provide amplification, wherein, to generate the first observation of the amplified analog residue value, the amplification circuit will receive the analog residue value of a first polarity, and wherein, to generate the second observation of the amplified analog residue value, the amplification circuit will receive the analog residue value of a second polarity opposite to the first polarity.

[0109] Example 23 may include the ADC circuit according to Example 22, wherein the auto-zero residue amplification circuit includes a first switch and a second switch that are closed during a phase to invert the polarity of the analog residue value.

[0110] Example 24 may include the ADC circuit according to Example 22, wherein the polarity of the analog residue value is inverted prior to amplification to generate the second observation.

[0111] Example 25 may include the ADC circuit according to Example 21, wherein the second digital code includes a weighted combination of the first observation and the second observation, and wherein the absolute value of a first weighting factor of the first observation is substantially equal to the absolute value of a second weighting factor of the second observation.

[0112] Example 26 may include an ADC circuit according to Example 21, wherein the quantizer circuit is to combine the first observation value and the second observation value to produce at least the combination of the first observation value and the second observation value, and wherein the first observation value and the second observation value are to be combined so that the offset is substantially canceled.

[0113] Example 27 may include an ADC circuit according to Example 26, wherein the auto-zero residual amplification circuit includes an active circuit, wherein the offset is caused by the active circuit, and wherein the offset contributes to the first observation and the second observation.

[0114] Example 28 may include the ADC circuit of Example 21, wherein the first digital code is generated based at least in part on the analog input value and a dither value.

[0115] Example 29 may include an ADC circuit according to Example 21, wherein the auto-zero amplifier circuit is further used to generate a third observation value of the amplified analog residual value, and wherein at least the combination of the first observation value and the second observation value includes a weighted combination of the first observation value, the second observation value and the third observation value.

[0116] Example 30 may include an ADC circuit according to Example 21, wherein the first observation value is represented by a first analog value, wherein the second observation value is represented by a second analog value, and wherein the first analog value and the second analog value are to be combined to produce a combined analog value, and the combined analog value is to be used to produce the second digital code.

[0117] Example 31 may include an ADC circuit according to Example 30, wherein a charge sharing operation is utilized to comb the first analog value and the second analog value.

[0118] Example 32 may include the ADC circuit according to Example 21, wherein the analog residual value is converted into a charge amount as an input of the auto-zero residual amplification circuit.

[0119] Example 33 may include an ADC circuit according to Example 32, wherein the charge quantity is a first charge quantity, and wherein the quantizer circuit is to receive a second charge quantity, the second charge quantity representing at least the combination of the first observation value and the second observation value.

[0120] Example 34 may include an ADC circuit according to Example 33, wherein the semiconductor device is used to store the second amount of charge.

[0121] Example 35 may include the ADC circuit of Example 24, wherein the polarity of the amplified analog residual value is swapped after amplification to produce the second observation value.

[0122] Example 36 may include an auto-zero residual amplifier circuit for offset cancellation. The auto-zero residual amplifier circuit includes: an amplifier circuit configured to amplify a first observation of an analog residual value and a second observation of the analog residual value received by the auto-zero residual amplifier circuit, the analog residual value being a residual of a digital code generated by an analog-to-digital conversion of an analog input value, wherein the amplified first observation and the second observation will be used together with the digital code to generate a digital output code representative of the analog input value; and one or more switches coupled between the amplifier circuit and an input of the auto-zero residual amplifier circuit, the analog residual value being received via the input of the auto-zero residual amplifier circuit, wherein the one or more switches selectively apply the first observation and the second observation to the amplifier circuit.

[0123] Example 37 may include the auto-zero residual amplifier circuit according to Example 36, wherein the second set of one or more switches will apply the first observation to the second capacitor and the third capacitor during the first phase, and wherein the second set of one or more switches will apply the second observation to the first capacitor and the fourth capacitor during the second phase.

[0124] Example 38 may include the auto-zero residual amplifier circuit according to Example 37, wherein the one or more switches include a first set of one or more switches, and wherein the auto-zero residual amplifier circuit further includes a first capacitor and a second capacitor for storing and combining a first charge, a third capacitor and a fourth capacitor for storing and combining a second charge, and a second set of one or more switches coupled between the amplifier circuit and the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor, the second set of one or more switches configured to selectively apply the first observation and the second observation to the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor, the first observation and the second observation forming the first charge on the first capacitor and the second capacitor and the second charge on the third capacitor and the fourth capacitor.

[0125] Example 39 may include the auto - zeroing residual amplifier circuit according to Example 38, wherein the second set of one or more switches applies the first observed value to the second capacitor and the third capacitor in the first output polarity during the first phase, wherein the second set of one or more switches applies the second observed value to the first capacitor and the fourth capacitor in the second output polarity during the second phase, and wherein the second output polarity is opposite to the first output polarity.

[0126] Example 40 may include the auto - zeroing residual amplifier circuit according to Example 38, further comprising a third set of one or more switches, the third set of one or more switches being coupled between the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor and the output of the auto - zeroing residual amplifier circuit, wherein the third set of one or more switches combines the first charges of the first capacitor and the second capacitor during a third phase, wherein the third set of one or more switches combines the second charges of the third capacitor and the fourth capacitor during the third phase, and wherein the third phase is separated from the first phase and the second phase.

[0127] Example 41 may include the auto - zeroing residual amplifier circuit according to Example 36, further comprising one or more capacitors, the one or more capacitors being coupled between the input of the amplifier circuit and the output of the amplifier circuit, the one or more capacitors providing feedback for the auto - zeroing residual amplifier circuit.

[0128] The foregoing outlines the features of one or more embodiments of the subject matter disclosed herein. These embodiments are provided to enable a person having ordinary skill in the art (PHOSITA) to better understand various aspects of the present disclosure. Certain readily understandable terms may be cited, as well as underlying technologies and / or standards, without detailed description. It is expected that the PHOSITA will have or have access to background knowledge or information of those technologies and standards sufficient to practice the teachings of the present disclosure.

[0129] The PHOSITA will understand that they can readily use the present disclosure as a basis for designing or modifying other processes, structures, or variations to achieve the same purposes and / or realize the same advantages of the embodiments introduced herein. The PHOSITA will also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0130] Note that the activities discussed above with reference to the accompanying drawings apply to any integrated circuit that involves signal processing (e.g., gesture signal processing, video signal processing, audio signal processing, analog-to-digital conversion, digital-to-analog conversion), especially those integrated circuits that can execute specialized software programs or algorithms, some of which may be associated with processing digital real-time data. Certain embodiments may involve multi-DSP, multi-ASIC, or multi-SoC signal processing, floating-point processing, signal / control processing, fixed-function processing, microcontroller applications, etc. In some cases, the features discussed herein may apply to medical systems, scientific instruments, wireless and wired communications, radar, industrial process control, audio and video devices, current sensing, instruments (which can be highly precise), and other digital processing-based systems. Additionally, some of the embodiments discussed above may be provided in digital signal processing techniques for medical imaging, patient monitoring, medical instruments, and home healthcare. This may include, for example, lung monitors, accelerometers, heart rate monitors, or pacemakers, as well as their peripherals. Other applications may involve automotive technologies for safety systems (e.g., stability control systems, driver assistance systems, braking systems, infotainment, and any type of internal application). Additionally, powertrain systems (e.g., in hybrid and electric vehicles) may use high-precision data conversion, rendering, and display products in battery monitoring, control systems, reporting control, maintenance activities, etc. In other example scenarios, the teachings of the present disclosure may apply to industrial markets that include process control systems that contribute to increased productivity, energy efficiency, and reliability. In consumer applications, the teachings of the signal processing circuits discussed above can be used for image processing, autofocus, and image stabilization (e.g., for digital cameras, camcorders, etc.). Other consumer applications may include audio and video processors for home theater systems, DVD recorders, and high-definition televisions. Yet other consumer applications may involve advanced touchscreen controllers (e.g., for any type of portable media device). Thus, these technologies can easily become part of smartphones, tablets, security systems, PCs, gaming technologies, virtual reality, simulation training, etc.

[0131] The features of several embodiments are outlined above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0132] Certain embodiments of the present disclosure can readily include a System-on-Chip (SoC) Central Processing Unit (CPU) package. An SoC represents an integrated circuit (IC) that integrates the components of a computer or other electronic system onto a single chip. It can contain digital, analog, mixed-signal, and radio-frequency functions: all of these functions can be provided on a single chip substrate. Other embodiments can include a Multi-Chip Module (MCM), where multiple chips are located within a single electronic package and are configured to interact closely with each other through the electronic package. In appropriate cases, any module, function, or block element of an ASIC or SoC can be provided in a reusable "black box" Intellectual Property (IP) block, which can be distributed separately without disclosing the logical details of the IP block. In various other embodiments, the digital signal processing function can be implemented in one or more silicon cores in an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), and other semiconductor chips.

[0133] In some cases, the teachings of the present disclosure can be encoded onto one or more tangible, non-transitory computer-readable media having executable instructions stored thereon, which, when executed, direct a programmable device (such as a processor or DSP) to perform the methods or functions disclosed herein. In cases where the teachings herein are embodied at least in part in a hardware device (such as an ASIC, an IP block, or an SoC), the non-transitory medium can include the hardware device programmed with logic hardware to perform the methods or functions disclosed herein. The teachings can also be practiced in the form of a Register Transfer Level (RTL) or other hardware description languages such as VHDL or Verilog, which can be used to program a manufacturing process to produce the disclosed hardware elements.

[0134] In an example implementation, at least some portions of the processing activities outlined herein can also be implemented in software. In some embodiments, one or more of these features can be implemented in hardware provided external to the elements of the disclosed drawings, or combined in any suitable manner to achieve the intended function. The various components can include software (or reciprocal software) that can be coordinated to achieve the operations outlined herein. In additional embodiments, these elements can include any suitable algorithms, hardware, software, components, modules, interfaces, or objects that facilitate their operation.

[0135] Furthermore, some components associated with the described microprocessor can be removed or otherwise combined. In a general sense, the arrangements depicted in the figures may be more logical in their representation, while the physical architecture can include various arrangements, combinations, and / or mixtures of these elements. It must be noted that countless possible design configurations can be used to achieve the operational objectives outlined herein. Thus, there are countless alternative arrangements, design choices, device possibilities, hardware configurations, software implementations, device options, etc. for the associated infrastructure.

[0136] Any appropriately configured processor component can execute any type of instruction associated with data to implement the operations detailed herein. Any processor disclosed herein can transform an element or article (e.g., data) from one state or thing to another. In another example, some of the activities outlined herein can be implemented with fixed logic or programmable logic (e.g., software and / or computer instructions executed by a processor), and the elements identified herein can be a type of programmable processor, programmable digital logic (e.g., FPGA, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), ASIC including digital logic, software, code, electronic instructions, flash memory, optical disk, CD-ROM, DVD ROM, magnetic card or optical card, other types of machine-readable media suitable for storing electronic instructions, or any suitable combination thereof. In operation, the processor can store information in any suitable type of non-transitory storage medium (e.g., random access memory (RAM), read-only memory (ROM), FPGA, EPROM, electrically erasable programmable ROM (EEPROM), etc.), software, hardware, or any other suitable component, device, element, or object (as appropriate and based on specific needs). Additionally, based on specific needs and implementations, the information tracked, sent, received, or stored in the processor can be provided in any database, register, table, cache, queue, control list, or storage structure, all of which can be referenced within any suitable time frame. Any memory item discussed herein should be understood to be included within the broad term "memory". Similarly, any potential processing elements, modules, and machines described herein should be interpreted to be encompassed within the broad terms "microprocessor" or "processor". Further, in various embodiments, the processors, memories, network cards, buses, storage devices, associated peripheral devices, and other hardware elements described herein can be implemented by processors, memories, and other related devices configured by software or firmware to emulate or virtualize the functions of those hardware elements.

[0137] The computer program logic for implementing all or part of the functions described herein is embodied in various forms, including but not limited to source code form, computer-executable form, hardware description form, and various intermediate forms (e.g., mask works, or forms generated by assemblers, compilers, linkers, or locators). In an example, the source code includes a series of computer program instructions implemented in various programming languages, such as object code, assembly language, or high-level languages such as OpenCL, RTL, Verilog, VHDL, Fortran, C, C++, JAVA, or HTML, for use with various operating systems or operating environments. The source code can define and use various data structures and communication messages. The source code can be in computer-executable form (e.g., via an interpreter), or the source code can be converted (e.g., via a converter, assembler, or compiler) into computer-executable form.

[0138] In the discussion of the above embodiments, capacitors, buffers, graphic elements, interconnection boards, clocks, DDRs, camera sensors, converters, inductors, resistors, amplifiers, switches, digital cores, transistors, and / or other components can be easily replaced, substituted, or otherwise modified to meet the needs of a particular circuit system. Additionally, it should be noted that the use of complementary electronic devices, hardware, non-transitory software, etc. provides equally viable options for implementing the teachings of the present disclosure.

[0139] In one example embodiment, any number of the circuits in the figure can be implemented on a board of an associated electronic device. The board can be a general-purpose circuit board that can accommodate various components of the internal electronic system of the electronic device and further provide connectors for other peripheral devices. More specifically, the board can provide electrical connections through which other components of the system can communicate electrically. Any suitable processor (including digital signal processors, microprocessors, support chipsets, etc.), memory elements, etc. can be appropriately coupled to the circuit board based on specific configuration requirements, processing requirements, computer design, etc. Other components, such as external storage devices, additional sensors, controllers and peripherals for audio / video displays, can be connected to the board as plug-in cards, via cables, or integrated onto the board. In another example embodiment, the circuits in the figure can be implemented as stand-alone modules (e.g., devices having associated components and circuit systems configured to perform specific applications or functions), or as plug-in modules inserted into specific application hardware of an electronic device.

[0140] Note that, in many of the examples provided herein, interactions may be described with two, three, four, or more electrical components. However, this is done for clarity and illustrative purposes only. It should be understood that the system may be integrated in any suitable manner. Along similar design alternatives, any of the components, modules, and elements shown in the figures may be combined in a variety of possible configurations, all of which are clearly within the broad scope of the present disclosure. In some cases, it may be easier to describe one or more functions of a given set of processes by referring to only a limited number of electrical components. It should be understood that the figures and their teachings are readily extensible and can accommodate a large number of components as well as more complex / intricate arrangements and configurations. Thus, the examples provided should not limit the scope or inhibit the broad teachings of the circuits, as they may be applied to numerous other architectures.

[0141] Those skilled in the art can determine many other changes, substitutions, variations, alterations, and modifications, and it is the intention of the present disclosure to cover all such changes, substitutions, variations, alterations, and modifications that fall within the scope of the appended claims. To assist the United States Patent and Trademark Office (USPTO) and any readers of any patents issued on the basis of this application in interpreting the claims appended hereto, the applicant wishes to note that the applicant: (a) does not intend to rely on 35 U.S.C. § 112(f) as it existed on the date of filing of this application, unless the terms "means" or "step" are specifically used in a particular claim; and (b) does not intend to limit the present disclosure in any way not reflected in the appended claims by any statement in this disclosure.

Claims

1. An analog-to-digital converter (ADC) circuit, comprising: A sample quantization residue generation (SQRG) circuit, the SQRG circuit being configured to: Generate a first digital code based at least in part on an analog input value received by the ADC circuit ； And Generate an analog residue value based at least in part on the first digital code and the analog input value; An auto-zero residue amplification circuit, the auto-zero residue amplification circuit being configured to: Amplify the analog residue value; Generate a first observation value of the amplified analog residue value, and Generate a second observation value of the amplified analog residue value; A quantizer circuit, the quantizer circuit being configured to generate a second digital code, the second digital code representing at least a combination of the first observation value and the second observation value; And A digital circuit, the digital circuit being configured to generate a digital output code, the digital output code representing the analog input value, wherein the first digital code and the second digital code are combined to generate the digital output code.

2. The ADC circuit according to claim 1, Wherein, The auto-zero residue amplification circuit includes an amplification circuit for providing amplification, wherein, in order to generate the first observation value of the amplified analog residue value, the amplification circuit will receive the analog residue value of a first polarity, and wherein, in order to generate the second observation value of the amplified analog residue value, the amplification circuit will receive the analog residue value of a second polarity, the second polarity being opposite to the first polarity.

3. The ADC circuit according to claim 2, Wherein, The auto-zero residue amplification circuit includes a first switch and a second switch, the first switch and the second switch being closed during a phase to reverse the polarity of the analog residue value.

4. The ADC circuit according to claim 1, Wherein, The second digital code includes a weighted combination of the first observation value and the second observation value, and wherein the absolute value of a first weighting factor of the first observation value is substantially equal to the absolute value of a second weighting factor of the second observation value.

5. The ADC circuit according to claim 1, Wherein, The quantizer circuit combines the first observation value and the second observation value to generate at least the combination of the first observation value and the second observation value, and wherein the first observation value and the second observation value are combined to substantially eliminate an offset.

6. The ADC circuit according to claim 1, Wherein, The first digital code is generated based at least in part on the analog input value and a dither value.

7. The ADC circuit according to claim 1, Wherein, The auto-zero residue amplification circuit will further be configured to generate a third observation value of the amplified analog residue value, and wherein at least the combination of the first observation value and the second observation value includes a weighted combination of the first observation value, the second observation value, and the third observation value.

8. The ADC circuit according to claim 1, Wherein, The first observed value is represented by a first analog value, wherein the second observed value is represented by a second analog value, and wherein the first analog value and the second analog value are to be combined to produce a combined analog value, the combined analog value being used to produce the second digital code.

9. The ADC circuit according to claim 1, wherein, the analog residual value includes the electric charge amount that is the input of the auto-zeroing residual amplification circuit.

10. The ADC circuit according to claim 1, wherein: the quantizer circuit includes a capacitive digital-to-analog converter having a first stage and a second stage; the first stage samples the first observed value; and the second stage samples the second observed value.

11. An auto-zeroing residual amplification circuit for offset cancellation, the auto-zeroing residual amplification circuit comprising: an amplification circuit configured to amplify a first observed value of an analog residual value received by the auto-zeroing residual amplification circuit and a second observed value of the analog residual value, the analog residual value being the residual of a digital code generated by an analog-to-digital conversion of an analog input value, wherein the amplified first observed value and the amplified second observed value are to be used together with the digital code to produce a digital output code representing the analog input value; and one or more switches coupled between the amplification circuit and the input of the auto-zeroing residual amplification circuit, the analog residual value being received via the input of the auto-zeroing residual amplification circuit, wherein the one or more switches selectively apply the first observed value and the second observed value to the amplification circuit.

12. The auto-zeroing residual amplification circuit according to claim 11, wherein, the one or more switches apply the first observed value to the amplification circuit with a first polarity during a first phase, wherein the one or more switches apply the second observed value to the amplification circuit with a second polarity during a second phase, the second polarity being opposite to the first polarity, and wherein the second phase is separated from the first phase.

13. The auto-zeroing residual amplification circuit according to claim 12, wherein, the one or more switches include a first set of one or more switches, and wherein the auto-zeroing residual amplification circuit further comprises: a first capacitor and a second capacitor for storing and combining a first charge, a third capacitor and a fourth capacitor for storing and combining a second charge, and a second set of one or more switches coupled between the amplification circuit and the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor, the second set of one or more switches configured to selectively apply the first observed value and the second observed value to the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor, the first observed value and the second observed value forming the first charge on the first capacitor and the second capacitor and the second charge on the third capacitor and the fourth capacitor.

14. The automatic zeroing residual amplifier circuit according to claim 11, further comprising one or more capacitors, the one or more capacitors being coupled between an input of the amplifier circuit and an output of the amplifier circuit, and the one or more capacitors providing feedback for the automatic zeroing residual amplifier circuit.

15. A method for eliminating offset, the method comprising: amplifying an analog residual value, where the analog residual value is based on an analog input value and a first digital code generated from the analog input value; generating a first observation value of the amplified analog residual value; generating a second observation value of the amplified analog residual value; and generating a second digital code, the second digital code representing at least a combination of the first observation value and the second observation value.

16. The method according to claim 15, further comprising: generating the first digital code based on the analog input value; and generating an analog representation of the first digital code; and generating the amplified analog residual value based on the analog input value and the analog representation of the first digital code.

17. The method according to claim 15, wherein: generating the first observation value includes receiving the analog residual value of a first polarity; and generating the second observation value includes receiving the analog residual value of a second polarity, the second polarity being opposite to the first polarity.

18. The method according to claim 15, wherein, generating the combination of at least the first observation value and the second observation value includes combining the first observation value and the second observation value and substantially eliminating the offset.

19. The method according to claim 15, further comprising: generating a third observation value of the amplified analog residual value; wherein, generating the combination includes generating a weighted combination of the first observation value, the second observation value, and the third observation value.

20. The method according to claim 15, wherein, generating the second digital code includes: combining a first analog value representing the first observation value and a second analog value representing the second observation value to generate a combined analog value, the combined analog value being used to generate the second digital code.

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