Gain-related fast hybrid DC offset correction circuit and method, and zero-intermediate-frequency receiver

Abstract

The invention discloses a gain-dependent rapid hybrid direct current offset correction circuit, which comprises a direct current correction controller, a hybrid direct current offset corrector and a digital domain direct current offset corrector, the direct current offset correction controller is used for outputting a first control signal enable mix according to state information rxstate sent by a state controller of the zero intermediate frequency receiver so as to start the hybrid direct current offset corrector; the hybrid direct-current offset corrector is used for operating a hybrid direct-current offset correction algorithm to perform hybrid direct-current offset correction to obtain a correction code word when the first control signal enable signal is a first value; and the digital domain direct current offset corrector is used for operating a digital domain direct current offset correction algorithm when the first control signal enable mix signal is a second value, and performing digital domain direct current correction according to the correction code word. Compared with a traditional direct current offset correction method, the method provided by the invention has the characteristics that the correction speed is high, the correction precision is high, and the correction precision and the correction speed are not sensitive to the gain change of a receiver.

Description

Technical Field

[0001] This application relates to the technical field of radio frequency transceiver integrated SoC monolithic integrated circuits, and particularly relates to a gain-related fast hybrid DC offset correction circuit, method, and zero-IF receiver. Background Art

[0002] Due to its advantages such as single-stage frequency conversion and easy integration, with the rapid development of integrated circuits, the on-chip zero-IF receiver has gradually become a research hotspot. The on-chip zero-IF receiver consists of units such as mixers, low-pass filters, digital-to-analog converters, and digital signal processing paths. When implementing the above receiver signal link using semiconductor processes, due to non-ideal factors such as signal paths from the local oscillator terminal to the RF terminal in the mixer during physical implementation, there is a certain amount of DC signal in the received signal. The presence of the DC signal reduces the effective input range at the ADC input and affects the performance of the receiver. When the DC signal is too large, it even affects the normal operation of the signal reception channel.

[0003] To overcome the performance degradation problem caused by DC offset, different literatures have proposed different offset correction circuits. Generally, DC offset correction circuits can be divided into front-end correction and back-end correction. The front-end correction circuit starts before the zero-IF receiver operates to correct the circuit; while the back-end correction circuit corrects the DC offset when the zero-IF receiver is operating normally. Front-end correction and back-end correction each have their own advantages and disadvantages. Front-end correction works before the circuit operates normally and cannot follow the parameter changes when the PVT parameters of the zero-IF receiver change; back-end correction can follow the parameter changes, but the correction time is long and it affects the normal operating state of the circuit. Neither front-end correction nor back-end correction takes into account the gain change of the receiver. However, with the change of wireless signals, the gain of the receiving channel usually changes with the signal amplitude. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, this application provides a gain-related fast hybrid DC offset correction circuit, method, and zero-IF receiver to solve at least one defect in the prior art.

[0005] To achieve the above and other purposes, this application provides a gain-related DC offset correction circuit applied to a zero-IF receiver. The correction circuit includes: a DC correction controller, a hybrid DC offset corrector, and a digital domain DC offset corrector;

[0006] The DC offset correction controller is used to output a first control signal enable_mix to activate the hybrid DC offset corrector according to the status information rx_state sent by the status controller of the zero-IF receiver;

[0007] A hybrid DC offset corrector is used to run a hybrid DC offset correction algorithm to obtain a correction codeword when the first control signal enable_mix is at a first value for hybrid DC offset correction;

[0008] A digital domain DC offset corrector is used to run a digital domain DC offset correction algorithm when the first control signal enable_mix is at a second value and perform digital domain DC correction according to the correction codeword.

[0009] In an embodiment of the present application, the DC offset correction circuit further includes a DC offset correction DAC;

[0010] The hybrid DC offset corrector is used to output a codeword mix_code when the first control signal enable_mix is at a first value and send the codeword mix_code into the DC offset correction DAC;

[0011] The DC offset correction DAC is used to convert the codeword mix_code from a digital codeword to an analog current; the analog current output by the DC offset correction DAC is added to the output current of the mixer, and after passing through a low-pass filter, an ADC, and a digital filter, a digital codeword is obtained;

[0012] The hybrid DC offset corrector performs DC value detection based on the digital codeword and generates a corresponding correction codeword.

[0013] In an embodiment of the present application, the correction circuit further includes:

[0014] A memory for storing the correction codeword and the link sequence gain_index[i] configured by the gain controller of the zero-IF receiver as an associated relationship.

[0015] In an embodiment of the present application, during the hybrid DC correction process, the hybrid DC offset corrector outputs a second control signal lock_mix to indicate whether the hybrid DC correction is completed;

[0016] When the second control signal lock_mix is at a first value, it indicates that the hybrid DC correction is completed;

[0017] When the second control signal lock_mix is at a second value, it indicates that the hybrid DC correction is not completed.

[0018] In an embodiment of the present application, the hybrid DC offset corrector includes: a first-stage accumulation unit, a gain unit, and a second-stage accumulation unit;

[0019] The number of accumulation points of the first-stage accumulation unit is N A , and the output signal A i of the gain unit is:

[0020]

[0021] where k att is the gain of the gain unit, and x i [n] represents the i-th segment accumulation interval of the signal x[n] output by the digital filter. Within the accumulation interval, the DC offset value of the signal does not change. The signal x[n] is expressed as:

[0022] x[n] = asin(2πfn) + d (2)

[0023] where: a represents the signal amplitude, f represents the signal frequency, and d is the DC component of the signal;

[0024] Within the i-th segment accumulation interval, the signal x i [n] is

[0025] x i [n] = a i sin(2πfn) + d - k conv d comp,i = a i sin(2πfn) + d i (3)

[0026] where a i represents the signal amplitude, d comp,i represents the correction codeword, and k conv is the gain coefficient;

[0027] The output value A of the gain unit i is the current DC offset value of the signal,

[0028]

[0029] The second-stage accumulation unit receives the output value A of the gain unit i and obtains the next update value d comp,i+1 :

[0030] d comp,i+1 = d comp,i + k att d i N A (5)

[0031] Substitute d i = d - k conv × d comp,i into the above formula to obtain:

[0032]

[0033] where:

[0034]

[0035] After multiple iterations of Equation (7), the DC offset value in the signal is reduced or eliminated.

[0036] To achieve the above and other objectives, the present application provides a gain-related DC offset correction method, which is applied to a zero-IF receiver. The zero-IF receiver includes a gain controller and a state controller; the correction method includes:

[0037] The DC offset correction controller outputs a first control signal enable_mix according to the state information rx_state sent by the state controller of the zero-IF receiver to start the hybrid DC offset corrector.

[0038] When the first control signal enable_mix is at a first value, the hybrid DC offset corrector runs a hybrid DC offset correction algorithm to perform hybrid DC offset correction to obtain a correction codeword.

[0039] When the first control signal enable_mix is at a second value, the digital domain DC offset corrector runs a digital domain DC offset correction algorithm and performs digital domain DC correction according to the correction codeword.

[0040] In an embodiment of the present application, the step of when the first control signal enable_mix is at a first value, the hybrid DC offset corrector runs a hybrid DC offset correction algorithm to perform hybrid DC offset correction to obtain a correction codeword includes:

[0041] When the first control signal enable_mix is at a first value, the hybrid DC offset corrector outputs a codeword mix_code and sends the codeword mix_code into the DC offset correction DAC.

[0042] The DC offset correction DAC converts the codeword mix_code from a digital codeword to an analog current, adds the analog current to the output current of the mixer, and obtains a digital codeword after passing through a low-pass filter, an ADC, and a digital filter.

[0043] The hybrid DC offset corrector performs DC value detection according to the digital codeword and generates a corresponding correction codeword.

[0044] In an embodiment of the present application, the correction method further includes:

[0045] Storing the correction codeword and the link sequence gain_index[i] configured by the gain controller of the zero-IF receiver as an associated relationship.

[0046] In an embodiment of the present application, the hybrid DC offset corrector includes: a first-stage accumulation unit, a gain unit, and a second-stage accumulation unit; the hybrid DC offset corrector detects a DC value according to the digital codeword and generates a corresponding correction codeword, including:

[0047] The number of accumulation points of the first-stage accumulation unit is N A , and the output signal A of the gain unit i is:

[0048]

[0049] where k att is the gain of the gain unit, and x i [n] represents the i-th accumulation interval of the signal x[n] output by the digital filter. The DC offset value of the signal does not change within the accumulation interval. The signal x[n] is expressed as:

[0050] x[n] = asin(2πfn) + d (2)

[0051] where: a represents the signal amplitude, f represents the signal frequency, and d is the DC component of the signal;

[0052] Within the i-th accumulation interval, the signal x i [n] is

[0053] x i [n] = a i sin(2πfn) + d - k conv d comp,i = a i sin(2πfn) + d i (3)

[0054] where a i represents the signal amplitude, d comp,i represents the correction codeword, and k conv is the gain coefficient;

[0055] The output value A of the gain unit i is the current DC offset value of the signal,

[0056]

[0057] The second-stage accumulation unit receives the output value A of the gain unit i and obtains the next update value d comp,i+1 :

[0058] d comp,i+1 = d comp,i + k att d i N A(5)

[0059] Let d i = d - k conv ×d comp,i Substitute it into the above formula to get:

[0060]

[0061] Where:

[0062]

[0063] After multiple iterations of Equation (7), the DC offset value in the signal is reduced or eliminated.

[0064] To achieve the above and other purposes, the present application provides a zero-IF receiver, including a mixer, a low-pass filter, an ADC, a digital filter, a gain controller, and a state controller; the zero-IF receiver further includes the above-mentioned DC offset correction circuit.

[0065] Advantages of the present application:

[0066] A gain-related DC offset correction circuit of the present application is applied to a zero-IF receiver. The correction circuit includes a DC correction controller, a hybrid DC offset corrector, and a digital-domain DC offset corrector; the DC offset correction controller is used to output a first control signal enable_mix to start the hybrid DC offset corrector according to the status information rx_state sent by the state controller of the zero-IF receiver; the hybrid DC offset corrector is used to run the hybrid DC offset correction algorithm to perform hybrid DC offset correction to obtain a correction codeword when the first control signal enable_mix is a first value; the digital-domain DC offset corrector is used to run the digital-domain DC offset correction algorithm when the first control signal enable_mix is a second value and perform digital-domain DC correction according to the correction codeword. Compared with the traditional DC offset correction method, the method proposed in the present application has the characteristics of fast correction speed, high correction accuracy, and insensitivity of correction accuracy and correction speed to the change of the receiver gain.

[0067] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0069] Figure 1 It is a principle block diagram of a gain-related DC offset correction circuit according to an embodiment of the present application;

[0070] Figure 2 It is a schematic storage structure of correction codewords and link sequences according to an embodiment of the present application;

[0071] Figure 3 It is a circuit diagram of an accumulator according to an embodiment of the present application;

[0072] Figure 4 It is a flowchart of a gain-related DC offset correction method according to an embodiment of the present application. Specific embodiments

[0073] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0074] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. Therefore, only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0075] Although terms such as "first", "second", "A", and "B" may be used herein to describe various elements, these elements should not be limited by these terms and are only used to distinguish one element from another. For example, without departing from the scope of the following technology, the first element may be called the second element, and similarly, the second element may be called the first element. The term "and / or" includes combinations of multiple related items or any item among multiple related items.

[0076] As used herein, unless the context indicates otherwise, the singular form is also intended to include the plural form. It will be understood that the term "comprising" means the presence of the described features, quantities, steps, operations, elements, or combinations thereof, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0077] Before the detailed description, it is intended to clarify that the division of components in this specification is only based on the main functions of each component. That is, two or more of the following-described components can be combined into one component, or can be divided into two or more components according to more detailed functions. In addition to the main functions of the components, each of the following-described components can also perform some or all of the functions of other components, and some of the main functions of each component can be specifically performed by other components.

[0078] Regarding the problem of not considering the change in the receiver gain existing in solving the DC offset problem through foreground calibration and background calibration. This application provides a gain-related fast hybrid DC offset correction circuit. As Figure 1 shown in the principle block diagram of the zero-IF receiver and the proposed DC offset correction circuit, where the part within the dashed box is the proposed DC offset correction circuit part, and the part outside the dashed box is the main signal path of the zero-IF receiver. The main signal path of the zero-IF receiver and the DC offset circuit work together under the coordination of the receiver state controller (RX ENSM). The calibration process is generally divided into two stages: foreground calibration and background calibration. The foreground calibration provides the calibration initial point for the background calibration.

[0079] This application provides a gain-related DC offset correction circuit, which is applied to a zero-IF receiver. The zero-IF receiver includes: a mixer (MIXER), a low-pass filter (LPF), an ADC, a digital filter (Digital Filter), a gain controller (Gain controller), and a state controller; when the circuit is working properly, the RF signal passes through the antenna and the mixer (MIXER), and is converted from an RF signal into an analog baseband signal; subsequently, after being filtered by the analog low-pass filter (LPF), it enters the ADC. The ADC quantizes the analog baseband signal into a digital baseband signal, enters the digital filter and the on-line DC offset correction process, and then sends the digital signal to the host computer. When the input wireless signal power changes, the link changes the signal gain under the control of the gain controller, so that the output signal amplitude is stabilized within a set range. Please refer to Figure 1 , the correction circuit includes: a DC correction controller (DCOC controller), a hybrid DC offset corrector (MIX DCOC Algorithm), and a digital domain DC offset corrector (DIG DCOC Algorithm);

[0080] The DC offset correction controller is used to output a first control signal enable_mix to start the hybrid DC offset corrector according to the state information rx_state sent by the state controller of the zero-IF receiver;

[0081] A hybrid DC offset corrector is used to run a hybrid DC offset correction algorithm to obtain a correction codeword when the first control signal enable_mix is at a first value for hybrid DC offset correction.

[0082] A digital domain DC offset corrector is used to run a digital domain DC offset correction algorithm when the first control signal enable_mix is at a second value and perform digital domain DC correction based on the correction codeword.

[0083] Of course, when the chip is powered on, the state controller issues instructions to the gain controller and the DC offset correction controller. The gain controller configures the channel gains in a certain order, which can be configured from large to small according to the gain, or from small to large, or in other set ways in the form of a table. At the same time, the gain controller sends the current gain information to the DC offset correction controller; among them, the gain information includes: link gain A[i] and gain index gain_index[i]. If the gain configuration is not completed, the gain controller traverses all gain combinations according to the set gain control method and sorts all these gains in a certain way, such as from large to small or from small to large according to the gain. Let the link gain configured for the i-th time be A[i], and the corresponding sequence be gain_index[i]. After the gain configuration is completed, the gain controller sends the link gain A[i] and the corresponding gain index gain_index[i] to the DC offset correction controller. The DC offset correction controller receives the link gain A[i] and the gain index gain_index[i] and processes them in combination with the state information rx_state sent by the state controller. When rx_state is in the offline calibration state, the DC offset correction controller starts and runs the hybrid DC offset correction algorithm.

[0084] It should be noted that for the hybrid DC offset corrector, the first value can be "1" and the second value can be "0".

[0085] In an embodiment, the DC offset correction circuit further includes a DC offset correction DAC; the hybrid DC offset corrector is used to output a codeword mix_code when the first control signal enable_mix is at a first value and send the codeword mix_code into the DC offset correction DAC; the DC offset correction DAC is used to convert the codeword mix_code from a digital codeword to an analog current; the analog current output by the DC offset correction DAC is added to the output current of the mixer, and after passing through a low-pass filter, an ADC, and a digital filter, a digital codeword is obtained; the hybrid DC offset corrector detects the DC value according to the digital codeword and generates a corresponding correction codeword.

[0086] Specifically, the DC correction controller outputs a first control signal enable_mix, and runs the hybrid DC offset correction algorithm when the first control signal enable_mix changes from 0 to 1. The first control signal enable_mix is simultaneously used as the gating signal of the multiplexer; when the first control signal enable_mix is 1, the multiplexer selects the output codeword mix_code of the hybrid DC offset corrector and sends the codeword mix_code to the DC offset correction DAC (DCOC DAC) to realize the conversion from the digital codeword to the analog current. At this time, the output current of the DC offset correction DAC is added to the output of the mixer, and after passing through the low-pass filter, ADC and digital filter, it is sent to the hybrid DC offset corrector to form a complete digital-analog hybrid correction loop. The hybrid DC offset corrector runs the hybrid DC offset correction algorithm to detect the DC value according to the received digital codeword and generate the corresponding correction codeword mix_code to achieve DC correction.

[0087] In one embodiment, the hybrid DC offset corrector includes: a first-stage accumulation unit, a gain unit, and a second-stage accumulation unit;

[0088] The number of accumulation points of the first-stage accumulation unit is N A , and the output signal A i of the gain unit is:

[0089]

[0090] where k att is the gain of the gain unit, x i [n] represents the i-th segment accumulation interval of the signal x[n] output by the digital filter, and the DC offset value of the signal does not change within the accumulation interval. The signal x[n] is expressed as:

[0091] x[n] = asin(2πfn) + d (2)

[0092] where: a represents the signal amplitude, f represents the signal frequency, and d is the DC component of the signal;

[0093] Within the i-th segment accumulation interval, the signal x i [n] is,

[0094] x i [n] = a i sin(2πfn) + d - k conv d comp,i = a i sin(2πfn) + d i (3)

[0095] Among them, a i represents the signal amplitude, d comp,i represents the correction codeword, and k conv is the gain coefficient;

[0096] The output value A of the gain unit i is the current DC offset value of the signal,

[0097]

[0098] The second-stage accumulation unit receives the output value A of the gain unit i and obtains the next update value d comp,i+1 :

[0099] d comp,i+1 = d comp,i + k att d i N A (5)

[0100] Substitute d i = d - k conv × d comp,i into the above formula to obtain:

[0101]

[0102] Among them:

[0103]

[0104] After multiple iterations of formula (7), the DC offset value in the signal is reduced or eliminated.

[0105] Specifically, when the hybrid DC offset corrector performs correction, it includes:

[0106] Assume that the signal output from the digital filter is x[n]; after entering the offset correction algorithm, the signal x[n] first performs accumulation to estimate the DC value of the current signal. In implementation, the accumulator can include a first-stage accumulation unit composed of an adder and a delay unit, a gain unit, and a second-stage accumulation unit composed of an adder and a delay unit. Assume that the number of accumulated data points of the first-stage accumulation unit is set to N A , in implementation, the number of accumulation points N A is usually online programmable.

[0107] To adjust the closed-loop control loop gain, a gain unit is introduced after the output of the first-stage accumulation unit. Assume the gain is k att , then the output signal A after passing through the gain unit i is:

[0108]

[0109] where x i [n] represents the i-th segment accumulation interval of the signal x[n]. It is assumed that the DC offset value of the signal does not change within this accumulation interval. Assume that the signal x[n] can be expressed as:

[0110] x[n] = a sin(2πfn) + d (2)

[0111] where: a represents the signal amplitude, f represents the signal frequency, and d is the DC component of the signal. Since the compensated DC value changes during the DC offset compensation process, the DC value d also changes with time. Assume that within the integration time interval of the i-th segment, the output value of the DC offset compensation algorithm is d comp,i (d comp,i is Figure 1 the calibration codeword mix_code in comp,i . For simplicity of description in the following formula, use d conv to replace it). The conversion gain coefficient from the calibration codeword through the DAC to the ADC input is set to k i , and the signal is x i [n], then:

[0112] x i [n] = a conv sin(2πfn) + d - k comp,i d i = a i sin(2πfn) + d

[0113] At this time, the output value A i of the gain unit is the current DC offset value of the signal and can be expressed as:

[0114]

[0115] After obtaining the DC offset value A i , it is sent to the first-stage accumulation unit to obtain the next update value d comp,i+1 :

[0116] d comp,i+1 = d comp,i + k att d i N A (5)

[0117] Substitute d i = d - k conv × d comp,i into the above formula to obtain:

[0118]

[0119] Wherein:

[0120]

[0121] After the formula (7) is iterated multiple times, the DC offset value in the signal can be reduced or eliminated. Usually, the number of iterations is software programmable. When the number of iterations exceeds the preset value, the mixed-signal DC offset correction algorithm converges, and the lock_mix signal changes from 0 to 1.

[0122] In one embodiment, during the mixed DC correction process, the mixed DC offset corrector outputs a second control signal lock_mix to indicate whether the mixed DC correction is completed;

[0123] When the second control signal lock_mix is the first value, it indicates that the mixed DC correction is completed;

[0124] When the second control signal lock_mix is the second value, it indicates that the mixed DC correction is not completed.

[0125] It should be noted that for the mixed DC offset corrector, the first value can be "1" and the second value can be "0".

[0126] As the algorithm iterates, the correction codeword mix_code tends to converge. During the correction process, the mixed DC offset corrector outputs a second control signal lock_mix to indicate whether the algorithm converges. When the mixed DC offset correction is not completed, the second control signal lock_mix remains 0; the entire process waits for the algorithm to converge. When the algorithm converges, the second control signal lock_mix changes from 0 to 1, indicating that the mixed DC offset correction for the current gain configuration A[i] is completed and proceeds to the next step.

[0127] In one embodiment, the correction circuit further includes:

[0128] A memory (MEM) for storing the correction codeword and the link sequence gain_index[i] configured by the gain controller of the zero-IF receiver as an associated relationship.

[0129] Specifically, the correction codeword mix_code is sent to the DC offset correction DAC on the one hand and to the gating circuit on the other hand. The second control signal lock_mix is simultaneously used as the control signal for the gating circuit. After the second control signal lock_mix changes from 0 to 1, the gating circuit is opened. The correction codeword mix_code obtained from the mixed DC offset corrector is then sent to the data input terminal of the memory, forming a storage table with the link sequence gain_index[i], where the link sequence gain_index[i] serves as the row number of the storage table, and the correction codeword mix_code serves as the stored content corresponding to the row.Figure 2 It is a schematic storage structure for calibration codewords and link sequences. In implementation, those skilled in the art can also design other memory structures, but it does not affect the solution proposed in this application. For example, on-chip memories can have different implementation forms, such as SRAM (Static Random-Access Memory), ROM (Read-Only Memory), OTP (One Time Programmable), FLASH (flash memory), etc.

[0130] After storing the calibration codeword mix_code, perform gain configuration, and then complete calibration.

[0131] After traversing all possible gain values, the gain controller sends an indication signal to the state controller, indicating that the DC offset in all gain cases has completed offline calibration. After receiving the indication signal, the state controller changes the rx_state state from the off_calibration state to the normal_work state.

[0132] After the DC offset correction controller receives that the rx_state signal is in the normal_work state, it switches the correction mode from the offline correction mode to the normal reception mode. At this time, the DC offset correction controller pulls the first control signal enable_mix from 1 to 0. When the first control signal enable_mix is 0, the mixed DC offset corrector is turned off and the digital domain DC offset corrector is turned on. During normal operation, the DC offset correction controller receives the current link gain A[i] and the gain index gain_index[i] sent from the gain controller. The DC offset correction controller retrieves the corresponding calibration codeword mix_code from the memory according to the input gain index gain_index[i]. Under the control of the first control signal enable_mix, the multiplexer connecting the input end of the DC offset correction DAC selects the calibration codeword mix_code as the output, sends the calibration codeword mix_code into the DC offset correction DAC, and then the DC offset correction DAC converts the calibration codeword mix_code from a digital codeword to an analog current, and adds the analog current to the output current of the mixer. After passing through a low-pass filter, an ADC, and a digital filter, a digital codeword is obtained; the digital domain DC offset corrector detects the DC value according to the digital codeword and generates a corresponding calibration codeword to complete the DC correction.

[0133] In the above process, it is necessary to rely on the hybrid direct offset correction algorithm and the digital DC offset correction algorithm. In terms of the essence of the algorithms, the hybrid DC offset correction algorithm and the digital domain DC offset correction algorithm are the same. Comparatively speaking, the hybrid DC offset algorithm has one more conversion process from the digital domain to the analog domain and then from the analog domain to the digital domain than the digital domain DC offset algorithm.

[0134] For the digital domain DC offset correction algorithm, k in Equation (7) can be directly set to 1, and the correction method is the same as that of the hybrid DC offset correction method. conv to be 1, and the correction method is the same as that of the hybrid DC offset correction method.

[0135] Since in the hybrid DC offset correction, the signal will pass through a mixer, a low-pass filter, an ADC, a digital filter, etc.; therefore, before each accumulation, a time for waiting for the analog RF circuit to stabilize can be set. In the digital domain DC offset correction algorithm, this stabilization time can be accurately set according to the delay during system implementation.

[0136] The method proposed by the present invention, compared with the traditional DC offset correction circuit, has the characteristics of fast correction speed, high correction accuracy, and insensitivity of the correction accuracy and correction speed to the change of the receiver gain.

[0137] This application provides a zero-IF receiver, including a mixer, a low-pass filter, an ADC, a digital filter, a gain controller, and a state controller; the zero-IF receiver further includes the DC offset correction circuit described above.

[0138] Please refer to Figure 4 , this application provides a gain-related DC offset correction method, which is applied to a zero-IF receiver. The zero-IF receiver includes a gain controller and a state controller; the correction method includes:

[0139] Step S410, the DC offset correction controller outputs a first control signal enable_mix according to the state information rx_state sent by the state controller of the zero-IF receiver to start the hybrid DC offset corrector;

[0140] Step S420, when the first control signal enable_mix is at a first value, the hybrid DC offset corrector runs the hybrid DC offset correction algorithm to perform hybrid DC offset correction to obtain a correction codeword;

[0141] Step S430, when the first control signal enable_mix is at a second value, the digital domain DC offset corrector runs the digital domain DC offset correction algorithm and performs digital domain DC correction according to the correction codeword.

[0142] In one embodiment, when the first control signal enable_mix is at a first value, the hybrid DC offset corrector operates the hybrid DC offset correction algorithm to perform hybrid DC offset correction to obtain a correction codeword, including:

[0143] When the first control signal enable_mix is at a first value, the hybrid DC offset corrector outputs a codeword mix_code and sends the codeword mix_code into the DC offset correction DAC;

[0144] The DC offset correction DAC converts the codeword mix_code from a digital codeword to an analog current, adds the analog current to the output current of the mixer, and obtains a digital codeword after passing through a low-pass filter, an ADC, and a digital filter;

[0145] The hybrid DC offset corrector performs DC value detection based on the digital codeword and generates a corresponding correction codeword.

[0146] In one embodiment, the correction method further includes:

[0147] Storing the correction codeword and the link sequence gain_index[i] configured by the gain controller of the zero-IF receiver as an associated relationship.

[0148] In an embodiment of the present application, the hybrid DC offset corrector includes: a first-stage accumulation unit, a gain unit, and a second-stage accumulation unit; the hybrid DC offset corrector performs DC value detection based on the digital codeword and generates a corresponding correction codeword, including:

[0149] The number of accumulation points of the first-stage accumulation unit is N A , and the output signal A i of the gain unit is:

[0150]

[0151] where k att is the gain of the gain unit, x i [n] represents the i-th accumulation interval of the signal x[n] output by the digital filter, and the DC offset value of the signal does not change within the accumulation interval. The signal x[n] is expressed as:

[0152] x[n] = asin(2πfn) + d (2)

[0153] where: a represents the signal amplitude, f represents the signal frequency, and d is the DC component of the signal;

[0154] Within the i-th accumulation interval, the signal x i [n] is,

[0155] x i [n]=a i sin(2πfn)+d-k conv d comp,i =a i sin(2πfn)+d i (3)

[0156] Wherein, a i represents the signal amplitude, d comp,i represents the correction codeword, k conv is the gain coefficient;

[0157] The output value A of the gain unit i is the current DC offset value of the signal,

[0158]

[0159] The second-stage accumulation unit receives the output value A of the gain unit i and obtains the next update value d comp,i+1 :

[0160] d comp,i+1 =d comp,i +k att d i N A (5)

[0161] Substitute d i =d-k conv ×d comp,i into the above formula to obtain:

[0162]

[0163] Wherein:

[0164]

[0165] After multiple iterations of formula (7), the DC offset value in the signal is reduced or eliminated.

[0166] Specifically, the correction method of the embodiment of the present application includes:

[0167] The first step: When the chip is powered on, the state controller issues instructions to the gain controller and the DC offset correction controller. The gain controller configures the channel gains in a certain order, which can be configured from large to small according to the gain, or from small to large, or in other set ways in the form of a table. At the same time, the gain controller sends the current gain information to the DC offset controller.

[0168] Step 2: Detect whether the gain configuration is completed. If the gain configuration is not completed, the gain controller traverses all gain combinations according to the set gain control method, and sorts all these gains in a certain way, such as from large to small or from small to large. Let the link gain configured for the i-th time be A[i], and the corresponding sequence be gain_index[i]. After the gain configuration is completed, the gain controller sends the link gain A[i] and the corresponding index gain_index[i] to the DC offset correction controller. The DC offset controller receives the link gain A[i] and the gain index gain_index[i], and processes them in combination with the status information rx_state sent by the status controller. When rx_state is in the offline calibration state, the DC offset correction controller starts the hybrid DC offset correction algorithm.

[0169] Step 3: Start the hybrid DC offset correction algorithm. In this stage, the DC offset controller outputs the first control signal enable_mix from 0 to 1 to start the hybrid DC offset corrector to run the hybrid DC offset correction algorithm. The first control signal enable_mix is also used as the gating signal of the multiplexer; when the first control signal enable_mix is 1, the multiplexer selects the output codeword mix_code of the hybrid DC offset correction algorithm and sends this codeword mix_code into the DC offset correction DAC (DCOC DAC) to realize the conversion from the digital codeword to the analog current. At this time, the output current of the DC offset correction DAC is added to the output of the mixer, and after passing through the low-pass filter, ADC and digital filter, it is sent into the hybrid DC offset corrector to form a complete digital-analog hybrid correction loop. The hybrid DC offset corrector detects the DC value according to the received digital codeword and generates the corresponding correction codeword mix_code to achieve DC correction.

[0170] As the algorithm iterates, the correction codeword mix_code tends to converge. During the correction process, the hybrid DC offset correction algorithm outputs the second control signal lock_mix to indicate whether the algorithm converges. When the hybrid DC offset correction is not completed, the second control signal lock_mix remains 0; the entire process waits for the algorithm to converge. When the algorithm converges, the second control signal lock_mix changes from 0 to 1, indicating that the hybrid DC offset correction for the current gain configuration A[i] is completed, and enters the next step.

[0171] Step 4: Store the correction value. The correction codeword mix_code is sent to the DC offset correction DAC on one hand and to the gating circuit on the other hand. The second control signal lock_mix serves as the control signal for the gating circuit at the same time. After the second control signal lock_mix changes from 0 to 1, the gating circuit is opened. The correction codeword mix_code obtained from the hybrid DC offset corrector is sent to the data input terminal of the memory, forming a storage table with the gain index gain_index[i]. Here, the gain index gain_index[i] serves as the row number of the storage table, and the correction codeword mix_code serves as the stored content corresponding to the row.

[0172] After the storage of the correction codeword mix_code is completed, return to Step 2.

[0173] Step 5: End the hybrid DC offset correction and receive the normal operation indication. After traversing all possible gain values, the gain controller sends an indication signal to the state controller, indicating that the DC offset has been corrected offline for all gain cases. After receiving the indication signal, the state controller changes the state of rx_state from the off_calibration state to the normal_work state.

[0174] Step 6: After the DC offset correction controller receives that the rx_state signal is in the normal_work state, it switches the correction mode from the offline correction mode to the normal reception mode. At this time, the DC offset correction controller pulls down the first control signal enable_mix from 1 to 0. When the first control signal enable_mix is 0, the hybrid DC offset corrector is turned off, and the digital domain DC offset corrector starts to run the digital domain DC offset correction algorithm. During normal operation, the DC offset correction controller receives the current gain information and the corresponding gain index sent from the gain controller. The DC offset correction controller retrieves the corresponding stored correction codeword mix_code from the memory according to the input gain index. Under the control of the first control signal enable_mix, the multiplexer connecting the input terminal of the DC offset correction DAC selects the correction codeword mix_code as the output and sends mix_code into the DC offset correction DAC.

[0175] In the above process, it is necessary to rely on the hybrid direct offset correction algorithm and the digital DC offset correction algorithm. In terms of the essence of the algorithm, the hybrid DC offset correction and the digital domain DC offset correction are the same. Comparatively speaking, the hybrid DC offset algorithm has one more conversion process from the digital domain to the analog domain and then from the analog domain to the digital domain than the digital domain DC offset algorithm. Therefore, in this article, the hybrid DC offset correction algorithm is taken as an example to describe its working process.

[0176] The above embodiments are only used to exemplarily illustrate the principles and effects of the present application, rather than to limit the present application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present application should still be covered by the claims of the present application.

Claims

1. A gain-dependent DC offset correction circuit, applied to a zero intermediate frequency receiver, characterized in that: The correction circuit includes: a DC correction controller, a hybrid DC offset corrector, and a digital domain DC offset corrector; A DC offset correction controller, configured to output a first control signal enable_mix to start a hybrid DC offset corrector according to state information rx_state sent by a state controller of a zero intermediate frequency receiver; A hybrid DC offset corrector, configured to execute a hybrid DC offset correction algorithm to perform hybrid DC offset correction to obtain a correction codeword when a first control signal enable_mix is ​​at a first value; The digital domain DC offset corrector is used to run a digital domain DC offset correction algorithm when the first control signal enable_mix signal is a second value, and perform digital domain DC correction according to the correction codeword.

2. The gain-dependent DC offset correction circuit according to claim 1, characterized in that: The DC offset correction circuit also includes a DC offset correction DAC; The hybrid DC offset corrector is used to output a codeword mix_code when the first control signal enable_mix is ​​a first value, and send the codeword mix_code to the DC offset correction DAC; The DC offset correction DAC is used to convert the codeword mix_code from a digital codeword to an analog current; the analog current output by the DC offset correction DAC is added to the output current of the mixer, and a digital codeword is obtained after passing through a low-pass filter, an ADC and a digital filter; The hybrid DC offset corrector performs DC value detection according to the digital codeword and generates a corresponding correction codeword.

3. The gain-dependent DC offset correction circuit according to claim 2, characterized in that: The correction circuit also includes: The memory is used to store the correction codeword and the link sequence gain_index[i] configured by the gain controller of the zero intermediate frequency receiver as an associated relationship.

4. The gain-dependent DC offset correction circuit according to claim 3, characterized in that: During the hybrid DC correction process, the hybrid DC offset corrector outputs a second control signal lock_mix to indicate whether the hybrid DC correction is completed; When the second control signal lock_mix is ​​a first value, it indicates that the mixed DC correction is completed; When the second control signal lock_mix is ​​at the second value, it indicates that the mixed DC correction is not completed.

5. The gain-dependent DC offset correction circuit according to claim 2, characterized in that: The hybrid DC offset corrector comprises: a first-stage accumulation unit, a gain unit, and a second-stage accumulation unit; The number of accumulated points of the first-level accumulation unit is N A , the output signal A of the gain unit i for: Among them, k att is the gain of the gain unit, x i [n] represents the i-th accumulation interval of the signal x[n] output by the digital filter. The DC offset value of the signal does not change within the accumulation interval. The signal x[n] is expressed as: x[n]=asin(2πfn)+d (2) Where: a represents the signal amplitude, f represents the signal frequency, and d represents the DC component of the signal; In the accumulation interval of the i-th segment, the signal x i [n] is, x i [n]=a i sin(2πfn)+d-k conv d comp,i =a i sin(2πfn)+d i (3) Among them, a i Indicates the signal amplitude, d comp,i represents the correction codeword, k conv is the gain coefficient; The output value of the gain unit A i is the current DC offset value of the signal, The second stage accumulation unit receives the output value A of the gain unit i In the next update, we get the next update value d comp,i+1 : d comp,i+1 =d comp,i +k att d i N A (5) D i =dk conv ×d comp,i Substituting into the above formula, we get: in: After multiple iterations of equation (7), the DC offset value in the signal is reduced or eliminated.

6. A gain-dependent DC offset correction method, applied to a zero intermediate frequency receiver, wherein the zero intermediate frequency receiver comprises a gain controller and a state controller; characterized in that: The correction method comprises: Outputting a first control signal enable_mix to start a hybrid DC offset corrector through a DC offset correction controller according to state information rx_state sent by a state controller of a zero intermediate frequency receiver; When the first control signal enable_mix is ​​at a first value, the hybrid DC offset corrector runs a hybrid DC offset correction algorithm to perform hybrid DC offset correction to obtain a correction codeword; When the first control signal enable_mix is ​​at the second value, the digital domain DC offset corrector runs a digital domain DC offset correction algorithm and performs digital domain DC correction according to the correction codeword.

7. The gain-dependent DC offset correction method according to claim 6, characterized in that: The hybrid DC offset corrector runs a hybrid DC offset correction algorithm to perform hybrid DC offset correction to obtain a correction codeword when the first control signal enable_mix is ​​a first value, including: When the first control signal enable_mix is ​​at a first value, the mixed DC offset corrector outputs a codeword mix_code, and sends the codeword mix_code to the DC offset correction DAC; The DC offset correction DAC converts the codeword mix_code from a digital codeword to an analog current, and adds the analog current to the output current of the mixer to obtain a digital codeword after passing through a low-pass filter, an ADC and a digital filter; The hybrid DC offset corrector performs DC value detection according to the digital codeword and generates a corresponding correction codeword.

8. The gain-dependent DC offset correction method according to claim 7, characterized in that: The correction method also includes: The correction codeword and the link sequence gain_index[i] configured by the gain controller of the zero intermediate frequency receiver are stored as an associated relationship.

9. The gain-dependent DC offset correction method according to claim 7, characterized in that: The hybrid DC offset corrector comprises: a first-stage accumulation unit, a gain unit, and a second-stage accumulation unit; the hybrid DC offset corrector performs DC value detection according to the digital codeword and generates a corresponding correction codeword, including: The number of accumulated points of the first-level accumulation unit is N A , the output signal A of the gain unit i for: Among them, k att is the gain of the gain unit, x i [n] represents the i-th accumulation interval of the signal x[n] output by the digital filter. The DC offset value of the signal does not change within the accumulation interval. The signal x[n] is expressed as: x[n]=asin(2πfn)+d (2) Where: a represents the signal amplitude, f represents the signal frequency, and d represents the DC component of the signal; In the accumulation interval of the i-th segment, the signal x i [n] is, x i [n]=a i sin(2πfn)+d-k conv d comp,i =a i sin(2πfn)+d i (3) Among them, a i Indicates the signal amplitude, d comp,i represents the correction codeword, k conv is the gain coefficient; The output value of the gain unit A i is the current DC offset value of the signal, The second stage accumulation unit receives the output value A of the gain unit i In the next update, we get the next update value d comp,i+1 : d comp,i+1 =d comp,i +k att d i N A (5) D i =dk conv ×d comp,i Substituting into the above formula, we get: in: After multiple iterations of equation (7), the DC offset value in the signal is reduced or eliminated.

10. A zero intermediate frequency receiver, comprising a mixer, a low-pass filter, an ADC, a digital filter, a gain controller and a state controller; characterized in that: The zero intermediate frequency receiver also includes a DC offset correction circuit as described in any one of claims 1-5.

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