Intelligent cable core aligning device based on multi-frequency signal synchronous transmission technology

Abstract

The invention provides an intelligent cable core aligning device based on a multi-frequency signal synchronous transmission technology, and the device comprises a signal transmission control unit which is used for executing the core management of a transmitting end, completing the execution of a man-machine operation instruction, simulating and synthesizing a multi-frequency signal, and controlling the output of a signal; the signal receiving control unit is used for receiving and decomposing the signal sent by the transmitting end and completing the process of automatically receiving the signal by the receiving end; the signal automatic analysis unit is used for automatically analyzing the frequency and the duty ratio of the multi-frequency signal received from the cable; the wire core authentication identification unit is used for carrying out ID number identification according to the received and analyzed signal characteristic quantity; and the retrieval result display unit is used for displaying the wire core serial number and the authentication identifier of the receiving end according to the human-computer interface display process of the wire core authentication identifier unit. According to the invention, the problems of labor waste, time waste and error proneness in core alignment work can be solved.

Description

Technical Field

[0001] This application relates to the technical field of power cable detection, and particularly to an intelligent cable core-pairing device based on multi-frequency signal synchronous transmission technology. Background Art

[0002] In the actual construction and maintenance applications of power systems, cable core-pairing work is an essential task. The traditional method uses manual intercom and single-line confirmation, which has a large workload, takes a long time, and is prone to human errors due to the long distance between the two sides. Once there is a mistake, it will bring major safety hazards to the subsequent tests and operations. Especially in the technical transformation and infrastructure projects, there are a large number of cables, which are numerous and complex, and the work is cumbersome and error-prone, increasing the on-site safety risks invisibly. Summary of the Invention

[0003] This application aims to solve at least one of the technical problems in the related technologies to some extent.

[0004] To this end, the first object of this application is to propose an intelligent cable core-pairing device based on multi-frequency signal synchronous transmission technology.

[0005] The second object of this application is to propose an intelligent cable core-pairing based on multi-frequency signal synchronous transmission technology.

[0006] The third object of this application is to propose a computer-readable storage medium.

[0007] To achieve the above object, the first aspect embodiment of this application proposes an intelligent cable core-pairing device based on multi-frequency signal synchronous transmission technology, including:

[0008] A signal transmission control unit, used to execute the core management at the transmitting end, and complete the control functions of executing human-machine operation instructions, simulating and synthesizing multi-frequency signals, and outputting control signals;

[0009] A signal reception control unit, used to receive and decompose the signals sent by the transmitting end, and complete the process of automatically receiving signals at the receiving end;

[0010] A signal automatic analysis unit, used to automatically analyze the frequency and duty cycle of the multi-frequency signals on the received cables;

[0011] A core authentication identification unit, used to perform ID number identification according to the received and analyzed signal feature quantities;

[0012] A retrieval result display unit, used to display the core serial numbers and authentication identifications at the receiving end according to the core authentication identification unit during the process of human-machine interface display.

[0013] Optionally, it further includes:

[0014] The power input module is used to provide a stable power supply for the internal circuit and chips, automatically adapt to the 12V battery power supply, and convert the voltage to 5V and 3.3V, which is suitable for the power consumption of the internal circuit and chips.

[0015] Optionally, it further includes:

[0016] The signal transmitting and transmitting unit is used to synchronously transmit the multi-frequency signal simulated and synthesized by the signal transmitting control unit to the starting end of the cable and transmit it along the cable;

[0017] The signal feedback and verification unit is used to identify and verify the pulse information fed back by the receiving end.

[0018] Optionally, the signal transmitting control unit includes a first CPU controller, a first clock unit, a memory unit, and a signal isolation and amplification unit, where:

[0019] The first CPU controller uses a 32-bit high-speed chip adopting the low-power and high-performance Cortex-M3 core high-speed processor technology, and is used to be responsible for the analog synthesis of signals and the output of control signals;

[0020] The first clock unit is composed of a passive crystal oscillator and a precision ceramic capacitor to form the clock reference for the operation of the first CPU controller, and is used to achieve accurate time recording of the information at the transmitting end and ensure the accurate timing of signal processing;

[0021] The memory unit uses the I2C communication method for data transmission, and is used to store permanently saved codes, instructions, variables, and the single-chip microcomputer program executed by the first CPU controller;

[0022] The signal isolation and amplification unit uses a high-speed optoelectronic isolation device and an amplitude boosting amplifier circuit, and is used to achieve level safety isolation between the external circuit and the internal first CPU controller and synchronous amplitude boosting amplification.

[0023] Optionally, the signal receiving control unit includes a second CPU controller, a second clock unit, a signal isolation unit, and a human-machine interface and communication interface unit, where:

[0024] The second CPU controller uses a 32-bit high-speed chip adopting the low-power and high-performance Cortex-M3 core high-speed processor technology, and is used to be responsible for signal isolation, control of the main program, automatic parsing of multi-frequency signals, signal feedback control, core identification and marking, and control of the human-machine interface display process;

[0025] The second clock unit is composed of a passive crystal oscillator and a precision ceramic capacitor to form the clock reference for the operation of the second CPU controller, and is used to achieve accurate time recording of the information at the receiving end and ensure the accurate timing of signal processing;

[0026] The signal isolation unit adopts a high-speed optoelectronic isolation device circuit, which is used to achieve the level safety isolation between the external circuit connected by the cable and the second CPU controller, and avoid damage to the control caused by interference signals;

[0027] The human-computer interaction interface and communication interface unit adopts a TTL communication interface and a touch screen, and is used to display the received signals and the authentication identifiers of the wire cores.

[0028] Optionally, the signal automatic parsing unit is used for:

[0029] Obtain the currently received multi-frequency signal source from the signal isolation unit, and parse the received multiple signals for frequency, duty cycle, and continuous emission duration;

[0030] Label the wire cores at the transmitting end with letters A - T according to the parsing results;

[0031] Label the wire cores at the receiving end with numbers 1 - 25 according to the GPIO port numbers in the second CPU controller.

[0032] Optionally, the wire core authentication identifier unit is used for:

[0033] Establish a correspondence table according to the correspondence between frequency, duty cycle, continuous emission duration and letter labels, and the correspondence between the GPIO port numbers in the second CPU controller and the digital labels of the wire cores, and store the relationship table in the second CPU controller.

[0034] Optionally, the retrieval result display unit adopts a touch screen, which is used to display the correspondence table output by the wire core authentication identifier unit, and the touch screen communicates with the second CPU controller through a serial port.

[0035] To achieve the above object, the second aspect embodiment of the present application proposes an intelligent cable pair core method based on multi-frequency signal synchronous transmission technology, including:

[0036] At the transmitting end, use the signal transmission control unit to generate multiple multi-frequency signals and perform synchronous transmission;

[0037] Transmit the multi-frequency signals along the cable to the receiving end, receive and parse the received signals through the signal receiving control unit, and complete the automatic reception and decomposition of the signals;

[0038] Automatically parse the frequency and duty cycle of the multi-frequency signals on the received cable through the signal automatic parsing unit, assign letter labels to the wire cores at the transmitting end according to the parsing results, and label the wire cores at the receiving end with numbers according to the GPIO port numbers in the second CPU controller;

[0039] Through the core authentication identification unit, according to the correspondence relationship between frequency, duty cycle, continuous emission duration and letter label, and the correspondence relationship between the GPIO port number in the second CPU controller and the digital label of the core, a correspondence table is formed and stored.

[0040] Use the core authentication identification unit to display the correspondence table output by the core authentication identification unit through the touch screen.

[0041] To achieve the above object, an embodiment of the third aspect of the present application proposes a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the method described in the second aspect.

[0042] The technical solutions provided by the embodiments of the present application at least bring the following beneficial effects:

[0043] This device can significantly simplify the complex process of traditional cable core matching work and greatly improve work efficiency. By using dual-terminal devices at both ends of the cable head and tail to synchronously transmit multi-channel multi-frequency signals with one key, the receiving end can quickly identify the core numbers at one time, realizing the automation and intelligence of on-site operations. And the device intuitively displays the recognition results through the LCD display screen, ensuring that users can clearly and accurately obtain core information, avoiding errors in manual operations, and further improving accuracy and safety.

[0044] In addition, adopting this technical solution can also significantly shorten the operation and maintenance time, improve the overall operation and maintenance efficiency, and ensure quick response and operation in the construction site and network communication environment. By realizing automatic one-key core identification, the operation process is more convenient, greatly reducing the work burden and error rate of on-site construction personnel, and improving work safety and reliability.

[0045] In short, through the application of multi-frequency signal synchronous transmission technology, this device provides a simple, fast, accurate and intelligent on-site cable core matching solution, greatly improving the efficiency and safety of cable core matching work.

[0046] The additional aspects and advantages of the present application will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0048] Figure 1 is a schematic structural diagram of an intelligent cable core matching device based on multi-frequency signal synchronous transmission technology provided by an embodiment of the present application;

[0049] Figure 2 Internal schematic diagrams of the signal transmission control unit and the signal reception control unit provided by the embodiments of the present application;

[0050] Figure 3 Program flow chart of an intelligent cable core-pairing device based on multi-frequency signal synchronous transmission technology provided by the embodiments of the present application. Specific embodiments

[0051] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application and should not be construed as limiting the present application.

[0052] In view of the problems existing in the prior art, the embodiments of the present application provide an intelligent cable core-pairing device based on multi-frequency signal synchronous transmission technology. Figure 1 Structural schematic diagram of an intelligent cable core-pairing device based on multi-frequency signal synchronous transmission technology provided by the embodiments of the present application. As Figure 1 shown, the device includes a plurality of functional modules that work together to achieve intelligent and automated cable core-pairing operations, which specifically include a signal transmission control unit 10, a signal reception control unit 20, a signal automatic analysis unit 30, a core authentication identification unit 40, and a retrieval result display unit 50.

[0053] In the embodiments of the present application, first, the signal transmission control unit 10 is responsible for executing the core management tasks at the transmitting end. This unit completes the execution of human-machine operation instructions, ensures the analog synthesis of multi-frequency signals, and controls the output of signals. The core function of the signal transmission control unit is to synchronously transmit multiple frequency signals into the cable to ensure that the signals can be accurately and effectively transmitted to the receiving end. The high efficiency of this unit is the key to achieving fast and accurate cable core-pairing operations.

[0054] The signal reception control unit 20 is responsible for receiving and decomposing the multi-frequency signals sent from the transmitting end, and completing the process of automatically receiving signals at the receiving end. This unit extracts the signals from the cable and performs preliminary decoding and processing on them to prepare for signal automatic analysis and subsequent processing. It ensures the integrity and accuracy of the data through precise signal reception, providing high-quality signal input for subsequent signal analysis and authentication identification.

[0055] Next, the signal automatic analysis unit 30 automatically analyzes the received multi-frequency signal for characteristic data such as frequency and duty cycle. This unit can quickly identify various parameters in the signal and automatically calculate key data such as the frequency characteristics and duty cycle of the signal. These analysis results play a decisive role in the subsequent core identification and can effectively reduce errors in manual operations.

[0056] The core identification unit 40 identifies the core ID number based on the received and analyzed signal characteristic quantities (such as frequency, duty cycle, etc.). This unit matches the analysis result of the signal with the core to ensure that each core can be uniquely identified and marked, avoiding problems caused by identification errors in traditional manual operations. This unit makes the core authentication process more intelligent and automated, improving the accuracy.

[0057] Finally, the retrieval result display unit 50 is responsible for displaying on the human-machine interface according to the output of the core identification unit. This unit displays the core serial number and authentication mark of the receiving end through the touch screen. Users can directly view the specific information of the core, thus completing the core operation more intuitively and conveniently. The touch screen display not only improves the operation efficiency but also provides real-time feedback to ensure that the operator can handle any problems in a timely manner.

[0058] In addition, as Figure 1 shown, the device further includes a power input module 60. This module is responsible for providing stable power support for the internal circuits and chips of the device. The power input module can automatically adapt to 12V battery power supply and convert the input voltage to 5V and 3.3V to meet the voltage requirements of each module of the device. Through this power management function, the stable operation of the entire system in different working environments is ensured, and the safety and reliability of the device are improved. The design of this module enables the device to be flexibly used at the construction site or other application scenarios, while reducing the failure risk caused by unstable power supply..

[0059] In addition, as Figure 1 shown, the device further includes: a signal transmission unit 70 and a signal feedback verification unit 80. The functions of these two units are as follows:

[0060] The signal transmission unit 70 is used to synchronously transmit the multi-frequency signal synthesized by the signal transmission control unit to the starting end of the cable and transmit it along the cable. Through this unit, the signal at the transmitting end can be stably transmitted to the receiving end, ensuring the integrity and accuracy of signal transmission.

[0061] The signal feedback and verification unit 800 is used to receive and process the pulse information fed back from the receiving end. It identifies and verifies the received pulse information to ensure the correctness and stability of the signal. If the received pulse signal meets the predetermined standard, the signal feedback and verification unit will confirm the validity of the signal and prepare to feedback it to the transmitting end. This process helps to improve the accuracy and reliability of the signal and ensure the efficient operation of the entire system.

[0062] In addition, as Figure 3 shown, when all feedback signals are detected, the detection of feedback information is carried out again.

[0063] The addition of these two units makes the entire signal transmission process more intelligent and reliable, further enhancing the automation level of the device, avoiding the need for manual intervention, and improving the stability of the system.

[0064] In the embodiment of the present application, as Figure 2 shown, the signal transmission control unit 10 further includes a first CPU controller 101, a first clock unit 102, a memory unit 103, and a signal isolation and amplification unit 104.

[0065] The specific functions are as follows:

[0066] The first CPU controller 101 adopts the low-power and high-performance Cortex-M3 core high-speed processor technology and integrates a 32-bit high-speed chip. This processor is responsible for the analog synthesis of signals and the output of control signals. Through its efficient computing power, the first CPU controller can accurately control the generation and synchronization of multi-frequency signals and ensure the efficiency and stability of signal transmission.

[0067] It should be noted that, as Figure 3 shown, when all multi-frequency signals are transmitted, the analog synthesis process of multi-frequency signals is executed again.

[0068] The first clock unit 102 consists of a passive crystal oscillator and a precision ceramic capacitor and serves as the clock reference for the first CPU controller 101 to ensure the accurate time recording of information at the transmitting end. This unit provides a stable clock signal to ensure the timing accuracy in the signal processing process and avoid signal loss or errors caused by unstable timing.

[0069] The memory unit 103 uses the I2C communication method for data transmission and is used to store permanently saved codes, instructions, variables, and execute the single-chip microcomputer program of the first CPU controller 101. This unit not only provides sufficient storage space for data processing during operation but also provides reliable storage for the instruction set and program code for the system to ensure the stable operation of the system.

[0070] The signal isolation and amplification unit 104 uses high-speed optoelectronic isolation devices and an amplitude amplification circuit to achieve level safety isolation between the external circuit and the first CPU controller 101, preventing electrical noise and interference generated by the external circuit from affecting the normal operation of the internal control unit. At the same time, the signal isolation and amplification unit also enhances the signal strength through the amplitude amplification circuit to ensure that the multi-frequency signal can be efficiently transmitted to the starting end of the cable.

[0071] Through the collaborative work of these module units, the signal transmission control unit 10 can efficiently and stably execute the generation, control, and transmission of signals, providing a reliable guarantee for the normal operation of the system.

[0072] In the embodiment of the present application, as Figure 2 shown, the signal reception control unit 20 further includes a second CPU controller 201, a second clock unit 202, a signal isolation unit 203, and a human-machine interface and communication interface unit 204. The specific functions are as follows:

[0073] The second CPU controller 201 adopts the low-power and high-performance Cortex-M3 core high-speed processor technology and is equipped with a 32-bit high-speed chip. This processor is responsible for multiple tasks such as signal isolation, execution of the main control program, automatic parsing of multi-frequency signals, signal feedback control, core authentication identification, and human-machine interface display control. It is the core of the signal reception control unit, ensuring that the system can efficiently and accurately process the received signals and perform necessary operation feedback.

[0074] The second clock unit 202 consists of a passive crystal oscillator and a precision ceramic capacitor and serves as the clock reference for the second CPU controller 201 to ensure accurate time recording of the received information. This clock unit provides a stable and accurate clock signal, enabling the timing in the signal processing process to be consistent and avoiding signal parsing errors caused by inaccurate timing.

[0075] The signal isolation unit 203 uses a high-speed optoelectronic isolation device circuit to achieve level safety isolation between the received cable signal and the second CPU controller 201. This design can effectively prevent interference signals in the external circuit from damaging the second CPU controller 201 and ensure the stability and accuracy of the system.

[0076] The human-machine interface and communication interface unit 204 uses a TTL communication interface to connect to a touch screen and is used to display the received signals and the core authentication identification. Through the touch screen, users can intuitively view the core authentication information and signal status, thus realizing convenient operation and real-time feedback. The design of this unit improves the interactivity and visualization of the operation. Users can directly perform relevant operations through the touch screen, improving the usability and response speed of the system.

[0077] Through the cooperation of these four modular units, the signal reception control unit 20 can accurately receive, process, and feedback signals at the receiving end, ensuring that the entire system can efficiently and stably perform multi-frequency signal synchronous transmission and core automatic identification of the wire core.

[0078] In the embodiment of the present application, the signal automatic parsing unit 30 is specifically used to perform the following tasks:

[0079] First, the signal automatic parsing unit 30 obtains the currently received multi-frequency signal source from the signal isolation unit 203. This unit performs a detailed analysis of the received multiplexed signals, mainly processing characteristic parameters such as the frequency, duty cycle, and continuous emission duration of the signals. Through these characteristic data, the signal automatic parsing unit 30 can effectively extract the key attributes of each signal, ensuring the smooth progress of subsequent processing steps.

[0080] Next, according to the signal characteristic results obtained by parsing, the signal automatic parsing unit 30 assigns letter labels to the wire cores at the transmitting end, with the label range from A to T. This letter label is used to uniquely identify each wire core and corresponds one-to-one with the frequency characteristics of the signal, ensuring the accuracy of identification.

[0081] In addition, the signal automatic parsing unit 30 also assigns digital labels to the wire cores at the receiving end according to the GPIO port numbers in the second CPU controller, with the label range from 1 to 25. The digital label and the letter label cooperate to provide double protection for the identification of the wire core, ensuring that each wire core can be uniquely and accurately identified.

[0082] Through these steps, the signal automatic parsing unit 30 ensures the accurate parsing of multi-frequency signals and the rapid and accurate identification of wire cores, which helps to improve the efficiency and accuracy of the wire core matching work of the cable.

[0083] In the embodiment of the present application, the wire core authentication and identification unit 40 is specifically used to perform the following tasks:

[0084] The wire core authentication and identification unit 40 establishes a detailed correspondence table based on the correspondence between the received multi-frequency signal characteristic data (such as frequency, duty cycle, continuous emission duration) and the letter labels, combined with the correspondence between the GPIO port numbers in the second CPU controller and the digital labels of the wire cores at the receiving end. This table records the letter labels, digital labels of each wire core, and their corresponding characteristic data such as frequency, duty cycle, and emission duration.

[0085] Through this process, the wire core authentication and identification unit 40 can accurately identify each wire core according to the parsed signal characteristic information and assign a unique label to each wire core. The established correspondence table is stored in the second CPU controller to ensure the secure storage of information and subsequent rapid search and use.

[0086] This process ensures the efficiency and accuracy of the core identification, and provides reliable data support for subsequent operations and displays, making the core pairing process of the cable more intelligent and automated.

[0087] In addition, it should be noted that, as Figure 3 shown, after all frequency band signals are processed, the receiving end starts to re-detect the multi-frequency signal and send back feedback information to the transmitting end.

[0088] In the embodiment of the present application, the retrieval result display unit 50 uses a touch screen, which is mainly used to display the correspondence table output by the core authentication identification unit 40. The touch screen can intuitively display the letter label, digital label of each core, as well as information such as related frequency, duty cycle, and emission duration. Users can quickly view the detailed authentication identification of each core to ensure the accuracy of the core pairing operation.

[0089] In addition, the touch screen communicates with the second CPU controller through a serial port. This communication method enables the second CPU controller to transmit data to the touch screen in real time, ensuring the timely update and feedback of information. Through the efficient data transmission of the serial port, users can obtain real-time operation feedback on the touch screen, improving the interactivity and user experience of the system.

[0090] To implement the above embodiment, the present application also proposes an intelligent cable core pairing method based on multi-frequency signal synchronous transmission technology, including:

[0091] At the transmitting end, use the signal transmission control unit to generate multiple multi-frequency signals and synchronously transmit them;

[0092] Transmit the multi-frequency signal along the cable to the receiving end, receive and analyze the received signal through the signal receiving control unit to complete the automatic reception and decomposition of the signal;

[0093] Automatically analyze the frequency and duty cycle of the multi-frequency signal received on the cable through the signal automatic analysis unit, and assign letter labels to the cores at the transmitting end according to the analysis results, and perform digital labeling on the cores at the receiving end according to the GPIO port numbers in the second CPU controller;

[0094] Through the core authentication identification unit, form a correspondence table according to the correspondence between frequency, duty cycle, continuous emission duration and letter label, and the correspondence between the GPIO port numbers in the second CPU controller and the digital labels of the cores, and store it;

[0095] Use the core authentication identification unit to display the correspondence table output by the core authentication identification unit through the touch screen.

[0096] Regarding the method in the above embodiments, the specific manner in which each step performs operations has been described in detail in the embodiments related to the device, and will not be elaborated here.

[0097] To implement the above embodiments, the present application also proposes a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, are used to implement the method provided in the foregoing embodiments.

[0098] The collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information involved in the present application all comply with the provisions of relevant laws and regulations and do not violate public order and good customs.

[0099] It should be noted that personal information from users should be collected for legal and reasonable purposes and not shared or sold outside of these legitimate uses. In addition, such collection / sharing should be carried out after obtaining the informed consent of the user, including but not limited to notifying the user to read the user agreement / user notice and signing an agreement / authorization including authorizing relevant user information before the user uses the function. In addition, any necessary steps should be taken to protect and safeguard access to such personal information data and ensure that others with access to the personal information data comply with their privacy policies and procedures.

[0100] The present application anticipates providing embodiments that allow users to selectively block the use or access of personal information data. That is, the present disclosure anticipates providing hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, the risk can be minimized by restricting data collection and deleting the data. In addition, when applicable, personal identifiers are removed from such personal information to protect the privacy of the user.

[0101] In the description of the foregoing embodiments, the descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0102] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0103] Any process or method description represented in a flowchart or described otherwise herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logical function or process. The scope of the preferred embodiments of the present application includes additional implementations, where functions may be executed in a substantially simultaneous manner or in an order opposite to that shown or discussed, according to the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application pertain.

[0104] The logic and / or steps represented in a flowchart or described otherwise herein, for example, can be considered as a sequenced list of executable instructions for implementing a logical function, and can be specifically implemented in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of the computer-readable medium include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing as necessary, and then stored in a computer memory.

[0105] It should be understood that each part of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one of the following techniques known in the art or a combination thereof can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), and the like.

[0106] Those of ordinary skill in the art can understand that all or part of the steps carried by the method of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0107] In addition, each functional unit in various embodiments of the present application can be integrated in a processing module, or each unit can exist physically alone, or two or more units can be integrated in a module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the above integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0108] The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disk, or the like. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

[0109] It should be understood that various forms of the processes shown above can be used, reordering, adding, or deleting steps. For example, the steps described in the present application can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present application can be achieved. No limitation is imposed herein.

[0110] The above specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present application should be included within the protection scope of the present application.

Claims

1. An intelligent cable core alignment device based on multi-frequency signal synchronous transmission technology, characterized in that: include: The signal transmission control unit is used to perform the core management of the transmitter, complete the control functions of human-machine operation instruction execution, multi-frequency signal simulation synthesis and control signal output; The signal receiving control unit is used to receive and decompose the signal sent by the transmitting end, and complete the process of the receiving end automatically receiving the signal; The signal automatic analysis unit is used to automatically analyze the frequency and duty cycle of the multi-frequency signal received on the cable; The wire core authentication identification unit is used to identify the ID number according to the received and analyzed signal characteristics; The search result display unit is used to display the wire core serial number and the authentication mark of the receiving end according to the process of the wire core authentication mark unit performing human-machine interface display.

2. The device according to claim 1, characterized in that Also includes: The power input module is used to provide stable power for internal circuits and chips. It automatically adapts to 12V battery power and converts the voltage into 5V and 3.3V, which is suitable for internal circuits and chips.

3. The device according to claim 2, characterized in that Also includes: A signal transmission unit, used for synchronously transmitting the multi-frequency signal simulated and synthesized by the signal transmission control unit to the starting end of the cable and transmitting it along the cable; The signal feedback verification unit is used to identify and verify the pulse information fed back by the receiving end.

4. The device according to claim 3, characterized in that The signal transmission control unit includes a first CPU controller, a first clock unit, a memory unit and a signal isolation and amplification unit, wherein: The first CPU controller adopts a 32-bit high-speed chip using low-power, high-performance Cortex-M3 core high-speed processor technology, which is responsible for analog synthesis of signals and control signal output; The first clock unit uses a passive crystal oscillator and a precision magnetic sheet capacitor to form a clock reference for the operation of the first CPU controller, which is used to achieve accurate time recording of the transmitter information and ensure accurate timing of signal processing; The memory unit uses I2C communication mode for data transmission and is used to store permanently saved codes, instructions, variables and execute the single chip microcomputer program of the first CPU controller; The signal isolation and amplification unit adopts a high-speed photoelectric isolation device and an amplitude-boosting amplification circuit to achieve level safety isolation and synchronous amplitude-boosting amplification between an external circuit and the first internal CPU controller.

5. The device according to claim 4, characterized in that The signal receiving control unit includes a second CPU controller, a second clock unit, a signal isolation unit, and a human-computer interaction interface and communication interface unit, wherein: The second CPU controller adopts a 32-bit high-speed chip using low-power, high-performance Cortex-M3 core high-speed processor technology, which is responsible for signal isolation, main control program, automatic analysis of multi-frequency signals, signal feedback control, wire core authentication identification and human-machine interface display control process; The second clock unit uses a passive crystal oscillator and a precision magnetic sheet capacitor to form a clock reference for the operation of the second CPU controller, which is used to achieve accurate time recording of the receiving end information and ensure accurate timing of signal processing; The signal isolation unit adopts a high-speed photoelectric isolation device circuit to achieve level safety isolation between the external circuit connected by the cable and the second CPU controller to avoid interference signals from causing damage to the control; The human-machine interaction interface and communication interface unit adopts a TTL communication interface and a serial touch screen to display the received signal and the authentication mark of the line core.

6. The device according to claim 5, characterized in that The automatic signal analysis unit is used for: Acquire the currently received multi-frequency signal source from the signal isolation unit, and analyze the frequency, duty cycle, and continuous transmission duration of the received multi-channel signals; According to the analysis results, the core of the transmitting end is labeled AT; The wire cores at the receiving end are digitally numbered 1-25 according to the GPIO port number in the second CPU controller.

7. The device according to claim 6, characterized in that The wire core authentication identification unit is used to: A correspondence table is established based on the correspondence between frequency, duty cycle, continuous transmission duration and letter labels, and the correspondence between the GPIO port number in the second CPU controller and the digital label of the wire core, and the relationship table is stored in the second CPU controller.

8. The device according to claim 7, characterized in that The search result display unit adopts a touch screen for displaying the corresponding relationship table output by the wire core authentication identification unit, and the touch screen communicates with the second CPU controller through a serial port.

9. An intelligent cable core alignment method based on multi-frequency signal synchronous transmission technology, applied to the device described in any one of claims 1 to 8, characterized in that: include: At the transmitting end, a signal transmission control unit is used to generate multi-channel multi-frequency signals and transmit them synchronously; The multi-frequency signal is transmitted along the cable to the receiving end, and the received signal is received and analyzed by the signal receiving control unit to complete the automatic reception and decomposition of the signal; The multi-frequency signal received on the cable is automatically analyzed for frequency and duty cycle by the signal automatic analysis unit, and letter labels are assigned to the wire cores of the transmitting end according to the analysis results, and digital labels are assigned to the wire cores of the receiving end according to the GPIO port number in the second CPU controller; Through the core authentication identification unit, a corresponding relationship table is formed and stored according to the corresponding relationship between the frequency, duty cycle, continuous transmission time and letter label, and the corresponding relationship between the GPIO port number in the second CPU controller and the digital label of the core; The wire core authentication identification unit is used to display the corresponding relationship table output by the wire core authentication identification unit through the touch screen.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to claim 9 when executed by a processor.

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